This document is commercially confidential and must NOT be disclosed to third parties without prior consent.
The information provided herein is believed to be reliable. But production testing may not include testing of
all parameters. AIROHA Technology Corp. reserves the right to change information at any time without
notification. ( HTTP://WWW.AIROHA.COM.TW
Created
Spec Update
Spec Revised
Errata and Update (internal release only)
Update (internal release only)
Update
Update
AR1000E only for approval sheet draft
AR1000/AR1010 version
Update for AR1000 F
Page 10, Sec 6.1, DATA In, BUSEN to CLOCK P-edge Hold time unit added.
Page 13, Sec 7.3, Audio output L/R imbalance and stereo separation spec updated.
Changing List (from 0.11 to 0.20):
Page 5, Chap 1, Package thickness updated.
Page 6, Chap 3, pin out updated (pin2pin4) & (pin19pin20).
Page 7, Chap 4, pin out updated (pin2pin4) & (pin19pin20).
Page 12, Chap 7, Register Table added.
Page 17, Chap 9, Package thickness updated & Foot Print information added.
Worldwide FM band support: 76~108MHz
Highest integration level with minimized external BOM cost
Frequency synthesizer with integrated VCO and Automatic Frequency Control (AFC)
Integrated XO with external reference clock input or external 32.768KHz crystal
Automatic Gain Control (AGC) on LNA/VGA amplifiers
Signal strength measurement
Programmable de-emphasis time constant (50/75us)
Adaptive noise suppression
Analog output with volume control and Line-level outputs
Serial control interface for 2-wire and 3-wire modes
Support both RDS & RBDS (AR1000 only)
Embedded Seek tuning function
Integrated LDO regulators support 2.7 to 5.5 V supply voltage
QFN 4x4x0.6mm 24-pin package
2 Description
AR1000/AR1010 is a highly integrated single chip stereo FM radio receiver for all kinds of
applications. AR1000/AR1010 supports worldwide FM bands from 76 to 108MHz. It
integrates LNA, Mixer, Oscillator and LDO regulator to minimize the external BOM cost. The
built-in FM signal processing unit with noise reduction mechanism provides optimum sound
quality. A simple 2-wire/3-wire interface allows easy control from the host. For AR1000, a
Radio Data System (RDS) and Radio Broadcast Data System (RBDS) demodulator and
decoder are also supported.
AR1000 and AR1010 are pin-to-pin compatible and are the same in all FM radio receiver
functions, specs and packages except the RDS/RBDS function. AR1000 supports RDS/RBDS
receiver function, while AR1010 do not.
Page 6 of 6 CONFIDENTIAL
AR1000 & AR1010 Single Chip FM Radio
1 GNDRF GND RF Ground
2 RFIN Input, Analog RF Input
3 GNDMIX GND Mixer Ground
4 NC Not Connected
5 BUSMODE Input, Digital Control 2-wire/3-wire Bus Mode Selection
6 GPIO2 Input/Output, Digital General I/O Port 2
7 GPIO3 Input/Output, Digital General I/O Port 3
8 XTAL1 Analog XTAL Input
9 XTAL2 Analog XTAL Oscillator Input
10 BUSEN Input, Digital Control Serial Interface
11 CLOCK Input, Digital Control Serial Interface
12 DATAIO Input/Output, Digital Serial Interface
13 VDDD VCC Supply Supply Voltage for Digital Circuits
14 VCCIO VCC Supply Supply Voltage for I/O Ports
15 GPIO1 Input/Output, Digital General I/O Port 1
16 GNDD GND Digital Ground
17 LOUT Output, Analog Left Audio Output
18 ROUT Output, Analog Right Audio Output
19 GNDA1 GND Analog Ground
20 GNDA2 GND Analog Ground
21 VANA1 VCC Supply Supply Voltage for Analog Circuits
22 VANA2 VCC Supply Supply Voltage for Analog Circuits
23 VCON Input, Analog VCO Tank Input
24 VCOP Input, Analog VCO Tank Input
Page 8 of 8 CONFIDENTIAL
AR1000 & AR1010 Single Chip FM Radio
AR1000/AR1010 is a single chip FM radio receiver IC, which supports full Europe/US/Japan
bands. AR1000/AR1010 integrates on-chip LNA, Mixer, VGA, XO, FM signal processing unit,
serial digital I/O interfaces and regulator. The highest integration level minimizes external
BOM cost and provides optimum sound quality. A RDS/RBDS decoder is also included in
AR1000 to provide broadcasted data.
5.2 Radio Receiver
The Radio Receiver part comprises a LNA, a Low-IF mixer and a VGA. The front-end gain of
the LNA could be adjusted automatically and thus optimize the received signal-to-noise ratio.
The RF signal is then converted to Low-IF band and amplified by the VGA, which is also
automatically adjusted. After then the received signal is fed into the FM signal processing
unit.
Page 9 of 9 CONFIDENTIAL
AR1000 & AR1010 Single Chip FM Radio
An internal reference oscillator is integrated, so only an external 32.768KHz crystal or a
32.768KHz REFCLK signal is required.
5.3 FM signal processing Unit
The main function of the FM signal processing unit includes FM Demodulation, Stereo
Decoding and RDS/RBDS Decoding. The received FM signal at VGA output is first
demodulated into stereo multiplexed signals (Left+Right and Left–Right) and then decoded
into Left and Right signals individually by the stereo decoder. Two time constants (50 or 75µs)
of de-emphasis are provided and programmable through the serial interface.
The decoded stereo signals are output to the LOUT and ROUT pins. The output volume could
be adjusted or mute through the serial interface. The stereo output could be blocked and
only mono signal is output under weak signals.
In AR1000, a RDS/RBDS decoder is also implemented for RDS/RBDS decoding,
synchronization, error detection and error correction.
5.4 Serial I/O interface
Serial 2-wire and 3-wire interfaces are provided to read and write the control registers.
The 2-wire/3-wire bus is selected with BUSMODE pin. 3-wire mode is selected if BUSMODE is
HIGH, and 2-wire mode is selected if BUSMODE is LOW.
Page 10 of 10 CONFIDENTIAL
AR1000 & AR1010 Single Chip FM Radio
CLOCK Frequency 0 400 KHz
TS1 CLOCK Input to DA TA N-edge Setup time (START)600 ns
TH1 CLOCK Input to DATA N-edge Hold time (START)600 ns
TS2 DATA Input to CL OCK P-edge Setup time 100 ns
TH2 DATA Input to CLOCK N-edge Hold time 0 900 ns
TS3 CLOCK Input to DATA P-edge Setup time (STOP) 600 ns
T
STOP to START time 1300 ns
BUF
TOF DATA Output Fall time 20 250 ns
TIR DATA Input & CLOCK Rise time 20 300 ns
TIF DATA Input & CLOCK Fall time 20 300 ns
T
CLOCK HIGH duration 600 ns
HIGH
T
CLOCK LOW duration 1300 ns
LOW
TPS Input Filter Pulse Suppression 50 ns
CLOCK
DATA
CLOCK
DATA
70%
30%
70%
30%
2-Wire Interface Read and Write Timing Parameters
TS1T
STARTSTARTSTOP
T
H1
T
IR
LOW
T
HIGH
T
IR
T
T
S2
H2
T
IF
T
PS
TIFT
T
S3
OF
2-Wire Interface Read and Write Procedure
A6~A0,
R/W
D15~D8D7~D0
T
BUF
START
Page 12 of 12 CONFIDENTIAL
AR1000 & AR1010 Single Chip FM Radio
AR1000/AR1010 could be damaged by any stress in excess of the absolute maximum ratings listed below.
ITEM MIN. MAX.
Power supply voltage (VDDD, VANA) – 0.3V 5.5V
IO port supply voltage (VCCIO) HOST_IO_VCC – 0.3V HOST_IO_VCC + 0.3V
Pin voltage – 0.3V HOST_IO_VCC + 0.3V
Maximum power dissipation - 1W
Operating temperature – 40°C +85°C
Storage temperature – 65°C +150°C
LNA input level - +10 dBm
7.2 DC Electrical Specifications
Recommended operating ambient temperature range TA = -20 to 85°C
Item Symbol Test Condition Min. Typ. Max. Unit
Analog Supply Voltage VANA 2.7 5.5 V
Digital Supply Voltage VDDD 2.7 5.5 V
Interface Supply Voltage VCCIO 1.5 3.6 V
Analog Supply Current IA ENABLE=1 8.5 mA
Analog Power Down Current I
Digital Supply Current / without RDS ID ENABLE=1, rds_en=0 4.5 mA
Digital Supply Current / with RDS
(AR1000 only)
Digital Power Down Current I
Interface Supply Current IIO ENABLE=1 470 µA
Interface Power Down Current I
Digital Input Voltage – High Level VIH 0.7*VCCIO VCCIO+0.3 V
Digital Input Voltage – Low Level VIL - 0.3 0.3*VCCIO V
Digital Input Current – High Level IIH V
Digital Input Current – Low Level IIL V
Interface Output Voltage – High Level VOH I
Interface Output Voltage – Low Level VOL I
Page 13 of 13 CONFIDENTIAL
AR1000 & AR1010 Single Chip FM Radio