Agilent N4903A Data Sheet

New capabilities:

• Integrated and calibrated jitter sources: PJ,SJ, RJ,
BUJ, ISI and sinusoidal interference

• Jitter tolerance compliance testing: PCI Express®,
SATA, Fibre Channel, FB-DIMM, CEI, 10 GbE, XFP/XFI

• Bit recovery mode for analyzing undeterministic
patterns

• SSC generation

• CDR with tunable loop bandwidth for compliant
measurements for all data rates

• Pattern sequencer and capture to simplify the
handling of complex data patterns

• Subrate clock outputs

• Fast total jitter measurement

• All options upgradeable

Automated jitter tolerance
compliance

Automated jitter characterization

Calibrated jitter composition

Integrated into one box

Compliant to latest serial bus
standards

Smartest Characterization
and Compliance

Agilent J-BERT N4903A
High-Performance
Serial BERT with complete
jitter tolerance testing

7 Gb/s and 12.5 Gb/s

Data Sheet

Version 2.2

Includes preliminary specifications

for tunable CDR (option UTR)

2 J-BERT N4903A High-Performance Serial BERT Data Sheet

Serial BERT applications and selection guide

Device Under Test Typical Requirements Recommended Agilent BERT

For R&D and characterization For Manufacturing

Optical Transceivers, i.e.: PRBS N4903A N4906B opt. 012

SONET, SDH, Signal precision
10GbE, Eye masks
XFP/XFI Data rates 10 Gb/s

High-speed serial computer Test pattern sequences N4903A* N4906B
buses, and backplanes, i.e. CDR opt. 012/101/102

PCI Express Gen I and II, Differential inputs
SATA II and III, SAS, Datarates < 7 Gb/s
Infiniband-DDR, CEI
Fibre Channel 4 G/8 G, etc.

0.6 – 2.5 Gb/s transceiver, i.e. Fast bit synchronization N4906B N5980A
E-PON/ G-PON OLTs, Data rates < 3.5 Gb/s opt. 003*
Gigabit Ethernet
Fibre channel 1x/2x
* or ParBERT 81250

N4903A

N4906B

High-Performance Serial BERT
with complete jitter tolerance
testing 7 and 12.5 Gb/s

Serial BERT
3 and 12.5 Gb/s

Agilent’s N4900 Serial BERT series offers
key benefits:

• Excellent precision and sensitivity for accurate
measurements

• Choice of feature set and frequency classes to tailor
to test needs and budget

• Pass/Fail testing

• State-of-the-art user interface with color touch
screen

• Remote control via LAN, USB and GBIB interfaces.
Compatible with existing command set Agilent 71612,
81630A Series, N4900 Series

• Small form factor saves rack or bench space

Agilent Technologies N4900 Series

The newest member of Agilent’s N4900 Serial BERT
series is the powerful J-BERT N4903A High­Performance Serial BERT. It addresses the needs of
R&D and validation teams to characterize serial I/O
ports or ASICs up to 12.5 Gb/s. Integrated and cali­brated jitter sources for jitter tolerance measurements
also allow designers to characterize and prove com­pliance of their receiver’s jitter tolerance.

The J-BERT N4903A High-Performance Serial BERT
is the ideal choice for characterization. It offers fully
integrated and calibrated jitter tolerance tests inte­grated in a high-performance BERT.

The N4906B Serial BERT offers an economic BERT
solution for manufacturing and telecom device test­ing.

Available N4903A configurations:

Speed classes, including built-in CDR:

150 Mb/s to 12.5 Gb/s N4903A-C13
150 Mb/s to 7 Gb/s N4903A-C07

Jitter Tolerance Options:

RJ, PJ, SJ, BUJ injection N4903A-J10
ISI and Sinusoidal N4903A-J20
Interference injection
Compliance suite N4903A-J12
Upgrade to RJ, SJ, PJ, BUJ N4903A-U10
Upgrade to Compliance Suite N4903A-U12
Upgrade to 12.5 Gb/s N4903A-U13
Upgrade to ISI and S.I. N4903A-J20

Pattern Generator Options:

SSC clocking N4903A-J11
(only in combination with–J10)

Error Detector Options:

Bit Recovery Mode N4903A-A01
Upgrade to CDR N4903A-UTR
with tunable loop bandwidth

J-BERT N4903A High-Performance Serial BERT Data Sheet 3

J-BERT key characteristics:

• 150 Mb/s to 7 Gb/s or 12.5 Gb/s – enough margin for

characterizing today’s most popular serial interfaces

• Calibrated and integrated jitter injection (opt. J10). All

in one box: RJ, PJ, BUJ, ISI, sinusoidal interference to
stress the receiver with >50% eye closure

• Automated and compliant jitter tolerance tests covers

popular serial bus standards: PCI Express, SATA, Fibre
Channel, SATA, FB-DIMM, CEI 6G/11G, 10GbE/XAUI,
XFI/XFP

• Delay control input for generator to apply any external

jitter source

• Bit recovery mode to test unknown data traffic

• Pattern sequencer to generate complex training

sequences

• SSC clocking for computer buses

• Subrate clocks to generate reference clocks easily

• Differential I/O for DATA and CLOCK and most

supplementary signals for testing serial interfaces

• Integrated CDR (clock data recovery) to test clock-

less interfaces

• Upgrade option for tunable loop bandwidth CDR

• Highest performance BERT for accurate measurements

• All options retrofitable

J-BERT N4903A High-Performance
Serial BERT

The J-BERT N4903A High-Performance Serial BERT
provides the only complete jitter tolerance test.
It is the ideal choice for R&D and validation teams
characterizing and stressing chips and transceiver
modules that have serial I/O ports up to 7 Gb/s or

12.5 Gb/s. It can characterize a receiver’s jitter tol­erance and prove its compliance to today’s most
popular standards, such as PCI Express, SATA,

Fibre Channel, Fully Buffered DIMM, CEI, 10 GbE/
XAUI, and XFP/XFI.

Accurate characterization is achieved with clean sig-

nals from the pattern generator, which feature excep­tionally l ow jitter and extremely fast transition times.
Test set-up time is reduced significantly, because
the J-BERT N4903A matches most recent serial bus
standards optimally:

• undeterministic patterns can now be analyzed
with th e Bit Recovery Mode.

•A pattern sequencer helps to set up training

sequences quickly, to get complex devices into

loop-back test mode.

• Reference clocks can be provided by the subrate
clock outputs, which can generate any ratio of
clock to data rate.

• All I/Os are differential and a built-in CDR allows
testing of clock-less interfaces.

The J-BERT N4903A is a future-proof Serial BERT
platform, which is configurable for today’s test and
budget requirements but also allows upgrades to all
options and full speed.

Measurements

BER and Measurement suite

• BERT Scan

• Output Timing Jitter

• Spectral Jitter Decomposition

• Eye Contour

• Quick Eye diagram and BER contour

• Fast Eye Mask

• Output Level and Q Factor

• Error Location Capture

• Fast Total Jitter

• Pattern capture

Jitter Tolerance Tests:

• Manual Jitter Composition (opt. J10)

• Automated Jitter Tolerance

• Characterization (opt. J10)

• Automated Jitter Tolerance Compliance (opt. J12)

Applications

• PCI Express

•SATA

• Fibre Channel

• Fully Buffered DIMM

• CEI

• 10 GbE /XAUI

• XFP/XFI

Figure 1: Manual jitter composition. This allows a combination
of jitter types to be injected.

4 J-BERT N4903A High-Performance Serial BERT Data Sheet

Jitter Tolerance Tests

Calibrated Jitter Injection:

• Periodic Jitter (option J10)

• Sinusoidal Jitter (option J10)

• Random Jitter (option J10)

• Bounded Uncorrelated Jitter (option J10)

• Intersymbol Interference (ISI) (option J20)

• Sinusoidal Interference (option J20)

External Jitter Injection:

Using an external source connected to delay
control input.

User Controls

Manual Jitter Composition (option J10)

of PJ, SJ, RJ, BUJ, ISI and Sinusoidal Interference.
This screen allows the user to set up combinations
of jitter types and jitter magnitudes easily. Therefore
a calibrated ‘stressed eye’ with more than 50% eye
closure can be set up for receiver testing. Additional
jitter can be injected with the interfence channel
(Opt. J20). It adds ISI and differential/single mode
noise.

Automated Jitter Tolerance Characterization (option J10)

Automated sweep over SJ frequency based on the
start/stop frequency, steps, accuracy, BER-level, con­fidence level and DUT relax time. The green dots
indicate where the receiver tolerated the injected jit­ter. The red dots show where the BER level was
exceeded. This automated characterization capability
saves significant programming time.

Automated Jitter Tolerance Compliance (option J12)

Automatically tests compliance against a receiver’s
jitter tolerance curve limits specified by a standard
or the user. Most of the popular serial bus standards
define jitter tolerance curves. This option includes a
library of jitter tolerance curves for: SATA, Fibre
Channel, 10 GE/XAUI, CEI 6/11G, and XFI/XFP.
Pass/Fail is shown on a graphical result screen,
which can be saved and printed.

Figure 2: Automated jitter tolerance characterization. The green
circles show where DUT works within the required BER-level.

Figure 3: Result screen of the automated jitter tolerance compli­ance. A library of jitter tolerance curves are available.

J-BERT N4903A High-Performance Serial BERT Data Sheet 5

Figure 5: Spectral jitter decomposition for debugging jitter
sources in a design.

Figure 6: Eye contour with colors indicating BER-level.

Figure 7: BERT Scan incl. Rj/Dj separation, total jitter.

User Interface and Measurement Suite

Quick Eye Diagram

The quick eye diagram allows a one-shot check for a
valid signal. Due to the higher sampling depth of a
BERT, the eye contour lines visualize the measured
eye at a deeper BER level for more accurate results.
Extrapolated eye contour lines display th e eye open­ing for even lower BER levels, such as 10

-15

,
reducing the measurement time significantly. The dis­play shows numerical results for 1-/0-level, eye
amplitude and width, total jitter and more. The
screen can be printed and saved for documenting
test results. (See figure 4)

Spectral Jitter Decomposition

It measures the spectral decomposition of jitter com­ponents. When debugging designs, the jitter decompo­sition simplifies identifying deterministic jitter
sources. (See figure 5)

Eye Contour

The eye opening is a key characteristic of a device.
The BER is displayed as a function of sampling delay
and sampling threshold. Different views are available:
Eye Contour (see Figure 6), pseudo colors and
equal-BER plots.

BERT Scan including RJ/DJ separation

This measurement shows the BER versus the sam­pling point delay, which is displayed as a “bathtub”
curve or as histogram. The measurement results are
displayed in a table with set-up and hold time over
phase margin, total jitter in rms or peak- to-peak,
and random and deterministic jitter. The measure­ment method is equivalent to IEEE 802.3ae. (See fig­ure 7)

Figure 4: Quick eye diagram with BER contour.

Figure 8: Bit recovery mode for analyzing non-deterministic
traffic.

6 J-BERT N4903A High-Performance Serial BERT Data Sheet

Bit Recovery Mode (option A01)

This mode is useful for analyzing non-deterministic
traffic . This is helpful when you need to analyze
real-world traffic, for example in a PCI Express link
where so-called ‘skip ordered sets’ are added unpre­dictably to avoid FIFO overflow. This simplifies set­up by eliminating the need to set up expected data
for the error detector. Two analyzer sampling points
are used to measure a relative BER, which makes
the following measurements possible with relative
BER:

• BERT Scan including RJ/DJ separation

• Output levels and Q-factor

• Eye contour

• Fast eye mask

• Fast Total Jitter

• Spectral jitter decomposition

Automatic Alignment

The J-BERT N4903A High-Performance Serial BERT
is able to align the voltage threshold and the delay
offset of the sampling point automatically, either
simultaneously or separately. It is possible to search
for the 0/1 threshold automatically on command, and
to track the 0/1 threshold continuously.

Fast Total Jitter

Agilent implemented a new measurement technique
for TJ (BER), the Fast Total Jitter Measurement. This
method provides fast and feasible total jitter meas­urements, around 40 times faster than a common
BERT Scan but with comparable confidence level.
Instead of comparing bits until the BER reaches a
defined number of bits or a defined number of
errors, it only compares bits until it can decide with
a 95% confidence level whether the actual BER is
above or below the desired BER.

Figure 9: Auto alignment (Center) simplifies correct
sampling even for stressed eyes.

Figure 10: Fast total jitter measurement for quick and
accurate total jitter measurements.

J-BERT N4903A High-Performance Serial BERT Data Sheet 7

Pattern generator key characteristics:

• Differential outputs for data, clocks and trigger

• Variable output voltages covering LVDS, ECL, CML

• Transitions times <20 ps

• Clean pulses with Jitter < 9 ps pp

• High-precision delay control input to inject jitter from
an external source

• Calibrated and integrated jitter injection
(option J10, J20, both retrofitable)

• Subrate clocks for generating any reference clock

• Pattern sequencing and 32 Mbit pattern

• SSC clocks for computer buses (option J11)

Figure 12: Clean output signal. 10 Gb/s, LVDS levels.

Figure 13: Pattern generator setup screen with graphical dis­play of signal levels.

Table 1: Output characteristics for J-BERT N4903A generator.
All timing parameters are measured at ECL levels

Range of operation 150 Mb/s to 12.5 Gb/s (opt.

C13) Can be programmed up to

13.5 Gb/s.
150 Mb/s to 7 Gb/s (opt. C07)
< 620 MHz only with external
clock.

Frequency accuracy ± 15 ppm typical
Format NRZ, normal or inverted
Amplitude/Resolution 0.10 V to 1.8 V, 5mV steps

Adresses LVDS, CML, PECL,
ECL (terminated to 1.3V/
0 V/-2 V), low voltage CMOS

Output voltage window -- 2.0 V to +3.0 V
Predefined levels ECL, PECL (3.3 V), LVDS, CML
Transition times
(20% to 80%) < 20 ps
(10% to 90%)

2)

< 25 ps

Jitter 9 ps pp typical with disabled jitter

sources

Clock/data delay range ± 0.75 ns in 100 fs steps
External termination -- 2V to +3 V
voltage

3)

Crossing point Adjustable 20% to 80% typical to

emulate duty cycle distortions

Single error inject Adds single errors on demand
Fixed error inject Fixed error ratios of 1 error in

10nbits, n = 3, 4, 5, 6, 7, 8, 9

Interface

1)

Differential or single-ended,
DC coupled, 50Ω

Connector 2.4 mm female

1)

Unused outputs must be terminated with 50Ω to GND.

2)

At 10 Gb/s and 7 Gb/s

3)

For positive termination voltage or termination to GND, exter­nal termination voltage must be less than 3 V below VOH. For
negative termination voltage, external termination voltage must
be less than 2 V below VOH. External termination voltage must
be less than 3 V above VOL.

Figure 11: Generator connectors on front panel.

Data Output (DATA OUT)

Specifications

Pattern Generator Specifications

Table 7: Specifications for the 10 MHz reference output

Amplitude 1V into 50 Ω typical
Interface AC coupled,

50 Ω output impedance

Connector BNC, rear panel

Table 4: Specifications for delay control input

Range --100 ps to +100 ps
Sensitivity 400 ps/V typical
Linearity ± 5 % typical
Modulation 1 GHz typical at 10.8 Gb/s
bandwidth data rate
Levels --250 mV to +250 mV
Interface DC coupled, 50 Ω nominal
Connector SMA female

8 J-BERT N4903A High-Performance Serial BERT Data Sheet

Clock Output (CLK OUT)

Table 2: Clock output characteristics. All timing parameters
are measured at ECL levels
Frequency range 150 MHz to 12.5 GHz (opt. C13)

Can be programmed up to

13.5 GHz
150 MHz to 7 GHz (opt. C07)
<620 MHz only with external
clock

Amplitude/Resolution 0.1 V pp to 1.8 V pp, 5mV steps
Output voltage window -- 2.00 to +2.8V
Transition times
(20% to 80%) < 20 ps
(10% to 90%)

2)

< 25 ps

External termination --2 V to +3 V
voltage

3)

Jitter 1 ps rms typical with disabled

jitter sources

SSB phase noise < --75 dBc with internal

clock source. 10 GHz @ 10
kHz offset, 1 Hz bandwidth

Interface

1)

Differential or single-ended,
DC coupled, 50 Ω output
impedance

Connector 2.4 mm female

1)

Unused outputs must be terminated with 50 Ω to GND.

2)

At 10 Gb/s and 7 Gb/s

3)

For positive termination voltage or termination to GND, exter
nal termination voltage must be less than 3 V below VOH. For
negative termination voltage, external termination voltage
must be less than 2 V below VOH. External termination
voltage must be less than 3 V above VOL.

Table 3: Specifications for clock input and 10 MHz reference
input

Amplitude 200 mV to 2 V
Interface AC coupled, 50 Ω nominal
Connectors Clock input: SMA female,

front panel
10 MHz Reference Input:
BNC, rear panel

Table 5: Specifications for error inject input

Levels TTL compatible
Interface DC coupled, 50 Ω nominal
Connector SMA female

Table 6: Specifications for subrate clock output

Divider factors n = 2,3…128
Levels High: + 0.5 V

Low: -- 0.5 V typical

Transition times 35 ps typical
Interface DC coupled, 50 Ω, differential

or single-ended

Connector SMA female

Clock Input (CLK IN) and 10 MHz Reference Input
(10 MHZ REF IN)
Clock input: uses an external clock as generator clock.

10 MHz Reference input: If a 10 MHz reference clock is

applied, the internal PLL (used to generate the inter­nal clock for the generator) is locked to the applied
signal.

Delay Control Input (DELAY CTRL IN)

The external signal applied to delay control input,
varies the delay between Data Output to Clock
Output. This can be used to generate jittered signals
to stress the device under test in addition to the
calibrated jitter infection from N4903A.

Error Add Input (ERROR ADD)

The external error add input adds a single error to
the data output for each rising edge at the input.

Subrate Clock Output (SUB CLK OUT)

The subrate clock output is used to generate refer­ence clocks, which are subrates of the data rate, for
example , a 100 MHz clock for 2.5 or 5 Gb/s PCI
Express data rate.

10 MHz Reference Output (10 MHZ REF OUT)

J-BERT N4903A High-Performance Serial BERT Data Sheet 9

Table 8: Specifications for trigger output

Pulse width Square wave
Transition times 35 ps typical
Levels High: +0.5V; Low --0.5V typ
Interface DC coupled, 50 Ω nominal,

single ended or differential

Connector SMA female

Table 9: Specifications for auxiliary input

Levels TTL compatible
Interface DC coupled, 50 Ω nominal
Connector SMA female

Table 10: Spread spectrum clocking (SSC) characteristics

Frequency deviation 0 to --0.5%,

2% typical accuracy

Modulation Frequency 28 kHz to 34 kHz
Waveform Triangle
Signals impacted Subrate clock output,

data output, clock output,
trigger output

Patterns

PRBS: 2

n

-1 with n = 7, 10, 11, 15, 23, 31,

and 2

n

with n = 7, 10, 13, 15, 23, 31.

User-definable pattern: 32 Mbit, independent for pattern
generator and error detector.

Generator Pattern Sequencing

The generators pattern sequences can be started on
command or by a signal applied to the auxiliary
input.
Number of blocks: up to 4; the block resolution of user
definable pattern is 512 bits.
Loops: over 4 or fewer blocks. 1 loop level. Loop
counter and infinite .

Alternate Pattern

This allows switching between two patterns of equal
length that have been programmed by the user, each
of which can be up to 16 Mbit. Switching is possible
using a front panel key, over GPIB or by applying
the appropriate signal to the auxiliary input port.
Changeover occurs at the end of the pattern. The
length of the alternating patterns should be a multi­ple of 512 bits. Two methods of controlling pattern
changeover a re available: one-shot and alternate.

Zero substitution

Zeros can be substituted for data to extend the
longest run of zeros in the patterns listed below. The
longest run can be extended to the pattern length-1.
The bit following the substituted zeros is s et to 1.

Variable mark density

The ratio of ones to total bits in the predefined pat­terns listed below can be set to 1/8, 1/4, 1/2, 3/4, or
7/8.

Library of predefined patterns

SONET, SDH, FDDI, Fibre Channel, 10 GbE, K28.5

Trigger Outputs (TRIGGER OUT)

This provides a trigger signal synchronous with the
pattern, for use with an oscilloscope or other test
equipment. Typically there is a delay of 32 ns
between trigger and data output for data rates ≥
620 Mb/s. The trigger output has two modes.
Pattern trigger mode: for PRBS patterns; the pulse is
synchronized with a user specified trigger pattern.
One pulse is generated for every 4th PRBS pattern.
Divided clock mode: the trigger is a square wave with
the frequency of the clock rate divided by 2, 4, 8,
10, 16, 20, 32, 64, and 128.

AUX Input (AUX IN)

When the alternate pattern mode is activated, the
memory is split into two parts, and the user can
define a pattern for each part. Depending on the
operating mode of the auxiliary input, the user can
switch the active pattern in real-time by applying a
pulse (Mode 1) or a logical state (Mode 2) to the
auxiliary input. If the alternate pattern mode is not
activated, the user can suppress the data on the
data output by applying a logical high to the auxil­iary input (Mode 3).

SSC – Spread Spectrum Clocking (option --J11)

The built-in SSC clock modulation source is available
only in combination with option J10.
It generates a frequency modulated clock signal as
used in some computer storage standards to spread
EMI. If spread spectrum clocking is enabled, sinu­soidal jitter is disabled, however all other jitter
sources can be used.

Figure 14: Pattern generator sequencer helps to set up com­plex training sequences

Table 11: Specifications for error detector

Range of operation 150 Mb/s to 12.5 Gb/s

(opt. C13)
150 Mb/s to 7 Gb/s
(opt. C07)

Format NRZ
Maximum input amplitude 2.0 V
Termination voltage

1)

-- 2 V to +3V or off
(true differential mode)

Sensitivity

2)

< 50 mV pp

Intrinsic transition time

4)

25 ps typical 20% to 80%,
single ended

Decision threshold range --2V to +3 V in 1mV steps
Maximum levels --2.2V to +3.2V
Phase margin

3)

1 UI – 12 ps typical

Clock/Data sampling delay ± 0.75 ns in 100 fs steps
Interface Single-ended: 50 Ω nominal,

Differential: 100 Ω nominal

Connector 2.4 mm female

1)

Selectable 2V operating voltage window, which is in the
range between --2.0V to +3.0 V. The data signals, termination
voltage and decision threshold have to be within this voltage
window.

2)

At 10 Gb/s, BER 10

-12

, PRBS 231-1.

3)

Based on the internal clock.

4) At cable input, @ ECL levels

10 J-BERT N4903A High-Performance Serial BERT Data Sheet

Error detector key characteristics:

• True differential inputs to match today’s ports

• Built-in CDR for clock-less data

• Auto-alignment of sampling point

• Bit Recovery Mode for unknown data traffic (opt. AO1)

• Burst Mode for testing recirculation loop

• BER result and Measurement suite

• Quick eye diagram

• Pattern capture

• CDR with tunable loop bandwith (opt. UTR)

Table 12: Specification for the clock input
Frequency range 150 MHz to 12.5 GHz

(option C13)
150 MHz to 7 GHz
(option C07)

Amplitude 100 mV to 1.2 V
Sampling Positive or negative

clock edge

CDR output jitter 0.01 UI rms typical
Clock data recovery (CDR) Loop bandwidth

1)

typical

9.2 Gb/s to 11.32 Gb/s 8 MHz

4.23 Gb/s to 6.40 Gb/s 4 MHz

2.115 Gb/s to 3.20 Gb/s 2 MHz

1.058 Gb/s to 1.6 Gb/s 1 MHz
Interface AC coupled, 50 Ω nominal
Connector SMA female

1)

The CDR works with specified PRBS patterns up to 231-1. The

CDR expects a DC balanced pattern and a transition density of 50%.

Figure 15: Front panel connectors for error detector.

Error Detector Specifications

Please note: Options and capabilities described in ITALIC are
preliminary.

Table 13: Preliminary specifications for CDR with tunable loop
bandwidth (N4903A option UTR)
Data rate range 1 Gb/s to 12.5 Gb/s.

(opt. C13)

1)

1 Gb/s to 7 Gb/s (opt. CO7)

Tunable loop bandwidth 100 kHz to 12 MHz
Compliant CDR settings for PCIe, SATA, FC, FB-DIMM,

CEI, 10 GbE/XAUI, XFP/XFP

Tolerates SSC

1

) With bit recovery mode enabled the max. data rate is 11.5 Gb/s

BER Result Display

The N4903A error detector measures:

1. BER

2. Accumulated BER results

• Accumulated errored O’s and 1’s

• G.821

• Error-free intervals

• Accumulated parameters

• Burst results

3. Eye results

Eye Diagram Result Display

• 1-/0- level

• Eye height/amplitude/width

• Jitter p-p and rms

• Cross voltage

• Signal to noise ratio

• Duty cycle distortion

• Extinction ratio

Data Inputs (DATA IN)

Clock Inputs (CLK IN)

The error detector requires an external clock signal
to sample data or it can recover the clock from the
data signal using the built-in clock data recovery
(CDR).

J-BERT N4903A High-Performance Serial BERT Data Sheet 11

Table 13: Specifications for trigger output

Clock divider 4, 8, 16 up to 11Gb/s

32, 40, 64, 128 up to 12.5 Gb/s

Levels High: +0.5 V typical

Low: -- 0.5 V typical

Minimum pulse width Pattern length x clock period/2

e.g.10 Gb/s with 1000 bits = 50 ns

Interface DC coupled, 50 Ω nominal
Connector SMA female

Table 15: Specifications for the auxiliary output

Amplitude 600 mV typical
Interface AC coupled, 50 Ω nominal
Connector SMA female

Table 16: Specifications for gating input

Burst synchronization time 1536 bits for PRBS

15 kbit for pattern

Backlash 1536 bits in non-CDR mode

1.5 µs in CDR-mode

Gate passive time 2560 bits in non-CDR mode

2560 bits or 1.5 µs whichever
is longer, in CDR-mode

Interface levels TTL levels
Pulse width 256 clock periods
Connector SMA female

Table 14: Specifications for error output

Interface format RZ, active high
Levels High: 1 V typical

Low: 0 V typical

Pulse width 128 clock periods
Interface DC coupled, 50 Ω nominal
Connector SMA female

Trigger Output (TRIG OUT)

Pattern trigger mode

This provides a trigger synchronized with the select­ed error detector reference pattern. In pattern mode
the pulse is synchronized to repetitions of the output
pattern. It generates 1 pulse for every 4th PRBS pat­tern.

Divided clock mode

In divided clock mode, the trigger is a square wave.

Error output (ERR OUT)

This provides a signal to indicate received errors.
The output is the logical 'OR' of errors in a 128 bit
segment of the data.

Auxiliary output (AUX OUT)

This output can be used to provide either clock or
data signals:
Clock: clock signals from the input or the recovered
clock signals in CDR mode.

Data: weighted and sampled data.

Gating Input (GATE IN)

If a logical high is applied to the gating input the
analyzer will ignore the incoming bits during a BER
measurement. The ignored bit sequence is a multiple
of 512 bits. For measuring data in bursts of bits,
rather than a continuous stream of bits, a special
operating mode is used. This is the burst sync mode.
In this case, the signal at the gating input controls
the synchronization and the error counting for each
burst.

This is an important feature for recirculation loop
measurements. If clock data recovery (CDR) is used
to recover the clock from the burst data, the CDR
takes 2 µs from the start of the burst data to settle.
The number of bits needed to synchronize itself dur­ing a burst depends on whether the pattern consists
of hardware based PRBS data or memory based data.
To run p roperly in burst mode the system needs a
backlash of data after the gating input returns to
high. During each burst, the gating input has to
remain passive.

Data Intput

Gate Intput

Burst

CDR Settling Time

Sync. Time

Backlash

Checked Data

Figure 16: Burst mode allows recirculation loop testing

High
Low

Data Input

Gate Input

Pattern Capture

The error detector can capture up to 32 MB data bits
from the device under test. The captured data bits are
displayed in the pattern editor in hex or binary for­mat. The data bits can be used as expected data for
BER testing or can be saved for post processing.

=

Figure 18: Periodic jitter maximum for datarates ≤ 3.375 Gb/s
using the 500 ps delay line

12 J-BERT N4903A High-Performance Serial BERT Data Sheet

Periodic Jitter (option J10)

This injects sinusoidal, rect­angular or triangular jitter over
a wide frequency range.

Table 17: Specifications for periodic jitter (PJ)

Range

1)

0 to 200 ps pp @ all datarates
0 to 500 ps pp @ datarates ≤

3.375 Gb/s

Modulation 1 kHz to 300 MHz sinewave
frequency 1 kHz to 20 MHz triangle

1 kHz to 20 MHz square wave

Modulation frequency 0.5% ± 25 Hz typical
accuracy
Jitter amplitude 10% ± 1ps typical
accuracy
Signals impacted Data outputs-for all datarates

subrate clock outputs-for
datarates ≤ 3.375 Gb/s when
using 500 ps delay line

1)

Available range depends on modulation frequency and data rate

(see figure 17 and 18)

Jitter Tolerance Test Specifications

The built-in jitter sources cover PCI Express, SATA,
Fibre channel, FB-DIMM, CEI 6 G/11 G, 10 GbE
and XFI/XFP jitter tolerance test needs. If jitter
sources are enabled, the intrinsic jitter at the pat­tern generators clock and data ouputs is 1.4 ps rms
typical.

Table 18: Specifications for sinusoidal jitter (SJ)

Range

1)

1000 UI @ 10 kHz
2 UI @ 5 MHz
For frequencies between 10 kHz
and 5 MHz the jitter amplitude

10 MHz
n x f (mod)

Modulation 100 Hz to 5 MHz
frequency (For higher modulation

frequencies see table 17 and 18)

Modulation frequency 0.5% typical
accuracy
Jitter amplitude 2% ± 1ps typical
accuracy
Signals impacted Data and subrate clock outputs.

User selectable: all pattern gener­ator outputs (data, clock, subrate
clock and trigger outputs.)

1)

Available range depends on modulation frequency and data rate
(see figure 19)

Sinusoidal Jitter (option J10)

This injects sinusoidal jitter in
the lower frequency range with
multiple UIs.

Figure 19: Sinusoidal jitter maximum UI

Figure 17: Periodic jitter maximum for all data rates using the 200
ps delay line

UI

Table 20: Specifications for bounded uncorrelated jitter (BUJ)

Range 0 to 200 ps pp @ all datarates
PRBS polynomials 2

n

-1; n = 7, 8, 9, 10, 11, 15, 23, 31

Data rate of PRBS 200 Mb/s to 3.2 Gb/s
generator
Filters 20/50/100/200 MHz lowpass 3rd order
Jitter amplitude 10% ± 1 ps typical for settings shown in
accuracy table 21

Table 21: BUJ accuracy applies for these BUJ calibration settings.

Table 19: Specifications for random jitter (RJ)

J-BERT N4903A High-Performance Serial BERT Data Sheet 13

Random Jitter (option J10)

This injects random jitter with a
high bandwidth and excellent
crest factor.

Range 0 to 14 ps rms
Crestfactor 14 (pp to rms ratio)
Bandwidth 50 kHz to 1 GHz
Filter 10 MHz high-pass,

500 MHz low-pass.
Can be turned on/off individually
to limit jitter bandwidth.

Jitter amplitude 10 % ± 0.2 ps typical
accuracy

BUJ calibration datarate for PRBS filter
setting PRBS generator

CEI 6G 1.1 Gb/s PRBS 2

9

-1 100 MHz
CEI 11G 2 Gb/s PRBS 211-1 200 MHz
Gaussian 2 Gb/s PRBS 231-1 100 MHz

Figure 20: Overview of jitter injection capabilities

Total Jitter

A combination of internally generated PJ, RJ, BUJ
and external jitter (injected using external delay con­trol input) is possible:

For all datarates:

RJ + PJ + BUJ + external delay control input: total
delay variation is 200 ps pp max

For datarate s ≤ 3.375 Gb/s:

A 200 ps delay line or a 500 ps delay line can be
used.
If the 500 ps delay line is used: only PJ or only SJ
or only SSC can be injetced.
Total delay variation for periodic jitter is shown in
figure 17.
Total delay variation is 200 ps max. for RJ + exter­nal delay control input.

Note: Other settings are not calibrated and do not
necessarily generate the desired jitter histograms for
all datarates of the PRBS generator.

Bounded Uncorrelated Jitter (option J10)

This injects a high-probability
jitter using a PRBS generator
and low-p ass filters.

Figure 22: Typical S21parameter for ISI channel of 9 inch length

Table 22: Specifications for intersymbol interference (ISI)

Sinusoidal Interference (option J20)

This adds common mode, differ­ential or single-ended sine wave
signal on top of the data outputs,
to test common mode rejection of

a receiver and to emulate vertical
eye closure. Sinusoidal interference is injected before
the signal passes through the ISI board traces (“near
end”) when using P1 as input. For “far end” injection
P2 has to be used as input.

14 J-BERT N4903A High-Performance Serial BERT Data Sheet

Table 23: Specifications for sinusoidal interference (SI)

Amplitude

1)

0 to 400 mV Common mode, single
ended and differential (differential
amplitude 0 to 800 mV.)

Frequency 10 MHz to 3.2 GHz in 100 kHz steps
Level accuracy ± 10% ± 10 mV typical

1)

The output signal amplitude is reduced by 3 dB when sinusoidal

interference is enabled.

Figure 21: Interference channel connectors

Interference Channel (option J20)

The option J20 is only available in addition to
option J10. It includes semi-rigid cable set to con­nect data outputs to P1 and P1 (N4915A-002).

Interference Channel Input and Output (P1, P2)

User selectable board traces are
switched into the signal path to
emulate a backplane.

Figure 23: Typical ISI (measured in UI) for traces depending on datarate, pattern and trace length.

Trace length 3.5” (minimum), 9” (minimum with

S.I. enabled) 16”, 20”, 24”, 28”, 32”,
36”, 40”, 44” inches of board trace type
Nelco 4000-6. When using in
combination with sinusoidal interfer­ence, minimum trace length is 9 inches.

S

21

parameter See figure 22
Range See figure 23-
Max. input levels -- 5.5 V to +5.5 V
Connectors 2.4 mm, female

J-BERT N4903A High-Performance Serial BERT Data Sheet 15

Mainframe Characteristics

Table 24: General mainframe characteristics

Operating temperature 5°C to 40°C
Storage temperature -- 40°C to +70°C
Operating humidity 95% rel. humidity,

non-condensing

Storage humidity 50% rel. humidity
Power requirements 100 to 240 V, ±10 %,

47 to 63 Hz, 450 VA

Physical dimensions Width: 424.5 mm

Height: 221.5 mm
Depth: 580.0 mm

Weight (net) 26 kg
Weight (shipping) (max) 37.5 kg
Recommended 1 year
re-calibration period
Warranty period 1 year return-to-Agilent.

See order instructions for
extended warranty

Figure 24: Rear panel view

Display

8" color LCD touch screen

Data Entry

• Color touch screen display, numeric keypad with
up/down arrows, dialknob control or external key
board and mouse via USB interface

• Pattern export/import

Hard Disk

For local storage of user patterns and data. An
external disk is also available for using over the USB
interface.

Removable Storage

Floppy Disk Drive 1.44 MB

Remote Control Interfaces

GPIB (IEEE 488), LAN, USB 2.0.
Language: SCPI, IVI.COM. SCPI commmands can be
exported via copy/paste from the Utility Menu/Output
Window

IO Libraries

Agilents IO Libraries suite ships with the N4903A to
help quickly establish an error-free connection
between your PC and instruments regardless of the
vendor.

Other Interfaces

Parallel printer port , 2 x LAN, VGA output, 4 x USB

2.0, 1 x USB 1.1 (front).

Operating System

Microsoft Windows X P Professional

Regulatory Standards

Safety: IEC 61010-1:2001

EN 61010-1:2001
CAN/CSA-C22.2 No.61010-1-04
UL 61010-1:2004

EMC: EN 61326:1997 + A1:1998 + A2:2001

IEC 61326:1997 + A1:1998 + A2:2000

Quality Management: ISO 9004

Specification Assumption

The specifications in this brochure describe the
instrument’s warranted pe rformance. Non-warranted
values are described as typical.
All specifications are valid in a range from 5 °C to
40 °C ambient temperature after a warm-up phase
of 30 minutes. If not otherwise stated, all inputs and
outputs need to be terminated with 5 0 Ω to ground.
All specifications, if not otherwise stated, are valid
using the recommended cable set N4910A (2.4 mm,
24” matched pair).

Order Instructions

J-BERT N4903A High-Performance Serial BERT

Pattern generator & error detector; includes
5x 50 Ω SMA terminations, 6x adapter SMA female to

2.4 mm male, USB cable, commercial calibration
report and certificate (“UK6”), Getting Started Guide,
Agilent I/O library.

Speed classes with built-in CDR:

150 Mb/s to 12.5 Gb/s N4903A-C13
150Mb/s to 7Gb/s N4903A-C07

Pattern Generator Capabilities:

SSC Generation N4903A- J11
(Only with opt. J10)

Analyzer Capabilites:

Bit Recovery Mode N4903A-A01

Jitter Tolerance Options:

RJ, PJ, SJ, BUJ Injection N4903A-J10
Interference Channel N4903A-J20
(Includes short cable kit N4915A-002)
Jitter Tolerance Compliance Suite N4903A-J12
(Only with opt. J10)

Upgrades: N4903AU

To 150 Mb/s to 12.5 Gb/s N4903A-U13
To bit recovery m ode-A01 N4903A-U01
To jitter tolerance-J10 N4903A-U10
(Requires recalibration at Agilent)
To SSC-J11 N4903A-U11
To interference channel-J20 N4903A-J20
To jitter compliance-J12 N4903A-U12
To CDR with tunable N4903A-UTR
loop bandwidth

Warranty:

Extended Warranty R1280A

Calibration:

Calibration Services R1282A
Commercial Calibration (N4903A- UK6)
with test data is always included

Productivity Assistance:

Remote or on-site
Productivity assistance R1380-N49xx

PS-S20 and
PS-S20-02

Recommended accessories:

2.4 mm cable kit N4910A
Rack mount kit N4914A-FG
One 47 ps transition time N4915A-001
converter
One adapter 3.5 mm female N4911A-002
to 2.4mm male
50 Ω terminations, 2.4 mm N4912A
Short cable kit, N4915A-002

2.4 mm to SMA
Clock cable, 2.4mm to SMA N4915A-003

16 J-BERT N4903A High-Performance Serial BERT Data Sheet

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© Agilent Technologies, Inc. 2006
Printed in USA, 31 May 2006

5989-2899EN

If you would like to learn more about jitter, please visit our website:

www.agilent.com/find/jittermaster

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