Agilent MGA-83563 DATA SHEET
Agilent MGA-83563
Description
Agilent’s MGA-83563 is an easyto-use GaAs RFIC amplifier that
offers excellent power output and
efficiency. This part is targeted
for 3V applications where constant-envelope modulation is
used. The output of the amplifier
is matched internally to 50Ω.
However, an external match can
be added for maximum efficiency
and power out (PAE = 37%, Po =
22 dBm). The input is easily
matched to 50 Ω.
Due to the high power output of
this device, it is recommended for
use under a specific set of
operating conditions. The thermal
sections of the Applications
Information explain this in detail.
The circuit uses state-of-the-art
PHEMT technology with proven
reliability. On-chip bias circuitry
allows operation from single
supply voltage.
+22 dBm P
3V Power Amplifier
SAT
for 0.5 – 6 GHz Applications
Data Sheet
Features
• Lead-free Option Available
at 2.4 GHz,
SAT
at 2.4 GHz,
SAT
Attention:
Observe precautions for
handling electrostatic
sensitive devices.
Surface Mount Package
SOT-363 (SC-70)
Pin Connections and
Package Marking
V
16
d1
GND
INPUT
Note:
Package marking provides orientation
and identification; “x” is date code.
83x
25
34
OUTPUT
and V
GND
GND
Equivalent Circuit
(Simplified)
• +22 dBm P
3.0 V
+23 dBm P
3.6 V
• 22 dB Small Signal Gain at
2.4 GHz
• Wide Frequency Range 0.5
to 6 GHz
• Single 3 V Supply
• 37% Power Added
Efficiency
• Ultra Miniature Package
d2
Applications
• Amplifier for Driver and
Output Applications
ESD Machine Model (Class A)
ESD Human Body Model (Class 0)
Refer to Agilent Application Note A004R:
Electrostatic Discharge Damage and Control.
V
INPUT
OUTPUT
and V
d1
BIAS
BIAS
d2
GROUND
MGA-83563 Absolute Maximum Ratings
Absolute
Symbol Parameter Units Maximum
V Maximum DC Supply Voltage V 4
P
in
T
ch
T
STG
800
700
(mW)
600
500
400
300
200
100
POWER DISSIPATED AS HEAT
Pd = (VOLTAGE) x (CURRENT) – (Pout)
0
10 30 50 70 90 150110
Temperature/ Power Derating Curve.
CW RF Input Power dBm +13
Channel Temperature °C 165
Storage Temperature °C -65 to 150
1 x 10
6
Hrs MTTF
130
CASE TEMPERATURE (°C)
[1]
2
Thermal Resistance
θ
Notes:
1. Operation of this device above any one
of these limits may cause permanent
damage.
= 25°C (TC is defined to be the
2. T
C
temperature at the package pins where
contact is made to the circuit board).
ch to c
= 175°C/W
[2]
:
3.0V
2.2 nH 18 nH20 pF
83
RF
1.2 nH
INPUT
Figure 1. MGA-83563 Final Production Test Circuit.
V
d
L120 pF
83
Tuner
RF
INPUT
Circuit A: L1 = 2.2 nH for 0.1 to 3 GHz
Circuit B: L1 = 0 nH (capacitor as close as possible) for 3 to 6 GHz
Figure 2. MGA-83563 Test Circuit for Characterization.
Tuner
1 pF
50 pF
Bias
Tee
RF
OUTPUT
RF
OUTPUT
3
MGA-83563 Electrical Specifications,
Vd = 3 V, TC = 25°C, using test circuit of Figure 2, unless noted.
Std.
Symbol Parameters and Test Conditions Units Min. Typ. Max. Dev.
P
SAT
Saturated Output Power
PAE Power Added Efficiency
I
d
Device Current
[3,5]
[3]
[3]
f = 2.4 GHz dBm 20.5 22.4 0.75
f = 2.4 GHz % 25 37 2.5
mA 152 200 12.4
[4]
Gain Small Signal Gain f = 0.9 GHz dB 20
f = 1.5 GHz 22
f = 2.0 GHz 23
f = 2.4 GHz 22
f = 4.0 GHz 22
f = 5.0 GHz 19
f = 6.0 GHz 17
P
SAT
Saturated Output Power f = 0.9 GHz dBm 20.9
f = 1.5 GHz 21.7
f = 2.0 GHz 21.8
f = 2.4 GHz 22
f = 4.0 GHz 21.9
f = 5.0 GHz 19.7
f = 6.0 GHz 18.2
PAE Power Added Efficiency f = 0.9 GHz % 41
f = 1.5 GHz 41
f = 2.0 GHz 40
f = 2.4 GHz 37
f = 4.0 GHz 32
f = 5.0 GHz 18
f = 6.0 GHz 14
P
1 dB
Output Power at 1 dB Gain Compression
[5]
f = 0.9 GHz dBm 19.1
f = 1.5 GHz 19.7
f = 2.0 GHz 19.7
f = 2.4 GHz 19.2
f = 4.0 GHz 18.1
f = 5.0 GHz 16
f = 6.0 GHz 15
VSWR
Input VSWR into 50 Ω
in
Circuit A f = 0.9 to 1.7 GHz 3.5
= 1.8 to 3.0 GHz 2.6
f
Circuit B f = 3.0 to 6.0 GHz 2.3
VSWR
Output VSWR into 50 Ω
out
Circuit A f = 0.9 to 2.0 GHz 1.4
= 2.0 to 3.0 GHz 2.5
f
Circuit B f = 3.0 to 4.0 GHz 3.5
f = 4.0 to 6.0 GHz 4.5
ISOL Isolation f = 0.9 to 3.0 GHz dB -38
f = 3.0 to 6.0 GHz -30
IP
3
Third Order Intercept Point f = 0.9 GHz to 6.0 GHz dBm 29
Notes:
3. Measured using the final test circuit of Figure 1 with an input power of +4 dBm.
4. Standard Deviation number is based on measurement of at least 500 parts from three non-consecutive wafer lots during
the initial characterization of this product, and is intended to be used as an estimate for distribution of the typical
specification.
5. For linear operation, refer to thermal sections in the Applications section of this data sheet.
4
MGA-83563 Typical Performance,
26
24
22
20
(dB)
18
GAIN
16
14
3.3V
12
3.0V
2.7V
10
012 3 4 65
FREQUENCY (GHz)
Figure 3. Tuned Gain vs. Frequency
and Voltage.
26
24
22
20
(dB)
18
GAIN
16
14
-40°C
12
+25°C
+85°C
10
012 3 4 65
FREQUENCY (GHz)
Figure 6. Gain vs. Frequency and
Temperature.
24
22
20
(dBm)
1dB
18
P
2.7V
16
3.0V
3.3V
3.6V
14
012 3 4 65
Figure 4. Output Power at 1 dB
Compression vs. Frequency and Voltage.
24
22
(dBm)
20
18
OUTPUT POWER
16
14
012 3 4 65
Figure 7. Saturated Output Power
(+4 dBm in) vs. Frequency and
Temperature.
Vd = 3 V, TC = 25°C, using test circuit of Figure 2, unless noted.
24
22
20
(dBm)
SAT
18
P
2.7V
16
3.0V
3.3V
3.6V
14
012 3 4 65
FREQUENCY (GHz)
-40°C
+25°C
+85°C
FREQUENCY (GHz)
Figure 5. Saturated Output Power
(+4 dBm in) vs. Frequency and Voltage
12
10
(dB)
8
6
NOISE FIGURE
4
2
012 3 4 65
Figure 8. Noise Figure vs. Frequency
and Temperature.
FREQUENCY (GHz)
-40°C
+25°C
+85°C
FREQUENCY (GHz)
.
10
8
6
VSWR
INPUT
4
2
OUTPUT
0
012 3 4 65
FREQUENCY (GHz)
Figure 9. Input and Output VSWR
vs. Frequency.
200
180
160
(mA)
d
140
120
100
80
60
40
DEVICE CURRENT, I
-40°C
+25°C
20
+85°C
0
012 43
FREQUENCY (GHz)
Figure 10. Supply Current vs. Voltage
and Temperature. Pin = -27 dBm.
190
I
d
170
(mA)
d
150
130
110
DEVICE CURRENT, I
90
-14 -10 -6 -2 2 6
INPUT POWER (dBm) @ 2.4 GHz
PAE
50
40
30
20
10
0
Figure 11. Device Current and Power
Added Efficiency vs. Input Power.
Note: Figure 1 test circuit.
PAE (%)
5
MGA-83563 Typical Performance,
continued
Vd = 3 V, TC = 25°C, using test circuit of Figure 2, unless noted.
24
2.7V
3.0V
22
3.3V
3.6V
20
(dBm)
18
16
14
OUTPUT POWER
12
10
-10 -8 -6 -2
INPUT POWER (dBm) @ 2.4 GHz
-4 2064
Figure 12. Output Power vs. Input
Power and Voltage.
Note: Figure 1 test circuit.
-20
-25
-30
(dB)
-35
33
2.7V
3.0V
32
3.3V
(dBm)
3.6V
31
30
29
28
27
26
THIRD ORDER INTERCEPT
25
-14 -10 -6
INPUT POWER (dBm) @ 2.4 GHz
-2 62
Figure 13. Third Order Intercept
vs. Input Power and Voltage.
Note: Figure 1 test circuit.
50
45
40
(dBm)
3
35
30
PAE (%) and IP
25
20
012 3 4 65
FREQUENCY (GHz)
Figure 14. Power Added Efficiency
and Third Order Intercept vs.
Frequency (V
= 3.6 V).
d
-40
ISOLATION
-45
-50
012 3 4 65
FREQUENCY (GHz)
Figure 15. Isolation vs. Frequency.
6
MGA-83563 Test Circuit
Typical s-parameters are shown
below for various inductor values
(L). Those marked “Sim” are
simulated and those marked
“Meas” are measured using an
frequency before designing an
input, output, or power matching
structure.
V
d
L
50 pF
ICM (Intercontinental Microwave) fixture. Figure 17 shows
IN
the available gain for each L
value. The user should first select
the L value for the application
Figure 16. S-parameter Test Circuit.
s-parameter reference plane
Table 1.
MGA-83563 Typical Scattering Parameters
83
[1]
Bias
Tee
OUT
26
18 nH
24
22
20
(dB)
18
GAIN
16
14
12
10
Figure 17. Available Gain (G
Frequency for the MGA-83563 Amplifier
over Various Inductance Values.
8.2 nH
4.7 nH
2.2 nH
1.2 nH
0 nH
012 3 4 65
FREQUENCY (GHz)
max
TC = 25°C, Vd = 3.0 V, Id = 165 mA, CW Operation, Pin = -27 dBm
Freq. RLin S
11
|S21|2 S
21
Gain S
12
RL
out
S
22
Gmax
L GHz dB Mag Ang Gain Mag Ang dB Mag Ang dB Mag Ang K dB
Sim 18.0 nH 0.6 -4.6 0.59 -48 23.9 15.61 43 -46.7 0.005 105 -21.1 0.09 150 4.47 25.8
Sim 18.0 nH 0.8 -9.6 0.33 -57 24.6 16.96 6 -39.0 0.011 102 -16.8 0.15 -130 2.37 25.2
Sim 18.0 nH 1.0 -16.0 0.16 -27 24.1 16.02 -25 -35.5 0.017 87 -10.1 0.31 -146 1.80 24.6
Sim 18.0 nH 1.4 -10.1 0.31 22 21.7 12.22 -68 -32.8 0.023 66 -5.8 0.51 177 1.48 23.5
Sim 18.0 nH 1.8 -7.3 0.43 17 19.1 9.03 -97 -31.7 0.026 54 -4.4 0.61 150 1.45 22.0
Sim 8.2 nH 0.8 -4.1 0.63 -36 21.2 11.52 48 -47.4 0.004 95 -17.2 0.14 121 6.01 23.5
Sim 8.2 nH 1.0 -5.8 0.51 -45 22.7 13.65 22 -41.1 0.009 111 -35.2 0.02 130 3.13 24.0
Sim 8.2 nH 1.4 -13.0 0.22 -45 23.7 15.30 -27 -33.7 0.021 94 -10.4 0.30 -139 1.54 24.3
Sim 8.2 nH 1.8 -13.0 0.22 13 22.4 13.15 -68 -30.9 0.029 74 -5.5 0.53 -179 1.21 24.1
Sim 8.2 nH 2.0 -10.7 0.29 18 21.3 11.65 -84 -30.3 0.031 67 -4.4 0.60 166 1.16 23.7
Sim 8.2 nH 2.4 -8.2 0.39 15 19.1 8.98 -111 -29.5 0.034 57 -3.4 0.68 141 1.14 22.5
Sim 4.7 nH 1.4 -6.7 0.46 -44 22.1 12.72 4 -37.6 0.013 109 -26.7 0.05 -78 2.44 23.1
Sim 4.7 nH 1.8 -12.0 0.25 -43 22.9 13.99 -37 -32.3 0.024 94 -9.9 0.32 -143 1.44 23.7
Sim 4.7 nH 2.0 -14.3 0.19 -23 22.6 13.53 -57 -30.8 0.029 85 -7.1 0.44 -164 1.26 23.7
Sim 4.7 nH 2.4 -11.9 0.26 10 21.1 11.36 -90 -29.2 0.035 70 -4.3 0.61 163 1.09 23.4
Sim 4.7 nH 2.8 -9.4 0.34 12 19.1 9.03 -115 -28.3 0.038 61 -3.2 0.69 138 1.05 22.5
Meas 2.2 nH 1.8 -6.3 0.49 -53 21.5 11.92 -23 -37.2 0.014 90 -15.1 0.18 -100 2.40 22.8
Meas 2.2 nH 2.0 -7.4 0.43 -51 21.9 12.48 -45 -34.8 0.018 85 -9.7 0.33 -130 1.82 23.3
Meas 2.2 nH 2.4 -7.9 0.40 -36 20.9 11.07 -82 -32.4 0.024 68 -6.2 0.49 -175 1.52 22.8
Meas 2.2 nH 2.8 -7.1 0.44 -27 19.0 8.93 -113 -31.2 0.027 56 -4.1 0.63 150 1.40 22.1
Meas 2.2 nH 3.0 -6.6 0.47 -25 18.0 7.90 -123 -31.0 0.028 52 -4.1 0.62 138 1.48 21.1
Sim 1.2 nH 2.4 -7.9 0.40 -41 20.5 10.61 -36 -33.4 0.021 97 -18.0 0.13 -120 1.98 21.3
Sim 1.2 nH 2.8 -10.8 0.29 -37 20.7 10.90 -67 -30.4 0.030 88 -9.6 0.33 -168 1.47 21.6
Sim 1.2 nH 3.0 -11.9 0.25 -29 20.5 10.56 -82 -29.4 0.034 82 -7.4 0.43 176 1.34 21.6
Sim 1.2 nH 3.2 -12.3 0.24 -20 20.0 9.97 -95 -28.6 0.037 76 -5.9 0.51 161 1.24 21.5
Sim 1.2 nH 3.6 -11.7 0.26 -7 18.6 8.49 -120 -27.5 0.042 67 -4.1 0.62 137 1.14 21.0
Meas 0.0 nH 3.0 -5.6 0.53 -33 17.9 7.87 -13 -39.1 0.011 109 -12.8 0.23 -7 4.07 19.6
Meas 0.0 nH 3.4 -4.7 0.58 -31 20.1 10.13 -43 -34.1 0.020 107 -7.9 0.40 -73 1.72 22.7
Meas 0.0 nH 3.8 -5.5 0.53 -50 20.0 9.95 -81 -31.7 0.026 94 -6.2 0.49 -132 1.43 22.6
Meas 0.0 nH 4.0 -7.4 0.43 -52 19.4 9.28 -94 -30.9 0.028 93 -4.5 0.60 -148 1.38 22.1
Meas 0.0 nH 4.2 -8.4 0.38 -48 18.7 8.62 -106 -30.2 0.031 91 -3.5 0.67 -163 1.27 21.9
Meas 0.0 nH 4.6 -9.0 0.36 -44 17.0 7.08 -129 -28.8 0.036 84 -3.1 0.70 173 1.25 20.5
Meas 0.0 nH 5.0 -9.2 0.35 -39 15.4 5.87 -145 -27.9 0.040 78 -3.0 0.71 155 1.29 19.0
Meas 0.0 nH 5.4 -9.7 0.33 -32 13.8 4.88 -159 -27.2 0.044 77 -3.0 0.71 140 1.38 17.3
Meas 0.0 nH 5.8 -7.8 0.41 -29 12.4 4.16 -170 -25.9 0.051 73 -3.6 0.66 127 1.47 15.7
Meas 0.0 nH 6.0 -6.6 0.47 -46 12.1 4.03 177 -24.9 0.057 64 -3.3 0.68 123 1.33 15.9
Note:
1. Reference plane per Figure 43 in Applications Information section.
) vs.
7
RF
Input
RF
Input
RFC
V
d
3
L2
1
6
MGA-83563 Applications
Information
The MGA-83563 is two-stage,
medium power GaAs RFIC
amplifier designed to be used for
driver and output stages in
MGA-83563 for linear applications
at reduced power levels is
discussed in the “Thermal Design
for Reliability” and “Use of the
MGA-83563 for Linear Applications” in this applications note.
transmitter applications operating
within the 500 MHz to 6 GHz
frequency range.
This device is designed for
operation in the saturated mode
where it delivers a typical output
power of +22 dBm (158 mW) with
a power-added efficiency of 37%.
The MGA-83563 has a large signal
gain of 18 dB requiring an input
signal level of only +4 dBm to
drive it well into saturation. The
high output power and high
efficiency of the MGA-83563,
combined with +3-volt operation
and subminiature packaging,
make this device especially useful
for battery-powered, personal
communication applications such
as wireless data, cellular phones,
and PCS.
The upper end of the frequency
range of the MGA-83563 extends
Application Guidelines
The use of the MGA-83563 is very
straightforward. The on-chip,
partial RF impedance matching
and integrated bias control circuit
simplify the task of using this
device.
The design steps consist of (1)
selecting an interstage inductor
from the data provided, (2)
adding provision for bringing in
the DC bias, and (3) designing
and optimizing an output impedance match for the particular
frequency band of interest. The
input is already well matched to
50 ohms for most frequencies and
in many cases no additional input
matching will be necessary.
Each of the three design steps for
using the MGA-83563 will now be
discussed in greater detail.
Figure 18. Interstage Inductor L2 and
Bias Current.
The values for inductor L2 are
somewhat dependent on the
specific printed circuit board
material, thickness, and RF layout
that are used. The inductor values
shown in Figure 19 have been
created for the PCB and RF
layout that is used for the circuit
examples presented in this
application note. The methodology that was used to determine
the optimum values for L2 and for
creating Figure 19 is presented in
the Appendix. If the user’s PCB
and/or layout differ significantly
from the example circuits, refer
to the Appendix for a description
of how to determine the values of
L2 for any arbitrary frequency,
PCB material, or RF layout.
to 6 GHz making it a useful
solution for medium power
amplifiers in wireless communications products such as 5.7 GHz
spread spectrum or other ISM/
license-free band applications.
Internal capacitors on the RFIC
chip limit the low-end frequency
response to applications above
approximately 500 MHz.
The thermal limitations of the
subminiature SOT-363 (SC-70)
package generally restrict the use
of the MGA-83563 to applications
that use constant envelope types
of modulation. These types of
systems are able to take full
advantage of the MGA-83563’s
high efficiency, saturated mode of
operation. The use of the
Step 1 — Selecting the
Interstage Inductor
The drain of the first stage FET of
this two-stage RFIC amplifier is
connected to package Pin 1. The
supply voltage Vd is connected to
this drain through an inductor,
L2, as shown in Figure 18. The
supply end of the inductor is
bypassed to ground.
This interstage inductor serves
the purpose of completing the
impedance match between the
first and second stages. The value
of inductor L2 depends on the
particular frequency for which
the MGA-83563 is to be used and
is chosen from the look-up graph
in Figure 19.
Step 2 — Bias Connections
The MGA-83563 is a voltage-
biased device and operates from
a single, positive power supply.
The supply voltage, typically
+3-volts, must be applied to the
drains of both stages of the RFIC
amplifier. The connection to the
first stage drain is made through
the interstage inductor, L2, as
described in the previous step.
The supply voltage is applied to
the second stage drain through
Pin 6, which is also the RF Output
connection. Referring to
Figure 18, an inductor (RFC) is
used to separate the RF output
signal from the DC supply. The
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