HP 8110A pulse generator
Multi-channel product Note
Test Signals for Multi-Input Digital Devices
============================================
___ ___ ___
___| |___| |___| |___ Multi-phase clocks
___ ___ ___
___| |___| |___| |_
___ ___ ___
___| |___| |___|
___ ___ _
__| |___| |___|
0010110000100111100101000000 Parallel data
0111111011001010011011111111
1100000001111000001111100100
____
_| | _ | |_ | |_| |_
__| |_| |__| |_| | 3- and 4-levels
_|_ ___ |___
___| |___|_| | |___| |___ Glitch simulation
=============================================
Foreword
Compact, convenient, flexible
Designed for characterizing digital circuits in the lab and
in the automatic test environment, the HP 8110A pulse generator
has extensive functionality and high parametric performance.
Its small size and weight pair well with HP's oscilloscopes so
that a powerful stimulus-response tool can be applied rapidly
to new problems as they occur.
Through master-slaving, multi-input devices can be stimulated
with signals that match the real environment. Low per-channel
volume, easy hook-up to systems, and the ability to compensate
for skews introduced by test heads and cables, are some of the
attributes that make this approach practical and economic.
Applications
CAD emulation can only go so far; thorough characterization
under realistic conditions is needed before you can proceed with
confidence through the product cycle. For these measurements,
repeatable signals are needed that are accurate models of the
real ones. This means not only simulating the necessary clocks,
control impulses and two- or multi-level data streams, but also
the effects of crosstalk, ground-bounce and distortion.
The same HP 8110A master-slave setup will generate any of
these signal types, even a mix of them. In the case of data, a
few extra initialization steps are needed to ensure frame
synchronization, but the hardware and connections remain the
same. This document therefore focuses on multi-channel clock
and pulse applications on the one hand, and multi-channel data
applications on the other. It is hoped that this results in a
good overview of the possibilities without going into detail of
all possible signal mixes.
Contents
Part
Multiple clocks and pulse sequences............ 4
Multi-channel digital signals.................. 5
Some application tips.......................... 6
Appendices:
A: HP 8110A modules ....................... 7
B: Connections and accessories............. 8
C: HP 8110A timing ranges................. 9
D: Automatic synchronization............... 10
Part 4: Multi-phase clocks
---------------------------
An HP 8110A master-slave setup generates accurate clock
signals and can also simulate "real life" clocks where phase
and duty cycle have been corrupted through the clock
distribution path.
The same setup can also generate parallel pulse sequences
(and data, too, but this is described later).
It's easy to set up phase, duty cycle and squareness of
clock signals because these period-dependent parameters can be
set up directly. On the other hand, when time intervals are
required, a keystroke changes the display to delay and width
(or leading edge and trailing edge delays, as required by the
application).
In reality, the signals may well be subject to ground-bounce,
ringing and crosstalk. To help understand these problems early
in design, the HP8110A lets you simulate these effects before
hardware is completed. This is possible because you can set up
an interferance pulse in one channel and combine it internally
with a clean waveform in the other. An application of this kind,
with say 4 clock phases, two of which with simulated distortion,
would be met by a setup with 2 slaves and just 12 inches height.
With the appropriate number of HP 8110As connected as shown
in Appendix B, set the instruments as follows:
Master
- Recall the default settings.
- Set a deskew delay of 26 ns in both channels (this is
the typical value of slave propagation delay).
Slave(s)
- Recall the default settings.
- TRG-MODE page: set pulse period to "ext CLK-IN",
"leading edge".
- TRG-LEV page: change default value of "CLK-IN:
threshold" as follows:
- One slave: 1.2 V.
- Two slaves: 0.6 V.
- Three slaves: 0.6 V for the slave via one splitter,
0.3 V when via two splitters.
- Four slaves: 0.3 V.
If deskew at the device-under-test is an important
consideration, connect the HP 8110A outputs to an oscilloscope
with the cables you would normally use with the device. Use a
slave trigger output to trigger the oscilloscope. Set the master
to a fairly low frequency to avoid pulse-position ambiguity, and
adjust master and slave delays to "tune out" the skews.
For continuous sequences of higher stability, you can use the
master's internal PLL, or External Clock input, instead of the
internal oscillator. All that now has to be done is to set the
required parameters and enable the outputs. Frequency* (and
any other parameters) can now be adjusted any time as needed.
* Frequency and other timing parameters: A glitch may occur
when crossing a boundary from one range to another.
Synchronization is not impaired. A list of ranges is given
in Appendix C so that boundary glitches can be avoided .
Triggered signals, such as clock bursts can be generated by
setting the master to one of the following:
- Gated pulses
Pulse period: VCO or PLL.
Gate source: Ext Input
- Triggered burst
Pulse period: VCO.
Trigger source: Ext Input or PLL
or:
Pulse period: PLL.
Trigger source: Ext Input.
In a triggered mode, the slave(s) must be switched to "Meas
Once" to avoid a false measurement. Use this procedure to
initialize:
- Master: set to Continuous mode.
- Slave: go to TIMING page and, with "Per" ( or "Freq") value
highlighted, select "Meas Once" in the MODIFY panel. Now
press Enter to measure the frequency.
- Return the master to the required mode.
If the clock frequency of a triggered sequence is to be adjusted
during a measurement, remember that the timing parameters (even
if set in terms of phase or % of period) will NOT change with
frequency because of the need to operate in "Meas Once" mode.
Part 5: Multi-channel digital signals
-------------------------------------Digital devices all need "data" of some kind to be tested
realistically. Requirements in practice will be manifold: chip
control signals, device-triggered sequences, parallel data, RZ
or NRZ formats, and 3- or 4-level codes.
The kind of measurement (for example: pattern compare,
state or timing analysis, eye-pattern or BER) will also
influence the stimulus requirements. These are addressed by the
following
HP 8110A capabilities:
- a pattern mode with an editor that includes prbs,
- internal or external starting and clocking,
- channel addition for multi-level communications codes, plus
timing and level capabilities available in all modes.
As an example, consider an 8-bit MUX with chip select and
reset inputs. An HP 8110A master with three slaves can
stimulate not only the eight data lines but also -thanks to the
strobe channels- the control lines as well.
With the appropriate number of HP 8110As connected as
shown in Appendix B, set the instruments as follows:
Master
- Recall the default settings.
- Set a deskew delay of 26 ns in both channels (this is
the typical value of slave propagation delay).
Slave(s)
- Recall the default settings.
- TRG-MODE page: set pulse period to "ext CLK-IN",
"leading edge".
- TRG-LEV page: change default value of "CLK-IN:
threshold" as follows:
- One slave: 1.2 V.
- Two slaves: 0.6 V.
- Three slaves: 0.6 V via one splitter,
0.3 V via two splitters.
- Four slaves: 0.3 V.
If deskew at the device-under-test is an important consideration, connect the HP 8110A outputs to an oscilloscope with the
cables you would normally use with the device. Use a slave
trigger output to trigger the oscilloscope. Set the master to a
fairly low frequency to avoid pulse-position ambiguity, and
adjust master and slave delays to "tune out" the skews.
Continuous Sequences
To set up the sequences, proceed as follows:
1. Set master and slaves to Continuous Pattern mode
2. Select the format (RZ or NRZ) needed in each channel.
3. Set all HP 8110As to the same pattern length.
4. Enter the data required.
5. Set timing and output values as required.
6. Synchronize as shown in Table 1.
Table 1: Data generator synchronization
______________________________________________________________
| |
|-Set master to "Triggered Pattern" and "Trg'd by: MAN key" |
| (the object of this is to stop the master so that no clock |
| pulses get to the slaves during this synchronization). |
|-Set the master to Burst mode, then back to Triggered |
| Pattern mode. |
|-Set the slave(s) to Burst mode, then back to Pattern mode |
| (this and the previous step clears all the address counters |
| so that all channels will start at bit 1 on the first clock).|
|-Enable all outputs. |
|-Set the master to the required mode: |
| -"Continuous Pattern" |
| or "Triggered Pattern" / "Trg'd by: PLL" |
| or "Triggered Pattern" / "Trg'd by: EXT-IN" |
|______________________________________________________________|
For continuous sequences of higher stability, you can use the
master's internal PLL, or External Clock input, instead of the
internal oscillator.
Triggered Sequences
As implied by the last step of Table 1, externally or
internally (PLL)-triggered patterns are also feasible. In the
case of externally-triggered patterns, the PLL can be used as
the period source for higher accuracy. Here, two important
conditions must be observed:
Loading...