Agilent 16800 Series
Portable Logic Analyzers
Data Sheet
Quickly debug, validate,
and optimize your digital
system – at a price that
fits your budget.
Features and benefits
• 250 ps resolution (4 GHz) timing
zoom to find elusive timing problems
quickly, without double probing
• 15” display, with available touch
screen, allows you to see more data
and navigate quickly
• View Scope – time-correlated
measurements and displays of your
logic analyzer and oscilloscope data
let you effectively track down
problems across the analog and
digital portions of your design
• Eight models with
34/68/102/136/204 channels,
up to 32 M memory depth and
models with a pattern generator
provide the measurement flexibility
for any budget
• Application support for every aspect
of today’s complex designs – FPGA
dynamic probe, digital VSA (vector
signal analysis) and broad processor
and bus support
Table of Contents
Selection Guide for 16800 Series Portable Logic Analyzers . . . . . . . . . . . . . . . . . . . . . . . . 2
Logic Analysis for Tracking Real-time System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Agilent 16800 Series Logic Analyzer Specifications and Characteristics . . . . . . . . . . . . 5
A Built-in Pattern Generator Gives You Digital Stimulus and Response in a
Single Instrument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pattern Generator Specifications and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Unleash the Complementary Power of a Logic Analyzer and an Oscilloscope . . . . . . . 23
Get Instant Insights into your Design with Multiple Views and Analysis Tools . . . . . . 24
16800 Series Instrument Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16800 Series Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
16800 Series Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
16800 Series Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Support, Services, and Assistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2
Selection Guide for 16800 Series Portable Logic Analyzers
Agilent Model Number 16821A, 16822A, 16823A
Half Channel Full Channel
Maximum clock 300 MHz 180 MHz
Data channels 24 48
Memory depth in vectors 16 M 8 M
Logic levels supported 5 V TTL, 3-state TTL, 3-state TTL/CMOS,
3-state 1.8 V, 3-state 2.5 V, 3-state 3.3 V, ECL,
5 V PECL, 3.3 V LVPECL, LVDS
Models with a built-in pattern generator give you more
measurement flexibility
16801A, 16802A, 16803A, 16804A 16806A
Agilent Model Number 16821A
1
16822A
1
16823A
1
Logic analyzer channels 34 68 102 136 204
Pattern generator channels
1
48 48 48 N/A N/A
High-speed timing zoom 4 GHz (250 ps) with 4 GHz (250 ps) with 64 K depth
64 K depth
Maximum timing sample rate 1.0 GHz (1.0 ns) / 1.0 GHz (1.0 ns) / 500 MHz (2.0 ns)
(Half/full ch) 500 MHz (2.0 ns)
Maximum state clock rate 250 MHz with 450 MHz with option 500
option 250 250 MHz with option 250
Maximum state data rate 250 Mb/s with 500 Mb/s with option 500
option 250 250 Mb/s with option 250
Maximum memory depth 1 M with option 001 1 M with option 001
4 M with option 004 4 M with option 004
16 M with option 016 16 M with option 016
32 M with option 032 32 M with option 032
Supported signal types Single-ended Single-ended
Automated threshold/sample position Ye s Ye s
Simultaneous eye diagrams, all channels
Probe compatibility 40-pin cable connector 40-pin cable connector
1 Pattern generator available with 16821A, 16822A and 16823A.
Choose from eight models to get the measurement capability for your specific application
Probes are ordered separately. Please
specify probes when ordering to ensure
the correct connection between your
logic analyzer, pattern generator, and
the device under test.
3
Logic Analysis for Tracking Real-time System Operation
Agilent 16800 Series portable logic
analyzers offer the performance,
applications, and usability your
digital development team needs
to quickly debug, validate, and
optimize your digital system – at
a price that fits your budget.
The logic analyzer’s timing and
state acquisition gives you the
power to:
• Accurately measure precise
timing relationships using
4 GHz (250 ps) timing zoom
with 64 K depth
• Find anomalies separated in
time with memory depths
upgradeable to 32 M
• Buy what you need today and
upgrade in the future. 16800
Series logic analyzers come
with independent upgrades for
memory depth and state speed
• Sample synchronous buses
accurately and confidently
using eye finder. Eye finder
automatically adjusts
threshold and setup and
hold to give you the highest
confidence in measurements
on high-speed buses
• Track problems from symptom
to root cause across several
measurement modes by
viewing time-correlated data
in waveform/chart, listing,
inverse assembly, source code,
or compare display
• Set up triggers quickly and
confidently with intuitive,
simple, quick, and advanced
triggering. This capability
combines new trigger
functionality with an intuitive
user interface
• Access the signals that hold
the key to your system’s
problems with the industry’s
widest range of probing
accessories with capacitive
loading down to 0.7 pF
• Monitor and correlate multiple
buses with split analyzer
capability, which provides
single and multi-bus support
(timing, state, timing/state or
state/state configurations)
Accurately measure precise
timing relationships
16800 Series logic analyzers let
you make accurate high-speed
timing measurements with 4 GHz
(250 ps) high-speed timing zoom. A
parallel acquisition architecture
provides high-speed timing
measurements simultaneously
through the same probe used for
state or timing measurements.
Timing zoom stays active all the
time with no tradeoffs. View data
at high resolution over longer
periods of time with 64-K-deep
timing zoom.
Figure 1. With eight models to choose from, you can get a
logic analyzer with measurement capabilities that meet
your needs.
4
Logic Analysis for Tracking Real-time System Operation
Automate measurement setup and
quickly gain diagnostic clues
16800 Series logic analyzers make
it easy for you to get up and
running quickly by automating
your measurement setup process.
In addition, the logic analyzer’s
setup/hold window (or sampling
position) and threshold voltage
settings are automatically
determined so you can capture
data on high-speed buses with the
highest accuracy. Auto Threshold
and Sample Position mode allow
you to...
• Obtain accurate and reliable
measurements
• Save time during measurement
setup
• Gain diagnostic clues and
identify problem signals
quickly
• Scan all signals and buses
simultaneously or just a few
• View results as a composite
display or as individual signals
• See skew between signals
and buses
• Find and fix inappropriate
clock thresholds
• Measure data valid windows
• Identify signal integrity
problems related to rise times,
fall times, data valid window
widths
Identify problem signals over
hundreds of channels simultaneously
As timing and voltage margins
continue to shrink, confidence
in signal integrity becomes an
increasingly vital requirement
in the design validation process.
Eye scan lets you acquire signal
integrity information on all
the buses in your design, under
a wide variety of operating
conditions, in a matter of
minutes. Identify problem signals
quickly for further investigation
with an oscilloscope. Results can
be viewed for each individual
signal or as a composite of
multiple signals or buses.
Extend the life of your equipment
Easily upgrade your 16800 Series
logic analyzer. “Turn on”
additional memory depth and
state speed when you need more.
Purchase the capability you
need now, then upgrade as your
needs evolve.
Figure 2. Identify problem signals quickly by viewing eye
diagrams across all buses and signals simultaneously.
5
Agilent 16800 Series Logic Analyzer Specifications and Characteristics
Channel count per measurement mode
16801A/16821A 16802A/16822A 16803A/16823A 16804A 16806A
State analysis [1] 32 data + 2 clocks 64 data + 4 clocks 98 data + 4 clocks 132 data + 4 clocks 200 data + 4 clocks
Conventional timing 34 68 102 136 204
Transitional timing for 34 68 102 136 204
sample rates < 500 MHz
Transitional timing for – 34 68 102 170
500 MHz sample rate
[1] Unused clock channels can be used as data channels.
Timing zoom
(simultaneous state and timing without double probing – all channels,
all the time)
Timing analysis sample rate 4 GHz (250 ps)
Time interval accuracy
Within a pod pair ± (1.0 ns + 0.01% of time interval reading)
Between pod pairs ± (1.75 ns +0.01% of time interval reading)
Memory depth 64 K samples
Trigger position Start, center, end, or user-defined
Minimum data pulse width 1 ns
Other
Voltage threshold –5 V to 5 V (10 mV increments)
Threshold accuracy ± 50 mV + 1% of setting
6
Agilent 16800 Series Logic Analyzer Specifications and Characteristics
Option 500 (available on 16802A, 16803A,
State (synchronous) analysis mode Option 250 16804A, 16806A, 16822A and 16823A)
tWidth* [1] 1.5 ns 1.5 ns
tSetup 0.5 tWidth 0.5 tWidth
tHold 0.5 tWidth 0.5 tWidth
tSample range [2] –3.2 ns to +3.2 ns –3.2 ns to +3.2 ns
tSample adjustment resolution 80 ps typical 80 ps typical
Maximum state data rate on each channel 250 Mb/s 500 Mb/s
Memory depth [4] Option 001: 1 M samples Option 001: 1 M samples
Option 004: 4 M samples Option 004: 4 M samples
Option 016: 16 M samples Option 016: 16 M samples
Option 032: 32 M samples Option 032: 32 M samples
Number of independent analyzers [5] 2 (1 for 16801A or 16821A) 1
Number of clocks [6] 4 (2 for 16801A or 16821A) 1
Number of clock qualifiers [6] 4 (2 for 16801A or 16821A) N/A
Minimum time between active 4.0 ns 2.0 ns
clock edges* [7]
Minimum master-to-slave clock time 1 ns N/A
Minimum slave-to-master clock time 1 ns N/A
Minimum slave-to-slave clock time 4.0 ns N/A
Minimum state clock pulse width
Single edge 1.0 ns 1.0 ns
Multiple edge 1.0 ns 2.0 ns
* Items marked with an asterisk (*) are specifications. All others are characteristics.
“Typical” represents the average or median value of the parameter based on measurements from a significant number of units.
[1] Minimum eye width in system under test.
[2] Sample positions are independently adjustable for each data channel input. A negative sample position causes the input to be synchronously sampled by that amount before
each active clock edge. A positive sample position causes the input to be synchronously sampled by that amount after each active clock edge. A sampling position of zero
causes the input to be synchronously sampled coincident with each clock edge.
[3] Use of eye finder is recommended in 450 MHz and 500 Mb/s state mode.
[4] In 250 Mb/s state mode, with all pods assigned, memory depth is half the maximum memory depth. With one pod pair (34 channels) unassigned, the memory depth is full. One
pod pair (34 channels) must remain unassigned for time tags in 500 Mb/s state mode.
[5] Independent analyzers may be either state or timing. When the 500 Mb/s state mode is selected, only one analyzer may be used.
[6] In the 250 Mb/s state mode, the total number of clocks and qualifiers is 4(2 for 16801A or 16821A).
[7] Tested with input signal Vh = +1.3 V, Vl = +0.7 V, threshold = +1.0 V, tr/tf = 180 ps ± 30 ps (10%, 90%).
Individual
Data Channel
tSetup tHold
Sampling Position
Clock Channel
tWidth
Data EyevHeight
vThreshold
OV
tSample
7
Agilent 16800 Series Logic Analyzer Specifications and Characteristics
Option 500 (available on 16802A, 16803A,
State (synchronous) analysis mode Option 250 16804A, 16806A, 16822A and 16823A)
Clock qualifier setup time 500 ps N/A
Clock qualifier hold time 0 N/A
Time tag resolution 2 ns 1.5 ns
Maximum time count between stored states 32 days 32 days
Maximum trigger sequence speed 250 MHz 500 MHz
Maximum trigger sequence levels 16 16
Trigger sequence level branching Arbitrary 4-way if/then/else 2-way if/then/else
Trigger position Start, center, end, or user-defined Start, center, end, or user-defined
Trigger resources 16 patterns evaluated as =, =/, >, ≥, <, ≤ 14 patterns evaluated as =, =/, >, ≥, <, ≤
14 double-bounded ranges evaluated as 7 double-bounded ranges evaluated as
in range, not in range in range, not in range
1 timer for every 34 channels 1 occurrence counter per sequence level
2 global counters 4 flags
1 occurrence counter per sequence level
4 flags
Trigger resource conditions Arbitrary Boolean combinations Arbitrary Boolean combinations
Trigger actions Go To Go To
Trigger, send e-mail, and fill memory Trigger and fill memory
Trigger and Go To
Store/don’t store sample
Turn on/off default storing
Timer start/stop/pause/resume
Global counter increment/decrement/reset
Occurrence counter reset
Flag set/clear
Store qualification Default (global) and per sequence level Default (global)
Maximum global counter 2E+24 N/A
Maximum occurrence counter 2E+24 2E+24
Maximum pattern width Smaller of 128 bits or maximum number Smaller of 128 bits or maximum number
of channels of channels
Maximum range width Smaller of 64 bits or maximum number Smaller of 64 bits or maximum number
of channels of channels
Timers range 60 ns to 2199 seconds N/A
Timer resolution 2 ns N/A
Timer accuracy ± (5 ns +0.01%) N/A
Timer reset latency 60 ns N/A
8
Agilent 16800 Series Logic Analyzer Specifications and Characteristics
Timing (asynchronous) analysis mode Conventional timing Transitional timing [8]
Sample rate on all channels 500 MHz 500 MHz
Sample rate in half channel mode 1 GHz N/A
Number of independent analyzers [5] 2 (1 for 16801A or 16821A) 2 (1 for 16801A or 16821A)
Sample period (half channel) 1.0 ns N/A
Minimum sample period (full channel) 2.0 ns 2.0 ns
Minimum data pulse width 1 sample period + 1.0 ns 1 sample period + 1.0 ns
Time interval accuracy ± (1 sample period + 1.25 ns + 0.01% of ± (1 sample period + 1.25 ns + 0.01% of
time interval reading) time interval reading)
Memory depth in full channel mode Option 001: 1 M samples Option 001: 1 M samples
Option 004: 4 M samples Option 004: 4 M samples
Option 016: 16 M samples Option 016: 16 M samples
Option 032: 32 M samples Option 032: 32 M samples
Memory depth in half channel mode Option 001: 2 M samples N/A
Option 004: 8 M samples
Option 016: 32 M samples
Option 032: 64 M samples
Maximum trigger sequence speed 250 MHz 250 MHz
Maximum trigger sequence levels 16 16
Trigger sequence level branching Arbitrary 4-way if/then/else Arbitrary 4-way if/then/else
Trigger position Start, center, end, or user-defined Start, center, end, or user-defined
[5] Independent analyzers may be either state or timing. When the 500 Mb/s state mode is selected, only one analyzer may be used.
[8] Transitional timing speed and memory depth are halved unless a spare pod pair (34 channels) is unassigned.
9
Agilent 16800 Series Logic Analyzer Specifications and Characteristics
Timing (asynchronous) analysis mode Conventional timing Transitional timing
Trigger resources 16 patterns evaluated as =, =/, >, ≥, <, ≤ 15 patterns evaluated as =, =/, >, ≥, <, ≤
14 double-bounded ranges evaluated as 14 double-bounded ranges evaluated as
in range, not in range in range, not in range
3 edge/glitch 3 edge/glitch
1 timer for every 34 channels 1 timer for every 34 channels
(no timer for 16801A or 16821A) (no timer for 16801A or 16821A)
2 global counters 2 global counters
1 occurrence counter per sequence level 1 occurrence counter per sequence level
4 flags 4 flags
Trigger resource conditions Arbitrary Boolean combinations Arbitrary Boolean combinations
Trigger actions Go To Go To
Trigger, send e-mail, and fill memory Trigger, send e-mail, and fill memory
Trigger and Go To Trigger and Go To
Turn on/off default storing Turn on/off default storing
Timer start/stop/pause/resume Timer start/stop/pause/resume
Global counter increment/decrement/reset Global counter increment/decrement/reset
Occurrence counter reset Occurrence counter reset
Flag set/clear Flag set/clear
Maximum global counter 2E+24 2E+24
Maximum occurrence counter 2E+24 2E+24
Maximum range width 32 bits 32 bits
Maximum pattern width Smaller of 128 bits or maximum number Smaller of 128 bits or maximum number
of channels of channels
Timer value range 60 ns to 2199 seconds 60 ns to 2199 seconds
Timer resolution 2 ns 2 ns
Timer accuracy ± (5 ns +0.01%) ± (5 ns +0.01%)
Greater than duration 4.0 ns to 67 ms in 4.0 ns increments 4.0 ns to 67 ms in 4.0 ns increments
Less than duration 8.0 ns to 67 ms in 4.0 ns increments 8.0 ns to 67 ms in 4.0 ns increments
Timer reset latency 60 ns 60 ns
10
A Built-in Pattern Generator Gives You Digital Stimulus and Response
in a Single Instrument
Selected 16800 Series models
(16821A, 16822A and 16823A)
also include a 48-channel pattern
generator to drive down risk early
in product development. With a
pattern generator you can:
• Substitute for missing boards,
integrated circuits (ICs) or
buses instead of waiting for
missing pieces
• Write software to create
infrequently encountered test
conditions and verify that the
code works – before complete
hardware is available
• Generate patterns necessary to
put a circuit in a desired state,
operate the circuit at full speed
or step the circuit through a
series of states
• Create a circuit initialization
sequence
Agilent 16800 Series portable
logic analyzers with a pattern
generator offer a variety of
features that make it easier for you
to create digital stimulus tests.
Vectors up to 48 bits wide
Vectors are defined as a “row” of
labeled data values, with each
data value from one to 48 bits
wide. Each vector is output on
the rising edge of the clock.
Create stimulus patterns for the
widest buses in your system.
Depth up to 16 M vectors
With the pattern generator, you
can load and run up to 16 M
vectors of stimulus. Depth on this
scale is most useful when coupled
with powerful stimulus generated
by electronic design automation
tools, such as SynaptiCAD’s
WaveFormer and VeriLogger.
These tools create stimulus using
a combination of graphically
drawn signals, timing parameters
that constrain edges, clock signals,
and timing and Boolean equations
for describing complex signal
behavior. The stimulus also can
be created from design simulation
waveforms. The SynaptiCAD tools
allow you to convert .VCD files
into .PGB files directly, offering
you an integrated solution that
saves you time.
Synchronized clock output
You can output data synchronized
to either an internal or external
clock. The external clock is input
via a clock pod, and has no
minimum frequency (other than
a 2 ns minimum high time).
The internal clock is selectable
between 1 MHz and 300 MHz in
1-MHz steps. A Clock Out signal is
available from the clock pod and
can be used as an edge strobe with
a variable delay of up to 8 ns.
Initialize (INIT) block for
repetitive runs
When running repetitively, the
vectors in the initialize (init)
sequence are output only once,
while the main sequence is
output as a continually repeating
sequence. This “init” sequence is
very useful when the circuit or
subsystem needs to be initialized.
The repetitive run capability
is especially helpful when
operating the pattern generator
independent of the logic analyzer.
“Send Arm out to…” coordinates
activity with the logic analyzer
Verify how your system responds
to a specific stimulus sequence by
arming the logic analyzer from
the pattern generator. A “Send
Arm out to…” instruction acts as a
trigger arming event for the logic
analyzer or other test equipment
to begin measurements. Arm
setup and trigger setup of the
logic analyzer determines the
action initiated by “Send Arm
out to…”.
Figure 3. Models with a built-in pattern generator give you
more measurement flexibility.
11
“Wait for External Event…” for
input pattern
The clock pod also accepts a 3-bit
input pattern. These inputs are
level-sensed so that any number
of “Wait for External Event”
instructions can be inserted into
a stimulus program. Up to four
pattern conditions can be defined
from the OR-ing of the eight
possible 3-bit input patterns. A
“Wait for External Event” also can
be defined to wait for an Arm. This
Arm signal can come from the
logic analyzer. “Wait for External
Event…” allows you to execute
a specific stimulus sequence
only when the defined external
event occurs.
Simplify creation of stimulus programs
with user-defined macros and loops
User macros permit you to define
a pattern sequence once, then
insert the macro by name
wherever it is needed. Passing
parameters to the macro will
allow you to create a more
generic macro. For each call to
the macro you can specify unique
values for the parameters.
Loops enable you to repeat a
defined block of vectors for a
specified number of times. Loops
and macros can be nested, except
that a macro cannot be nested
within another macro. At compile
time, loops and macros are
expanded in memory to a
linear sequence.
Convenient data entry and
editing feature
You can conveniently enter
patterns in hex, octal, binary,
decimal, and signed decimal
(two’s complement) bases. To
simplify data entry, you can view
the data associated with an
individual label with multiple
radixes. Delete, Insert, and Copy
commands are provided for easy
editing. Fast and convenient
Pattern Fills give the programmer
useful test patterns with a few
key strokes. Fixed, Count, Rotate,
Toggle, and Random patterns are
available to help you quickly
create a test pattern, such
as “walking ones.” Pattern
parameters, such as step size and
repeat frequency, can be specified
in the pattern setup.
ASCII input file format: your design
tool connection
The pattern generator supports
an ASCII file format to facilitate
connectivity to other tools in your
design environment. Because the
ASCII format does not support the
instructions listed earlier, they
cannot be edited into the ASCII
file. User macros and loops also
are not supported, so the vectors
need to be fully expanded in the
ASCII file. Many design tools will
generate ASCII files and output
the vectors in this linear sequence.
Data must be in hex format, and
each label must represent a set of
contiguous output channels.
Configuration
The pattern generator operates
with the clock pods, data pods,
and lead sets described later in
this document. At least one clock
pod and one data pod must be
selected to configure a functional
system. You can select from a
variety of pods to provide the
signal source needed for your logic
devices. The data pods, clock pods
and data cables use standard
connectors. The electrical
characteristics of the data cables
are described for users with
specialized applications who want
to avoid the use of a data pod.
Direct connection to your
target system
You can connect the pattern
generator pods directly to a
standard connector on your target
system. Use a 3M brand #2520
Series or similar connector. The
clock or data pods will plug right
in. Short, flat cable jumpers can
be used if the clearance around
the connector is limited. Use a 3M
#3365/20, or equivalent, ribbon
cable; a 3M #4620 Series or
equivalent connector on the
pattern generator pod end of the
cable, and a 3M #3421 Series or
equivalent connector at your
target system end of the cable.
Probing accessories
The probe tips of the
Agilent 10474A, 10347A, 10498A,
and E8142A lead sets plug
directly into any 0.1-inch grid
with 0.026-inch to 0.033-inch
diameter round pins or 0.025-inch
square pins. These probe tips
work with the Agilent 5090-4356
surface mount grabbers and
with the Agilent 5959-0288
through-hole grabbers, providing
compatibility with industry
standard pins.
A Built-in Pattern Generator Gives You Digital Stimulus and Response
in a Single Instrument
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