Agilent 16717A Help Volume

Help Volume

HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

The HP 16717A 333 MHz State/2 GHz Timing Zoom logic analyzer offers deep memory and very fast sample rates - up to 2 GHz for areas around the trigger - with up to 340 channels. This logic analyzer also marks the debut of VisiTrigger, HP’s new patented logic analyzer triggering system.

Getting Started

•“Analyzer Probing Overview” on page 99

•“Setting Up a Measurement” on page 10

•“When Something Goes Wrong” on page 33

•“Error Messages” on page 33

Measurement Examples

•“Making a Basic Timing Measurement” on page 22

•“Making a Basic State Measurement” on page 18

• Advanced Measurement Examples (see the Measurement Examples help

volume)

•“Interpreting the Data” on page 26

More Features

“Arming Control - Multiple Instruments and Analyzers” on page 30

Using Inverse Assembly (see the Listing Display Tool help volume)

Using Symbols (see page 102)

Working with Markers (see the Markers help volume)

“Loading and Saving Logic Analyzer Configurations” on page 32

“Testing the Logic Analyzer Hardware” on page 42

“Specifications and Characteristics” on page 94

Interface Reference

“The Sampling Tab” on page 43

“The Format Tab” on page 52

“The Trigger Tab” on page 63

“The Symbols Tab” on page 102

Main System Help (see the HP 16600A/16700A Logic Analysis System help volume)

Glossary of Terms (see page 129)

HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

1 HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

Setting Up a Measurement 10

Connect the Analyzer to the Target System 10 Define the Type of Measurement 11 Set Up the Bus Labels 13 Define Trigger Conditions 14 Run the Measurement 15 Examine the Data 16

Making a Basic State Measurement 18

Making a Basic Timing Measurement 22

Interpreting the Data 26

Analysis Using Waveform 26 Analysis Using Listing 28 Arming Control - Multiple Instruments and Analyzers 30

Loading and Saving Logic Analyzer Configurations 32

When Something Goes Wrong 33

Interference with Target System 33 Error Messages 33 Nothing Happens 34 Suspicious Data 34

Testing the Logic Analyzer Hardware 42

Contents

The Sampling Tab 43

Acquisition Depth 43 2 GHz Timing Zoom 44 Setting the Acquisition Mode 44 Performing Clock Setup (State only) 45 Naming the Analyzer 48 Turning the Analyzer Off 48 Sample Period (Timing Only) 49 Trigger Position Control 50

The Format Tab 52

Activity Indicators 52 Assigning Pods to the Analyzers 53 Data On Clocks Display 54 Labels: Mapping Analyzer Channels to Your Target 58 Setting Up the Pod Clock 58 Pod Selection 59 Setting the Pod Threshold 60 State Clock Setup/Hold (State only) 60

The Trigger Tab 63

Contents

E-mail Notify on Trigger 65

What is SMTP 66 Understanding Logic Analyzer Triggering 66 Setting Up a Trigger 69 Inserting and Deleting Sequence Steps 70 Editing Sequence Levels 72 Setting Up Loops and Jumps in the Trigger Sequence 72 Saving and Recalling Trigger Sequences 73 Clearing Part or All of the Trigger 74 Overview of the Trigger Sequence 75 Trigger Functions 76 Trigger Function Libraries 77 Working with Advanced Functions 86 Defining Events 89 Tagging Data with Time or State Tags (State Only) 93

Specifications and Characteristics 94

What is a Specification 94 What is a Characteristic 94 What is a Calibration Procedure 95 What is a Function Test 95 HP 16717A Logic Analyzer Specifications 95 HP 16717A Logic Analyzer Characteristics 96

Analyzer Probing Overview 99

The Symbols Tab 102

Displaying Data in Symbolic Form 103

Contents

Setting Up Object File Symbols 104

To Load Object File Symbols 104 Relocating Sections of Code 106 To Delete Object File Symbol Files 107 Symbol File Formats 107 Creating ASCII Symbol Files 108 Creating a readers.ini File 113

User-Defined Symbols 115

To Create User-Defined Symbols 115 To Replace User-Defined Symbols 115 To Delete User-Defined Symbols 116 To Load User-Defined Symbols 116

Using Symbols In The Logic Analyzer 117

Using Symbols As Trigger Terms 117 Using Symbols as Search Patterns in Listing Displays 118 Using Symbols as Trigger Terms in the Source Viewer 118 Using Symbols as Pattern Filter Terms 119 Using Symbols as Ranges in the Software Performance Analyzer 119

Help - How to Navigate Quickly 122

Help - System Overview 123

Run/Group Run Function 124

Setting a tool for independent or Group Run 125 Setting Single or Repetitive Run 126 Checking Run Status 126 Demand Driven Data 127

Glossary

Index

HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

Setting Up a Measurement

After you have connected the logic analyzer probes to your target system, (see page 10) there are five basic steps for any measurement.

1. “Define the Type of Measurement” on page 11

2. “Set Up the Bus Labels” on page 13

3. “Define Trigger Conditions” on page 14

4. “Run the Measurement” on page 15

5. “Examine the Data” on page 16 Refine measurement by repeating steps 3 - 5.

If you load a configuration file, it will set up the logic analyzer and trigger. For your particular measurement, you may need to change some settings.

See Also “Making a Basic Timing Measurement” on page 22

“Making a Basic State Measurement” on page 18

Measurement Examples (see the Measurement Examples help volume)

Making Basic Measurements for a self-paced tutorial

Connect the Analyzer to the Target System

Before you begin setting up a measurement, you need to physically connect the logic analyzer to your target system. Attach the pods in a way that keeps logically related channels together and be sure to

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Setting Up a Measurement

ground each pod. Analysis probes, available for most common microprocessors, can simplify the connection process.

The logic analyzer pods carry the signals to the logic analyzer from your target system. Connect the pods either directly to the target system or to an analysis probe. You can attach the pods either directly to a 40-pin header, to a 20-pin header with an adapter, or use the General Purpose Probes to attach to individual channels.

If you are using an analysis probe, Setup Assistant will guide you through the process based on your logic analyzer and the analysis probe.

Step 1: Describe the Measurement (see page 11)

See Also “Analyzer Probing Overview” on page 99 for more detail on types of probes

Setup Assistant (see the Setup Assistant help volume)

Logic Analysis System and Measurement Modules Installation Guide for probe pinout and circuit diagrams.

Define the Type of Measurement

There are two types of measurements: state measurements and timing measurements. Use the Sampling tab to select either type

and to specify the details particular to that type.

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Setting Up a Measurement

Choose State or Timing

In a state measurement, the analyzer uses an external clock to determine when to sample. Each time the analyzer receives a state clock pulse, it samples and stores the logic state of the target system.

In a timing measurement, the analyzer is analogous to an oscilloscope. It samples at regular time intervals and displays the information in a waveform similar to the oscilloscope.

Set Measurement Mode

Each measurement type has different measurement modes. In general, there is a trade-off between number of signals and speed.

Because the measurement type and mode affect clocking and trigger options, you must set the measurement type first.

Set up State Clock

For state measurements, you must specify a clock to match the clocking arrangement used by your target system. It can be as simple as a single rising edge, or a complex arrangement of up to four signals. If the clock is incorrect, the trace data may indicate a problem where there isn’t one. Specify the state clock in Clock Setup.

The equivalent in timing mode of the state clock is the Sample Period. The Sample Period sets the time between logic analyzer samples. For reliable data, the sample period should be no more than half of your clock period. Many engineers prefer setting it to one-fourth of the clock period.

Set up the Trace

The remaining controls finish your description of how you want to capture data. The trigger position determines where the events you specify in the trigger sequence will be relative to the majority of the data the logic analyzer captures.

Memory depth is affected by the measurement mode. Some logic analyzers also let you limit how big the acquisition will be with an Acquisiton Depth control.

Step 2: Set Up the Bus Labels (see page 13)

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Setting Up a Measurement

See Also “The Sampling Tab” on page 43 for information on setting type and

assigning pods

“Setting the Acquisition Mode” on page 44 for links to this analyzer's modes

“Performing Clock Setup (State only)” on page 45

Set Up the Bus Labels

The next step is to finish defining the physical connection between the target system and the analzyer. Use the Format tab to tell the analyzer what you want to measure on the target system. If you load a configuration file, this step is taken care of for you.

Group and Label Signals

Because the logic analyzer can capture dozens or even hundreds of signals, you need to organize the signals by grouping and labeling channels. Labels are used to group these channels into logical signals; for example, "addr bus". These groupings are then used in the trigger tab and the data displays. A label can have up to 32 channels. Each measurement can define 126 labels. Active channels are indicated like

so .

Set Threshold Level

The logic analyzer needs to know what threshold level the target system is using. You can set the analyzer to use TTL or ECL logic levels,

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

Setting Up a Measurement

or set a different threshold voltage. The logic analyzer requires a minimum voltage swing of 500 mV at the probe tip to recognize changes in logic levels.

Step 3: Define Trigger Conditions (see page 14)

See Also “Assigning Bits to a Label” on page 54

“The Format Tab” on page 52

Define Trigger Conditions

The third step is to define the trigger. The trigger settings tell the analyzer when you want to capture data. Controls for this are located under the Tri g g e r tab. Configuration files saved from previous measurements automatically define trigger settings.

Set Up a Trigger Sequence

The trigger sequence is like a small program that controls when the logic analyzer stores data. There are trigger functions for the common tasks, or you can set up your own. The logic analyzer starts at the first trigger level, and stays there until the defined event occurs. When that happens, it goes to the next level and follows the instructions there.

Define Events

Trigger events can be used like variables in the trigger sequence. Some

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

trigger functions only let you insert events that pertain to the description of the function. The advanced functions let you insert any type of event.

Step 4: Run the Measurement (see page 15)

See Also “Defining Events” on page 89

“Understanding Logic Analyzer Triggering” on page 66

“Setting Up a Trigger” on page 69

“The Trigger Tab” on page 63

Measurement Examples (see the Measurement Examples help volume)

Setting Up a Measurement

Run the Measurement

You run the measurement by selecting the Run button. The Run button is labeled either Run, Group Run, or Run All. The difference between the three types is that Run starts only the instrument you are using, Group Run starts all instruments attached to group run in the Intermodule window, and Run All starts all instruments currently placed in the workspace.

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Setting Up a Measurement

Select Single or Repetitive

Runs can be single or repetitive. Single runs gather data until the logic analyzer memory is full, and then stop. Repetitive runs keep repeating the same measurement and are useful for gathering statistics. To stop a run, click Stop.

NOTE: Repetitive runs on a logic analyzer don’t do equivalent time sampling like

oscilloscopes do.

If Nothing Happens...

Analyzers with deep memory take a noticeable amount of time to complete a run. Because data is not displayed until acquisition completes, it may look like nothing is happening. Check the Run Status window to see if the logic analyzer is still running. Messages such as "Waiting in level 1" may indicate you need to refine your trigger. If the status shows as "Stopped", the analyzer either finished the acquisition, or was unable to run. The cause of the problem is listed in the bottom half of the Run Status window, and the messages are explained in more detail in “Error Messages” on page 33.

Step 5: Examine the Data (see page 16)

See Also “When Something Goes Wrong” on page 33

Examine the Data

Data from your measurement can be viewed in various display windows or offline. Some of the things you can do in the display windows are

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Setting Up a Measurement

• Search for patterns

• Display time-correlated data

• Use markers to make measurements and gather statistics

Search for Patterns

You can search displays for certain values, and place markers on them. There are two global markers which keep their place across all measurement views, even across instruments.

Display Correlated Data

There are several tools for correlation. The Intermodule window allows you to specify complex triggering configurations using several instruments. It is also useful for starting acquisitions at the same time. Global markers mark the same events in different displays, so you can switch views without having to reorient yourself. The Compare tool lets you compare two different acquisitions to look for changes.

Use Markers to Make Measurements

The markers can be positioned relative to the beginning, end, trigger, or another marker, as well as set to a specific pattern, state, or time. The Markers tab in the Display windows shows the time or state value as you move the markers or take new acquisitions.

See Also Working with Markers (see the Markers help volume)

Using the Chart Display Tool (see the Chart Display Tool help volume)

Using the Distribution Display Tool (see the Distribution Display Tool help volume)

Using the Listing Display Tool (see the Listing Display Tool help volume)

Using the Digital Waveform Display Tool (see the Waveform Display Tool help volume)

Using the Compare Analysis Tool (see the Compare Tool help volume)

“Interpreting the Data” on page 26

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

Making a Basic State Measurement

This example uses the circuit board that is supplied with the Making Basic Measurements kit as the target system. The kit is supplied with

every logic analysis system, or can be ordered from your HP Sales Office.

There are six major steps to making a basic measurement.

Connect the Logic Analyzer to your Target Sys t e m

1. Connect probes.

• Connect Pod 1 of the logic analyzer to J1 on the target system.

The training board has terminations and headers already built in to the system, so you can connect the logic analyzer pod directly to the board.

2. Define the type of measurement On the HP 16600A-series or HP 16700A logic analysis system, open a logic analyzer setup window.

a. In the main window, right-click the logic analyzer icon.

b. Select Setup... from the menu.

c. Click the Sampling tab.

d. If the logic analyzer is not already set for State, change the type to

State.

3. Set up the clock to match the target system's clocking scheme.

a. In the bottom half of the Sampling tab window, choose the correct

edges to match your clock. For Pod 1 attached to the training board, the correct clock is the falling edge on J.

1. Click on Off under J and choose "Falling Edge" from the menu.

4. Group and label bits.

a. Click on the Format tab.

b. Optional - Insert a second label.

1. Right-click Label1.

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

Making a Basic State Measurement

2. Select Insert after....

3. In the Enter Label Name box, click OK.

c. Optional - Rename Label1.

1. Right-click Label1.

2. Select Rename....

3. Enter a new name in the name field.

4. Click OK to close the Rename Label box.

d. Right-click the bit assignment field.

The bit assignment field is the field to the right of a label name, and under a pod column.

e. Select ........******** from the menu.

If none of the choices match your own system, select Individual... and click on the individual bits to assign them (*) or ignore them (.).

5. Define trigger events for patterns on buses.

a. Click the Trigger tab.

b. Optional - Rename Pattern1.

1. Double-click in the Pattern1 field.

2. Enter a new name.

c. Select the appropriate label.

1. Click the field to the far-right of the label name.

2. To define the event as a combination of labels, click Insert... To use a different label to define the event, click Replace...

3. In the dialog box, click the label name you want to use and then click OK.

d. Click in the field with XX and enter the value you want to trigger on.

e. Optional - Repeat steps a - d for Pattern2.

6. Optional - Add additional trigger events to the trigger specification. The logic analyzer automatically triggers on Pattern1, the first trigger event. You can set up more complex triggers by editing the sequence levels

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Making a Basic State Measurement

and combining trigger events.

a. Click the 1 box and select Edit...

b. In the dialog box, click the Pattern1 button just after Trigger on and

select Combo...

c. In the Combination box, click Off next to Pattern2 and select On.

d. To change the trigger to Pattern1 and Pattern2, click the Or box to

the right of the events and select And.

e. Click on OK.

f. Click on Close.

The analyzer is now set to trigger when it detects both the pattern defined by Pattern1 and the pattern defined by Pattern2 on the target system’s buses. The trigger sequence windows shows

Trigger on "(Pattern1.Pattern2)" 1 time

See Also “The Tri gger Tab” on page 63

1. Click Run.

2. Examine the data.

a. Click the Navigate button.

b. Point to Analyzer<A> in the menu and select Listing<1>.

Depending on what other instruments are active, there may be more than one Analyzer<A>. Choose the one that refers to your analyzer.

c. To have the listing display appear automatically when you run the logic

analyzer, select Options -> Popup on Run -> On in the menu bar of the listing display.

d. To insert additional labels, right-click the label name.

Making a Basic Timing Measurement

This example uses the circuit board that is supplied with the Making Basic Measurements kit as the target system. The kit is supplied with

every logic analysis system, or can be ordered from your HP Sales Office.

There are six major steps to making a basic measurement.

Connect the Logic Analyzer to the Target System

1. Connect probes.

• Connect Pod 1 of the logic analyzer to J1 on the target system.

The training board has terminations and headers already built in to the system, so you can connect the logic analyzer pod directly to the board.

2. Define the type of measurement. On the HP 16600A-series or HP 16700A logic analysis system, open a logic analyzer setup window.

a. In the main window, right-click the logic analyzer icon.

b. Select Setup... from the menu.

c. Click the Sampling tab.

d. If the logic analyzer is not already set for Timing, change the type to

Timing.

3. Group and label bits.

a. Click the Format tab.

b. Optional - Insert a second label.

1. Right-click Label1.

2. Select Insert after....

3. In the Enter Label Name box, click OK.

c. Optional - Rename Label1

1. Right-click Label1.

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Making a Basic Timing Measurement

2. Select Rename....

3. Enter a new name in the name field.

4. Click OK to close the Rename Label box.

d. Click the bit assignment field.

The bit assignment field is the field to the right of a label name, and under a pod column.

e. Select ........******** from the menu.

If none of the choices match your own system, select Individual... and click on the individual bits to assign them (*) or ignore them (.).

4. Define trigger events for a bus.

a. Click the Trigger tab.

b. Click the Pattern tab.

c. Optional - Rename pattern Pattern1.

1. Double-click in the Pattern1 field.

2. Enter a new name.

d. Select the appropriate label.

1. Click the field to the far-right of the label name.

2. To define the event as a combination of labels, click Insert... To use a different label to define the event, click Replace...

3. In the dialog box, click the label name you want to use and then click OK.

e. Click in the field with XX and enter the value you want to trigger on.

5. Define trigger events for an edge.

a. Click the Edge tab.

b. Optional - Rename Edge1.

1. Double-click in the Edge1 field.

2. Enter a new name.

c. Select the appropriate label.

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Making a Basic Timing Measurement

1. Click the label field immediately to the right of the label name.

2. To define the event as a combination of labels, click Insert... To use a different label to define the event, click Replace... Edges within an event are always OR’d together, which means only one of the edges on one of the labels needs to occur for the edge event to become true.

3. In the dialog box, click the label name you want to use and then click OK.

d. Click the edge assignment field (........) and enter the edge or

edges you want to trigger on. Remember, if more than one edge is specified, then when the logic analyzer detects any of the edges the event becomes true.

6. Add the edge event to the trigger specification.

a. Right-click the 1 box and select Edit...

b. In the dialog box, click the Pattern1 button and select Combo...

c. In the Combination box, click Off next to Edge1 and select On.

d. Click the Or box where the path from Pattern1 and the path from

Edge1 come together, and select And.

e. Click on OK.

The analyzer is now set to trigger when it detects Edge1 and Pattern1 on the bus. The trigger sequence window shows

Trigger on Pattern1.Edge1 occurs 1 times

The logic analyzer automatically triggers on the first trigger event. You can set up more complex triggers by editing the sequence levels and defining additional trigger events.

See Also “The Tri gger Tab” on page 63

1. Click Run.

2. Examine the data.

a. Click the Navigate button.

b. Point to Analyzer<A> in the menu and select Waveform<1>.

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

Depending on what other instruments are active, there may be more than one Analyzer<A>. Choose the one that refers to your analyzer.

c. To have the waveform display appear automatically when you run the

logic analyzer, select Options -> Popup on Run -> On in the menu bar of the waveform display.

d. To insert additional labels, or expand overlaid signals, right-click the

label name.

Interpreting the Data

After you’ve acquired a trace with the logic analyzer, you can analyze it in the display tools. The logic analysis system also provides filtering and compare tools for more complex analysis.

The logic analyzer is automatically connected to the Waveform and Listing displays when you set up a measurement. To move to that display,

1. Right-click the blue Navigate button.

2. Move the cursor over the name of the analyzer whose data you want to view.

3. Click on Waveform or Listing. Source Viewer brings up a Listing display but requires an inverse assembler and an ADDR label.

•“Analysis Using Waveform” on page 26

•“Analysis Using Listing” on page 28

Analysis Using Waveform

Waveform is most useful for timing data. If you look at state data that uses store qualification, you won’t be able to easily see where samples were not stored. Timing data, however, is periodic and stores all samples and so works well with Waveform.

Example: Looking for a Missing Pattern

You can easily use the waveform tool to make timing measurements. For example, if you were triggering when a pattern doesn’t follow an edge within a certain time (see the Measurement Examples help volume), you would probably want to look at your data set to see if the pattern ever did occur. This might be the case when you verifying that the system is responding to an interrupt.

After triggering on an instance where the response did not appear

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

Interpreting the Data

quickly enough, you might take these steps in the Waveform display:

1. Find the edge.

a. Click Search.

b. Click the down arrow after the Label field, and select the label

containing the edge.

c. Click the Value field and type 1.

d. Click Next to locate the edge transition.

2. Place a marker on the edge.

Click Set G1. This sets global marker G1 at the location of the edge you just found.

3. Search for the pattern. Searches start at your current location. Since you just set the global marker G1, it indicates where the search starts from.

a. Click the down arrow after the Label field, and select the label

containing the pattern.

b. Click the Value field and type the pattern you are searching for.

c. Click the down arrow after the When field and select Entering.

d. Click Next to find the next occurrence of that pattern after G1.

If the logic analysis system cannot find the pattern, a "Value not found" message pops up.

4. Place a marker on the pattern.

Click Set G2. This will set global marker G2 at the location of the pattern.

5. Find the time between the edge and the pattern.

a. Click Markers.

b. In the G2 row, click the down arrow after from, and select G1.

The value after the from field changes to the time between G1 and G2. You can toggle between time and samples by clicking the arrow after the Time or Samples field.

See Also Using the Digital Waveform Display Tool (see the Waveform Display Tool

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Interpreting the Data

help volume)

Using the Listing Display Tool (see the Listing Display Tool help volume)

Using the Chart Display Tool (see the Chart Display Tool help volume)

Using the Distribution Display Tool (see the Distribution Display Tool help volume)

Using the Compare Analysis Tool (see the Compare Tool help volume)

Using the Pattern Filter Analysis Tool (see the Pattern Filter Tool help volume)

Analysis Using Listing

Listing is more useful than Waveform when your target system is running code because it shows the labels as states rather than transitions. Listing is especially useful when you have defined meaningful symbol names for your states. If you have an inverse assembler, you might prefer Source Viewer which functions like Listing.

Example: Examining a Subroutine

Listing is the preferred display tool for state measurements. for example, if you were trying to see if a subroutine were exiting abnormally, you might want to measure the number of states between entering and exiting the subroutine. After acquiring data with the logic analyzer, you could examine the data set in the Listing display like this:

1. Find the start of the subroutine.

Assume the subroutine starts at the address 0x58FC.

a. Click Search.

b. Click the down arrow after the Label field, and select ADDR.

c. Click the Value field, and type in the starting address, 0x58FC.

d. Click the down arrow after the When field and select Present.

e. Click Next or Prev to move the display to the address.

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2. Place a marker on the start of the subroutine.

Click Set G1. This sets global marker G1 at the address you just found.

3. Find the end of the subroutine.

Assume the end of the subroutine is at address 0x58FF. Searches always start at the current location. Since you just set the global marker G1, it indicates where the search starts from.

a. Click the Value field, and enter 58FF.

b. Click Next to find the next occurrence of 0x58FF after the starting

address.

4. Place a marker on the end of the subroutine.

Click Set G2 to set global marker G2 at this position. This lets you refer to G2 when you want to know where the subroutine ends.

5. Find the number of states between the start and end of the subroutine.

Since you’ve placed markers at the start and end of the subroutine, all you have to do is find the number of states between those markers.

a. Click Markers.

b. In the G2 row, click the second down arrow and select Sample.

c. Click the down arrow after from, and select G1.

The value after the from field changes to the number of states between G1 and G2. You can toggle between time and states by clicking the arrow after the Time or Samples field.

Now you know how long the execution stayed in the subroutine, and can also examine the data set between G1 and G2 to look for unusual data.

See Also Using the Digital Waveform Display Tool (see the Waveform Display Tool

help volume)

Using the Listing Display Tool (see the Listing Display Tool help volume)

Using the Chart Display Tool (see the Chart Display Tool help volume)

Using the Distribution Display Tool (see the Distribution Display Tool help volume)

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Using the Compare Analysis Tool (see the Compare Tool help volume)

Using the Pattern Filter Analysis Tool (see the Pattern Filter Tool help volume)

Arming Control - Multiple Instruments and Analyzers

An instrument must be armed before it can look for its trigger. If you have not specified any arming actions, by default the instrument is set to be armed immediately when you Run the measurement.

You can configure an analyzer instrument to be armed by either another instrument (different slot or frame), or, by the second analyzer within the same instrument if that second analyzer is turned on.

To configure an analyzer instrument to arm other instruments, it must first be included in the Group Run Arming Tree (see the HP 16600A/ 16700A Logic Analysis System help volume). Next, in the analyzer instrument Setup window, go to Settings under Trigge r, and specify the analyzer which will drive the Arm Out signal. The specified analyzer’s Trigger and fill memory action becomes Trigger, arm out, and fill memory.

To change the source of Arm In or the destination of Arm Out, use the Intermodule Window (see the HP 16600A/16700A Logic Analysis System help volume).

Setting One Analyzer to Arm the Other

1. Activate the second analyzer.

a. In Format, click Pod Assignment...

b. In the Pod Assignment dialog, change the analyzer type from Off.

The system pauses while setting up the second analyzer. When it is done, a setup window for the second analyzer appears.

2. In Trigger, click the Trigger Functions tab.

3. Select Wait for second analyzer to trigger from the function list.

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Interpreting the Data

4. Select one of the sequence levels next to where you want to insert Wait for second analyzer, then click Insert before or Insert after.

If the second analyzer isn’t activated, a warning message appears and the level is not inserted.

If you are using Advanced functions, you can also insert an Analyzer <2> triggers event directly into a sequence level.

Setting the Analyzer to Wait for Another Module

1. Set up the Intermodule Arming Tree.

a. In the System window, click Intermodule.

b. In the Intermodule window, click the analyzer’s icon and select an

"armed by" option. Independent will remove the analyzer from a group run. Group Run will cause the analyzer to be started simultaneously with other instruments in the group run. The other choices will cause the analyzer to wait for a signal from the specified module.

2. In Trigger, click the Trigger Functions tab.

3. Select Wait for arm in from the function list.

4. Select one of the sequence levels next to where you want to insert Wait for arm in, then click Insert before or Insert after. If the analyzer isn’t armed by another module and group run is not set to Group run armed from Port In, a warning message appears and the level is not inserted.

If you are using Advanced functions, you can also insert an Arm in from IMB event directly into a sequence level.

NOTE: If the trigger sequence does not pass through the level containing the wait

term, the logic analyzer will not wait for the arming signal.

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

Loading and Saving Logic Analyzer Configurations

The HP 16717A logic analyzer settings and data can be saved to a configuration file. The configuration file will include references to any custom trigger libraries you have created, but if the configuration is loaded into an analyzer on a system that does not have the trigger libraries they will not work correctly.

You can also save any tools connected to the logic analyzer. Later, you can restore your data and settings by loading the configuration file into the logic analyzer.

The HP 16717A logic analyzer can load configurations for HP 16715A, 16716A, and 16717A logic analyzers with no restrictions. It can also load configuration files generated for HP 16550A, 16554A, 16555A, 16555D, 16556A, 16556D, 16557D, 16710A, 16711A, 16712A, and 16600A-series built-in logic analyzer but much of the triggering setup will not transfer. Labels, pod and clock assignments, and measurement mode will still work. Setup-and-hold values are translated by preserving the hold value and adjusting setup accordingly.

NOTE: The HP 16600A-series and HP 16700A logic analysis systems can translate

configuration files from HP 16500 and HP 16505A logic analysis systems if the measurement module is the same. If the modules are different, first load the configuration file into a module of the same model number on the new logic analysis system. Re-save the configuration, then load this configuration into the destination module on the new system.

See Also Loading Configuration Files (see the HP 16600A/16700A Logic Analysis

System help volume)

Saving Configuration Files (see the HP 16600A/16700A Logic Analysis System help volume)

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

When Something Goes Wrong

•“Nothing Happens” on page 34

•“Error Messages” on page 33

•“Suspicious Data” on page 34

•“Interference with Target System” on page 33

Interference with Target System

When Something Goes Wrong

Capacitive Loading on the Target System

Excessive capacitive loading can degrade signals, resulting in suspicious data or even system lockup. All analysis probes add capacitive loading, as can custom probes you design for your target. To reduce loading, remove as many pin protectors, extenders, and adapters as possible.

Careful layout of your target system can minimize loading problems and result in better margins for your design. This is especially important for systems running at frequencies greater than 50 MHz.

Error Messages

“Slow or Missing Clock” on page 35

“Waiting for Trigger” on page 36

“Measurement Initialization Error” on page 35

“Maximum of 32 Channels Per Label” on page 35

“Trigger inhibited during timing prestore” on page 36

“Trigger function initialization failure.” on page 40

“Goto action specifies an undefined level” on page 41

“No Trigger action found in the trace specification” on page 41

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

When Something Goes Wrong

“No more Edge/Glitch resources available for this pod pair” on page 37

“No more Pattern resources available for this pod pair” on page 38

“Branch expression is too complex” on page 38

“Trigger Specification is too complex” on page 38

“Timer value checked as an event, but no start action specified” on page 39

“Counter value checked as an event, but no increment action specified” on

page 39

“Cannot specify range on label with clock bits that span pod pairs” on page 40

Nothing Happens

Look for an error message in the message bar at the top of the window. Common messages are "slow or missing clock" and "Waiting for trigger".

If Run briefly changed to Stop or Cancel, click the blue Navigate button, click the logic analyzer’s slot, then select the Waveform or Listing display.

See Also “Slow or Missing Clock” on page 35

“Waiting for Trigger” on page 36

Suspicious Data

Intermittent Data Errors

Unwanted Triggers

Check for poor connections, incorrect signal levels on the hardware, incorrect logic levels under the logic analyzer’s Config tab, or marginal timing for signals.

If you are using an inverse assembler or a pipeline, triggers can be caused by instructions that were fetched but not executed. To fix, add the prefetch queue or pipeline depth to the trigger address.

The depth of the prefetch queue depends on the processor that you are

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

When Something Goes Wrong

analyzing, and can be quite deep.

Another solution which is sometimes preferred with very deep prefetch queues is to add writes to dummy variables to your software. Put the instruction just before the area you want to trigger on, then trigger on the actual write to this variable. Although the instruction is prefetched, the analyzer can be set to only trigger when the write is executed.

Maximum of 32 Channels Per Label

The logic analyzer can only assign up to 32 channels for each label. If you need more than 32 channels, assign them to two labels and use the labels in conjunction.

Measurement Initialization Error

The logic analyzer module failed the internal calibration which it performs when Run is selected. An internal calibration failure can indicate either a software or a hardware problem.

Possible Causes

• Hardware failure

• Software failure

Run the Self-Test Utility (see page 42) on the logic analyzer and contact your HP Sales Office for service or software upgrades.

Slow or Missing Clock

The message "Slow or Missing Clock" only appears in state measurements. However, if you have another instrument armed by the

state analyzer, a slow or missing clock on the state analyzer will prevent the other instrument from triggering also.

Possible Causes

• Target system is not running properly

Check that the system is running properly. The logic analyzer and other probing fixtures such as pin extenders can place too much capacitive load on a system.

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

When Something Goes Wrong

• Incorrect clock specification

Make sure the target system clock matches the clock specified under Sampling. Also check that the probe's clock channels are attached to the target's clock lines either directly or through an analysis probe. If you are using an analysis probe, the probe's User's Guide should show the correct connections and settings.

• Bad probe connection

Check that the probe is securely attached to the clock line and is receiving a signal. The logic analyzer shows activity indicators under the Sampling and Format tabs.

• Incorrect signal level

The clock's threshold level is set by the pod threshold. For the logic analyzer's J clock, check the pod threshold of pod 1 of the master card.

See Also “Performing Clock Setup (State only)” on page 45

“Setting the Pod Threshold” on page 60

Trigger inhibited during timing prestore

The "trigger inhibited" informational message appears when you have a logic analyzer making a timing measurement, and it is set to a slow sample rate. The logic analyzer will fill the designated amount of pretrigger memory before checking for the trigger condition.

To calculate how long this should take, multiply the sample rate by the percentage of pre-trigger memory and the acquisition depth. For example, if

sample period = 1.0 ms (sample rate = 10

samples/sec.)

trigger position = center (percentage of pre-trigger memory = 50%)

acquisition depth = 64K (roughly 64 x 10

samples)

then the approximate time is 32 seconds.

Waiting for Trigger

This message indicates that the specified trigger pattern has not occurred. This may be expected, as when you are waiting to trigger on

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

When Something Goes Wrong

an unusual event.

Possible Causes

• Misaligned boundaries for addresses

When the target is a microprocessor that fetches only from long-word aligned addresses, if the trigger is set to look for an opcode fetch at an address that is not properly aligned, the trigger will never be found.

• Trigger set incorrectly

Some strategies you can use when verifying or debugging trigger sequence levels are:

• Look at the run status message line or open the Run Status window. It will tell you what level of the sequence the logic analyzer is in.

• Stop the measurement and look at the data that was captured. This is particularly useful when you use store qualifiers to store "no states" (or only the states you are interested in) and the branches taken are stored.

• Save the trigger setup, then simplify it to see what part of the sequence does get captured. When you learn what needs to be changed, you can recall the original trigger setup and make changes to it.

See Also “Default Storing (State only)” on page 89

“Saving and Recalling Trigger Sequences” on page 73

No more Edge/Glitch resources available for this pod pair

This error occurs when you have used more than 2 edges or glitches per pod pair in the trigger specification.

Possible Solutions

• Phrase some of the edges as patterns.

For example, if you are looking for a rising edge on a read/write line, you can check for R/W = 0 in one level followed by R/W = 1 in the next level.

• Move some of the edges to another pod pair.

Even if a label spans pod pairs, only the edge resources of the pod pair the specific channel is on are used.

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

When Something Goes Wrong

No more Pattern resources available for this pod pair

This error occurs when you have used up all the pattern resources available. Each pod pair has about 28 pattern resources. Some pattern events use more than 1 resource.

Possible Solutions

• Keep labels within a pod pair

If a label (bus) spans pod pairs (for example, pods 2 and 3) then when you use the label in a trigger sequence it will use up at least one pattern resource on both pod pairs. If you hook up your probes in such a way that the signals are on a single pod pair, you can free up a pattern resource on the other pod pair.

• Move some labels to another pod pair

Each pod pair has its own set of pattern resources. Putting your two mostused labels on different pod pairs can improve your resource usage.

Branch expression is too complex

The "Branch expression is too complex" message means that the trigger sequence compiler could not allocate enough space to evaluate all events in the indicated branch.

Other branches may also be too complex. The trigger sequence compiler stops compiling when it encounters the first fatal error.

Possible Causes

• More than 16 events OR'd together.

Because of hardware limitations, the trigger sequence compiler can only OR together up to 16 simple events.

Trigger Specification is too complex

The "Trigger Specification is too complex" message means that the trigger sequence compiler could not allocate enough combination resources to evaluate the expression.

The root cause of the problem is that the compiler has run out of the

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When Something Goes Wrong

buses it combines events with.

Possible Causes

• More than 16 events OR'd together.

If you have more than 16 events OR'd together, even if they are in different sequence levels, the compiler may run out of combiners. One way to conserve combiner resources is to change ORs to ANDs. This method uses DeMorgan's Theorem and will not help if there are more ANDs than ORs in the trigger sequence.

a. Click the trigger sequence level and choose Breakdown function.

b. Change ORs to ANDs.

c. Click IF and select IF NOT.

• Resouces also being used for store qualification.

If Default Storing contains Store by default Custom, and the events do not match those of the trigger sequence, the logic analyzer has to split resources between the two. If you can change your default storing slightly to match the trigger sequence events, you may be able to use the trigger sequence as originally entered.

Timer value checked as an event, but no start action specified

This warning occurs because you have used a timer in your trigger sequence, but do not start it with either Start from reset or Resume in

any action. You do not need to start the timer in the same sequence level. The timer will still function if not started, but will not change value.

Counter value checked as an event, but no increment action specified

This warning occurs because you have used a counter in your trigger sequence, but do not have Counter Increment as an action. You do not

need to increment the counter in the same sequence level. The counter event will still function, but will not change value. The default value for both counters is 0.

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

When Something Goes Wrong

Trigger function initialization failure.

The "trigger function initialization failure" messages mean that you tried to insert a trigger function which required a change in your setup.

Possible Causes

• Tried to insert "Wait for arm in" trigger function

A "Wait for arm in" trigger level causes the logic analyzer to wait for a signal from another module or Port In. These signals are passed through the Intermodule Bus. To prevent the logic analyzer from hanging, it must be added to the Group Run Arming Tree. To do this, open the Intermodule window by clicking the Intermodule icon in the System window. In the Intermodule window, click the analyzer icon and select any option except for Independent.

• Tried to insert "Wait for other machine to trigger" function

A "Wait for the other machine to trigger" trigger level causes the logic analyzer to wait for a signal from the other logic analyzer machine in the module. If this machine is not on, the current logic analyzer will hang. To turn the other machine on, click Pod Assignment under Format. Set the type of the other machine to State or Timing.

• In Format, no labels have bits assigned to them.

When you insert a trigger function, the logic analyzer sets up a field for you to enter values. The field length is based on the number of bits assigned to the first active label, or the label you specify. If there are no bits assigned to the label, the logic analyzer cannot complete the value field.

See Also Using the Intermodule Window (see the HP 16600A/16700A Logic

Analysis System help volume)

“Assigning Bits to a Label” on page 54

Cannot specify range on label with clock bits that span pod pairs

A label that contains clock bits being used as data bits, can only be included in a range term if the clock bits are confined to a single pod pair.

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

When Something Goes Wrong

Goto action specifies an undefined level

The "undefined level" messages mean that the trigger sequence contains goto statements that point to non-existant levels. This is detected when the trigger sequence is evaluated. The logic analyzer will not run if there are undefined levels, even if there is no possibility of the goto sequence being called.

Possible Causes

• The last sequence level calls "goto next"

To check this, click Overview under the Trigger tab.

To fix, find the "goto next" statement and change it to point to an existing level.

No Trigger action found in the trace specification

This warning occurs when the trigger sequence you specified does not have at least one trigger and fill memory or trigger and goto action. The analyzer will still acquire data, but you will need to manually stop it.

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

Testing the Logic Analyzer Hardware

In order to verify that the logic analyzer hardware is operational, run the Self Test utility. The Self Test function of the logic analysis system performs functional tests on both the system and any installed modules.

1. Disconnect all probes of the logic analyzer module.

2. If you have any work in progress, save it to a configuration file. (see the HP 16600A/16700A Logic Analysis System help volume)

3. Disconnect all loads, adapters, or preprocessors from the probe cable ends.

4. From the system window, click the System Admin icon.

5. Click the Admin tab, then Self Test....

The system closes all windows before starting up Self Test.

6. Click Master Frame. If the module is in an expansion frame, click Expansion Frame.

7. Click the logic analyzer that you want to test.

8. In the Self Test dialog box, click Tes t A ll. You can also run individual tests by clicking on them. Tests that require you to do something must be run this way.

If any test fails, contact your local Hewlett-Packard Sales Office or Service Center for assistance.

See Also Self Test (see the HP 16600A/16700A Logic Analysis System help

volume)

HP 16717A 333 MHz State/2 GHz Timing Zoom Service Guide

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

The Sampling Tab

The options under Sampling tell the analyzer the overall way in which you want to make a measurement. The options include:

• The acquisition mode.

• The data sample rate.

• How much data before and after the trigger.

• How much data to acquire in all.

See Also “Naming the Analyzer” on page 48

“Turning the Analyzer Off” on page 48

“Setting the Acquisition Mode” on page 44

The Sampling Tab

“Sample Period (Timing Only)” on page 49

“Performing Clock Setup (State only)” on page 45

“Trigger Position Control” on page 50

“Acquisition Depth” on page 43

“2 GHz Timing Zoom” on page 44

Acquisition Depth

Acquisition Depth, located under Sampling and also under Trigger Settings, sets how much data will actually be acquired. While the

HP 16717A logic analyzer has a maximum memory depth of 2M samples in State Mode and 4M in Timing Mode, sometimes you may not want to wait for all that memory to fill up.

The numbers shown in the Acquisition Depth menu are approximations. The combination of count tags, pod assignments, and acquisition modes affect what choices are available. Also, the values are memory depth per channel.

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

The Sampling Tab

2 GHz Timing Zoom

Timing Zoom collects additional high-speed timing data around the trigger of the logic analyzer. It uses a 16K-sample, 2 GHz timing analyzer to sample data as closely as every 500 ps on all channels.

The Timing Zoom settings are accessed through the Timing Zoom button under Sampling.

NOTE: If you have both analyzers of the module turned on, you need to specify which

trigger you want to use Timing Zoom around. The Timing Zoom data for one analyzer may not overlap with the regular acquisition data of the second analyzer.

Tips for interpreting Timing Zoom Data

• In a state measurement, Timing Zoom data may appear to be slightly off from standard data. This is because the Timing Zoom data is asynchronous to the clock signal, whereas the standard data is not sampled until after the setup period.

• In Waveform displays, Timing Zoom and the regular data are in different windows. To view them together, select Edit -> Insert from the menu bar.

• In Waveform displays, if Timing Zoom and regular data do not correspond, check that the display is set to Seconds/div. Because Timing Zoom has a smaller sample period, when the display is set to Samples/div the data become more divergent the farther from the trigger you scroll.

Setting the Acquisition Mode

The measurement type affects all other areas of the logic analyzer setup. It is set under the Sampling tab.

If you want the logic analyzer to sample data according to the target system’s clock, select State. Each time the clock signal becomes valid, the analyzer will sample data from the system under test.

If you want the logic analyzer to sample the target system

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

The Sampling Tab

independently of its clock, select Timing. Since in timing mode the analyzer is clocked by a signal that is not related to the system under test, timing measurements capture traces of electrical activity over time. The HP 16717A logic analyzer can be split into two analyzers, but only one of them may be a timing analyzer.

State Mode and Timing Mode offer different options for the acquisition mode field in the top left corner under Controls. The acquisition mode affects the channel width, memory depth, and sample rate.

“State Acquisition Modes” on page 49

“Timing Acquisition Modes” on page 50

Performing Clock Setup (State only)

When you select State Mode, the Clock Setup area appears under the State Mode Controls in Sampling. The Clock Setup contains three controls and a display area. The clocks you specify here control when the analyzer samples your data. Ideally, the logic analyzer’s state clock setup should be identical to the target system’s clock. Differences could result in invalid data.

Mode field

The Mode field lets you select among Master only, Master/slave, and Demultiplex. The default is Master only. When you select the others,

another control to set the slave clock appears at the bottom of the Clock Setup area. It also enables the Pod Clock field under Format.

For more detail on the uses of Master/slave and Demultiplex clocking, see “Clock Modes (State only)” on page 46.

Advanced Clocking

Advanced clocking allows you to specify clock qualifiers on individual clock edges instead of the group of clock edges. When you select it, the individual clock channels are replaced by Master Clock... or Slave Clock... Clicking these brings up a dialog that lets you combine edges

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

The Sampling Tab

and qualifiers in more complex Boolean expressions. When you switch from Advanced Clocking to regular clocking, some of the qualifiers are erased.

Clock Channel Specifiers

The clock channel specifiers graphically show your clock setup. Edges are ORed ("+") together, and qualifiers are ANDed (".") to all edges. To qualify just one of the edges, switch to Advanced Clocking.

All clock channels for the clock setup must be on the pods of the master card of the module, but the pods do not need to be part of the state measurement.

See Also “Clock Modes (State only)” on page 46

Clock Modes (State only)

The Pod Clock field under Format appears when a clock mode other than Master only is selected in Sampling. The Pod Clock field indicates whether a pod’s data lines are to be sampled into memory by the master clock, slave clock, or both (demultiplex).

The Pod Clock field and the clocking arrangement are only available in a state analyzer.

Master

Data on all pods assigned to Master Clk is strobed into memory when the status of the clock lines match the clocking arrangement specified for Master in the clock setup.

Slave

Data on a pod designated Slave Clock is latched when the status of the slave clock inputs meet the requirements of the slave clocking arrangement. Then, followed by a valid master clock, the slave data is strobed into analyzer memory along with the master data.

If multiple slave clocks occur between master clocks, only the data latched by the last slave clock prior to a valid master clock is strobed into analyzer memory.

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The Sampling Tab

Latching Slave Data

Demultiplex

The demultiplex mode is used to store two different sets of data that occur at different times on the same channels. In demultiplex mode, only one pod of the pod pair is used, and that pod is selectable (see page 59). Channel assignments are displayed as Pod and Slave Pod. Assign slave and master data to separate labels for easy recognition of the two sets of data.

Both the master and slave clocks are used in the demultiplex mode. When the analyzer sees a match between the slave clock input and the slave clock arrangement, demux slave data is latched. Then, following a valid master clock, the slave data is strobed into analyzer memory along with the master data. If multiple slave clocks occur between master clocks, only the data latched by the last slave clock prior to the master clock is strobed into analyzer memory.

Latching Demultiplex Data

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

The Sampling Tab

Naming the Analyzer

The Analyzer Name field under Sampling lets you assign a specific name to the analyzer. When you have stored several measurement setups to disk and later reload them, having assigned a specific name to an analyzer can help identify what the setup is for. The analyzer name is also used in the workspace to label the analyzer icons and as part of the title of the analyzer setup window.

There are two analyzers per logic analyzer module. To activate the second one, go to the Workspace window and drag the second analyzer on to the workspace.

The default names for the analyzers are Analyzer<N> and Analyzer<N2>, where N is the slot of the analyzer module.

To Name an Analyzer

1. Click the Analyzer Name field.

2. Type in the new name.

The name now appears below the instrument tool icon in the workspace.

Turning the Analyzer Off

The On and Off checkboxes under the Sampling tab are a shortcut for activating and de-activating the analyzer.

Analyzers come up in the On state. If you select the checkbox, the label changes to Off and the Analyzer Shutdown Options dialog appears.

Soft

"Soft" shutdowns have the same effect as though you clicked Off in the Type control of the Pod Assignment dialog under Format. The analyzer window remains, but most options are unavailable. Soft shutdowns are easily reversed by clicking the box next to Off.

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

The Sampling Tab

Hard

"Hard" shutdowns have the same effect as deleting the analyzer icon from the workspace. The analyzer window and the windows of its display tools are closed, and the analyzer is removed from the workspace. To turn the analyzer back on, click the analyzer icon in the System window. You will need to restore any complex analysis or display tools.

Sample Period (Timing Only)

Sample Period is used to set the time between data samples. The inverse of sample period is sample rate. Every time a new sample is taken, the analyzer will see updated measurement data. The choices available for sample period depend on the acquisition mode.

If your analyzer is set to timing, the Sample Period control is located under the Sampling tab’s Timing Mode Controls and under the Trigger tab’s Settings sub-tab.

If your analyzer is set to state, the Sample Period control is not available. Its functionality is handled by the Clock Setup.

State Acquisition Modes

167 MHz / 2M State

All pods are available. Memory depth is 2M samples per channel. If time or state count is turned on in Trigger Settings, the total memory is split between data acquisition storage and time or state count storage. To maintain the full memory depth of 2M samples per channel, leave one pod pair unassigned. (To unassign a pod pair, click Pod Assignment under Format, then drag a pod pair to unassigned.) State clock speed matches your target system’s clock, up to 167 MHz.

333 MHz / 2M State

Similar to the 167 MHz State mode, except clocking is restricted to the J clock on Pod 1 of the master card of the module, and triggering is restricted to two trigger functions.

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

The Sampling Tab

NOTE: When Store Qualification is performed in the 333 MHz State mode, there may

be the case where data occupying memory is further disqualified. As a result, you may see a non-contiguous listing of states as well as a reduction of usable memory.

Timing Acquisition Modes

In conventional timing acquisition mode the analyzer stores measurement data at each sampling interval.

333 MHz Full Channel 2M Sample

The total memory depth is 2M samples per channel, with data being sampled and stored as often as every 3 ns. You can set the sample rate to go slower with the Sample Period control.

667 MHz Half Channel 4M Sample

Only one pod of each pod pair is available. Channels assigned to unavailable pods are ignored. You can specify which pod to use by toggling the Pod field in Format. The total memory depth is 4M samples per channel. Data is sampled and stored every 1.5 ns; this rate cannot be changed.

See Also “Sample Period (Timing Only)” on page 49

“Pod Selection” on page 59

Trigger Position Control

The Trigger Position control, located under Sampling and also Trigg e r Settings, determines how much data is stored before and after the trigger occurs for all subsequent acquisitions. The trigger point is

placed at a specified position relative to the data in memory. The analyzer triggers differently depending on if it is in Timing or State mode.

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

The Sampling Tab

Timing Mode

When a Run is started, the analyzer will not look for a trigger until at least the proper percentage of pretrigger data has been stored. After a trigger has been detected, the specified percentage of posttrigger data is stored before the analyzer halts.

State Mode

When the Run is started, the analyzer immediately looks for the trigger condition. The percentage of pretrigger data determines the maximum amount of pretrigger data to save.

The trigger position choices are Start, Center, End, or User Defined.

• Start

The trigger position is set at the starting point of available memory. This process results in maximum posttrigger data and minimum pretrigger data. Note that there will be a small amount of pretrigger data stored.

• Center

The trigger position is set at the center point of available memory. This results in half pretrigger data and half posttrigger data.

• End

The trigger position is set at the end point of available memory. This results in maximum pretrigger data and minimum posttrigger data. Note that there will be a small amount of posttrigger data stored.

• User Defined

When the trigger position is set to User Defined, a trigger position slider appears. Use this slider to set the trigger position any where between 0% and 100%. As the slider is adjusted, the % Post Store indicator shows the amount of data that will be stored after the trigger point.

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

The Format Tab

Under Format, you specify the parts of the target system that you want the logic analyzer to look at. You set up labels to match the buses of the target system, and set the threshold level for the signals. For a state measurement, you also adjust the setup and hold time.

For advanced measurements, Format is also where you assign pods and specify whether to look at channels on the master, slave, or demultiplexed clock.

Common Measurement Controls

Advanced Measurement Controls

See Also “Data On Clocks Display” on page 54

“Labels: Mapping Analyzer Channels to Your Target” on page 58

“Setting the Pod Threshold” on page 60

“State Clock Setup/Hold (State only)” on page 60

“Assigning Pods to the Analyzers” on page 53

“Clock Modes (State only)” on page 46

“Setting Up the Pod Clock” on page 58

“Pod Selection” on page 59

“Activity Indicators” on page 52

“Assigning Bits to a Label” on page 54

“Inserting and Deleting Labels” on page 55

“Turning Labels On and Off” on page 56

“Reordering the Bits in a Label” on page 57

“Label Polarity” on page 56

Activity Indicators

Activity indicators are the arrows and dashes associated with the pods.

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The Format Tab

They appear in various places, primarily above the column of bit assignment fields in Format and in the Clock Setup area.

When the logic analyzer is properly connected to an active target system, you see arrows in the Activity Indicator displays for each

channel. An active channel looks like .

A dash at the top of the activity indicator display indicates that the signal connected to that channel is electrically high (above the threshold voltage). A dash at the bottom indicates that the signal is electrically low. An arrow indicates that the signal is transitioning.

Activity indicators are not affected by label polarity. (see page 56)

You can use these indicators to check whether there is proper probe connection: bits that are stuck high or low may not be properly connected. You can also verify that the signals in your target system are active: bits that are stuck high or low are not crossing the threshold voltage.

Activity indicators are not displayed during an acquisition.

See Also “Setting the Pod Threshold” on page 60

Logic Analysis System and Measurement Modules Installation Guide for details on probing

Assigning Pods to the Analyzers

The Pod Assignment... button under Format can be used to start the second analyzer on the module and to assign pod pairs.

To Assign Pods to an Analyzer

1. In Format, click Pod Assignment... The Pod Assignment window appears.

2. Drag a pod pair and drop it below the analyzer that you want to assign it to.

3. For pods that you do not want to use, drag and drop them in the Unassigned Pods area. This preserves memory depth when count is turned on.

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The Format Tab

NOTE: When both analyzers are turned on, pods 1/2 and 3/4 of the master card can

not be assigned to the same analyzer.

Pods can only be assigned on a per-pair basis to either of the two analyzers. Each pod pair has two clock channels, but only the clock channels of pods on the master card can be used in the analyzer’s clocking setup. These pods do not need to be assigned to that particular analyzer, however.

To turn on an analyzer that is off, click Off and select State or Timing. (Only one analyzer at a time can be set to Timing.) A second analyzer window appears after a pause for setup.

Data On Clocks Display

The Data On Clocks display column, to the left of the pods’ bit reference line, is a display of all clock inputs available as data channels in the present configuration. This includes those clocks on expander cards, which cannot be used in the clock setup.

To use a clock channel as a data channel, assign the clock bit to a label. Labels containing clock bits cannot be used in range terms where the clock bits span more than one pod pair.

Activity indicators above the clock identifier show signal activity.

See Also “Assigning Bits to a Label” on page 54

“Activity Indicators” on page 52

Assigning Bits to a Label

The bits in a label correspond to the physical logic analyzer probe channels. When you run the analyzer, data is gathered on all bits

(channels) that are assigned to labels. Unassigned bits are inactive.

( * ) (asterisk) indicates an assigned bit. ( . ) (period) indicates an unassigned bit. ( R ) indicates an assigned bit in a reordered label.

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To Assign Bits

1. Click the bit assignment field to the right of the label name you want to define. Each bit assignment field corresponds to the data pod which is listed above it.

2. Either select one of the predefined groups, or Individual.

3. In Individual, click the bits to toggle them between an asterisk and a period.

NOTE: Labels can have a maximum of 32 channels assigned to them.

Bits assigned to a label are numbered from right to left. The least significant assigned bit on the far right is numbered 0. The next assigned bit to the left is numbered 1, and so on. Labels can contain bits that are not consecutive; however, bits are always numbered consecutively within a label. Above each column of bit assignment fields is a bit reference line that shows you the bit numbers and activity indicators.

The Format Tab

See Also “Reordering the Bits in a Label” on page 57

“Activity Indicators” on page 52

Inserting and Deleting Labels

To Insert Additional Labels

1. Click the label name that you want to insert another label next to.

2. Choose Insert before... or Insert after....

To Delete Labels

1. Click the label name that you want to delete.

2. Choose Delete.

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The Format Tab

The bit assignments of deleted labels are not saved. You can make a label inactive but not lose its assignment by turning it off (see page 56) instead.

Turning Labels On and Off

You may want to turn off labels that you have created so that the label is not displayed. When a label is turned off, its name and bit assignments are preserved.

To Turn Off a Label

1. Right-click the label name that you want to turn off.

2. Choose Label [ON] to toggle it off. If the label is the only one, it cannot be turned off or deleted. If there is more than one label but it is the only one on, turning it off turns the first label back on.

To Turn On a Label

1. Right-click the label name that you want to turn on.

2. Choose Label [OFF] to toggle it on.

To Display a Label that was Off

1. Turn on the label.

2. At the bottom of the window, click Apply. The label’s data appears in the display windows.

Label Polarity

The analyzer uses the label polarity to identify patterns when triggering and displaying data.

To change the label polarity, select the polarity field, which toggles between positive (+) and negative (-). Positive polarity means that a high voltage is a logical "1". Negative polarity means that a high voltage is a logical "0".

Changing the label polarity after you have set up other parts of the measurement changes these things:

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The Format Tab

• "1" and "0" values flip in trigger terms

• waveforms and bus values (where shown) invert in the Waveform Display

tool

• "1" and "0" values flip in the Listing Display tool

Changing the label polarity does not change these things:

• Edge definitions for clock setup and edge terms

• Symbol definitions for the logic analyzer

The default polarity for all labels is positive (+). The various display tools, in particular the Waveform Display tool, all show logical values and are affected by polarity changes.

NOTE: Negative logic is rare in circuits. The main exception at this time is RAMBUS.

Reordering the Bits in a Label

The bit reorder feature allows the channel order, as it appears in the label, to be assigned independently of the physical order. This feature allows the probe tips for each channel to be physically connected where convenient. The Reorder function can then be used to logically rearrange the bits in a label.

NOTE: Reordered labels can not be used as range terms in triggers.

To Reorder the Bits in a Label

1. Click the label name that you want to reorder.

2. Select Reorder Bits.

3. Set the bit order by using one of the following options:

• To reorder the bits individually, for each channel, type the number of the bit you want to map the channel to. You can also use the Spin Buttons to scroll through the list of bits.

• To arrange the bits sequentially, click the button at the top of the dialog, then select Default Order.

• To swap the high and low order bytes or words, click the button at the

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The Format Tab

top of the dialog, then select Big-Endian/Little-Endian.

4. Click OK. The label now shows an "R" to indicate bit assignment.

Labels: Mapping Analyzer Channels to Your Target

Labels group and identify related channels, such as buses, in a way that is relevant to your system under test.

A single label can include data and clock channels from more than one pod, but this places restrictions on the complexity of the trigger later.

You can define 126 labels per analyzer. Each label can contain up to 32 channels per label.

To Define a Label

1. (Optional) Click the label name field and select Rename

2. Type a new name and click OK.

3. Assign bits (see page 54) to the label.

4. If necessary, insert more labels (see page 55) in the list.

See Also “Assigning Bits to a Label” on page 54

“Reordering the Bits in a Label” on page 57

“Inserting and Deleting Labels” on page 55

“Turning Labels On and Off” on page 56

“Label Polarity” on page 56

Setting Up the Pod Clock

There is one Pod Clock field for each pod in the machine. It only becomes visible when the Clock Setup under the Sampling tab is set to Master/Slave or Demultiplex. The Pod Clock field is located just

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

below the Pod Threshold in Format.

The Pod Clock field is set to Master Clk by default. Use the Pod Clock field to indicate if the pod’s data is to be strobed into memory by the master clock, slave clock, or both, in the demultiplex mode.

When the Pod Clock is set to Demultiplex, only one pod of a pod pair is usable. That pod latches data on both the master and slave clocks, so it appears twice in the label area. To select which pod of a pod pair you want to demultiplex, click the Pod Field.

See Also “Performing Clock Setup (State only)” on page 45

“Clock Modes (State only)” on page 46 for details on slave and demultiplex

clocks

“Pod Selection” on page 59

The Format Tab

Pod Selection

The Pod field in Format identifies which pod of a pod pair the settings of the bit assignment field, pod threshold field, and pod clock fields effect. Most of the time it is simply informational. The exceptions are noted below.

Half-Channel Mode

In the half-channel mode, the Pod field becomes a button that you can use to select which pod of a pod pair all pod settings apply to. In the full-channel modes, this field is simply an identifier and is not selectable.

Demultiplex Clock Mode

In the demultiplex clock mode, use the pod field to select which pod of a pod pair is to be used to sample data. In the master or slave clock modes, this field is simply an identifier and is not selectable.

See Also “Setting the Acquisition Mode” on page 44

“Performing Clock Setup (State only)” on page 45

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The Format Tab

Setting the Pod Threshold

The pod threshold is a voltage level which the data must cross before the analyzer recognizes it as a change in logic levels. You can specify a threshold level for each pod. The level specified for the master pod that includes the clock is also used for the clock threshold.

To Set the Threshold

1. Under the Format tab, click the threshold field. The threshold field is located just below the pod name.

2. In the Pod threshold dialog, choose one of the threshold options described below.

3. If you do not want the change to apply to all pods, click the checked box next to Apply settings to all pods.

4. Click Close.

NOTE: The clock threshold level is the same as the level assigned in the Pod

Threshold field.

TTL

The threshold level is +1.5 volts.

ECL

The threshold level is -1.3 volts.

USER

When USER is selected, the threshold level is selectable from -6.0 volts to +6.0 volts.

State Clock Setup/Hold (State only)

Setup/Hold in Format adjusts the relative position of the clock edge with respect to the time period that data is valid. It is only available

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when the analyzer is set up for a state measurement.

To Change Clock Setup/Hold

1. Click the Setup/Hold button.

2. For each label, enter a setup and hold. The values are adjustable in 100 ps increments, with a fixed window of 2.5 ns.

3. If you need to adjust bits individually,

a. Select a label containing the bit.

If a bit is used in more than one label, this will change its setup and hold for its use in all labels.

b. Click Individual bits.

c. Enter the bit number you want to change.

d. Adjust the setup and hold.

4. Click OK.

The relationship of the clock signal and valid data under the default setup and hold is shown in the figure below for a generic logic analyzer.

Default Setup and Hold

If the relationship of the clock signal and valid data is such that the data is valid for 1 ns before the clock occurs and 3 ns after the clock occurs, you will want to use the 1.0 setup and 2.5 hold setting.

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The Format Tab

Clock Position in Valid Data

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The Trigger Tab

The Trigger tab is used to set up a sequence that tells the analyzer when to capture data. The key event is the trigger. In the HP 16717A logic analyzer, you can insert multiple trigger actions. When you insert multiple trigger actions, the trigger marker in the Display windows is placed on the first sample whose evaluation caused a branch through an associated trigger action.

The Trigger tab has two main areas: On top, tabs of functions and controls to build your trigger; and beneath the tabs, the current trigger sequence.

Some controls are also located in the logic analyzer window’s menu bar.

•“Understanding Logic Analyzer Triggering” on page 66

•“Setting Up a Trigger” on page 69

•“Inserting and Deleting Sequence Steps” on page 70

•“Editing Sequence Levels” on page 72

•“Setting Up Loops and Jumps in the Trigger Sequence” on page 72

•“Saving and Recalling Trigger Sequences” on page 73

•“Clearing Part or All of the Trigger” on page 74

See Also “Overview of the Trigger Sequence” on page 75

“Trigger Functions” on page 76

“Trigger Function Libraries” on page 77

“Working with Advanced Functions” on page 86

“Defining Events” on page 89

“Trigger Position Control” on page 50

“E-mail Notify on Trigger” on page 65

“Sample Period (Timing Only)” on page 49

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The Trigger Tab

“Tagging Data with Time or State Tags (State Only)” on page 93

“Default Storing (State only)” on page 89

“Arming Control - Multiple Instruments and Analyzers” on page 30

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E-mail Notify on Trigger

The E-mail on Trigger option is set within the trigger sequence. It directs the logic analyzer to e-mail you with a notice informing you that the analyzer has triggered and has started to fill memory. The automatically generated text is shown as follows: Example: system14 : Slot C : Analyzer C has triggered

Where system14 is the analysis system IP address or alias you have assigned to it; Slot C is the frame slot the module is in; Analyzer C identifies the specific analyzer module from others when configured in a multi-module frame configuration. Any text you add in the text entry area of the e-mail setup dialog will appear after the automatically generated text.

It should be noted that if you have specified the analyzer to store all states, and you are using a deep memory analyzer, even though you have been notified of a trigger, the analyzer could be busy filling memory for a period after your e-mail notification.

Setting Up E-mail on Trigger

The following procedure is performed under the Tri gger - Trigger Functions tabs, and from the trigger sequence level(s) that include

the trigger action. If you have a trigger sequence that includes multiple trigger actions (multi-level branching), and one trigger action includes sending e-mail, then e-mail is sent if any sequence level triggers. In other words, you cannot designate a different e-mail destination for each trigger action in a multi-level branching trigger sequence setup.

1. From a trigger sequence level that includes the trigger command, select the trigger action field and set it to Trigger, send e-mail, and fill memory.

2. Select the Setup field that appears.

3. Type in the name of your SMTP (see page 66) mail server. Contact your System Administrator if you do not know this information.

4. Type in the e-mail address(es) of who you want the message sent To: . Use a space to separate multiple addresses.

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E-mail Notify on Trigger

5. Type in the e-mail address of who the message is being sent From:. By default, this is the login name followed by @ followed by the hostname of your logic analyzer. If the SMTP server has a problem with the default sender address, you may want to specify one that is recognizable by the server. A possible address might be the one specified in the To : field.

6. Select Email on Repetitive Run if you want mail at each trigger of a repetitive run.

7. Select OK.

What is SMTP

SMTP (Simple Mail Transfer Protocol) is a TCP/IP protocol used in sending and receiving e-mail. A protocol is the special set of rules for communicating the end points in a telecommunication connection as they send signals back and forth.

Protocols exist at several levels in a telecommunication connection. There are hardware telephone protocols. There are protocols between the end points in communicating programs within the same computer or at different locations. Both end points must recognize and observe the protocol.

On the Internet, there are the following TCP/IP protocols:

• TCP (Transmission Control Protocol), which uses a set of rules to exchange messages with other Internet points at the information packet level.

• IP (Internet Protocol), which uses a set of rules to send and receive messages at the Internet address level.

• HTTP, FTP, SMTP and other protocols, each with defined sets of rules to use with other Internet points relative to a defined set of capabilities.

Understanding Logic Analyzer Triggering

What is a Trigger (see page 67)

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E-mail Notify on Trigger

What does "Trigger Position" Mean (see page 67)

What can be Used to Specify a Trigger (see page 67)

When to use a Combination, a Branch, or a Level (see page 68)

What is a Trigger

In simplest terms, a trigger is an event that tells the logic analyzer to finish filling its acquisition memory. The memory functions like a conveyor belt: new samples are always coming in, and old samples "falling off" (being overwritten). The logic analyzer has room for 2M samples. When this is full, the only way to fit in new data is to discard the old.

After you specify your trigger sequence and press run, the logic analyzer searches incoming data for events in the trigger sequence. Using the conveyor belt metaphor again, it is like someone tending the conveyor belt who has been told to stop the belt when a certain sample is seen.

The trigger is not like an oscilloscope trigger. Logic analyzers trigger only once per run, even when more than one sample matches the trigger event. Logic analyzer trigger events are like special switches to stop the evaluation process and just fill memory.

What does "Trigger Position" Mean

Because the logic analyzer is continually looking at data from your target system after you select Run, and because the trigger is a single event, you can arrange to collect data relative to it. It is like the person running the conveyor belt is told to stop the belt when the special sample reaches a certain position.

The default trigger position is in the middle. This means there are approximately as many samples before the trigger as after. You can also arrange for the trigger to be at the beginning of the "conveyor belt" (acquisition memory), the end, or any percentage along it.

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What can be Used to Specify a Trigger

The trigger sequence can be as simple as one event to look for, or a complicated set of branching levels that loop back and jump around. Both types of triggers use a small set of standard resources.

Label events Label events can look for a pattern on a bus, such as

ADDR<0880 or R/W=1. They can also look for values in (or out) of a range.

Tim er Timers are started in one sequence level and checked in another.

They act like stopwatches.

Edge Edge terms are similar to edges in oscilloscopes. They are only

available for some types of measurements. Edge terms can check for edges on more than one signal at a time, but not all edges have to occur at the same time. To require that, combine edge terms with ANDs.

Combinations of Events To check for more than one type of thing

happening in the same sample, combine events within a sequence level using AND and OR.

When to use a Combination, a Branch, or a Level

To check for simultaneous occurrences, use combinations of terms. All the events described by the terms must happen in the same sample.

To take different actions depending on which events happen in a sample, use branches within a sequence level. A branch functions like a set of "if statements" in programming. The sample is checked against all branches, and the first branch that matches is taken. See “Setting Up Loops and Jumps in the Trigger Sequence” on page 72 for more on branching.

To look for a sequence of events (for example, first look for a memory reference on ADDR, then a certain value on DATA, and when IRQ goes low, trigger) use different sequence levels. When a sample matches the event described in a sequence level, the analyzer goes to the next sequence level and compares the rest of the incoming events. When the logic analyzer reaches the trigger level and finds a sample that matches the trigger event you specify, the logic analyzer triggers.

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See Also “Setting Up a Trigger” on page 69

“Defining Events” on page 89

“Using Group Events” on page 92

Setting Up a Trigger

When setting up a trigger sequence, you typically trigger first on a simple pattern or edge. From that point, you execute an iterative process of adding or fine-tuning sequence levels until the analyzer consistently triggers at the desired point.

To Set Up a Trigger

1. Select the most appropriate trigger function and click replace. (see page 70)

E-mail Notify on Trigger

2. Define events. (see page 89)

3. If necessary, insert additional sequence levels. (see page 70)

When creating a trigger sequence to describe the sequence of pertinent events on your target system, you need to know if you are looking for

• events happening at the same time,

• different events that might be happening next, or

• a sequence of events.

For events happening at the same time, set up the trigger sequence to look for multiple events in the same level.

For different events that might be happening, the trigger sequence depends on what you want to do based on the events. If you want to take different actions or look for different occurrences afterwards, use separate branches (If-then-else if) within a sequence level. If it is only that different actions could lead to the same problem, group the events using AND and OR within a single branch of a single sequence level.

For a sequence of events, check for each event in a separate sequence

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level.

See Also “Trigger Functions” on page 76

“Working with Advanced Functions” on page 86

“Overview of the Trigger Sequence” on page 75

“E-mail Notify on Trigger” on page 65

Selecting a Function to Match Trigger Conditions

Review the list of trigger functions and select the one that matches the event you are looking for. In most cases one of the predefined functions provides a good starting point. If none of the predefined trigger functions match choose User level at the end of the list.

For a picture corresponding to the trigger function, select the function from the list. The area to the right shows a picture of the function’s effect. The function itself is not inserted into the trigger sequence unless you click Replace or Insert.

See Also “Trigger Functions” on page 76

Inserting and Deleting Sequence Steps

NOTE: For state measurements, the last level of the trigger sequence is always a

Store level. It cannot be deleted. For timing measurements, the last level must contain the TRIGGER action.

To Insert Sequence Steps

1. Click the sequence step that you want to insert other steps around.

2. Select a trigger function from the list under Trigger Functions.

3. Click Insert Before or Insert After.

To Delete Sequence Steps

1. Click the sequence step that you want to delete.

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2. Select Delete.

E-mail Notify on Trigger

Trigger Sequence Editing Options

When you click a sequence step, you see a selection menu with choices that allow you to modify the sequence. Choose the option you want from the choices below.

• Edit Changes the contents of the sequence step. You can change the resource terms or other assignment fields, such as durations and occurrences.

• Copy Copies the currently selected step. When you copy a level, the new level contains the same function as the original.

• Replace Replaces the currently selected level with the currently highlighted trigger function.

• Delete Deletes the level that is currently selected.

• Insert Before / Insert After Inserts an additional step before or after the selected step.

• Trigger Level (State only) Makes the current step the trigger level.

• Default (State only) Only appears in the menu for the last step in a state trigger sequence. The last state always stores to fill memory. Default returns the state to Store

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anystate.

Editing Sequence Levels

You can modify the contents of a level in the trigger sequence by editing the fields in it.

To Edit a Sequence Level:

1. Click the sequence step to make it editable. A yellow box appears around the level, and the editable fields become controls.

2. To replace it with a different function, double-click the desired function in the event list.

3. Click on an event to replace it with a different event, or insert additional events.

4. Set the values of the other fields, such as durations and occurrence counts.

See Also “Setting Pattern Duration and Occurrence Count” on page 88

“Using Occurrence Counters” on page 88

“Using Timer Terms” on page 91

“Setting Up Loops and Jumps in the Trigger Sequence” on page 72

Setting Up Loops and Jumps in the Trigger Sequence

Using Goto statements, you can set up loops or simple jumps in the trigger sequence. Loops are useful when you want to trigger after a

certain number of iterations. Jumps can be used to implement loops or just to set up parallel branches that look for different types of triggers.

Branches are implemented in the HP 16717A logic analyzer in the Advanced functions. You can also access branches in the other trigger functions by breaking them down (see page 85).

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NOTE: Use branches within a trigger sequence level when you want to test a single

sample for multiple conditions and take different actions based on which is true. Use different sequence levels when you want to test different samples.

To Set Up a Branch or Loop

1. Set up the events in the first If statement. If these events are found in the incoming data, the analyzer will execute the actions in the then portion. By default, one of the actions is Goto next.

2. To insert an Else if branch, click If and select Insert branch after.

See Also “Breaking Down and Restoring Functions” on page 85

Saving and Recalling Trigger Sequences

You can save a trigger sequence independently of configuration files within a session by using Save/Recall. Recalling a trigger sequence changes the trigger arming, memory depth, and trigger position as well as the trigger sequence and term definitions. Recalling a trigger sequence will not change the acquisition mode (full channel vs. half channel).

The HP 16717A logic analyzer provides memory locations to store up to 15 trigger sequences per machine for both state and timing. Five of the 15 memory positions are reserved for the last 5 runs. If you think you will want to recall a sequence after several runs, save it in one of the other 10 memory locations.

When you exit your HP 16600A-series or HP 16700A session, the trigger sequences are cleared. They can be saved across sessions or be shared across logic analyzers as part of a configuration file, however. You can also save parts of trigger sequences independently of configuration files by creating a trigger function library. (see page 77)

To Save a Trigger Sequence

1. In Trigger, click the Save/Recall tab.

2. Click Save.

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3. Select a memory location to store the trigger sequence in.

4. In the Buffer Name dialog, type a descriptive name for the trigger sequence.

To Recall a Trigger Sequence

1. In Trigger, click the Save/Recall tab.

2. Click Recall.

3. Choose the trigger sequence that you want.

If one of the settings in the recalled trigger sequence conflicts with the acquisition mode, it will be set to the closest setting for that mode. Also, if the trigger sequence uses a trigger function library that does not exist on this mainframe, it will not load correctly.

See Also “Loading and Saving Logic Analyzer Configurations” on page 32

“Trigger Function Libraries” on page 77

Clearing Part or All of the Trigger

To Clear Part or All of the Trigger:

1. Click Trigger.

2. Select Clear from the menu bar.

3. Choose the option you want from the choices described below:

• All

Clears the trigger sequence, acquisition depth, and trigger position back to their default values. Turns on Count Time. If the analyzer is set to State, also sets default storing back to store anything.

• Trigger Sequence

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Resets the trigger sequence to the default sequence for the analyzer acquisition mode.

• Settings Returns settings (acquisition depth and trigger position) to default settings. In state measurements, time tags are turned back on. In timing measurements, the sample period returns to its fastest setting.

• Save/Recall Memories Deletes all saved trigger sequence specifications.

• Clear Default Store (State only) Returns default storing to Store anything.

Overview of the Trigger Sequence

The trigger sequence is a sequence of steps (the levels) that control the path that the analyzer takes to find the trigger event. The path taken resembles a flow chart, with each step in the sequence being an opportunity to direct the analyzer’s selection. You can edit the overall trigger sequence by inserting or deleting sequence levels (see page 70).

Each step in the sequence is a trigger function. Most trigger functions are tailored to a specific type of measurement. The "Advanced" trigger functions let you work with the bare resources that the analyzer hardware uses. Both types of function are composed of events to evaluate, and actions to take.

When you run the analyzer, it searches for a match between the events and the measurement data. When a match is found, the logic analyzer executes any actions specified. Each function must have as one of its actions a Goto or Trigger and fill memory. This action controls what

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E-mail Notify on Trigger

level the analyzer evaluates next.

Each trigger function uses one or more of the analyzer’s internal sequence levels (see page 86). Each Advanced function uses one internal sequence level.

See Also “Understanding Logic Analyzer Triggering” on page 66 for more detail

“Setting Up a Trigger” on page 69 for actual steps

Trigger Functions

Trigger functions provide a simple way to set up the analyzer to trigger on common events and conditions. A library of functions is available for both state and timing measurements.

NOTE: Each trigger function requires at least one internal sequence level (see

page 86), and in some cases, multiple levels. The number of levels used by each function is described in the references below.

Timing Trigger Functions

State Trigger Functions

See Also “Setting Up a Trigger” on page 69

“Basic Timing Trigger Functions” on page 79

“Pattern/Edge Combinations” on page 80

“Time Violations” on page 80

“Timing User Level” on page 77

“Basic State Trigger Functions” on page 83

“Sequence-Dependent Trigger Functions” on page 83

“Time Violations” on page 84

“State Advanced Functions” on page 81

“Defining Events” on page 89

“Breaking Down and Restoring Functions” on page 85

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Trigger Function Libraries

Trigger function libraries allow you to create your own libraries of trigger sequences without having to save and load entire configuration files. They can be copied to other logic analysis systems and loaded into other logic analyzers with the function library capability.

When functions from trigger libraries are inserted into the trigger sequence, they can only be edited by breaking down the function. If a trigger sequence or configuration file uses a library that has been deleted, or a function that has been deleted from a library, the logic analyzer replaces the missing function with the default trigger function.

To Add Functions from Libraries into the Trigger Function List

1. Click Trigger function libraries...

2. Select the library from the list. Only libraries created in the same acquisition mode are available.

3. Click Load. All of the library’s functions are added to the list of Trigger Functions. The first function from the library is now selected in the list.

To Copy Trigger Function Libraries between Systems

1. Connect your logic analysis system to the network. (see the HP 16600A/ 16700A Logic Analysis System help volume)

2. Using a computer on your network, copy /hplogic/ trigger_functions/ to a central location, or directly to other logic

analyzers on the network.

Timing User Level

The Advanced trigger functions allow you to create a custom trigger sequence using events, comparison functions, and up to 4 branches.

All Advanced trigger functions use one internal sequence level.

The types of events include labels, timers, flags, and counters.

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• Advanced - If/then This function has only one branch. If the events in the "If" event list are true, it executes the actions after "then".

• Advanced - 2-way branch This function has two branches, of the form "If - then; else if - then". Each sample, the events in the first "If" branch are checked. If all events are true, then the "then" portion is executed. If they are not true, the events in the "else if" branch are checked. If the "else if" events are true, that "then" portion is executed. If neither branch is true, the logic analyzer remains in this sequence level and repeats the comparison with the next sample.

• Advanced - 3-way branch This function has three branches, of the form

If (events1) then (actions1) Else if (events2) then (actions2) Else if (events3) then (action3)

The logic analyzer evaluates each sample against the clauses in the order they are specified. The logic analyzer executes the set of actions in the "then" clause associated with the first listed "if" or "else if" clause that becomes true.

• Advanced - 4-way branch Like the 3-way branch, but with 3 "Else if" clauses.

• Advanced - pattern1 AND pattern2 Searches for two different patterns occuring in the same sample. If you set it to look for more than 1 occurrence, you can specify whether occurrences are consecutive or not. You can also add other events, including labels, to be searched for.

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• Advanced - pattern1 OR pattern2 Finds either pattern1 or pattern2 or both in a sample. If you set it to look for more than 1 occurrence, you can specify whether the occurrences are consecutive or not. You can also add other events, including labels, to be searched for.

See Also “Working with Advanced Functions” on page 86 for more information on

the user-defined mode.

Basic Timing Trigger Functions

The following basic trigger functions are found in Trigger Functions when the analyzer is in timing mode. Each function uses one internal sequence level.

• Find edge. This function becomes true when the edge you have designated is seen. It uses one internal sequence level.

• Find anystate n times. This function becomes true with the nth state it sees. It uses one internal sequence level. It is equivalent to having the analyzer wait in the sequence level for (n x Sample Period) seconds.

• Find nth occurrence of an edge. This function becomes true when it finds the designated occurrence of an edge you have designated. Note that the 500-MHz trigger sequencer may not count edges that occur closer than 2 ns. This function uses one internal sequence level.

• Find pattern present/absent for > duration. This function becomes true when it finds a pattern you have designated that has been present or absent for greater than or equal to the set

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duration. It uses one internal sequence level.

• Find pattern present/absent for < duration. This function becomes true when it finds a pattern you have designated that has been present or absent for less than the set duration. It uses five internal sequence levels.

Pattern/Edge Combinations

The following trigger functions are found in Trigger Function when the analyzer is in timing mode. These predefined functions use a pattern, edge, or a combination of both as the trigger element. The functions use either one or two internal sequence levels.

• Find edge AND pattern. This function becomes true when a selected edge is seen within the time window defined by a pattern you have designated. It uses one internal sequence level.

• Find pattern occurring too soon after edge. This function becomes true when a pattern you have designated is seen occurring within a set duration after a selected edge is seen. It uses two internal sequence levels.

• Find pattern occurring too late after edge. This function becomes true when one edge you have selected occurs, and for a designated period after that first edge is seen, a pattern is not seen. It uses two internal sequence levels.

Time Vi olat ions

The following trigger functions are found in Trigger Functions when the analyzer is in timing mode. These trigger functions are specifically tailored to trigger on events occurring out of a predefined time range. They use either one or two internal sequence levels.

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• Find width violation on a pattern/pulse. This function becomes true when the width of a pattern violates minimum and maximum width settings you have designated. It uses one internal sequence level.

• Find 2 edges too close together. This function becomes true when a second selected edge is seen occurring within a period you have designated after the occurrence of a first selected edge. It uses two internal sequence levels.

• Find 2 edges too far apart. This function becomes true when a second selected edge occurs beyond a period you have designated after the first selected edge. It uses two internal sequence levels.

• Wait t seconds This function becomes true after a period you have designated has expired. It uses one internal sequence level.

State Advanced Functions

The Advanced trigger functions allow you to create a custom trigger sequence using events, comparison functions, and up to 4 branches.

All Advanced trigger functions use one internal sequence level.

The types of events include labels, timers, flags, and counters.

• Advanced - If/then This function has only one branch. If the events in the "If" event list are true, it executes the actions after "then".

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• Advanced - 3-way branch This function has three branches, of the form

If (events1) then (actions1) Else if (events2) then (actions2) Else if (events3) then (action3)

• Advanced - 4-way branch Like the 3-way branch, but with 3 "Else if" clauses.

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searched for.

See Also “Working with Advanced Functions” on page 86 for more information on

the user-defined mode.

Basic State Trigger Functions

The following basic trigger functions are found in Trigger Functions when the analyzer is in state mode. Each macro uses one internal sequence level.

• Find Pattern n times. This function becomes true when it sees a pattern you have designated occurring a designated number of times. The pattern may occur consecutively, but does not have to. It uses one internal sequence level.

• Find anystate n times. This function becomes true with the nth state it sees. It uses one internal sequence level. It is equivalent to Wait n external clock states.

• Find pattern2 occurring immediately after pattern1. This function becomes true when the first pattern you have designated is seen immediately followed by a second designated pattern. It uses two internal sequence levels.

• Find pattern n consecutive times. This function becomes true when it sees a pattern you have designated occurring a designated number of consecutive times. It uses one internal sequence level.

Sequence-Dependent Trigger Functions

The following trigger functions are found in Trigger Functions when the analyzer is in state mode. These functions each trigger on a particular sequence of events.

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• Find too few states between pattern1 and pattern2. This function becomes true when a designated pattern1 is seen, followed by a designated pattern2, and with fewer than a selected number of states occurring between the two patterns. It uses four internal sequence levels.

• Find too many states between pattern1 and pattern2. This function becomes true when a designated pattern1 is seen, followed by more than a selected number of states, before a designated pattern2. It uses two internal sequence levels.

• Find n-bit serial pattern. This function becomes true when a specified serial pattern of n bits is found on the analyzed line. This function uses one internal sequence level for each bit specified in the trigger sequence.

• Find pattern2 n times after pattern1, before pattern3 occurs. This function becomes true when it first finds a designated pattern1, followed by a selected number of occurrences of a designated pattern2. In addition, if a designated pattern3 is seen anytime while the sequence is not yet true, the sequence starts over. This includes if pattern2's nth occurrence is at the same time as pattern3, the sequence starts over. It uses two internal sequence levels.

Time Violations

The following trigger functions are found in Trigger Functions when the analyzer is in state mode. These predefined functions are specifically tailored to trigger on events occurring out of a predefined time range. These functions use either one or two internal sequence levels.

• Find pattern2 occurring too soon after pattern1.

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This function becomes true when a designated pattern1 is seen, followed by a designated pattern2, and with less than a selected period occurring between the two patterns. It uses two internal sequence levels.

• Find pattern2 occurring too late after pattern1. This function becomes true when a designated pattern1 is seen, followed by at least a selected period, before a designated pattern2 occurs. It uses two internal sequence levels.

• Wait n external clock states. This function becomes true after a number of user clock states you have designated have occurred. It uses one internal sequence level.

Breaking Down and Restoring Functions

In the HP 16717A logic analyzer, you can either expand functions, or break them down. When you expand a function the logic analyzer shows you how the function would be implemented using Advanced functions, but you cannot edit the values. Expanded functions can be compressed back into their original form.

When you break down a trigger function, you gain access to all the resource assignment fields and branching options. You can change these fields to change the structure of the trigger sequence. You might need to do this to add events or branches to the more basic functions. When you break down a trigger function, you can return to the compressed form by selecting Edit -> Undo if you have not made any changes.

To Break Down Trigger Functions

1. Click the level number.

2. At the bottom of the menu, select Break down function. The trigger sequence area changes to show the entire trigger sequence as a series of user-level steps.

The contents of broken down functions are displayed in the long form used in a user-level sequence step. If the function uses two of the

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analyzer’s internal sequence levels, (see page 86) both levels are separated out and displayed in the trigger sequence area.

To Restore Functions

1. Click the level number.

2. Choose Compress function.

See Also “Working with Advanced Functions” on page 86 for information on working

with functions that are broken down.

How the Internal Sequence Levels Are Used

The analyzer has internal sequence levels that it uses to make up the trigger sequence. There are a total of 16 sequence levels available.

The actual number of levels used in a trigger sequence can vary depending on whether you elect to use predefined trigger functions or use the user-defined steps (see page 86) to construct a more custom trigger sequence.

When you use user-defined steps, all of the internal sequence levels are available. Each user-defined sequence level corresponds to one internal level. The only instance where multiple levels are used is when the < duration is assigned.

When you use predefined trigger functions (see page 76), more than one of the internal sequence levels may be required for a single trigger function. Even though some trigger functions use multiple sequence levels, trigger functions are easier to use, and they are the most efficient way to construct a trigger specification.

Working with Advanced Functions

NOTE: Before you begin to set up advanced sequence steps, note that in most cases

one of the predefined trigger functions (see page 76) will work.

You might need to set up an advanced sequence step to accommodate a condition not covered by the other functions, or if you need to set up

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additional loops and jumps in the sequence. Each advanced sequence step has a "fill-in-the-blanks" type statement like the more basic functions, but does not place restrictions on what you can add.

To Set Up an Advanced Function

1. In Trigger Functions, select one of the Advanced functions at the end of the list.

2. Click Replace or Insert.

3. Fill in the events as you would for a non-advanced function.

4. To change the event list in a branch,

a. click an existing event

b. choose the appropriate operation and event type from the list.

Timers, counters, and flags do not change value unless you insert an action in some level.

c. set the event values that you are looking for

d. verify that events are properly combined with OR and AND.

5. To change the actions in a branch, click an existing action then choose the appropriate operation and action type. All actions in an action list are executed when a branch is followed. If you specify Goto Next, make sure there is a next level or your logic analyzer will not run.

6. To insert a branch, click If or Else if and choose one of the operations from the menu.

For more information on the functions available in a user-defined step, refer to:

•“Defining Events” on page 89

•“Setting Pattern Duration and Occurrence Count” on page 88

•“Using Occurrence Counters” on page 88

•“Setting Up Loops and Jumps in the Trigger Sequence” on page 72

•“Using Timer Terms” on page 91

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Setting Pattern Duration and Occurrence Count

(Timing Only)

When a bit pattern is found during a trigger sequence, you can influence when the term actually becomes "true" by assigning a time duration or an occurrence count. The easiest way to do this is by using the Find pattern present for > duration and Find pattern present for < duration.

By breaking down the function (see page 85), you can also access the (present for >/occurs) control. This is also available in the Advanced functions.

To Set a Pattern Duration in Advanced Functions

1. Click (present for >/occurs) button and choose an option.

2. Set the duration or the number of occurrences.

When greater-than (>) is used, the analyzer continues sequence level evaluation only after the event has been true for greater than or equal to the time specified.

To evaluate a pattern for less-than (<), you need four internal sequence levels (see page 86). Copy the logic and branching used in the Find pattern present for < duration function. You can expose the logic by inserting the function, clicking the sequence level number, and selecting Expand function.

When occurs is selected, you can set how many times the event must appear, and whether the appearances must be consecutive or not. In functions that do not show the consecutively/eventually control, the samples may be interrupted by other values -- they do not need to be consecutive.

Using Occurrence Counters

Use the occurrence counter to delay the trigger sequence evaluation until a resource term has occurred in a designated number of samples. The samples do not need to be consecutive. Whatever positive number you assign to the counter, the pattern must be seen that number of times before the term becomes true.

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If the Else branch becomes true before all specified occurrences of the primary (Trigger on, or Find) branch, the Else branch is taken.

Default Storing (State only). When the analyzer is set to State, you can maximize memory by customizing what gets stored in memory. The controls are located in Trigger, under the Default Storing tab.

If you do not change anything, the logic analyzer is set to Store anything, which stores all samples. Store nothing prevents samples being stored, and must be overridden with a Store sample or Turn off default storing in the actions for the individual trigger sequence levels.

Store custom lets you filter the data you want to store. You can specify ranges of values that mark data of interest. You can also use the flags or timers to signal to the analyzer when you want to store data. (Be sure to set the flags or other events in the actions for the trigger sequence level.)

The HP 16717A logic analyzer does not use the "Branches taken" feature of earlier logic analyzers. The best way to simulate "Branches taken stored" is by setting up Store by default nothing, a store sample in each action sequence, and wherever you trigger, Turn off default storing.

NOTE: When Store Qualification is performed in the 333 MHz State mode, there may

be the case where data occupying memory is further disqualified. As a result, you may see a non-contiguous listing of states as well as a reduction of usable memory.

Defining Events

Events are defined in the trigger sequence. The most common event is a label. Other types of events are timers, counters, and flags. Label events let you specify patterns or ranges on a bus, or (in a timing measurement) edges and glitches.

Trigger functions restrict what sort of events you can insert. The instructions below cover the general case for labels. If you need to

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insert an event that a trigger function does not allow, first search the list for a more appropriate trigger function. If one does not exist, break down the trigger function (see page 85) and then insert the event.

To Define a Label Event

1. In a trigger sequence level, select a label and choose Insert or Replace.

2. Select the operator field to the right and specify an operation. Edge operators are only available in timing measurements, and not in all trigger functions.

3. Specify the value you want to find on the label. X means you don’t care about the values on the specified bits, and are not allowed in ranges. Edges by default look for any rising edges in the label. Click the edge assignment to change it.

Right-click on any of the value fields to quickly assign a preset value. Clear (=X) sets the value to all X (don’t cares). Set (=1) sets the value to all 1s. Reset (=0) sets the value to all 0s.

Notes on Specific Event Types

Ranges

The In range and Not in range operators consider the values you enter as the endpoints to be inside the range. Ranges cannot be set on reordered labels.

Edges The Edge operator ORs specified edges together. If you need to

AND edges, assign them to different events and join those with an AND.

Flags Flags can be used to signal between HP 16715A, 16716A, and

16717A modules. One side effect of this is that the 8 flags are shared across all modules in the system. If you have some modules in an HP 16701A expander frame, use flags 1 through 4 to signal from modules in the HP 16701A to modules in the HP 16700A, and flags 5 through 8 for the other direction. If all modules that use flags are installed in a single frame, you can use any of the 8 flags. By default, flags are Clear, and show as 0 in the Status tab.

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Timers and Counters The default values for timers are 0 ns and counters

are 0. Their values are changed by inserting appropriate actions. Start timers running with Timer Start from reset or Timer resume in an action.

See Also “Using Timer Terms” on page 91

“Using Group Events” on page 92

“Numeric Base” on page 92

“Breaking Down and Restoring Functions” on page 85

Using Timer Terms

Timers are like other events in that they are either true or false. They are controlled within the trigger sequence and act like a stopwatch. Timers start at 0, and can be set to Start, Stop, Pause, or Resume as the analyzer enters a trigger sequence level.

E-mail Notify on Trigger

The only restriction timers have is that no timer is available for the first pod pair assigned in a configuration. After the first pod pair, there is a timer available for each additional pod pair that is assigned to the measurement.

Timers are not started until you insert a Start from reset or Resume action in some sequence level. Timers continue doing whatever instruction they last received until either the acquisition completes or they receive a new instruction.

The minimum value you can test a timer for depends on the acquisition mode of the measurement.

To Include a Timer in a Trigger Sequence

1. Click an event.

• If the list mentions EVENTs, select an Insert EVENT or Replace EVENT, and choose Timer.

• If the list does not mention EVENTs, break down (see page 85) the level, then click an event.

2. Specify which timer, and the time value.

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3. Click the sequence level which should start the timer.

4. Click Trigger or Goto, and select Insert action -> Timer, and one of the actions.

5. Insert other timer actions in the same way as Step 4 as appropriate in other sequence levels.

Using Group Events

To setup an advanced sequence that evaluates multiple events as a group, instead of separate sequence levels (more common), you must reorganize all desired events in parens (). An example is when you use parens () in a complicated math equation.

Adding parens () for the purpose of grouping trigger events is a more advanced operation that can only be accessed through the "IF" operator in a sequence level. The "IF" operator is only available when you break down a Trigger Function, or, you use one of the advanced functions that contain the "IF" operator.

When the "IF" operator is available, select the "IF" operator field, then select Group Events. From the dialog that appears, follow the directions on placing parens () at the beginning and end of events.

Numeric Base

All labels have a numeric base field next to them. The base choices are Binary, Octal, Decimal, Hex, ASCII, Symbol and Twos Complement.

To Change the Numeric Base

1. Click the base button.

2. Choose the base that you want.

NOTE: If the numeric base is changed in one window, the base in other windows may

not change accordingly. For example, the base assigned to symbols is unique, as is the base assigned in the Listing window.

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Tagging Data with Time or State Tags (State Only)

The Count field under Settings in Trigger accesses a selection menu which is used to stamp the data at each memory location with either a Time tag or a State Count tag. The tags reduce the memory depth by half. To retain the full memory depth when using time or state tags leave one pod pair unassigned.

State Count

When the State Count option is selected, numbered tags are placed on all selected data. Pre-trigger data has negative numbers and posttrigger data has positive numbers. You select the data to be tagged when you turn on State Count. A field appears to the right of States that lets you define patterns.

State tag numbering can be set either relative to the previous tagged sample or absolute from the trigger point. Selecting Absolute or Relative is done by toggling the Absolute/Relative field in the Listing Display window.

Time Count

Time Count places time tags on all data. Pre-trigger data has negative time numbers and post-trigger data has positive time numbers. Time tag numbering is set to be either relative to the previous memory location or absolute from the trigger point. The time tag resolution is 4 ns.

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

Specifications and Characteristics

NOTE: Definition of Terms To understand the difference between specifications (see

page 94) and characteristics (see page 94), and what gets a calibration procedure (see page 95) and what gets a function test (see page 95), refer to appropriate links within this note.

“HP 16717A Logic Analyzer Specifications” on page 95

“HP 16717A Logic Analyzer Characteristics” on page 96

What is a Specification

A Specification is a numeric value, or range of values, that bounds the performance of a product parameter. The product warranty covers the performance of parameters described by specifications. Products shipped from the factory meet all specifications. Additionally, the products sent to HP Customer Service Centers for calibration and returned to the customer meet all specifications.

Specifications are verified by Calibration Procedures.

What is a Characteristic

Characteristics describe product performance that is useful in the application of the product, but that is not covered by the product warranty. Characteristics describe performance that is typical of the majority of a given product, but not subject to the same rigor associated with specifications.

Characteristics are verified by Function Tests.

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Specifications and Characteristics

What is a Calibration Procedure

Calibration procedures verify that products or systems operate within the specifications. Parameters covered by specifications have a corresponding calibration procedure. Calibration procedures include both performance tests and system verification procedure. Calibration procedures are traceable and must specify adequate calibration standards.

Calibration procedures verify products meet the specifications by comparing measured parameters against a pass-fail limit. The pass-fail limit is the specification less any required guardband.

The term "calibration" refers to the process of measuring parameters and referencing the measurement to a calibration standard rather than the process of adjusting products for optimal performance, which is referred to as an "operational accuracy calibration".

What is a Function Test

Function tests are quick tests designed to verify basic operation of a product. Function tests include operator’s checks and operation verification procedures. An operator’s check is normally a fast test used to verify basic operation of a product. An operation verification procedure verifies some, but not all, specifications, and often at a lower confidence level than a calibration procedure.

HP 16717A Logic Analyzer Specifications

The specifications are the performance standards against which the product is tested. These specifications apply only to the HP 16717A 333 MHz State/2 GHz Timing Zoom logic analyzer:

Maximum State Clock Speed: 333 MHz Threshold Accuracy: +/-(65 mV + 1.5% of threshold setting) Minimum Master-to-Master Clock Time: 5.988 ns at 167 MHz

3.003 ns at 333 MHz

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Specifications and Characteristics

Setup/Hold Time: *Single Clock, Single Edge: 4.5/-2.0 ns through -2.0/4.5 ns, adjustable in 100-ps increments *Multiple Edges: 5.0/-2.0 ns through -1.5/4.5 ns, adjustable in 100-ps increments

* Specified for an input signal VH=-0.9 V, VL=-1.7 V, threshold=-1.3 V, slew rate=1 V/ns

HP 16717A Logic Analyzer Characteristics

The characteristics are not specifications, but are included as additional information.

General information

- Channel Counts:

1-card module 64 data, 4 clock 2-card module 132 data, 4 clock 3-card module 200 data, 4 clock 4-card module 268 data, 4 clock 5-card module 336 data, 4 clock

Probes (at end of flying lead set)

- Input Resistance: 100 Kohm, +/- 2%

- Parasitic Tip Capacitance: 1.5 pF

- Minimum Voltage Swing: 500 mV peak-to-peak

- Minimum Input Overdrive: 250 mV

- Maximum Voltage: +/- 40 V peak CAT I

- Threshold Range: +/- 6.0 V, adjustable in 10-mV increments

- Power through pod cables: 1/3 amp per pod

State Analysis

- Maximum State Clock Speed: 333 MHz

- Maximum Memory Depth: 2 M

- *Minimum Setup/Hold Time: 4.5/-2.0 ns through -2.0/4.5 ns,

adjustable in 100-ps increments

- Minimum State Clock Width: 1.2 ns

- Minimum Master-to-Master Clock: 5.988 ns at 167 MHz

3.003 ns at 333 MHz

- Minimum Master-to-Slave Clock: 2 ns

- Minimum Slave-to-Slave Clock: 5.988 ns at 167 MHz

3.003 ns at 333 MHz

- State Clocks: 4

- State Clock Qualifiers: 4

- **Time Tag Resolution: 4 ns

- Maximum Time Count Between States: 17 seconds

- **Maximum State Tag Count: 2e32

- Store qualification Default and per sequence level

* Specified for single-edge, single-clock acquisition. Multi-edge setup/hold window is 3.0 ns. ** When all pods are being used, time or state tags halve the memory depth.

Timing Analysis Timing Zoom

- Sample Rates: 2 GHz/1 GHz/500 MHz/250 MHz

- Sample Period Accuracy: +/- 50 ps

- Channel-to-channel Skew: less than 1.0 ns

- Time Interval Accuracy: +/- (sample period + channel-to-

channel skew + 0.01% of time interval reading)

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Specifications and Characteristics

- Memory Depth: 16 K Conventional Timing

- Maximum Sample Rate: Half Channel 667 MHz Full Channel 333 MHz

- Memory Depth: Half Channel 4 M samples per channel Full Channel 2 M samples per channel

- Sample Period Accuracy: +/- (100 ps + 0.01% of sample period)

- Channel-to-Channel Skew: less than 1.5 ns, typical

- Time Interval Accuracy: +/-( sample period + channel-to channel skew + 0.01% of time interval reading)

Triggering

- Maximum Trigger Sequencer Speed: 333 MHz

- State Sequence Levels: 16

- Timing Sequence Levels: 16

- Sequence Level Branching: Arbitrary 4-way "If/then/else"

- Maximum Occurrence Count Value: 16,777,215

- Pattern Recognizers: 16

- Range Recognizers: 15

- Range Width: 32

- Occurrence Counters: 1 per sequence level

- Global Counters: 2

- Flags: 8, can be used between modules

- Flag set/reset to evaluation: 110 ns, typical

- Timers: (2 x number of cards) - 1

- Timer Value Range: 100 ns to 5497 seconds

- Timer Resolution: 5 ns

- Timer Accuracy: +/- 10 ns + 0.01%

- Timer Reset Latency: 70 ns

- Glitch/Edge Recognizers: 2 per pod pair (timing only)

- Minimum Detectable Glitch: 1.5 ns

- Greater Than Duration: 6 ns to 100 ms in 6-ns increments

- Less Than Duration: 12 ns to 100 ms in 6-ns increments

- Data In to Trigger Out: 150 ns, typical

Power Requirements All necessary power is supplied by the backplane connector of the logic analysis system mainframe.

Operating Environment Characteristics

- Indoor use only.

- Temperature Instrument (except disk and media): 0 to 50 degrees C (+32 to 122 degrees F) Probe lead sets and cables: 0 to 65 degrees C (+32 to 149 degrees F)

- Humidity Instrument, probe lead sets, and cables: up to 80% relative humidity at 40 degrees C (+104 degrees F)

- Altitude Operating, to 4600 m (15,000 ft) Non-operating, to 15,300 m (50,000 ft)

- Vibration Operating: Random vibration 5-500 Hz, 10 minutes per axis, approximately 0.2 g rms Nonoperating: Random vibration 5 to 500 Hz, 10 minutes per axis, approximately 2.41 g rms; and swept sine resonant search, 5 to 500 Hz, 0.50 g (0-peak), 5-minute resonant dwell at 4 resonances per axis.

Reliability is enhanced when operating within the following ranges:

- Temperature +20 to 35 degrees C (+68 to 95 degrees F)

- Humidity 20% to 80% non-condensing

Storage

Store or ship the logic analyzer in environments with the following limits:

- Temperature -40 to +75 degrees C

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Specifications and Characteristics

- Humidity up to 90% at 65 degrees C

- Altitude up to 15,300 meters (50,000 feet)

Protect the module from temperature extremes which cause condensation on the instrument.

Chapter 1: HP 16717A 333 MHz State/2 GHz Timing Zoom Logic Analyzer

Analyzer Probing Overview

The figures below shows a variety of simple probing connections. The specific probe type, number of probes, and location on the target circuit depends on your particular measurement.

For equivalent circuit diagrams and pinouts, see the description of the probe type in the Logic Analysis System and Measurement Modules

Installation Guide. If you have misplaced the Logic Analysis System and Measurement Modules Installation Guide, you can download

the latest version from the Web at <URL: http://www.hp.com/go/ LogicAnalyzer-Manuals/ >

Probe Lead-to-Board Connection

The standard lead set plugs directly into any .1-inch grid with 0.026 to

0.033-inch diameter round pins or 0.025-inch square pins. All probe tips work with the HP 5059-4356 surface mount grabbers and the HP 5959-0288 through-hole grabbers.

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Analyzer Probing Overview

Adapter-to-Board Connection

Both the 01650-63203 and the E5346A adapters include termination for the logic analyzer. The 01650-63203 termination adapter plugs into a 2 x 10 pin header with 0.1 inch spacing. The E5346A high-density adapter connects to an AMP "Mictor 38" connector. If possible, use support shrouds around the Mictor connector to relieve strain and improve connections.

Direct Pod-to-Board Connection

If you provide proper termination as part of the target board, you can plug the pod directly into the ©3M 2520-series, or similar alternative connector. Suggested termination is shown in the Logic Analysis System and Measurement Modules Installation Guide.

Also use this termination with the HP E5351A high-density, nonterminated adapter.

Pod-to-Analysis Probe Connection

Analysis probes (formerly called preprocessors) are microprocessorspecific interfaces that make it easier to probe buses. Generally,

100

Agilent 16717A Help Volume

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Setting Up a Measurement

Connect the Analyzer to the Target System

Define the Type of Measurement

Set Up the Bus Labels

Define Trigger Conditions

Run the Measurement

Examine the Data

Making a Basic State Measurement

Making a Basic Timing Measurement

Interpreting the Data

Analysis Using Waveform

Analysis Using Listing

Arming Control - Multiple Instruments and Analyzers

Loading and Saving Logic Analyzer Configurations

When Something Goes Wrong

Interference with Target System

Error Messages

Nothing Happens

Suspicious Data

Maximum of 32 Channels Per Label

Measurement Initialization Error

Slow or Missing Clock

Trigger inhibited during timing prestore

Waiting for Trigger

No more Edge/Glitch resources available for this pod pair

No more Pattern resources available for this pod pair

Branch expression is too complex

Trigger Specification is too complex

Timer value checked as an event, but no start action specified

Counter value checked as an event, but no increment action specified

Trigger function initialization failure.

Cannot specify range on label with clock bits that span pod pairs

Goto action specifies an undefined level

No Trigger action found in the trace specification

Testing the Logic Analyzer Hardware

The Sampling Tab

Acquisition Depth

2 GHz Timing Zoom

Setting the Acquisition Mode

Performing Clock Setup (State only)

Clock Modes (State only)

Naming the Analyzer

Turning the Analyzer Off

Sample Period (Timing Only)

State Acquisition Modes

Timing Acquisition Modes

Trigger Position Control

The Format Tab

Activity Indicators

Assigning Pods to the Analyzers

Data On Clocks Display

Assigning Bits to a Label

Inserting and Deleting Labels

Turning Labels On and Off

Label Polarity

Reordering the Bits in a Label

Labels: Mapping Analyzer Channels to Your Target

Setting Up the Pod Clock

Pod Selection

Setting the Pod Threshold

State Clock Setup/Hold (State only)

The Trigger Tab

E-mail Notify on Trigger

What is SMTP

Understanding Logic Analyzer Triggering

Setting Up a Trigger

Selecting a Function to Match Trigger Conditions

Inserting and Deleting Sequence Steps

Editing Sequence Levels

Setting Up Loops and Jumps in the Trigger Sequence

Saving and Recalling Trigger Sequences

Clearing Part or All of the Trigger

Overview of the Trigger Sequence

Trigger Functions

Trigger Function Libraries