Agilent 16712A Help Volume

Help Volume

Agilent Technologies 16712A 128K Sample Logic Analyzer

The Agilent Technologies 16712A logic analyzer offers a full set of data capture features and 128 K samples of memory. Special features of this model of logic analyzer include context store and transitional timing acquisition mode.

Getting Started

• “Analyzer Probing Overview” on page 107

• “Setting Up a Measurement” on page 10

• “When Something Goes Wrong” on page 33

• “Error Messages” on page 33

Measurement Examples

• “Making a Basic Timing Measurement” on page 22

• “Making a Basic State Measurement” on page 18

• Advanced Measurement Examples (see the Measurement Examples help

volume)

• “Interpreting the Data” on page 26

More Features

“Coordinating Measurements” on page 31

Using Inverse Assembly (see the Listing Display Tool help volume)

Using Symbols (see page 110)

Working with Markers (see the Markers help volume)

“Loading and Saving Logic Analyzer Configurations” on page 32

Agilent Technologies 16712A 128K Sample Logic Analyzer

“Testing the Logic Analyzer Hardware” on page 40

Interface Reference

“The Sampling Tab” on page 41

“The Format Tab” on page 53

“The Trigger Tab” on page 73

“The Symbols Tab” on page 110

“Specifications and Characteristics” on page 103

Main System Help (see the Agilent Technologies 16700A/B-Series Logic Analysis System help volume)

Glossary of Terms (see page 131)

Agilent Technologies 16712A 128K Sample Logic Analyzer

1 Agilent Technologies 16712A 128K Sample Logic Analyzer

Setting Up a Measurement 10

Connect the Analyzer to the Target System 10 Define the Type of Measurement 11 Set Up the Bus Labels 13 Define Trigger Conditions 14 Run the Measurement 15 Examine the Data 16

Making a Basic State Measurement 18

Making a Basic Timing Measurement 22

Interpreting the Data 26

Analysis Using Waveform 26 Analysis Using Listing 28

Coordinating Measurements 31

Loading and Saving Logic Analyzer Configurations 32

When Something Goes Wrong 33

Interference with Target System 33 Error Messages 33 Nothing Happens 39 Suspicious Data 39

Testing the Logic Analyzer Hardware 40

Contents

The Sampling Tab 41

Acquisition Depth 41 Setting the Acquisition Mode 42 Performing Clock Setup (State only) 42 Naming the Analyzer 45 Turning the Analyzer Off 46 Sample Period (Timing Only) 46 Trigger Position Control 51

The Format Tab 53

Importing Netlist and ASCII Files 54

Exporting ASCII Files 56 Importing ASCII Files 56 Termination Adapter 58 E5346A High Density Adapter 59 Mapping Connector Names 60 Import the Net List File 60 Verify Net to Label Mapping 61 Select/Create Interface Labels 62 Activity Indicators 62 Assigning Pods to the Analyzers 63 Data On Clocks Display 64 To reorder bits in a label 67 Labels: Mapping Analyzer Channels to Your Target 68 Setting Up the Pod Clock 68 Pod Selection 69 Setting the Pod Threshold 70 State Clock Setup/Hold (State only) 71

Contents

The Trigger Tab 73

Understanding Logic Analyzer Triggering 74 Setting Up a Trigger 76 Inserting and Deleting Sequence Steps 77 Editing Sequence Steps 78 Setting Up Loops and Jumps in the Trigger Sequence 79 Saving and Recalling Trigger Sequences 80 Clearing Part or All of the Trigger 81 Overview of the Trigger Sequence 81 Trigger Functions 82 Working with the User-level Function 89 Defining Resource Terms 92 Tagging Data with Time or State Tags (State Only) 99 Arming Control 99 Context Store Measurements (State Only) 101

Specifications and Characteristics 103

What is a Specification 103 What is a Characteristic 103 What is a Calibration Procedure 104 What is a Function Test 104 Agilent Technologies 16712A Logic Analyzer Specifications 104 Agilent Technologies 16712A Logic Analyzer Characteristics 105

Analyzer Probing Overview 107

The Symbols Tab 110

Displaying Data in Symbolic Form 111

Contents

Setting Up Object File Symbols 112

To Load Object File Symbols 112 Relocating Sections of Code 114 To Delete Object File Symbol Files 115 Symbol File Formats 115 Creating ASCII Symbol Files 116 Creating a readers.ini File 121

User-Defined Symbols 124

To Create User-Defined Symbols 124 To Replace User-Defined Symbols 124 To Delete User-Defined Symbols 125 To Load User-Defined Symbols 125

Using Symbols In The Logic Analyzer 126

Using Symbols As Trigger Terms 126 Using Symbols as Search Patterns in Listing Displays 127 Using Symbols as Trigger Terms in the Source Viewer 127 Using Symbols as Pattern Filter Terms 127 Using Symbols as Ranges in the Software Performance Analyzer 128

Glossary

Index

Agilent Technologies 16712A 128K Sample Logic Analyzer

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Setting Up a Measurement

After you have connected the logic analyzer probes to your target system, (see page 10) there are five basic steps for any measurement.

1. “Define the Type of Measurement” on page 11

2. “Set Up the Bus Labels” on page 13

3. “Define Trigger Conditions” on page 14

4. “Run the Measurement” on page 15

5. “Examine the Data” on page 16 Refine measurement by repeating steps 3 - 5.

If you load a configuration file, it will set up the logic analyzer and trigger. For your particular measurement, you may need to change some settings.

See Also “Making a Basic Timing Measurement” on page 22

“Making a Basic State Measurement” on page 18

Measurement Examples (see the Measurement Examples help volume)

Making Basic Measurements for a self-paced tutorial

Connect the Analyzer to the Target System

Before you begin setting up a measurement, you need to physically connect the logic analyzer to your target system. Attach the pods in a way that keeps logically related channels together and be sure to

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Setting Up a Measurement

ground each pod. Analysis probes, available for most common microprocessors, can simplify the connection process.

The logic analyzer pods carry the signals to the logic analyzer from your target system. Connect the pods either directly to the target system or to an analysis probe. You can attach the pods either directly to a 40-pin header, to a 20-pin header with an adapter, or use the General Purpose Probes to attach to individual channels.

If you are using an analysis probe, Setup Assistant will guide you through the process based on your logic analyzer and the analysis probe.

Step 1: Describe the Measurement (see page 11)

See Also “Analyzer Probing Overview” on page 107 for more detail on types of

probes

Setup Assistant (see the Setup Assistant help volume)

Logic Analysis System and Measurement Modules Installation Guide for probe pinout and circuit diagrams.

Define the Type of Measurement

There are two types of measurements: state measurements and timing measurements. Use the Sampling tab to select either type

and to specify the details particular to that type.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Setting Up a Measurement

Choose State or Timing

In a state measurement, the analyzer uses an external clock to determine when to sample. Each time the analyzer receives a state clock pulse, it samples and stores the logic state of the target system.

In a timing measurement, the analyzer is analogous to an oscilloscope. It samples at regular time intervals and displays the information in a waveform similar to the oscilloscope.

Set Measurement Mode

Each measurement type has different measurement modes. In general, there is a trade-off between number of signals and speed.

Because the measurement type and mode affect clocking and trigger options, you must set the measurement type first.

Set up State Clock

For state measurements, you must specify a clock to match the clocking arrangement used by your target system. It can be as simple as a single rising edge, or a complex arrangement of up to four signals. If the clock is incorrect, the trace data may indicate a problem where there isn’t one. Specify the state clock in Clock Setup.

The equivalent in timing mode of the state clock is the Sample Period. The Sample Period sets the time between logic analyzer samples. For reliable data, the sample period should be no more than half of your clock period. Many engineers prefer setting it to one-fourth of the clock period.

Set up the Trace

The remaining controls finish your description of how you want to capture data. The trigger position determines where the events you specify in the trigger sequence will be relative to the majority of the data the logic analyzer captures.

Memory depth is affected by the measurement mode. Some logic analyzers also let you limit how big the acquisition will be with an Acquisiton Depth control.

Step 2: Set Up the Bus Labels (see page 13)

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Setting Up a Measurement

See Also “The Sampling Tab” on page 41 for information on setting type and

assigning pods

“Setting the Acquisition Mode” on page 42 for links to this analyzer's modes

“Performing Clock Setup (State only)” on page 42

Set Up the Bus Labels

The next step is to finish defining the physical connection between the target system and the analzyer. Use the Format tab to tell the analyzer what you want to measure on the target system. If you load a configuration file, this step is taken care of for you.

Group and Label Signals

Because the logic analyzer can capture dozens or even hundreds of signals, you need to organize the signals by grouping and labeling channels. Labels are used to group these channels into logical signals; for example, "addr bus". These groupings are then used in the trigger tab and the data displays. A label can have up to 32 channels. Each measurement can define 126 labels. Active channels are indicated like

so .

Set Threshold Level

The logic analyzer needs to know what threshold level the target system is using. You can set the analyzer to use a Standard or a User

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Setting Up a Measurement

Defined threshold voltage. The logic analyzer requires a minimum voltage swing of 500 mV at the probe tip to recognize changes in logic levels.

Step 3: Define Trigger Conditions (see page 14)

See Also “Assigning Bits to a Label” on page 64

“The Format Tab” on page 53

Define Trigger Conditions

The third step is to define the trigger. The trigger settings tell the analyzer when you want to capture data. Controls for this are located under the Tri g ger tab. Configuration files saved from previous measurements automatically define trigger settings.

Set Up a Trigger Sequence

The trigger sequence is like a small program that controls when the logic analyzer stores data. There are trigger functions for the common tasks, or you can set up your own. The logic analyzer starts at the first trigger level, and stays there until the conditions described in that level become true. When that happens, the logic analyzer goes to the next level and follows the instructions there.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Define Terms

Trigger terms are like variables that you use in the trigger sequence. Depending on what analyzer you are using, you can either assign the values directly from within the trigger sequence or from the tabs (pattern, range, edge).

Step 4: Run the Measurement (see page 15)

See Also “Defining Resource Terms” on page 92

“Understanding Logic Analyzer Triggering” on page 74

“Setting Up a Trigger” on page 76

“The Trigger Tab” on page 73

Measurement Examples (see the Measurement Examples help volume)

Setting Up a Measurement

Run the Measurement

You run the measurement by selecting the Run button. The Run button is labeled either Run, Group Run, or Run All. The difference between the three types is that Run starts only the instrument you are using, Group Run starts all instruments attached to group run in the Intermodule window, and Run All starts all instruments currently placed in the workspace.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Setting Up a Measurement

Select Single or Repetitive

Runs can be single or repetitive. Single runs gather data until the logic analyzer memory is full, and then stop. Repetitive runs keep repeating the same measurement and are useful for gathering statistics. To stop a run, select the Stop button.

NOTE: Repetitive runs on a logic analyzer don’t do equivalent time sampling like

oscilloscopes do.

If Nothing Happens...

Analyzers with deep memory take a noticeable amount of time to complete a run. Because data is not displayed until acquisition completes, it may look like nothing is happening. Check the Run Status window to see if the logic analyzer is still running. Messages such as "Waiting in level 1" may indicate you need to refine your trigger. If the status shows as "Stopped", the analyzer either finished the acquisition, or was unable to run. The cause of the problem is listed in the bottom half of the Run Status window, and the messages are explained in more detail in “Error Messages” on page 33.

Step 5: Examine the Data (see page 16)

See Also “When Something Goes Wrong” on page 33

Examine the Data

Data from your measurement can be viewed in various display windows or offline. Some of the things you can do in the display windows are

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Setting Up a Measurement

• Search for patterns

• Display time-correlated data

• Use markers to make measurements and gather statistics

Search for Patterns

You can search displays for certain values, and place markers on them. There are two global markers which keep their place across all measurement views, even across instruments.

Display Correlated Data

There are several tools for correlation. The Intermodule window allows you to specify complex triggering configurations using several instruments. It is also useful for starting acquisitions at the same time. Global markers mark the same events in different displays, so you can switch views without having to reorient yourself. The Compare tool lets you compare two different acquisitions to look for changes.

Use Markers to Make Measurements

The markers can be positioned relative to the beginning, end, trigger, or another marker, as well as set to a specific pattern, state, or time. The Markers tab in the Display windows shows the time or state value as you move the markers or take new acquisitions.

See Also Working with Markers (see the Markers help volume)

Using the Chart Display Tool (see the Chart Display Tool help volume)

Using the Distribution Display Tool (see the Distribution Display Tool help volume)

Using the Listing Display Tool (see the Listing Display Tool help volume)

Using the Digital Waveform Display Tool (see the Waveform Display Tool help volume)

Using the Compare Analysis Tool (see the Compare Tool help volume)

“Interpreting the Data” on page 26

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Making a Basic State Measurement

This example uses the circuit board that is supplied with the Making Basic Measurements kit as the target system. The kit is supplied with

every logic analysis system, or can be ordered from your Agilent Technologies Sales Office.

There are six major steps to making a basic measurement.

Connect the Logic Analyzer to your Target Sys t e m

1. Connect probes.

• Connect Pod 1 of the logic analyzer to J1 on the target system.

The training board has terminations and headers already built in to the system, so you can connect the logic analyzer pod directly to the board.

2. Define the type of measurement On the Agilent Technologies 16700A/B logic analysis system, open a logic analyzer setup window.

a. In the main window, select the logic analyzer icon.

b. Choose Setup... from the menu.

c. Select the Sampling tab.

d. If the logic analyzer is not already set for State, change the type to

State.

3. Set up the clock to match the target system's clocking scheme.

a. In the bottom half of the Sampling tab window, choose the correct

edges to match your clock. For Pod 1 attached to the training board, the correct clock is the falling edge on J.

1. Select the Off button under J and choose "Falling Edge" from the

menu.

4. Group and label bits.

a. Select the Format tab.

b. Optional - Insert a second label.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Making a Basic State Measurement

1. Select the Label1 button.

2. Choose Insert after....

3. In the Enter Label Name box, select the OK button.

c. Optional - Rename Label1.

1. Select the Label1 button.

2. Choose Rename....

3. Enter a new name in the name field.

4. Select the OK button to close the Rename Label box.

d. Select the bit assignment button.

The bit assignment button is to the right of a label name, and under a pod column.

e. Choose ........******** from the menu.

If none of the choices match your own system, choose Individual... and select the individual bits to assign them (*) or ignore them (.).

5. Define trigger events for patterns on buses.

a. Select the Pattern subtab in the Trigger tab.

b. Optional - Rename Pattern1.

1. Select the Pattern1 field.

2. Enter a new name.

c. Select the appropriate label.

1. Select the label name button.

2. To define the event as a combination of labels, choose Insert... To use a different label to define the event, choose Replace...

3. In the dialog box, select the label name you want to use and then select the OK button.

d. Select the field with XX and enter the value you want to trigger on.

e. Optional - Repeat steps a - d for Pattern2.

6. Optional - Add additional trigger events to the trigger specification.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Making a Basic State Measurement

The logic analyzer automatically triggers on Pattern1, the first trigger event. You can set up more complex triggers by editing the sequence levels and combining trigger events.

a. Select the sequence level number 1 button and choose Edit...

b. In the dialog box, select the Pattern1 button just after Trigger on and

choose Combo...

c. In the Combination box, select the Off option button next to Pattern2

and choose On.

d. To change the trigger to Pattern1 and Pattern2, select the Or option

button to the right of the events and choose And.

e. Select the OK button.

f. Select the Close button.

The analyzer is now set to trigger when it detects both the pattern defined by Pattern1 and the pattern defined by Pattern2 on the target system’s buses. The trigger sequence windows shows

Trigger on "(Pattern1.Pattern2)" 1 time

See Also “The Tri gger Tab” on page 73

1. Select the Run button.

2. Examine the data.

a. Select the Window menu.

b. Select Analyzer<A> in the menu and choose Listing<1>.

Depending on what other instruments are active, there may be more than one Analyzer<A>. Choose the one that refers to your analyzer.

c. To have the listing display appear automatically when you run the logic

analyzer, select Options -> Popup on Run -> On in the menu bar of the listing display.

d. To insert additional labels, select the label name.

Making a Basic Timing Measurement

This example uses the circuit board that is supplied with the Making Basic Measurements kit as the target system. The kit is supplied with

every logic analysis system, or can be ordered from your Agilent Technologies Sales Office.

There are six major steps to making a basic measurement.

Connect the Logic Analyzer to the Target System

1. Connect probes.

• Connect Pod 1 of the logic analyzer to J1 on the target system.

The training board has terminations and headers already built in to the system, so you can connect the logic analyzer pod directly to the board.

2. Define the type of measurement. On the Agilent Technologies 16700A/B logic analysis system, open a logic analyzer setup window.

a. In the main window, select the logic analyzer icon.

b. Choose Setup... from the menu.

c. Select the Sampling tab.

d. If the logic analyzer is not already set for Timing, change the type to

Timing.

3. Group and label bits.

a. Select the Format tab.

b. Optional - Insert a second label.

1. Select the Label1 button.

2. Choose Insert after....

3. In the Enter Label Name box, select the OK button.

c. Optional - Rename Label1

1. Select the Label1 button.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Making a Basic Timing Measurement

2. Choose Rename....

3. Enter a new name in the name field.

4. Select the OK button to close the Rename Label box.

d. Select the bit assignment button.

The bit assignment button is to the right of a label name, and under a pod column.

e. Choose ........******** from the menu.

If none of the choices match your own system, choose Individual... and select the individual bits to assign them (*) or ignore them (.).

4. Define trigger events for a bus.

a. Select the Tr igger tab.

b. Select the Pattern subtab.

c. Optional - Rename pattern Pattern1.

1. Select the Pattern1 field.

2. Enter a new name.

d. Select the appropriate label.

1. Select the label name button.

2. To define the event as a combination of labels, choose Insert... To use a different label to define the event, choose Replace...

3. In the dialog box, select the label name you want to use and then select the OK button.

e. Select the field with XX and enter the value you want to trigger on.

5. Define trigger events for an edge.

a. Select the Edge subtab.

b. Optional - Rename Edge1.

1. Select the Edge1 field.

2. Enter a new name.

c. Select the appropriate label.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Making a Basic Timing Measurement

1. Select the label name button.

2. To define the event as a combination of labels, choose Insert... To use a different label to define the event, choose Replace... Edges within an event are always OR’d together, which means only one of the edges on one of the labels needs to occur for the edge event to become true.

3. In the dialog box, select the label name you want to use and then select the OK button.

d. Select the edge assignment button (........) and enter the edge or

edges you want to trigger on. Remember, if more than one edge is specified, then when the logic analyzer detects any of the edges the event becomes true.

6. Add the edge event to the trigger specification.

a. Select the sequence level number 1 button and choose Edit...

b. In the dialog box, select the Pattern1 button and choose Combo...

c. In the Combination box, select the Off option button next to Edge1 and

choose On.

d. Select the Or option button where the path from Pattern1 and the

path from Edge1 come together, and choose And.

e. Select the OK button.

The analyzer is now set to trigger when it detects Edge1 and Pattern1 on the bus. The trigger sequence window shows

Trigger on Pattern1.Edge1 occurs 1 times

The logic analyzer automatically triggers on the first trigger event. You can set up more complex triggers by editing the sequence levels and defining additional trigger events.

See Also “The Tri gger Tab” on page 73

1. Select the Run button.

2. Examine the data.

a. Select the Window menu.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

b. Select Analyzer<A> in the menu and choose Waveform<1>.

Depending on what other instruments are active, there may be more than one Analyzer<A>. Choose the one that refers to your analyzer.

c. To have the waveform display appear automatically when you run the

logic analyzer, select Options -> Popup on Run -> On in the menu bar of the waveform display.

d. To insert additional labels, or expand overlaid signals, select the label

name.

Interpreting the Data

After you’ve acquired a trace with the logic analyzer, you can analyze it in the display tools. The logic analysis system also provides filtering and compare tools for more complex analysis.

The logic analyzer is automatically connected to the Waveform and Listing displays when you set up a measurement. To move to that display,

1. Select the Window menu.

2. Select the name of the analyzer whose data you want to view.

3. Choose Waveform or Listing. Source Viewer brings up a Listing display but requires an inverse assembler and an ADDR label.

•“Analysis Using Waveform” on page 26

•“Analysis Using Listing” on page 28

Analysis Using Waveform

Waveform is most useful for timing data. If you look at state data that uses store qualification, you won’t be able to easily see where samples were not stored. Timing data, however, is periodic and stores all samples and so works well with Waveform.

Example: Looking for a Missing Pattern

You can easily use the waveform tool to make timing measurements. For example, if you were triggering when a pattern doesn’t follow an edge within a certain time (see the Measurement Examples help volume), you would probably want to look at your data set to see if the pattern ever did occur. This might be the case when you verifying that the system is responding to an interrupt.

After triggering on an instance where the response did not appear quickly enough, you might take these steps in the Waveform display:

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Interpreting the Data

1. Find the edge.

a. Select the Search tab.

b. Select the down arrow after the Label field, and select the label

containing the edge.

c. Select the Value field and enter 1.

d. Select the Next button to locate the edge transition.

2. Place a marker on the edge.

Select the Set G1 button. This sets global marker G1 at the location of the edge you just found.

3. Search for the pattern. Searches start at your current location. Since you just set the global marker G1, it indicates where the search starts from.

a. Select the down arrow after the Label field, and select the label

containing the pattern.

b. Select the Value field and enter the pattern you are searching for.

c. Select the down arrow after the When field and select Entering.

d. Select the Next button to find the next occurrence of that pattern after

G1.

If the logic analysis system cannot find the pattern, a "Value not found" message pops up.

4. Place a marker on the pattern.

Select the Set G2 button. This will set global marker G2 at the location of the pattern.

5. Find the time between the edge and the pattern.

a. Select the Markers tab.

b. In the G2 row, select the down arrow after from, and select G1.

The value after the from field changes to the time between G1 and G2. You can toggle between time and samples by selecting the arrow after the Time or Samples field.

See Also Using the Digital Waveform Display Tool (see the Waveform Display Tool

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Interpreting the Data

help volume)

Using the Listing Display Tool (see the Listing Display Tool help volume)

Using the Chart Display Tool (see the Chart Display Tool help volume)

Using the Distribution Display Tool (see the Distribution Display Tool help volume)

Using the Compare Analysis Tool (see the Compare Tool help volume)

Using the Pattern Filter Analysis Tool (see the Pattern Filter Tool help volume)

Analysis Using Listing

Listing is more useful than Waveform when your target system is running code because it shows the labels as states rather than transitions. Listing is especially useful when you have defined meaningful symbol names for your states. If you have an inverse assembler, you might prefer Source Viewer which functions like Listing.

Example: Examining a Subroutine

Listing is the preferred display tool for state measurements. for example, if you were trying to see if a subroutine were exiting abnormally, you might want to measure the number of states between entering and exiting the subroutine. After acquiring data with the logic analyzer, you could examine the data set in the Listing display like this:

1. Find the start of the subroutine.

Assume the subroutine starts at the address 0x58FC.

a. Select the Search tab.

b. Select the down arrow after the Label field, and select ADDR.

c. Select the Value field, and enter the starting address, 0x58FC.

d. Select the down arrow after the When field and select Present.

e. Select the Next or Prev button to move the display to the address.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Interpreting the Data

2. Place a marker on the start of the subroutine.

Select the Set G1 button. This sets global marker G1 at the address you just found.

3. Find the end of the subroutine.

Assume the end of the subroutine is at address 0x58FF. Searches always start at the current location. Since you just set the global marker G1, it indicates where the search starts from.

a. Select the Value field, and enter 58FF.

b. Select the Next button to find the next occurrence of 0x58FF after the

starting address.

4. Place a marker on the end of the subroutine.

Select the Set G2 button to set global marker G2 at this position. This lets you refer to G2 when you want to know where the subroutine ends.

5. Find the number of states between the start and end of the subroutine.

Since you’ve placed markers at the start and end of the subroutine, all you have to do is find the number of states between those markers.

a. Select the Markers tab.

b. In the G2 row, select the second down arrow and select Sample.

c. Select the down arrow after from, and select G1.

The value after the from field changes to the number of states between G1 and G2. You can toggle between time and states by selecting the arrow after the Time or Samples field.

Now you know how long the execution stayed in the subroutine, and can also examine the data set between G1 and G2 to look for unusual data.

See Also Using the Digital Waveform Display Tool (see the Waveform Display Tool

help volume)

Using the Listing Display Tool (see the Listing Display Tool help volume)

Using the Chart Display Tool (see the Chart Display Tool help volume)

Using the Distribution Display Tool (see the Distribution Display Tool

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Interpreting the Data

help volume)

Using the Compare Analysis Tool (see the Compare Tool help volume)

Using the Pattern Filter Analysis Tool (see the Pattern Filter Tool help volume)

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Coordinating Measurements

When you want to coordinate the triggering of two measurements happening on the same logic analyzer, you need to use arming control. The two measurement machines are by default controlled by the same run button. However, you can set machine 1 to arm machine 2, or the other way around.

If the timing measurement and state measurement are being handled by two different instruments, you can coordinate them by connecting both instruments to the same display, and then setting the correlation in the correlation dialog that appears.

You can tell which instrument is controlling a measurement by looking at the instrument icon. The letter on the icon represents the slot of the frame that the instrument is in. Icons with the same letter are controlled by the same instrument.

See Also Overview - Multiple Instrument Configuration (see the Agilent

Technologies 16700A/B-Series Logic Analysis System help volume)

Overview - Multiple Machine Configuration (see the Agilent Technologies 16700A/B-Series Logic Analysis System help volume)

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Loading and Saving Logic Analyzer Configurations

The Agilent Technologies 16712A logic analyzer settings and data can be saved to a configuration file. You can also save any tools connected to the logic analyzer. Later, you can restore your data and settings by loading the configuration file into the logic analyzer.

The Agilent Technologies 16712A logic analyzer can also load configuration files generated for Agilent Technologies 16550A, 16554A, 16555A, 16555D, 16556A, 16556D, 16557D, and the 16600A-series built-in logic analyzers as well as the Agilent Technologies 16710/11/ 12A family.

NOTE: The Agilent Technologies 16700A/B-series logic analysis systems can translate

configuration files from Agilent Technologies 16500 and 16505A logic analysis systems if the measurement module is the same. If the modules are different, first load the configuration file into a module of the same model number on the new logic analysis system. Re-save the configuration, then load this configuration into the destination module.

See Also Loading Configuration Files (see the Agilent Technologies 16700A/B-

Series Logic Analysis System help volume)

Saving Configuration Files (see the Agilent Technologies 16700A/BSeries Logic Analysis System help volume)

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

When Something Goes Wrong

•“Nothing Happens” on page 39

•“Error Messages” on page 33

•“Suspicious Data” on page 39

•“Interference with Target System” on page 33

Interference with Target System

When Something Goes Wrong

Capacitive Loading on the Target System

Excessive capacitive loading can degrade signals, resulting in suspicious data or even system lockup. All analysis probes add capacitive loading, as can custom probes you design for your target. To reduce loading, remove as many pin protectors, extenders, and adapters as possible.

Careful layout of your target system can minimize loading problems and result in better margins for your design. This is especially important for systems running at frequencies greater than 50 MHz.

Error Messages

“Slow or Missing Clock” on page 34

“Waiting for Trigger” on page 37

“Timer is Off in Sequence Level Where It Is Used” on page 36

“Timer is Specified in Sequence, But Never Started” on page 35

“Measurement Initialization Error” on page 34

“Two Pod Pairs are Needed To Use Both Timers” on page 36

“Maximum of 32 Channels Per Label” on page 34

“Trigger inhibited during timing prestore” on page 36

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

When Something Goes Wrong

“Correlation Invalid, Module Did Not Trigger” on page 38

“Correlation Invalid, Timer Overflowed” on page 38

“Measurement Error: Check Probe Parametrics or Grounding” on page 38

“Clock Lines Must Be Connected to the Card in Slot X” on page 37

Maximum of 32 Channels Per Label

The logic analyzer can only assign up to 32 channels for each label. If you need more than 32 channels, assign them to two labels and use the labels in conjunction.

See “Adding and Deleting Labels for Terms” on page 98 for how to use more than one label with trigger terms.

Measurement Initialization Error

The logic analyzer module failed the internal calibration which it performs when Run is selected. An internal calibration failure can indicate either a software or a hardware problem.

Possible Causes

• Hardware failure

• Software failure

Run the Self-Test Utility (see page 40) on the logic analyzer and contact your Agilent Technologies Sales Office for service or software upgrades.

Slow or Missing Clock

The message "Slow or Missing Clock" only appears in state measurements. However, if you have another instrument armed by the

state analyzer, a slow or missing clock on the state analyzer will prevent the other instrument from triggering also.

Possible Causes

• Target system is not running properly

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

When Something Goes Wrong

Check that the system is running properly. The logic analyzer and other probing fixtures such as pin extenders can place too much capacitive load on a system.

• Incorrect clock specification

Make sure the target system clock matches the clock specified under Sampling. Also check that the probe's clock channels are attached to the target's clock lines either directly or through an analysis probe. If you are using an analysis probe, the probe's User's Guide should show the correct connections and settings.

• Bad probe connection

Check that the probe is securely attached to the clock line and is receiving a signal. The logic analyzer shows activity indicators under the Sampling and Format tabs.

• Incorrect signal level

The clock's threshold level is set by the pod threshold. For the logic analyzer's J clock, check the pod threshold of pod 1 of the master card.

See Also “Performing Clock Setup (State only)” on page 42

“Setting the Pod Threshold” on page 70

Timer is Specified in Sequence, But Never Started

This error occurs because you have used a timer term in your trigger sequence, but not turned the timer on using the timer controls. Timer

controls are available in all sequence levels except the first. You do not need to turn on the timer in the same sequence level, but it does need to be on when it is used in the trigger sequence.

This error message always occurs with the

Timer is off in sequence level where it is used

warning.

See “Using Timer Terms” on page 96 for more information on timer control.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

When Something Goes Wrong

Timer is Off in Sequence Level Where It Is Used

Timer controls are available in all sequence levels except the first. You do not need to turn on the timer in the same sequence level, but it does need to be on when it is used in the trigger specification.

Possible Causes

This warning occurs because you have used a timer term in your trigger specification, but not turned the timer on using the timer

controls.

This warning message always occurs with the

Timer is specified in sequence, but never started

error message.

See “Using Timer Terms” on page 96 for more information on timer control.

Trigger inhibited during timing prestore

The "trigger inhibited" informational message appears when you have a logic analyzer making a timing measurement, and it is set to a slow sample rate. The logic analyzer will fill the designated amount of pretrigger memory before checking for the trigger condition.

To calculate how long this should take, multiply the sample rate by the percentage of pre-trigger memory and the acquisition depth. For example, if

sample period = 1.0 ms (sample rate = 10

samples/sec.)

trigger position = center (percentage of pre-trigger memory = 50%)

acquisition depth = 64K (roughly 64 x 10

samples)

then the approximate time is 32 seconds.

Two Pod Pairs are Needed To Use Both Timers

Possible Causes

This message only occurs when all pod pairs are assigned, and the machine which is using both timers has only one pod pair.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

You can either assign another pod pair to the machine with both timers, or change your trigger specification to use only one timer term.

See Also “Using Timer Terms” on page 96

Waiting for Trigger

This message indicates that the specified trigger pattern has not occurred. This may be expected, as when you are waiting to trigger on an unusual event.

Possible Causes

• Misaligned boundaries for addresses

When the target is a microprocessor that fetches only from long-word aligned addresses, if the trigger is set to look for an opcode fetch at an address that is not properly aligned, the trigger will never be found.

• Trigger set incorrectly

When Something Goes Wrong

Some strategies you can use when verifying or debugging trigger sequence levels are:

• Look at the run status message line or open the Run Status window. It will tell you what level of the sequence the logic analyzer is in.

• Stop the measurement and look at the data that was captured. This is particularly useful when you use store qualifiers to store "no states" (or only the states you are interested in) and the branches taken are stored.

• Save the trigger setup, then simplify it to see what part of the sequence does get captured. When you learn what needs to be changed, you can recall the original trigger setup and make changes to it.

See Also “Branches Taken Stored / Not Stored (State only)” on page 92

“Saving and Recalling Trigger Sequences” on page 80

Clock Lines Must Be Connected to the Card in Slot X

This message occurs if the logic analysis system has detected a slow or missing clock on a logic analyzer module that has an expander card.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

When Something Goes Wrong

Possible Causes

• Using a clock channel from an expander card

Reconnect the logic analyzer probes to use a clock channel from the master card of the module.

Only the clock channels of the master card can be used in the state clock. The master card of a module is identified in the system window.

• Clock properly connected, but slow

See “Slow or Missing Clock” on page 34.

Measurement Error: Check Probe Parametrics or Grounding

See “Analyzer Probing Overview” on page 107 or Logic Analysis System and Measurement Modules Installation Guide for details of

the logic analyzer connection methods.

Correlation Invalid, Module Did Not Trigger

The "correlation invalid" messages mean that although data was acquired, it cannot be accurately time correlated.

Possible Causes

• The module was stopped before it triggered

In the Agilent Technologies 16700A/B-series logic analysis system, when a module stops before it is triggered it cannot be accurately correlated with the other module.

Correlation Invalid, Timer Overflowed

The "correlation invalid" messages mean that although data was acquired, it cannot be accurately time correlated.

Possible Causes

The time between the triggers of the two modules was greater than 17 seconds, which caused the timer to overflow.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Nothing Happens

Look for an error message in the message bar at the top of the window. Common messages are "slow or missing clock" and "Waiting for trigger".

If the Run button briefly grayed-out (and the Stop or Cancel buttons briefly became active), select the Window menu, select the logic analyzer’s slot, then choose the Waveform or Listing display.

See Also “Slow or Missing Clock” on page 34

“Waiting for Trigger” on page 37

Suspicious Data

When Something Goes Wrong

Intermittent Data Errors

Unwanted Triggers

Check for poor connections, incorrect signal levels on the hardware, incorrect logic levels under the logic analyzer’s Config tab, or marginal timing for signals.

If you are using an inverse assembler or a pipeline, triggers can be caused by instructions that were fetched but not executed. To fix, add the prefetch queue or pipeline depth to the trigger address.

The depth of the prefetch queue depends on the processor that you are analyzing, and can be quite deep.

Another solution which is sometimes preferred with very deep prefetch queues is to add writes to dummy variables to your software. Put the instruction just before the area you want to trigger on, then trigger on the actual write to this variable. Although the instruction is prefetched, the analyzer can be set to only trigger when the write is executed.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Testing the Logic Analyzer Hardware

In order to verify that the logic analyzer hardware is operational, run the Self Test utility. The Self Test function of the logic analysis system performs functional tests on both the system and any installed modules.

1. Disconnect all probes of the logic analyzer module.

2. If you have any work in progress, save it to a configuration file. (see the

Agilent Technologies 16700A/B-Series Logic Analysis System help volume)

3. Disconnect all loads, adapters, or preprocessors from the probe cable ends.

4. From the system window, select the System Administration button.

5. Select the Admin tab, then select the Self Test... button. The system closes all windows before starting up Self Test.

6. Select Master Frame. If the module is in an expansion frame, select Expansion Frame.

7. Select the logic analyzer that you want to test.

8. In the Self Test dialog box, select Te s t A l l . You can also run individual tests by selecting them. Tests that require you to do something must be run this way.

If any test fails, contact your local Agilent Technologies Sales Office or Service Center for assistance.

See Also Self Test (see the Agilent Technologies 16700A/B-Series Logic Analysis

System help volume)

Agilent Technologies 16712A 128K Sample Service Guide

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

The Sampling Tab

The options under Sampling tell the analyzer the overall way in which you want to make a measurement. The options include:

• The acquisition mode.

• The data sample rate.

• How much data before and after the trigger.

• How much data to acquire in all.

See Also “Naming the Analyzer” on page 45

“Turning the Analyzer Off” on page 46

“Setting the Acquisition Mode” on page 42

The Sampling Tab

“Sample Period (Timing Only)” on page 46

“Performing Clock Setup (State only)” on page 42

“Trigger Position Control” on page 51

“Acquisition Depth” on page 41

Acquisition Depth

Acquisition Depth, located under Sampling and also under Trigge r Settings, sets how much data will actually be acquired. While the

Agilent Technologies 16712A logic analyzer has a maximum memory depth of 128 K samples in State Mode and 256K in Timing Mode, sometimes you may not want to wait for all that memory to fill up.

The numbers shown in the Acquisition Depth menu are approximations. The combination of count tags, pod assignments, and acquisition modes affect what choices are available. Also, the values are memory depth per channel.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

The Sampling Tab

Setting the Acquisition Mode

The measurement type affects all other areas of the logic analyzer setup. It is set under the Sampling tab.

If you want the logic analyzer to sample data according to the target system’s clock, select State. Each time the clock signal becomes valid, the analyzer will sample data from the system under test.

If you want the logic analyzer to sample the target system independently of its clock, select Timing. Since in timing mode the analyzer is clocked by a signal that is not related to the system under test, timing measurements capture traces of electrical activity over time. The Agilent Technologies 16712A logic analyzer can be split into two analyzers, but only one of them may be a timing analyzer.

State Mode and Timing Mode offer different options for the acquisition mode field in the top left corner under Controls. The acquisition mode affects the channel width, memory depth, and sample rate.

“State Acquisition Modes” on page 47

“Timing Acquisition Modes” on page 47

“Transitional Timing Acquisition Modes” on page 47

“Comparison of Transitional and Conventional Timing Modes” on page 50

Performing Clock Setup (State only)

When you select State Mode, the Clock Setup area appears under the State Mode Controls in Sampling. The Clock Setup contains three controls and a display area. The clocks you specify here control when the analyzer samples your data. Ideally, the logic analyzer’s state clock setup should be identical to the target system’s clock. Differences could result in invalid data.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

The Sampling Tab

Mode field

The Mode field lets you select among Master only, Master/slave, and Demultiplex. The default is Master only. When you select the others,

another control to set the slave clock appears at the bottom of the Clock Setup area. It also enables the Pod Clock field under Format.

For more detail on the uses of Master/slave and Demultiplex clocking, see “Clock Modes (State only)” on page 43.

Advanced Clocking

Advanced clocking allows you to specify clock qualifiers on individual clock edges instead of the group of clock edges. When you select it, the individual clock channels are replaced by Master Clock... or Slave Clock... Selecting these brings up a dialog that lets you combine edges and qualifiers in more complex Boolean expressions. When you switch from Advanced Clocking to regular clocking, some of the qualifiers are erased.

Clock Channel Specifiers

The clock channel specifiers graphically show your clock setup. Edges are ORed ("+") together, and qualifiers are ANDed (".") to all edges. To qualify just one of the edges, switch to Advanced Clocking.

All clock channels for the clock setup must be on the pods of the master card of the module, but the pods do not need to be part of the state measurement.

See Also “Clock Modes (State only)” on page 43

Clock Modes (State only)

The Pod Clock field under Format appears when a clock mode other than Master only is selected in Sampling. The Pod Clock field indicates whether a pod’s data lines are to be sampled into memory by the master clock, slave clock, or both (demultiplex).

The Pod Clock field and the clocking arrangement are only available in a state analyzer.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

The Sampling Tab

Master

Data on all pods assigned to Master Clk is strobed into memory when the status of the clock lines match the clocking arrangement specified for Master in the clock setup.

Slave

Data on a pod designated Slave Clock is latched when the status of the slave clock inputs meet the requirements of the slave clocking arrangement. Then, followed by a valid master clock, the slave data is strobed into analyzer memory along with the master data.

If multiple slave clocks occur between master clocks, only the data latched by the last slave clock prior to a valid master clock is strobed into analyzer memory.

Latching Slave Data

Demultiplex

The demultiplex mode is used to store two different sets of data that occur at different times on the same channels. In demultiplex mode, only one pod of the pod pair is used, and that pod is selectable (see page 69). Channel assignments are displayed as Pod and Slave Pod. Assign slave and master data to separate labels for easy recognition of the two sets of data.

Both the master and slave clocks are used in the demultiplex mode. When the analyzer sees a match between the slave clock input and the slave clock arrangement, demux slave data is latched. Then, following a valid master clock, the slave data is strobed into analyzer memory

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

The Sampling Tab

along with the master data. If multiple slave clocks occur between master clocks, only the data latched by the last slave clock prior to the master clock is strobed into analyzer memory.

Latching Demultiplex Data

Naming the Analyzer

The Analyzer Name field under Sampling lets you assign a specific name to the analyzer. When you have stored several measurement setups to disk and later reload them, having assigned a specific name to an analyzer can help identify what the setup is for. The analyzer name is also used in the workspace to label the analyzer icons and as part of the title of the analyzer setup window.

There are two analyzers per logic analyzer module. To activate the second one, go to the Workspace window and drag the second analyzer on to the workspace.

The default names for the analyzers are Analyzer<N> and Analyzer<N2>, where N is the slot of the analyzer module.

To Name an Analyzer

1. Select the Analyzer Name field.

2. Enter the new name.

The name now appears below the instrument tool icon in the workspace.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

The Sampling Tab

Turning the Analyzer Off

The On and Off checkboxes under the Sampling tab are a shortcut for activating and de-activating the analyzer.

Analyzers come up in the On state. If you select the checkbox, the label changes to Off and the Analyzer Shutdown Options dialog appears.

Soft

"Soft" shutdowns have the same effect as though you selected Off in the Type control of the Pod Assignment dialog under Format. The analyzer window remains, but most options are unavailable. Soft shutdowns are easily reversed by selecting the box next to Off.

Hard

"Hard" shutdowns have the same effect as deleting the analyzer icon from the workspace. The analyzer window and the windows of its display tools are closed, and the analyzer is removed from the workspace. To turn the analyzer back on, select the analyzer icon in the System window. You will need to restore any complex analysis or display tools.

Sample Period (Timing Only)

Sample Period is used to set the time between data samples. The inverse of sample period is sample rate. Every time a new sample is taken, the analyzer will see updated measurement data. The choices available for sample period depend on the acquisition mode.

If your analyzer is set to timing, the Sample Period control is located under the Sampling tab’s Timing Mode Controls and under the Trigger tab’s Settings sub-tab.

If your analyzer is set to state, the Sample Period control is not available. Its functionality is handled by the Clock Setup.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

The Sampling Tab

State Acquisition Modes

100 MHz / 128K State

All pods are available. Memory depth is 128 K samples per channel. If time or state count is turned on in Trigger Settings, the total memory is split between data acquisition storage and time or state count storage. To maintain the full memory depth of 128 K samples per channel, leave one pod pair unassigned. (To unassign a pod pair, select the Pod Assignment button under the Format tab; then, drag a pod pair to unassigned.) State clock speed matches your target system’s clock, up to 100 MHz.

Timing Acquisition Modes

In conventional timing acquisition mode the analyzer stores measurement data at each sampling interval.

128K Sample Full Channel 250MHz Max

The total memory depth is 128 K samples per channel, with data being sampled and stored as often as every 4 ns. You can set the sample rate to go slower with the Sample Period control.

256K Sample Half Channel 500MHz

Only one pod of each pod pair is available. Channels assigned to unavailable pods are ignored. You can specify which pod to use by toggling the Pod field. The total memory depth is 256K samples per channel. Data is sampled and stored every 2 ns; this rate cannot be changed.

See Also “Sample Period (Timing Only)” on page 46

“Pod Selection” on page 69

Transitional Timing Acquisition Modes

In transitional timing modes, the timing analyzer samples data at regular intervals just like it does in conventional timing mode. However, in transitional timing mode, it only stores data when there is a change on the lines assigned to a label within a pod pair.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

The Sampling Tab

Data is collected on a pod pair basis, even when labels cross pod boundaries. It is still displayed on a label basis, however. Because of this, some pod pairs with less active channels may take longer to fill memory and the end of the acquisition is delayed. Debugging will be simpler if you restrict labels to a single pod-pair when using transitional timing mode.

Each time a transition occurs on any of the assigned bits, all bits of the pod pair are stored along with a time tag. If transitions are exceptionally far apart, the timer which generates the time tags may overflow.

NOTE: The timer does not generate a warning when it overflows. If the time between

transitions in the display seems too short, it may be due to timer overflow.

“64K Full Channel Transitional 125-MHz Mode” on page 48

“Other Transitional Timing Considerations” on page 49

Minimum and Maximum Transitions Stored

64K Full Channel Transitional 125-MHz Mode. The total memory depth is 64K samples per channel.

The analyzer uses half its memory (64K) to store time tags. Because each pod pair stores transitions at its own rate, you do not have the option of using a free pod to retain full memory as you have in the state mode.

Data is sampled for new transitions every 8 ns; this rate cannot be changed. When a transition on any of the assigned channels is detected, the data for the entire pod pair is stored.

When a transition is detected after a sample with no detected transition, two samples are stored. One sample is a "before transition sample" and the other is an "after transition sample." As long as there are transitions in the subsequent sample, only one sample is stored. When the next sample occurs without a transition, the two stored sample sequences (one before, one after) repeats with the next detected transition.

Minimum Transitions Stored

Normally, transitions have not occurred at each sample period. This is

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

The Sampling Tab

illustrated below with time-tags 2, 5, 7, and 14. When transitions happen at this rate, two cycles are stored for every transition.

Maximum Transitions Stored

If transitions occur at a fast rate, such that there is a transition at each sample point, only one sample is stored for each transition as shown by time tags 17 through 21 below. If this continues for the entire trace, the number of transitions stored is 64K samples.

In most cases a transitional timing trace is stored by a mixture of the minimum and maximum cases.

“Other Transitional Timing Considerations” on page 49

Other Transitional Timing Considerations.

Pod Pairs are Independent

In single run mode, each pod pair runs independently. When one pod pair fills its trace buffer, it will not shut the others down. If there is a pod pair with enabled data bits and with no transitions, you get a message "Storing transitions after trigger for pods nn/nn." In repetitive run mode, a full pod pair waits 2 seconds, then halts all other pod pairs.

Increasing Duration of Storage

A transition on any one of the 34 bits for each pod pair (if they are all assigned to labels) will cause storage. Reducing the number of bits that are turned on for any one pod pair will more than likely increase data storage time. Separating channels which contain fast occurring transitions from channels with slow occurring transitions also helps. If separating the channels, be sure to use different pod pairs. It does not

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

The Sampling Tab

help to move fast lines from pod 1 to pod 2; they must be moved to pod 3, which is a different pod pair.

Invalid Data

The analyzer only looks for transitions on bits that are assigned. If the bit is assigned after a run by changing the label and selecting Apply in the analyzer window, another run is automatically started.

Comparison of Transitional and Conventional Timing Modes

In Conventional Timing Acquisition mode, the analyzer stores measurement data at each sampling interval. In Transitional Timing Acquisition mode, the timing analyzer samples data at regular intervals, but only stores data when there is a threshold level transition. Each time a level transition occurs on any of the bits of a pod pair, data on all channels is stored. A time tag is stored with each stored data sample so the measurement can be reconstructed and displayed later.

When using transitional timing, you might consider how many transitions can be stored. The number depends on the mode and frequency of transition occurrence.

See Also “Timing Acquisition Modes” on page 47

“Transitional Timing Acquisition Modes” on page 47

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

The Sampling Tab

Trigger Position Control

The Trigger Position control, located under Sampling and also Tr i gger Settings, determines how much data is stored before and after the trigger occurs for all subsequent acquisitions. The trigger point is

placed at a specified position relative to the data in memory. The analyzer triggers differently depending on if it is in Timing or State mode.

Timing Mode

When a Run is started, the analyzer will not look for a trigger until at least the proper percentage of pretrigger data has been stored. After a trigger has been detected, the specified percentage of posttrigger data is stored before the analyzer halts.

State Mode

When the Run is started, the analyzer immediately looks for the trigger condition. The percentage of pretrigger data determines the maximum amount of pretrigger data to save.

The trigger position choices are Start, Center, End, User Defined, or Delay. Delay is only available in timing mode.

• Start

The trigger position is set at the starting point of available memory. This process results in maximum posttrigger data and minimum pretrigger data. Note that there will be a small amount of pretrigger data stored.

• Center

The trigger position is set at the center point of available memory. This results in half pretrigger data and half posttrigger data.

• End

The trigger position is set at the end point of available memory. This results in maximum pretrigger data and minimum posttrigger data. Note that there will be a small amount of posttrigger data stored.

• User Defined

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

The Sampling Tab

When the trigger position is set to User Defined, a trigger position slider appears. Use this slider to set the trigger position any where between 0% and 100%. As the slider is adjusted, the % Post Store indicator shows the amount of data that will be stored after the trigger point.

• Delay

This option delays the start of data storage until some time after the trigger. The range of the delay time is affected by the sample period, but it could range between 16 ns to 8 ks.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

The Format Tab

Under Format, you specify the parts of the target system that you want the logic analyzer to look at. You set up labels to match the buses of the target system, and set the threshold level for the signals. For a state measurement, you also adjust the setup and hold time.

For advanced measurements, Format is also where you assign pods and specify whether to look at channels on the master, slave, or demultiplexed clock.

Common Measurement Controls

Advanced Measurement Controls

See Also “Data On Clocks Display” on page 64

“Labels: Mapping Analyzer Channels to Your Target” on page 68

“Setting the Pod Threshold” on page 70

“State Clock Setup/Hold (State only)” on page 71

“Assigning Pods to the Analyzers” on page 63

“Clock Modes (State only)” on page 43

“Setting Up the Pod Clock” on page 68

“Pod Selection” on page 69

“Activity Indicators” on page 62

“Assigning Bits to a Label” on page 64

“Inserting and Deleting Labels” on page 65

“Turning Labels On and Off” on page 66

“To reorder bits in a label” on page 67

“Importing Netlist and ASCII Files” on page 54

“Label Polarity” on page 66

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Importing Netlist and ASCII Files

Netlist Files

The Netlist Import feature provides a method for importing busses and signals from ASCII netlists created by EDA tools. In order for the feature to work, the device under test must either use the Agilent E5346A high density adapter or the Agilent Technologies Termination Adapter. The adapter must be included as a connector in the netlist.

You can create a Netlist file using an EDA tool. When importing a Netlist file, you can specify which connectors are of interest; connectors that are not specified will be ignored.

Example

NET‘/Bus1(3)‘J1-7

Bus1 Four bit bus

(3) Bit 3

J1-7 Connector J1, pin 7

To Import a Net List

1. Configure the connector names referenced in the Netlist to logic analyzer pods.

2. Specify the Net List file to import.

3. Verify that Nets were correctly mapped to Labels, Pods, and Channels.

ASCII Files

4. Select or create labels to appear in the interface.

Map the Connector Names (see page 60).

Import the Net List File (see page 60)

Verify Net to Label Mapping (see page 61)

Select/Create Interface Labels (see page 62)

You can create an ASCII file using any Windows, MS-DOS, or UNIX text editor. The ASCII file should contain bus names, pod/clock numbers, and channel definitions.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Importing Netlist and ASCII Files

For Example

Label1;A2[15:5];A1[5,2]

Label1 Bus Name

A2 and A1 Pod Numbers

[15:5] Channel 15 through Channel 5 ("***********.....")

[5,2] Channel 5 and Channel 2 ("..........*..*..")

When setting up the ASCII file a comma (",") separates individual channels, while a colon (":") creates a range of channels.

The following provides an explanation of how to setup and import ASCII files into a logic analysis system.

Setting Up ASCII Files

NOTE: If the analyzer is in state mode with the Clock Setup Mode set to

demultiplexer, slave pods will appear with an "S" in front of the pod designation.

For example:

Label1;SA2[5] reads as Label1 maps to Slave Pod A2 Channel 5.

Individual channels

Label1;A2[5] Label1 maps to Pod A2, Channel 5

Multiple channels

Label1;A1[5:2,0] Label1 maps to Pod A1, Channel 5 through Channel 2 and

Channel 0.

Individual channels on different pods

Label1;A2[1];A1 [0] Label1 maps to Pod A2, Channel 1 and Pod A1, Channel 0.

Multiple channels on different pods

Label1;A3[15:5]; A2[5];A1[6] Label1 maps to Pod A3, Channel 15 through Channel 5,

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Importing Netlist and ASCII Files

Pod A2 Channel 5, and Pod A1 Channel 6.

Clocks

Label1;CK[AK] Label1 maps to Slot A Clock K.

“Importing ASCII Files” on page 56

“Exporting ASCII Files” on page 56

See Also “Ter mination A d a p ter” on page 58

“E5346A High Density Adapter” on page 59

Considerations when creating an Import file.

When updating a label ensure that the label is turned on. Labels that are not active will not be updated.

Other considerations:

• Maximum of 126 labels

• Maximum of 20 characters per label. (The system truncates after 20

characters.)

• Maximum of 32 channels per label.

Exporting ASCII Files

1. Select the Format tab.

2. Select File, then select Export Label...

Importing ASCII Files

Shown below is the default setup:

Label1;A1[15:0]

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Importing Netlist and ASCII Files

To Import an ASCII file.

1. Create an ASCII file for importing into the logic analysis system. For example:

Lab2;A2[15:10,6,3]

NewLabel2;A2[15]

Label1;A1[15:0]

2. Select the Format tab.

3. Select File, then select Import Labels...

4. Select the ASCII file you created.

5. Select OK.

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Importing Netlist and ASCII Files

Termination Adapter

The logic analyzer cable must have the proper RC network at its input in order acquire data correctly. The Termination Adapter incorporates the RC network into a convenient package. It also reduces the number of pins required for the header on the target board from 40 pins to 20.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Importing Netlist and ASCII Files

E5346A High Density Adapter

The E5346A high-density adapter provides a convenient and easy way to connect an Agilent logic analyzer to the signals on your target system for packages that are difficult to probe. An Amp "Mictor 38" connector must be installed on your target system board.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Importing Netlist and ASCII Files

Mapping Connector Names

1. Select the Format tab.

2. Select File, then select Import Netlist.

3. Select Next to go to the Mapping Connector Names dialog.

4. Enter a connector name from the Netlist.

5. Select the type of adapter.

6. Select the logic analyzer pods that are plugged into the adapters.

7. To map more connector names, select Add Connector and repeat the

steps above.

8. Select Next.

Import the Net List File

1. Select Select Netlist File.

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Importing Netlist and ASCII Files

2. Select the file from the File Selection dialog box.

3. Select OK

4. Select Next

Verify Net to Label Mapping

1. Verify that each net was properly imported into a label.

2. Select Next

The list provided, see example below, is the mapping from the logic analyzer pods and channels to labels.

The label column is editable so you can make changes if necessary. If you need to delete labels, this can be done more efficiently in the next dialog box.

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Select/Create Interface Labels

Select any additional labels to be copied into the Format tab. Typically there is no need to add any more labels. However, this screen is useful when you want to designate a signal bit in a bus as a separate label name. It can also be used to delete unneeded labels.

Once you have completed editing the labels, select Done.

Activity Indicators

Activity indicators are the arrows and dashes associated with the pods. They appear in various places, primarily above the column of bit assignment fields in Format and in the Clock Setup area.

When the logic analyzer is properly connected to an active target system, you see arrows in the Activity Indicator displays for each

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

channel. An active channel looks like .

A dash at the top of the activity indicator display indicates that the signal connected to that channel is electrically high (above the threshold voltage). A dash at the bottom indicates that the signal is electrically low. An arrow indicates that the signal is transitioning.

Activity indicators are not affected by label polarity. (see page 66)

You can use these indicators to check whether there is proper probe connection: bits that are stuck high or low may not be properly connected. You can also verify that the signals in your target system are active: bits that are stuck high or low are not crossing the threshold voltage.

Activity indicators are not displayed during an acquisition.

See Also “Setting the Pod Threshold” on page 70

Logic Analysis System and Measurement Modules Installation Guide for details on probing

Importing Netlist and ASCII Files

Assigning Pods to the Analyzers

The Pod Assignment... button under Format can be used to start the second analyzer on the module and to assign pod pairs.

To Assign Pods to an Analyzer

1. In the Format tab, select the Pod Assignment... button. The Pod Assignment window appears.

2. Drag a pod pair and drop it below the analyzer that you want to assign it to.

3. For pods that you do not want to use, drag and drop them in the Unassigned Pods area. This preserves memory depth when count is turned on.

NOTE: When both analyzers are turned on, pods 1/2 and 3/4 of the master card can

not be assigned to the same analyzer.

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Pods can only be assigned on a per-pair basis to either of the two analyzers. Each pod pair has two clock channels, but only the clock channels of pods on the master card can be used in the analyzer’s clocking setup. These pods do not need to be assigned to that particular analyzer, however.

To turn on an analyzer that is off, select the Off option button and choose State or Tim in g. (Only one analyzer at a time can be set to Timing .) A second analyzer window appears after a pause for setup.

Data On Clocks Display

The Data On Clocks display column, to the left of the pods’ bit reference line, is a display of all clock inputs available as data channels in the present configuration. This includes those clocks on expander cards, which cannot be used in the clock setup.

To use a clock channel as a data channel, assign the clock bit to a label. Labels containing clock bits cannot be used in range terms where the clock bits span more than one pod pair.

Activity indicators above the clock identifier show signal activity.

See Also “Assigning Bits to a Label” on page 64

“Activity Indicators” on page 62

Assigning Bits to a Label

The bits in a label correspond to the physical logic analyzer probe channels. When you run the analyzer, data is gathered on all bits

(channels) that are assigned to labels. Unassigned bits are inactive.

( * ) (asterisk) indicates an assigned bit. ( . ) (period) indicates an unassigned bit. ( R ) indicates an assigned bit in a reordered label.

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To Assign Bits

1. Select the bit assignment label to the right of the label name you want to define. Each bit assignment label corresponds to the data pod which is listed above it.

2. Either choose one of the predefined groups, or Individual.

3. In Individual, select the bits to toggle them between an asterisk and a period.

NOTE: Labels can have a maximum of 32 channels assigned to them.

Bits assigned to a label are numbered from right to left. The least significant assigned bit on the far right is numbered 0. The next assigned bit to the left is numbered 1, and so on. Labels can contain bits that are not consecutive; however, bits are always numbered consecutively within a label. Above each column of bit assignment fields is a bit reference line that shows you the bit numbers and activity indicators.

See Also “To reorder bits in a label” on page 67

“Activity Indicators” on page 62

Inserting and Deleting Labels

To Insert Additional Labels

1. Select the label name button that you want to insert another label next to.

2. Choose Insert before... or Insert after....

To Delete Labels

1. Select the button of the label name that you want to delete.

2. Choose Delete.

The bit assignments of deleted labels are not saved. You can make a label inactive but not lose its assignment by turning it off (see page 66)

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instead.

Turning Labels On and Off

You may want to turn off labels that you have created so that the label is not displayed. When a label is turned off, its name and bit assignments are preserved.

To Turn Off a Label

1. Select the button of the label name that you want to turn off.

2. Choose Label [ON] to toggle it off.

If the label is the only one, it cannot be turned off or deleted. If there is more than one label but it is the only one on, turning it off turns the first label back on.

To Turn On a Label

1. Select the button of the label name that you want to turn on.

2. Choose Label [OFF] to toggle it on.

To Display a Label that was Off

1. Turn on the label.

2. At the bottom of the window, select the Apply button.

The label’s data appears in the display windows.

Label Polarity

The analyzer uses the label polarity to identify patterns when triggering and displaying data.

To change the label polarity, select the polarity field, which toggles between positive (+) and negative (-). Positive polarity means that a high voltage is a logical "1". Negative polarity means that a high voltage is a logical "0".

Changing the label polarity after you have set up other parts of the measurement changes these things:

• "1" and "0" values flip in trigger terms

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• waveforms and bus values (where shown) invert in the Waveform Display tool

• "1" and "0" values flip in the Listing Display tool

Changing the label polarity does not change these things:

• Edge definitions for clock setup and edge terms

• Symbol definitions for the logic analyzer

The default polarity for all labels is positive (+). The various display tools, in particular the Waveform Display tool, all show logical values and are affected by polarity changes.

NOTE: Negative logic is rare in circuits. The main exception at this time is RAMBUS.

To reorder bits in a label

In cases where buses in the device under test haven’t been probed with consecutive logic analyzer channels, you can reorder the bits in a label.

1. In the Format tab, select the label button whose bits you want to reorder.

2. Choose Reorder bits.

3. In the Change Bit Order dialog:

• To reorder the bits individually, enter the bit that the probe channel

should be mapped to.

• To swap the high and low order bytes or words, select the button Big

Endian to Little Endian at the bottom of the dialog.

• To return to sequentially ordered bits, select the button Default Order

at the bottom of the dialog.

4. Select the OK button.

The label now shows an "R" to indicate that the assigned bit has been reordered.

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NOTE: Labels with reordered bits cannot be used as range terms or <, <=,>, >= in

triggers.

Labels: Mapping Analyzer Channels to Your Target

Labels group and identify related channels, such as buses, in a way that is relevant to your system under test.

A single label can include data and clock channels from more than one pod, but this places restrictions on the complexity of the trigger later.

You can define 126 labels per analyzer. Each label can contain up to 32 channels per label.

To Define a Label

1. (Optional) Select the label name button and choose Rename

2. Enter a new name and select the OK button.

3. Assign bits (see page 64) to the label.

4. If necessary, insert more labels (see page 65) in the list.

See Also “Assigning Bits to a Label” on page 64

“To reorder bits in a label” on page 67

“Inserting and Deleting Labels” on page 65

“Turning Labels On and Off” on page 66

“Label Polarity” on page 66

Setting Up the Pod Clock

There is one Pod Clock field for each pod in the machine. It only becomes visible when the Clock Setup under the Sampling tab is set

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to Master/Slave or Demultiplex. The Pod Clock field is located just below the Pod Threshold in Format.

The Pod Clock field is set to Master Clk by default. Use the Pod Clock field to indicate if the pod’s data is to be strobed into memory by the master clock, slave clock, or both, in the demultiplex mode.

When the Pod Clock is set to Demultiplex, only one pod of a pod pair is usable. That pod latches data on both the master and slave clocks, so it appears twice in the label area. To select which pod of a pod pair you want to demultiplex, select the Pod Field.

See Also “Performing Clock Setup (State only)” on page 42

“Clock Modes (State only)” on page 43 for details on slave and demultiplex

clocks

“Pod Selection” on page 69

Pod Selection

The Pod field in Format identifies which pod of a pod pair the settings of the bit assignment field, pod threshold field, and pod clock fields effect. Most of the time it is simply informational. The exceptions are noted below.

Half-Channel Mode

In the half-channel mode, the Pod field becomes a button that you can use to select which pod of a pod pair all pod settings apply to. In the full-channel modes, this field is simply an identifier and is not selectable.

Demultiplex Clock Mode

In the demultiplex clock mode, use the pod field to select which pod of a pod pair is to be used to sample data. In the master or slave clock modes, this field is simply an identifier and is not selectable.

See Also “Setting the Acquisition Mode” on page 42

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“Performing Clock Setup (State only)” on page 42

Setting the Pod Threshold

The pod threshold is a voltage level which the data must cross before the analyzer recognizes it as a change in logic levels. You can specify a threshold level for each pod. The level specified for the master pod that includes the clock is also used for the clock threshold.

Standard

1. In the Format tab, select the threshold button located just below the pod

name.

2. In the Pod threshold dialog, choose one of the standard threshold options:

• TTL -- The threshold level is +1.50 volts.

• LVTTL -- The threshold level is +1.40 volts.

• SSTL2 -- The threshold level is +1.50 volts.

• SSTL3 -- The threshold level is +1.25 volts.

• LVCMOS 1.5v -- The threshold level is +0.75 volts.

• LVCMOS 1.8v -- The threshold level is +0.90 volts.

• LVCMOS 2.5v -- The threshold level is +1.25 volts.

• LVCMOS 3.3v -- The threshold level is +1.65 volts.

• CMOS 5.0v -- The threshold level is +2.50 volts.

• ECL -- The threshold level is -1.3 volts.

• LVPECL -- The threshold level is 2.00 volts.

3. If you don't want the change to apply to all pods, deselect the checked box

next to Apply settings to all pods.

4. Select the Close button.

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User Defined

When User Defined is selected, the threshold level is selectable from -

6.0 volts to +6.0 volts.

NOTE: The logic analyzer requires a minimum voltage swing of 500 mV at the probe

tip to recognize changes in logic levels.

NOTE: The threshold voltage specified also applies to the pod’s clock input.

State Clock Setup/Hold (State only)

Setup/Hold in Format adjusts the relative position of the clock edge with respect to the time period that data is valid. It is only available when the analyzer is set up for a state measurement.

To Change Clock Setup/Hold

1. Select the Setup/Hold button.

2. For each pod pair, choose a Setup/Hold selection from the selection list.

3. Select the OK button.

With a single clock edge assigned, the choices range from 4.0 ns Setup/

0.0 ns Hold, to 0.0 ns Setup/4.0 ns Hold. With both edges of a single

clock assigned, the choices are from 4.5 ns Setup/0.0 ns Hold, to 0.0 ns Setup/4.5 ns Hold. If multiple clocks are assigned, the choices range from 5.0 ns Setup/0.0 ns Hold, to 0.0 ns Setup/5.0 ns Hold.

The relationship of the clock signal and valid data under the default setup and hold is shown in the figure below for a generic logic analyzer.

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Default Setup and Hold

If the relationship of the clock signal and valid data is such that the data is valid for 1 ns before the clock occurs and 3 ns after the clock occurs, you will want to use the 1.0 setup and 2.5 hold setting.

Clock Position in Valid Data

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The Trigger Tab

The Trigger tab is used to set up a sequence that tells the analyzer when to capture data. The key event is the trigger.

The Trigger tab has two main areas: On top, tabs of functions and controls to build your trigger; and beneath the tabs, the current trigger sequence.

Some controls are also located in the logic analyzer window’s menu bar.

•“Understanding Logic Analyzer Triggering” on page 74

•“Setting Up a Trigger” on page 76

•“Inserting and Deleting Sequence Steps” on page 77

•“Editing Sequence Steps” on page 78

•“Setting Up Loops and Jumps in the Trigger Sequence” on page 79

•“Saving and Recalling Trigger Sequences” on page 80

•“Clearing Part or All of the Trigger” on page 81

See Also “Overview of the Trigger Sequence” on page 81

“Trigger Functions” on page 82

“Working with the User-level Function” on page 89

“Defining Resource Terms” on page 92

“Trigger Position Control” on page 51

“Sample Period (Timing Only)” on page 46

“Tagging Data with Time or State Tags (State Only)” on page 99

“Arming Control” on page 99

“Context Store Measurements (State Only)” on page 101

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Understanding Logic Analyzer Triggering

What is a Trigger (see page 74)

What does "Trigger Position" Mean (see page 74)

What can be Used to Specify a Trigger (see page 75)

When to use a Combination, a Branch, or a Level (see page 75)

What is a Trigger

In simplest terms, a trigger is an event that tells the logic analyzer to finish filling its acquisition memory. The memory functions like a conveyor belt: new samples are always coming in, and old samples "falling off" (being overwritten). The logic analyzer has room for 128 K samples. When this is full, the only way to fit in new data is to discard the old.

After you specify your trigger sequence and press run, the logic analyzer searches incoming data for events in the trigger sequence. Using the conveyor belt metaphor again, it is like someone tending the conveyor belt who has been told to stop the belt when a certain sample is seen.

The trigger is not like an oscilloscope trigger. Logic analyzers trigger only once per run, even when more than one sample matches the trigger event. Logic analyzer trigger events are like special switches to stop the evaluation process and just fill memory.

What does "Trigger Position" Mean

Because the logic analyzer is continually looking at data from your target system after you select Run, and because the trigger is a single event, you can arrange to collect data relative to it. It is like the person running the conveyor belt is told to stop the belt when the special sample reaches a certain position.

The default trigger position is in the middle. This means there are

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approximately as many samples before the trigger as after. You can also arrange for the trigger to be at the beginning of the "conveyor belt" (acquisition memory), the end, or any percentage along it.

What can be Used to Specify a Trigger

The trigger sequence can be as simple as one event to look for, or a complicated set of branching levels that loop back and jump around. Both types of triggers use a small set of standard resources.

Pattern Pattern terms are things such as ADDR=0880 or R/W=1.

Generally they represent values on buses. You can set patterns to match imprecise events, too. See “Using Bit Pattern Terms” on page 93.

Range Range terms match a range of values on a label or bus. For more

detail, see “Using Range Terms” on page 94

Tim er Timers are started in one sequence level and checked in another.

They act like stopwatches. See “Using Timer Terms” on page 96 for more information.

Edge Edge terms are similar to edges in oscilloscopes. They are only

available for some types of measurements. Edge terms can check for edges on more than one signal at a time, but not all edges have to occur at the same time. To require that, combine edge terms with ANDs.

Combinations of Terms To check for more than one type of thing

happening in the same sample, combine terms within a sequence level using AND and OR. There are restrictions on exactly which terms can be ANDed and which ORed. The restrictions are covered in “Using Combinations of Terms” on page 97.

When to use a Combination, a Branch, or a Level

To check for simultaneous occurrences, use combinations of terms. All the events described by the terms must happen in the same sample.

To take different actions depending on which events happen in a sample, use branches within a sequence level. A branch functions like a set of "if statements" in programming. The sample is checked against

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all branches, and the first branch that matches is taken. See “Setting Up Loops and Jumps in the Trigger Sequence” on page 79 for more on branching.

To look for a sequence of events (for example, first look for a memory reference on ADDR, then a certain value on DATA, and when IRQ goes low, trigger) use different sequence levels. When a sample matches the event described in a sequence level, the analyzer goes to the next sequence level and compares the rest of the incoming events. When the logic analyzer reaches the trigger level and finds a sample that matches the trigger event you specify, the logic analyzer triggers.

Setting Up a Trigger

When setting up a trigger sequence, you typically trigger first on a simple pattern or edge. From that point, you execute an iterative process of adding or fine-tuning sequence steps until the analyzer consistently triggers at the desired point.

To Set Up a Trigger

1. Define resource terms. (see page 92)

2. Select the most appropriate trigger function and select the Replace button. (see page 76)

3. Select the sequence level number button and choose Edit. (see page 78)

4. If necessary, insert and edit additional sequence steps. (see page 77)

See Also “Trigger Functions” on page 82

“Working with the User-level Function” on page 89

“Overview of the Trigger Sequence” on page 81

Selecting a Function to Match Trigger Conditions

Review the list of trigger functions and select the one that matches the event you are looking for. In most cases one of the predefined functions provides a good starting point. If none of the predefined trigger

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functions match choose User level at the end of the list.

For a picture corresponding to the trigger function, select the function from the list. The area to the right shows a picture of the function’s effect. The function itself is not inserted into the trigger sequence unless you select the Replace or Insert button.

See Also “Trigger Functions” on page 82

Inserting and Deleting Sequence Steps

NOTE: For state measurements, the last level of the trigger sequence is always a

Store level. It cannot be deleted. For timing measurements, the last level must contain the TRIGGER action.

To Insert Sequence Steps

Trigger Sequence Editing Options

1. Select the sequence level that you want to insert other steps around.

2. Select a trigger function from the list in the Trigger Functions tab.

3. Choose the Insert Before or Insert After button.

To Delete Sequence Steps

1. Select the sequence step that you want to delete.

2. Select the Delete button.

When you select a sequence level, you see a selection menu with choices that allow you to modify the sequence. Choose the option you want from the choices below.

• Edit

Changes the contents of the sequence step. You can change the resource terms or other assignment fields, such as durations and occurrences.

• Copy

Copies the currently selected step. When you copy a level, the new level contains the same function as the original.

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• Replace

Replaces the currently selected level with the currently highlighted trigger function.

• Delete

Deletes the level that is currently selected.

• Insert Before / Insert After

Inserts an additional step before or after the selected step.

• Trigger Level (State only)

Makes the current step the trigger level.

• Default (State only)

Only appears in the menu for the last step in a state trigger sequence. The last state always stores to fill memory. Default returns the state to Store anystate.

Editing Sequence Steps

You can modify the contents of a step in the trigger sequence by editing it.

To Edit a Sequence Step:

1. Select the sequence level number button and choose Edit....

2. Select a term name to choose a different term. You can also choose negations of terms and combinations of terms.

3. Set the values of the other fields, such as durations and occurrence counts.

4. Select the Close button to close the sequence step editing dialog.

To set the value of a term used in a sequence step, see “Defining Resource Terms” on page 92.

If you are editing a user-level function, refer to:

“Setting Pattern Durations and Occurrence Counts” on page 91 (Timing

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Only)

“Using Occurrence Counters” on page 91 (State Only)

“Using Timer Terms” on page 96

“Setting Up Loops and Jumps in the Trigger Sequence” on page 79

Setting Up Loops and Jumps in the Trigger Sequence

To set up loops and jumps in your trigger sequence, use Branches. Branches are available in most of the Trigg e r F unction s . You may need to break down the functions (see page 88) in order to set up branches.

NOTE: If either the < or the > durations are selected, only the primary Find or

Trigger on selection is available. If the occurs duration is selected, the

secondary (Else on) branch becomes available. If the Find field is an edge, only occurs is available.

To Set Up a Branch or Loop

1. Select the Find button and choose the term that you want to branch on. If

this term is found in the incoming data, the analyzer will follow this branch and go to the next trigger sequence level.

2. If you want a secondary branch, select the Else on button and choose the

term that you want to branch on.

3. Select the goto level option button and select the sequence level that you

want to branch to.

If the first branch is taken, the analyzer goes to the next level. If the term in the first branch is not found, the analyzer immediately evaluates the Else on secondary branching term. The analyzer only triggers when the TRIGGER primary branch is taken.

If the Else on term is found, the secondary branch is taken to the designated sequence level, and the occurrence counter is reset even if the branch loops back to the same level. If the Else on term is not

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found, the analyzer stays at the same sequence level until one of the two branches is found. If both branches are found true at the same time, the first branch is taken.

See Also “Breaking Down and Restoring Functions” on page 88

“Branches Taken Stored / Not Stored (State only)” on page 92

Saving and Recalling Trigger Sequences

You can save a trigger sequence independently of configuration files within a session by using Save/Recall. Recalling the stored trigger sequence can change the trigger arming, memory depth, and trigger position as well as the trigger sequence and term definitions. The trigger sequence specification will not change the acquisition mode (full channel vs. half channel).

The Agilent Technologies 16712A logic analyzer can hold up to 10 trigger sequence specifications per mode per machine, for a total of 40 specifications. When you exit your Agilent Technologies 16700A/B session, the trigger sequences are cleared. They can be saved across sessions or be shared across logic analyzers as part of a configuration file, however.

To Save a Trigger Sequence

1. In the Trigger tab, select the Save/Recall subtab.

2. Enter a descriptive name for the trigger sequence in the Title field.

3. Select the Save button.

4. Select a memory location to store the trigger sequence in.

To Recall a Trigger Sequence

1. In the Trigger tab, select the Save/Recall subtab.

2. Select the Recall button.

3. Choose the trigger sequence that you want.

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If one of the settings in the recalled trigger sequence conflicts with the acquisition mode, it will be set to the closest setting for that mode.

Clearing Part or All of the Trigger

To Clear Part or All of the Trigger:

1. Select the Tr i g ger tab.

2. Select Clear from the menu bar.

3. Choose the option you want from the choices described below:

• All

Clears sequence steps, resource terms, resource term names, and trigger position back to their default values. Turns on Count Time.

• Sequence Levels

Resets the trigger sequence to the default sequence for the analyzer acquisition mode.

• Resource Terms

Resets all resource term assignment fields, including labels and values, back to their default values. The default is usually for all terms to be on the first label, with value XXXX.

• Resource Term Names

Resets all the resource term names to their default values, Pattern1 through Pattern9 and Patt10.

• Save/Recall Memories

Deletes all saved trigger sequence specifications.

Overview of the Trigger Sequence

The trigger sequence is a sequence of steps that control the path that the analyzer takes to find the trigger event. The path taken resembles a

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flow chart, with each step in the sequence being an opportunity to direct the analyzer’s selection. You can edit the overall trigger sequence by inserting or deleting sequence steps (see page 77).

Each step in the sequence is either a predefined trigger function (see page 82) or a user-level step (see page 89). Both the trigger functions and user-level steps contain variables that you define. The variables, called resource terms (see page 92), represent edges and bit patterns in the data.

When you run the analyzer, it searches for a match between the resource term values and the measurement data. When a match is found, the sequencing continues to the next step, loops back (see page 79) to a previous step, or jumps ahead to another step. Eventually, a path of "true" steps leads to the trigger event.

Each macro uses one or more of the analyzer’s internal sequence levels (see page 89). Each user-level step uses one internal sequence level.

See Also “Understanding Logic Analyzer Triggering” on page 74 for more detail

“Setting Up a Trigger” on page 76 for actual steps

Trigger Functions

Trigger functions provide a simple way to set up the analyzer to trigger on common events and conditions. A library of functions is available for both state and timing measurements.

NOTE: Each trigger function requires at least one internal sequence level (see

page 89), and in some cases, multiple levels. The number of levels used by each function is described in the references below.

Timing Trigg er Functions

“Basic Timing Trigger Functions” on page 83

“Pattern/Edge Combinations” on page 84

“Time Violations” on page 85

“Timing User Level” on page 83

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State Trigger Functions

See Also “Setting Up a Trigger” on page 76

“Basic State Trigger Functions” on page 86

“Sequence-Dependent Trigger Functions” on page 86

“Time Violations” on page 87

“State User-level” on page 85

“Defining Resource Terms” on page 92

“Breaking Down and Restoring Functions” on page 88

Timing User Level

The User level trigger function allows you to create a custom trigger sequence using terms, a comparison function, and a secondary branch

if the comparison function is occurs. This trigger function uses one internal sequence level.

See Also “Working with the User-level Function” on page 89 for more information on

the user-defined mode.

Basic Timing Trigger Functions

The following basic trigger functions are found in Trigger Functions when the analyzer is in timing mode. Each function uses one internal sequence level.

• Find edge. This function becomes true when the edge you have designated is seen. It uses one internal sequence level.

• Find anystate n times. This function becomes true with the nth state it sees. It uses one internal sequence level. It is equivalent to having the analyzer wait in the sequence level for (n x Sample Period) seconds.

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• Find nth occurrence of an edge. This function becomes true when it finds the designated occurrence of an edge you have designated. Note that the 500-MHz trigger sequencer may not count edges that occur closer than 2 ns. This function uses one internal sequence level.

• Find pattern present/absent for > duration. This function becomes true when it finds a pattern you have designated that has been present or absent for greater than or equal to the set duration. It uses one internal sequence level.

• Find pattern present/absent for < duration. This function becomes true when it finds a pattern you have designated that has been present or absent for less than the set duration. It uses five internal sequence levels.

Pattern/Edge Combinations

The following trigger functions are found in Trigger Function when the analyzer is in timing mode. These predefined functions use a pattern, edge, or a combination of both as the trigger element. The functions use either one or two internal sequence levels.

• Find edge AND pattern. This function becomes true when a selected edge is seen within the time window defined by a pattern you have designated. It uses one internal sequence level.

• Find pattern occurring too soon after edge. This function becomes true when a pattern you have designated is seen occurring within a set duration after a selected edge is seen. It uses two internal sequence levels.

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• Find pattern occurring too late after edge. This function becomes true when one edge you have selected occurs, and for a designated period after that first edge is seen, a pattern is not seen. It uses two internal sequence levels.

Time Violat ion s

The following trigger functions are found in Trigger Functions when the analyzer is in timing mode. These trigger functions are specifically tailored to trigger on events occurring out of a predefined time range. They use either one or two internal sequence levels.

• Find width violation on a pattern/pulse. This function becomes true when the width of a pattern violates minimum and maximum width settings you have designated. It uses one internal sequence level.

• Find 2 edges too close together. This function becomes true when a second selected edge is seen occurring within a period you have designated after the occurrence of a first selected edge. It uses two internal sequence levels.

• Find 2 edges too far apart. This function becomes true when a second selected edge occurs beyond a period you have designated after the first selected edge. It uses two internal sequence levels.

• Wait t seconds This function becomes true after a period you have designated has expired. It uses one internal sequence level.

State User-level

The User-level trigger function allows you to create a custom trigger sequence using terms, a comparison function, and a jump or loop. This

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The Trigger Tab

trigger function uses one internal sequence level.

See Also “Working with the User-level Function” on page 89 for more information on

the user-defined mode.

Basic State Trigger Functions

The following basic trigger functions are found in Trigger Functions when the analyzer is in state mode. Each macro uses one internal sequence level.

• Find Pattern n times. This function becomes true when it sees a pattern you have designated occurring a designated number of times. The pattern may occur consecutively, but does not have to. It uses one internal sequence level.

• Find anystate n times. This function becomes true with the nth state it sees. It uses one internal sequence level. It is equivalent to Wait n external clock states.

• Find pattern2 occurring immediately after pattern1. This function becomes true when the first pattern you have designated is seen immediately followed by a second designated pattern. It uses two internal sequence levels.

• Find pattern n consecutive times. This function becomes true when it sees a pattern you have designated occurring a designated number of consecutive times. It uses one internal sequence level.

Sequence-Dependent Trigger Functions

The following trigger functions are found in Trigger Functions when the analyzer is in state mode. These functions each trigger on a particular sequence of events.

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• Find too few states between pattern1 and pattern2. This function becomes true when a designated pattern1 is seen, followed by a designated pattern2, and with fewer than a selected number of states occurring between the two patterns. It uses four internal sequence levels.

• Find too many states between pattern1 and pattern2. This function becomes true when a designated pattern1 is seen, followed by more than a selected number of states, before a designated pattern2. It uses two internal sequence levels.

• Find n-bit serial pattern. This function becomes true when a specified serial pattern of n bits is found on the analyzed line. This function uses one internal sequence level for each bit specified in the trigger sequence.

• Find pattern2 n times after pattern1, before pattern3 occurs. This function becomes true when it first finds a designated pattern1, followed by a selected number of occurrences of a designated pattern2. In addition, if a designated pattern3 is seen anytime while the sequence is not yet true, the sequence starts over. This includes if pattern2's nth occurrence is at the same time as pattern3, the sequence starts over. It uses two internal sequence levels.

Time Violations

The following trigger functions are found in Trigger Functions when the analyzer is in state mode. These predefined functions are specifically tailored to trigger on events occurring out of a predefined time range. These functions use either one or two internal sequence levels.

• Find pattern2 occurring too soon after pattern1.

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This function becomes true when a designated pattern1 is seen, followed by a designated pattern2, and with less than a selected period occurring between the two patterns. It uses two internal sequence levels.

• Find pattern2 occurring too late after pattern1. This function becomes true when a designated pattern1 is seen, followed by at least a selected period, before a designated pattern2 occurs. It uses two internal sequence levels.

• Wait n external clock states. This function becomes true after a number of user clock states you have designated have occurred. It uses one internal sequence level.

Breaking Down and Restoring Functions

When you break down a trigger function, you gain access to all the resource assignment fields and branching options. You can change these fields to change the structure of the trigger sequence. You might need to do this to create a custom trigger sequence or to add jumps.

To Break Down Trigger Functions

1. Select Modify in the Trigger window menu bar.

2. Choose Break down functions. The trigger sequence area changes to show the entire trigger sequence as a series of user-level steps.

The contents of broken down functions are displayed in the long form used in a user-level sequence step. If the function uses two of the analyzer’s internal sequence levels, (see page 89) both levels are separated out and displayed in the trigger sequence area.

To Restore Functions

1. Select Modify in the Trigger window menu bar.

2. Choose Restore functions.

Use Restore functions to restore all functions to their original

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structure. Note that when the functions are restored, all changes are lost and any branching that is part of the original structure is restored.

See Also “Working with the User-level Function” on page 89 for information on

working with functions that are broken down.

How the Internal Sequence Levels Are Used

The analyzer has internal sequence levels that it uses to make up the trigger sequence. There are a total of 16 sequence levels available.

The actual number of levels used in a trigger sequence can vary depending on whether you elect to use predefined trigger functions or use the user-defined steps (see page 89) to construct a more custom trigger sequence.

When you use user-defined steps, all of the internal sequence levels are available. Each user-defined sequence level corresponds to one internal level. The only instance where multiple levels are used is when the < duration is assigned.

When you use predefined trigger functions (see page 82), more than one of the internal sequence levels may be required for a single trigger function. Even though some trigger functions use multiple sequence levels, trigger functions are easier to use, and they are the most efficient way to construct a trigger specification.

Working with the User-level Function

NOTE: Before you begin to set up user-level sequence steps, note that in most cases

one of the predefined trigger functions (see page 82) will work.

You might need to set up a user-level sequence step to accommodate a condition not covered by the functions, or if you need to set up additional loops and jumps in the sequence. Each user-level sequence step has a "fill-in-the-blanks" type statement. You use resource terms to fill in the statement with the appropriate values.

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To Set Up a User-Defined Macro

1. In the Trigger Functions tab, select User-level at the end of the list.

2. Select the Replace or Insert button.

3. Select the new sequence level number button; choose Edit. A Trigger Sequence Step window appears.

4. For state measurements, select the While storing button; choose the resource term. The values represented by this term will be stored in memory while the logic analyzer is evaluating target system data against this step. The default, anystate, stores everything. Nostate stores nothing.

5. Select the Trigger on button or the Find button; choose the resource term.

6. In timing measurements, you have the choice of an occurrence counter or duration. To use the secondary branch, you must set this to occurs.

7. Set the occurrence field or duration.

8. If you want to use a loop or jump:

a. Select the Else on button; select resource term.

b. Select the goto level option button; choose a sequence level.

9. If you want to use a timer:

a. In the appropriate sequence level, start the timer by selecting the Off

option button and choosing Start. Timers do not start automatically.

b. In the Timer tab, assign a time value you want to check against.

c. To check the value, assign the timer to a resource field either on its

own, or as part of a combination.

For more information on the functions available in a user-defined step, refer to:

•“Defining Resource Terms” on page 92

•“Setting Pattern Durations and Occurrence Counts” on page 91 (Timing

Only)

•“Using Occurrence Counters” on page 91 (State Only)

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•“Setting Up Loops and Jumps in the Trigger Sequence” on page 79

•“Using Timer Terms” on page 96

Setting Pattern Durations and Occurrence Counts

(Timing Only)

When a bit pattern is found during a trigger sequence, you can influence when the term actually becomes "true" by assigning a time duration or an occurrence count.

The (>/</occurs) control may not be directly accessible if you are editing a trigger function. To reveal it, break down (see page 88) the function and then follow these instructions.

To Set a Pattern Duration

1. Select the (>/</occurs) option button and choose an option.

2. Set the duration or the number of occurrences.

When a greater-than or less-than duration is assigned, the secondary branch (Else on) is not available.

When greater-than (>) is used, the analyzer continues sequence level evaluation only after the resource term has been true for greater than or equal to the amount of duration specified.

When less-than (<) is used, the analyzer continues sequence level evaluation only after the resource term has been true for less than or equal to the amount of duration specified. For each less-than assignment, four internal sequence levels (see page 89) are used.

When occurs is selected, you can set an occurrence count. Use the occurrence counter to delay the trigger sequence evaluation until a resource term has occurred in a designated number of samples. These samples may be interrupted by other values -- they do not need to be consecutive.

Using Occurrence Counters

Use the occurrence counter to delay the trigger sequence evaluation until a resource term has occurred in a designated number of samples.

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The samples do not need to be consecutive. Whatever positive number you assign to the counter, the pattern must be seen that number of times before the term becomes true.

If the Else branch becomes true before all specified occurrences of the primary (Trigger on, or Find) branch, the Else branch is taken.

Branches Taken Stored / Not Stored (State only). Branches Tak en sets the analyzer to store, or not to store, the resource terms of

the branch that the analyzer followed in the trigger sequence. The Branches Taken control is located in Trigger, under the Settings tab.

Use Branches Taken if you want to maximize memory usage but have a complex trigger. With Branches Taken set to stored, you can use store qualifiers to not store the preliminary data ("While storing no state") but still reconstruct the events leading up to your trigger.

When the analyzer is set to Branches Taken Stored, all branch events (Find, Else On, or Trigger) are stored when they occur.

When the analyzer is set to Branches Taken Not Stored, the branch events will only be stored if the states they represent are included in the While Storing qualifier.

The While storing field specifies what is being stored in the analyzer’s memory before the trigger conditions are met. To set this, select the

While storing button and choose a pattern or range term for the store qualification.

Defining Resource Terms

Resource terms are variables that you can use in defining a trigger sequence. The terms available include patterns, edges, ranges, and

timers.

When the Agilent Technologies 16712A is configured as a state

analyzer, up to fourteen resource terms are available: 10 pattern terms Pattern1 - Pattern9 and Patt10, two range terms, and two timer terms. When configured as a timing analyzer, 16 resource

terms are available from the 14 terms already mentioned, plus two

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edge terms.

When the module is set up as two analyzers, each resource term can be used by either of the two analyzers, but not both at the same time.

To Define a Resource Term

1. In the Trigger tab, select the appropriate subtab to bring the group of

terms forward.

2. Optional - Highlight the term name and enter a new name.

For Timer terms, set the time value and skip the remaining steps.

3. Optional - Select the label button to the right of the term name and choose

Replace.

4. Select the label that you want to use.

5. Optional - add more labels (see page 98) to the term.

6. Optional - Set the numeric base.

7. Select the term value field, to the right of the label name.

8. For pattern and range terms, enter the term value. For edge terms, assign

edges or glitches to appropriate bits.

See Also “Using Bit Pattern Terms” on page 93

“Using Edge Terms” on page 95

“Using Range Terms” on page 94

“Using Combinations of Terms” on page 97

“Using Timer Terms” on page 96

“Adding and Deleting Labels for Terms” on page 98

“Numeric Base” on page 98

Using Bit Pattern Terms

Bit pattern resource terms can be set to match a numeric value or bit pattern on a group of data channels such as a bus. In order for a pattern to be found by the analyzer, the input data must match all bits of the pattern that are not defined as Don’t Cares (X). Patterns can also be

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used in a negated form.

To Define a Pattern Term

1. Select the label name button to the right of the term name and choose the label that you want to use.

2. If necessary, add more labels (see page 98) to the term.

3. Select the term value field, to the right of the label name.

4. Enter the pattern for each label. Depending on the base setting, such as hex or octal, some characters will not be accepted. Don’t cares are indicated by an X.

Right-click on any of the bit pattern value fields to quickly assign the pattern term to a preset value. Clear (=X) sets the value to all X (don’t cares). Set (=1) sets the value to all 1s. Reset (=0) sets the value to all 0s.

Using Range Terms

Range terms bracket groups of data values between upper and lower boundaries that you assign. The range term becomes true when the data is numerically between or on the two specified boundaries.

The labels used by a range must be contained in a single pod pair, with no clock channels or re-ordered bits allowed.

To Define a Range Term

1. Select the label name button to the right of the term name and choose the label that you want to use. Only one label can be used at a time for range terms.

2. Select the lower value field, to the right of the label name.

3. Enter the pattern for the low value of the range.

4. Select the upper value field, to the right of the label name.

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5. Enter the pattern for the upper value of the range. Depending on the base setting, such as Hex or Octal, some characters will not be accepted.

Right-click on either of the value fields to quickly assign the value to a preset value. Set (=1) sets the value to all 1s. Reset (=0) sets the value to all 0s.

Using Edge Terms

Edge terms are only available in timing mode. You can set an edge term to match transitions or glitches on one or more channels. When you specify an edge or glitch on more than one channel, the analyzer logically ORs the edges together. When the analyzer sees a transition that matches any of the ones specified in the edge term, the term becomes true. If you must have both edges occur in the same sample, assign the edges to different terms and combine them (see page 97) with an AND.

The following edge choices are available for each bit:

Rising edge (↑)

Falling edge (↓)

Either rising or falling

Glitch (*)

To Define an Edge Term

1. Select the label name button and choose the label that you want to use.

2. Select the edge value button, to the right of the label name.

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3. Set the edge or glitch for each channel. Don’t cares are indicated by a (.).

NOTE: After you close the edge term assignment dialog, you may see $ indicators in

the term value field. This symbol indicates that the value can’t be displayed in the selected base. Choose Binary base to see the actual assignments.

Using Timer Terms

Timers are like other resource terms in that they are either true or false. They are unlike other terms, however, in that they are controlled within the trigger sequence and act like a stopwatch. When a timer reaches its assigned count (expires), it becomes true. When a timer expires or stops, its count resets to zero.

Timers can be set to Start, Stop, Pause, or Continue as the analyzer enters a trigger sequence level. The two timers are global, so each sequence level except the first has the ability to control the same timer. As more sequence levels are added, the timer status in the new levels defaults to Off. If a timer is paused in one level, it must be continued in another level before it will be restarted. If the trigger sequence returns to the same sequence level again, the timer will be restarted.

Each Timer term can be used by either of the two analyzers, but not both.

To Assign a Time Value to the Timer Terms

1. Select the Timer subtab in the Trigger tab.

2. Select the timer value field, next to the timer name.

3. Enter a timer value.

4. Use the up/down arrow buttons to scroll through timer values.

The minimum value a timer can have is 400 ns, which is also the default value.

To Include a Timer in a Trigger Sequence

1. Assign a time value to the timer you want to use.

2. Select the sequence level you want to use it in, and choose Edit....

Chapter 1: Agilent Technologies 16712A 128K Sample Logic Analyzer

Timer control is not available in the first sequence level.

3. Select the Off option button at the bottom of the edit dialog box and choose Start. If the other analyzer is already using a timer, it won’t appear in this analyzer’s edit dialog.

4. Select the event field where you want to use the timer.

5. Choose either Timer or Combo....

Use Combo for cases such as an edge occurring after so many nanoseconds.

6. In the other trigger levels, you can Start, Pause, and Continue the timer. When a timer reaches its assigned value, it automatically stops.

See Also “Using Combinations of Terms” on page 97

Using Combinations of Terms

Resource terms can be used in combinations. Combinations use the logical AND, NAND, OR, NOR, and XOR functions to combine predefined resource terms.

The Trigger Tab

A combined term is evaluated as a single events. Components that are ANDed together must all occur in the same sample. Ones that are ORed together only require one of the components to happen.

If you intend for the logic analyzer to decide between two actions, use branches instead of combined terms. If you want the logic analyzer to find the terms in sequence, use different levels or a trigger function in the trigger sequence.

To Set Up a Combination

1. Edit the sequence step (see page 78) that you want a combination term to appear in.

2. Select the resource term assignment field that you want to make into a combination.

3. Choose Combo... from the menu of resource terms.

4. In the Combination dialog, select the On/Off/Not option button for each term that you want to use and select On or Not.

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Not selects the logical negation of the term.

5. Select the logical operator buttons and choose a logic operation. Not all operations are available at all levels of the combination tree.

NOTE: The combination of terms is now inserted into the term assignment field. If the

term is too long to fit, the display is truncated.

Adding and Deleting Labels for Terms

Labels are defined in Format, after which they are available throughout the other analyzer areas and attached display tools.

When you use more than one label to define a trigger term, the term conditions must be true on both labels for the term to be true.

To Add a Label to a Resource Term

1. Select the label name button.

2. Choose Insert.

3. Select the label that you want to add to the resource term.

To Delete a Label from a Resource Term

1. Select the label name button.

2. Choose Delete.

Numeric Base

All labels have a numeric base field next to them. The base choices are Binary, Octal, Decimal, Hex, ASCII, Symbol and Twos Complement.

To Change the Numeric Base

1. Select the the base option button.

2. Choose the base that you want.

NOTE: If the numeric base is changed in one window, the base in other windows may

not change accordingly. For example, the base assigned to symbols is unique, as is the base assigned in the Listing window.

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Tagging Data with Time or State Tags (State Only)

The Count field under Settings in Trig g e r accesses a selection menu which is used to stamp the data at each memory location with either a Time tag or a State Count tag. The tags reduce the memory depth by half. To retain the full memory depth when using time or state tags leave one pod pair unassigned.

State Count

When the State Count option is selected, numbered tags are placed on all selected data. Pre-trigger data has negative numbers and posttrigger data has positive numbers. You select the data to be tagged when you turn on State Count. A field appears to the right of States that lets you define patterns.

State tag numbering can be set either relative to the previous tagged sample or absolute from the trigger point. Selecting Absolute or Relative is done by toggling the Absolute/Relative field in the Listing Display window.

Time Count

Time Count places time tags on all data. Pre-trigger data has negative time numbers and post-trigger data has positive time numbers. Time tag numbering is set to be either relative to the previous memory location or absolute from the trigger point. The time tag resolution is 4 ns.

Arming Control

An instrument must be armed before it can look for its trigger. When you Run an instrument, it is armed immediately. When using logic analyzer modules that provide two separate analyzers, you can set one analyzer to arm the other within the same module by selecting Arming Control... under Settings in Tr i gge r.

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Selecting the Arming Control... button brings up the Machine Arming Tree dialog. In this dialog you can set what starts each

analyzer, and which one sends a signal to Arm Out. Arm Out is used to send signals to other instruments in the frame, or sent to Port Out. Port Out can be used to control additional instruments external to the logic analysis system.

To change the source of Arm In or the destination of Port Out, use the Intermodule dialog (see the Agilent Technologies 16700A/B-Series Logic Analysis System help volume).

Setting One Analyzer to Arm the Other

This procedure assumes you have both analyzers turned on. The second analyzer can be turned on by dragging it onto the workspace in the Workspace window.

1. Under the Trigger tab, select the Settings subtab.

2. Select the Arming Control... button.

3. Select the box of the machine that you want to have wait for its arm signal.

4. In the armed by menu, select the other machine. The arming signal path forms a tree in the Machine Arming Tree dialog.

5. Set the sequence level number to the trigger sequence level that will wait for the arm signal. It does not have to be the same as the trigger level.

6. Select the Close button.

NOTE: If the trigger sequence does not pass through the level containing the wait for

arm term, the trigger will not wait for the arming signal.

See Also Overview - Multiple Instrument Configuration (see the Agilent

Technologies 16700A/B-Series Logic Analysis System help volume)

Overview - Multiple Machine Configuration (see the Agilent Technologies 16700A/B-Series Logic Analysis System help volume)

100

Agilent 16712A Help Volume

Specifications and Main Features

Frequently Asked Questions

User Manual

Agilent Technologies 16712A 128K Sample Logic Analyzer

Contents

Agilent Technologies 16712A 128K Sample Logic Analyzer

Setting Up a Measurement

Connect the Analyzer to the Target System

Define the Type of Measurement

Set Up the Bus Labels

Define Trigger Conditions

Run the Measurement

Examine the Data

Making a Basic State Measurement

Making a Basic Timing Measurement

Interpreting the Data

Analysis Using Waveform

Analysis Using Listing

Coordinating Measurements

Loading and Saving Logic Analyzer Configurations

When Something Goes Wrong

Interference with Target System

Error Messages

Maximum of 32 Channels Per Label

Measurement Initialization Error

Slow or Missing Clock

Timer is Specified in Sequence, But Never Started

Timer is Off in Sequence Level Where It Is Used

Trigger inhibited during timing prestore

Two Pod Pairs are Needed To Use Both Timers

Waiting for Trigger

Clock Lines Must Be Connected to the Card in Slot X

Measurement Error: Check Probe Parametrics or Grounding

Correlation Invalid, Module Did Not Trigger

Correlation Invalid, Timer Overflowed

Nothing Happens

Suspicious Data

Testing the Logic Analyzer Hardware

The Sampling Tab

Acquisition Depth

Setting the Acquisition Mode

Performing Clock Setup (State only)

Clock Modes (State only)

Naming the Analyzer

Turning the Analyzer Off

Sample Period (Timing Only)

State Acquisition Modes

Timing Acquisition Modes

Transitional Timing Acquisition Modes

“64K Full Channel Transitional 125-MHz Mode” on page 48

“Other Transitional Timing Considerations” on page 49

Comparison of Transitional and Conventional Timing Modes

Trigger Position Control

The Format Tab

Importing Netlist and ASCII Files

Exporting ASCII Files

Importing ASCII Files

Termination Adapter

E5346A High Density Adapter

Mapping Connector Names

Import the Net List File

Verify Net to Label Mapping

Select/Create Interface Labels

Activity Indicators

Assigning Pods to the Analyzers

Data On Clocks Display

Assigning Bits to a Label

Inserting and Deleting Labels

Turning Labels On and Off

Label Polarity

To reorder bits in a label

Labels: Mapping Analyzer Channels to Your Target

Setting Up the Pod Clock

Pod Selection

Setting the Pod Threshold

State Clock Setup/Hold (State only)

The Trigger Tab

Understanding Logic Analyzer Triggering

Setting Up a Trigger