Agilent 1670G Specifications Sheet

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Service Guide

Publication number 01670-97023 November 2003

For Safety information, Warranties, and Regulatory information, see the pages at the end of the book.



Agilent Technologies 1670G-Series Logic Analyzers

The Agilent 1670G-Series are 150-MHz State/500-MHz Timing Logic Analyzers. There are two options available. One option is to add a 2 GSa/s digitizing oscilloscope. Another option is to add a 32 channel pattern generator.

Features

Some of the main features of the Agilent 1670G-Series Logic Analyzers are as follows:

•

132 data channels and 4 clock/data channels in the Agilent 1670G

•

98 data channels and 4 clock/data channels in the Agilent 1671G

•

64 data channels and 4 clock/data channels in the Agilent 1672G

•

32 data channels and 2 clock/data channels in the Agilent 1673G

•

3.5-inch flexible disk drive

•

2-GB hard disk drive

•

GPIB, RS-232-C, Centronics, and LAN interfaces

•

Thinlan and Ethertwist LAN ports

•

Variable setup/hold time

•

64K memory on all channels with 256K and 2M options

•

Marker measurements

•

12 levels of trigger sequencing for state and 10 levels of sequential triggering for timing

•

Full programmability

•

DIN mouse

•

DIN keyboard support

The pattern generator option includes the following features:

•

15 output channels at 200 MHz

•

32 output channels at 100 MHz

•

Memory depth of 258,048 vectors

•

Support for TTL, 3-state TTL/3.3v, 3-state TTL/CMOS, ECL terminated, ECL unterminated, and differential ECL (without pod).

ill

e osc

•

2 GSa/s digitizing for 500 MHz bandwidth single shot oscilloscope

•

>32000 samples per channel

•

Automatic pulse parameters displays time between markers, acquires until specified time between markers is captured, performs statistical analysis on time between markers

•

Lightweight mini probes

oscope option includes the following features:

Service Strategy

The service strategy for this instrument is the replacement of defective assemblies. This service guide contains information for finding a defective assembly by testing and servicing the Agilent 1670G-series logic analyzers.

This logic analyzer can be returned to Agilent for all service work, including troubleshooting. Contact your nearest Agilent Technologies Sales Office for details.

Agilent Technologies 1670G-Series Logic Analyzer

iii

In This Book

This book is the service guide for the Agilent 1670G-Series Logic Analyzers and is divided into eight chapters.

Chapter 1 contains information about the logic analyzer and includes accessories, specifications and characteristics, and equipment required for servicing.

Chapter 2 tells how to prepare the logic analyzer for use.

Chapter 3 gives instructions on how to test the performance of the logic analyzer.

Chapter 4 contains calibration instructions for the logic analyzer.

Chapter 5 contains self-tests and flowcharts for troubleshooting the logic analyzer.

Chapter 6 tells how to replace assemblies of the logic analyzer and how to return them to Agilent Technologies.

Chapter 7 lists replaceable parts, shows an exploded view, and gives ordering information.

Chapter 8 explains how the logic analyzer works and what the self-tests are checking.

Service Strategy 1–iii

1 General Information

Accessories 1–2 Specifications (logic analyzer) 1–3 Specifications (oscilloscope) 1–4 Specifications (pattern generator) 1–4 Characteristics (logic analyzer) 1–5 Characteristics (oscilloscope) 1–5 Characteristics (pattern generator) 1–6 Recommended Test Equipment (logic analyzer) 1–9 Recommended test equipment (oscilloscope) 1–10 Recommended test equipment (pattern generator) 1–11

2 Preparing for Use

To inspect the logic analyzer 2–2 To apply power 2–3 To operate the user interface 2–3 To clean the logic analyzer 2–3 To test the logic analyzer 2–4

3 Testing Performance

To perform the self-tests 3–3

To make the test connectors (logic analyzer) 3–7

To test the threshold accuracy (logic analyzer) 3–9

Set up the equipment 3–9 Set up the logic analyzer 3–10 Connect the logic analyzer 3–12 Test the ECL Threshold 3–13 Test the 0 V User threshold 3–15 Test the next pod 3–16

To test the single-clock, single-edge, state acquisition (logic analyzer) 3–17

Set up the equipment 3–17 Set up the logic analyzer 3–18 Connect the logic analyzer 3–20 Verify the test signal 3–23 Check the setup/hold combination 3–24 Test the next channels 3–28

To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) 3–29

Set up the equipment 3–29 Set up the logic analyzer 3–30 Connect the logic analyzer 3–32 Verify the test signal 3–35

Contents

Check the setup/hold with single clock edges, multiple clocks 3–36 Test the next channels 3–40

To test the single-clock, multiple-edge, state acquisition (logic analyzer) 3–41

Set up the equipment 3–41 Set up the logic analyzer 3–42 Connect the logic analyzer 3–44 Verify the test signal 3–47 Check the setup/hold with single clock, multiple clock edges 3–49 Test the next channels 3–52

To test the time interval accuracy (logic analyzer) 3–53

Set up the equipment 3–53 Connect the logic analyzer 3–54 Set up the logic analyzer 3–55 Acquire the data 3–58

To test the input resistance (oscilloscope) 3–59

Set up the equipment 3–59 Set up the logic analyzer 3–60 Connect the logic analyzer 3–61 Acquire the data 3–62

Perform an operational accuracy calibration 3–62

To test the voltage measurement accuracy (oscilloscope) 3–63

Set up the equipment 3–63 Set up the logic analyzer 3–64 Connect the logic analyzer 3–65 Acquire the data 3–66

To test the offset accuracy (oscilloscope) 3–67

Set up the equipment 3–67 Set up the logic analyzer 3–68 Connect the logic analyzer 3–69 Acquire the zero input data 3–70 Acquire the DC input data 3–71

To test the bandwidth (oscilloscope) 3–72

Set up the equipment 3–72 Set up the logic analyzer 3–73 Connect the logic analyzer 3–75 Acquire the data 3–76

To test the time measurement accuracy (oscilloscope) 3–77

Set up the equipment 3–77 Set up the logic analyzer 3–78 Connect the logic analyzer 3–80

Acquire the data 3–80

To test the trigger sensitivity (oscilloscope) 3–81

Set up the equipment 3–81 Set up the logic analyzer 3–82 Connect the logic analyzer 3–84 Acquire the data 3–84

Performance Test Record (logic analyzer) 3–85

Performance Test Record (oscilloscope) 3–88

Performance Test Record (pattern generator) 3–91

4 Calibrating and Adjusting

Contents

Logic analyzer calibration 4–2

To calibrate the oscilloscope 4–3

Set up the equipment 4–3 Load the Default Calibration Factors 4–4 Self Cal menu calibrations 4–5

To test the CAL OUTPUT ports 4–6

Set up the equipment 4–6 Set up the logic analyzer 4–7 Verify the DC CAL OUTPUT port 4–8 Set up the logic analyzer 4–9 Verify the AC CAL OUTPUT port 4–9

5 Troubleshooting

To use the flowcharts 5–2 To check the power-up tests 5–11 To run the self-tests 5–12 To test the power supply voltages 5–20 To test the LCD display signals 5–21 To test the keyboard signals 5–22 To test the flexible disk drive voltages 5–24 To test the hard disk drive voltages 5–26 To perform the BNC test 5–28 To test the logic analyzer probe cables 5–29 To verify pattern output (pattern generator option only) 5–33 The Ether address 5–35 To test the auxiliary power 5–36

6 Replacing Assemblies

To remove and replace the handle 6–5 To remove and replace the feet and tilt stand 6–5 To remove and replace the cover 6–5

vii

Contents

To remove and replace the disk drive assembly 6–6 To remove and replace the acquisition board 6–7 To remove and replace the CPU board 6–9 To remove and replace SIMM memory 6–10 To remove and replace the rear panel 6–11 To remove and replace the power supply 6–12 To remove and replace the oscilloscope board (oscilloscope option only) 6–13 To remove and replace pattern generator board ( pattern generator option only) 6–14 To remove and replace the front panel and keyboard 6–15 To remove and replace the LCD display and Inverter board 6–16 To remove and replace the handle plate 6–17 To remove and replace the fan 6–18 To remove and replace the pattern generator cables (pattern generator option only) 6–18 To remove and replace the GPIB and RS-232-C cables 6–19 To remove and replace the I/O board 6–19 To return assemblies 6–20

7 Replaceable Parts

Replaceable Parts Ordering 7–2 Replaceable Parts List 7–3 Exploded View 7–4 Power Cables and Plug Configurations 7–8

8 Theory of Operation

Block-Level Theory 8–3

The Agilent 1670G-Series Logic Analyzer 8–3 The Logic Acquisition Board 8–7 The Oscilloscope Board 8–10 The Pattern Generator Board 8–15

Self-Tests Descriptions 8–17

Power-up Self-Tests 8–17 System Tests (SysPV) 8–18 Analyzer Tests (Analy PV) 8–22 Oscilloscope tests (Scope PV) 8–25 Pattern Generator tests (Patt Gen) 8–26 GPIB 8–30 RS-232-C 8–32

viii

Accessories 1–2 Specifications (logic analyzer) 1–3 Specifications (oscilloscope) 1–4 Specifications (pattern generator) 1–4 Characteristics (logic analyzer) 1–5 Characteristics (oscilloscope) 1–5 Characteristics (pattern generator) 1–6 Recommended Test Equipment (logic analyzer) 1–9 Recommended Test Equipment (oscilloscope) 1–10 Recommended Test Equipment (pattern generator) 1–11

General Information

This chapter lists the accessories, the specifications and characteristics, and the recommended test equipment.

Accessories

The following accessories are supplied with the Agilent 1670G-series logic analyzers. The part numbers are current as of the print date of this edition of the Service Guide, but further upgrades may change the part numbers. Do not be concerned if the accessories you receive have different part numbers.

Accessories Supplied Part Number Qty

Probe tip assemblies 01650-61608 Note 1

Probe cables 01660-61605 Note 2

Grabbers (20 per pack) 5090-4356 Note 1

Probe ground (5 per pack) 5959-9334 Note 1

Double Probe Adapter 16542-61607 1

PS2 Mouse C3751-60201 1

Note 1 Quantities: 8 - 1670G

6 - 1671G

4 - 1672G

2 - 1673G

Note 2 Quantities: 4 - 1670G

3 - 1671G

2 - 1672G

1 - 1673G

Pattern Generator Option-Series Additional Accessories

Accessories Supplied Part Number Qty

Data Output Cable 16522-61601 4

Clock Output Cable 16522-61602 1

Oscilloscope Option-Series Additional Accessories

Accessories Supplied Part Number Qty

10:1 probes 1160A 2

BNC miniprobe adapter 1250-1454 1

Accessories Available

Other accessories available for the Agilent 1670G-series logic analyzer are listed in the Accessories for Agilent Logic Analyzers brochure.

1–2

General Information

Specifications (logic analyzer)

The specifications are the performance standards against which the product is tested.

Maximum State Speed (selectable) 150 MHz

Minimum Master to Master Clock Time

Threshold Accuracy ± (100 mV + 3% of threshold setting)

6.666 ns

Setup/Hold Time:

Single Clock, Single Edge 3.0/0.0 ns through -0.5/3.5 ns,

adjustable in 500-ps increments

Single Clock, Multiple Edges 3.5/0.0 ns through -0.5/4.0 ns,

adjustable in 500-ps increments

Multiple Clocks, Multiple Edges 4.0/0.0 ns through -0.5/4.5 ns,

adjustable in 500-ps increments

* Specified for an input signal VH = −0.9 V, VL = −1.7 V, slew rate = 1 V/ns, and threshold = −1.3 V.

1–3

General Information

Specifications (oscilloscope)

The Agilent 1670G Logic Analyzers with an oscilloscope also include the following specifications:

Bandwidth

Time Interval Measurement Accuracy

DC Offset Accuracy

Voltage Measurement Accuracy

Trigger Sensitivity

Input R (selectable)

* Specifications (valid within ± 10° C of auto-calibration temperature, excluding bandwidth−see note 1 for bandwidth specification.)

(*,1)

(*, 2)

(*)

(*, 3)

(*)

DC to 500 MHz (real time, dc-coupled)

±[(0.005% X ∆t)+

(2 x 10

−

x delay setting)+150 ps]

±(1.0% of channel offset + 2.0% of full scale) ± [(1.25% of full scale + offset accuracy)

+ (0.016 x V/div)]

DC to 50 MHz: 0.063 x full scale, 50 to 500 MHz: 0.125 x full scale

1 MΩ: ±1%, 50 Ω: ±1%

1. Upper bandwidth reduces by 2.5 MHz for every degree C above 35° C.

-6

2. Specification applies to the maximum sampling rate. At lower rates, the specification is:± [(0.005% x ∆t)+(2 x 10

(0.15 x sample interval)] for bandwidth limited signals (t

3. Digitizing level = (#vertical divisions)(

)(

LSB

= 1.4 x sample interval). Sample interval is defined as

), where LSB=2

# bit s in ADC

x delay setting) + 1

sample rate

Specifications (pattern generator)

There are no specifications for the pattern generator option of the Agilent 1670G-Series Logic Analyzers.

1–4

General Information

Characteristics (logic analyzer)

These characteristics are not specifications, but are included as additional information.

Full Channel Half Channel

Maximum State Clock Rate 150 MHz not applicable

Maximum Conventional Timing Rate 250 MHz 500 MHz

Memory Depth 64K 128K

Memory Depth (option #001) 256K 512K

Memory Depth (option #002) 2048K 4196K

Channel Count:

1670G 136 68 1671G 102 51 1672G 68 34 1673G 34 17

Characteristics (oscilloscope)

The Agilent 1670G Logic Analyzers with an oscilloscope also include the following characteristics:

Maximum Sample Rate 2 Gigasample per second

Number of Channels 2

Rise Time

(1)

ADC 8-bit real time

Vertical Resolution 8 bits over 4 vertical divisions (± 0.4%)

Waveform Record Length >32000 points

Vertical (DC) Gain Accuracy

(2)

Input Coupling 1 MΩ: ac and DC, 50 Ω: DC only

Input C Approximately 7 pF

0.35

1. Rise time is calculated from the formula: t

2. Vertical gain accuracy decreases 0.08% per degree C from software calibration temperature.

bandwidth

700 ps

±1.25% of full scale

1–5

General Information

Characteristics (pattern generator)

The Agilent 1670G Logic Analyzers with a pattern generator also include the following characteristics:

Output channels 16 channels at 200 MHz clock; 32 channels at

100 MHz clock

Memory depth 258,048 vectors

Logic levels (data pods) TTL, 3-state TTL/3.3v, 3-state TTL/CMOS,

ECL terminated, ECL unterminated, and differential ECL (without pod)

Data inputs 3-bit pattern - level sensing (clock pod)

Clock outputs Synchronized to output data, delay of 11 ns in 9 steps

(clock pod)

Clock input DC to 200 MHz (clock pod)

Internal clock period Programmable from 5 ns to 250 µs in a 1, 2, 2.5, 4, 5, 8

sequence

External clock period (user supplied) DC to 200 MHz

External clock duty cycle 2 ns minimum high time

Maximum number of "IF condition" 1 blocks at 50 MHz clock

Maximum number of different macros 100

Maximum number of lines in a macro 1024

Maximum number of macro invocations 1,000

Maximum number of Repeat loop 1,000 invocations

Maximum number of Wait event patterns 4

1–6

General Information

Characteristics (pattern generator)

Probes

Maximum Input Voltage

Auxiliary Power

Power Through Cables 1/3 amp at 5 V maximum per cable, CAT 1

Operating Environment (for indoor use only)

Temperature Instrument, 0 °C to 55 °C (+32 °F to 131 °F).

Humidity Instrument, probe lead sets, and cables, up to

Altitude To 3067 m (10,000 ft).

Vibration Operating: Random vibration 5 to 500 Hz,

+ 40V, CAT 1

Probe lead sets and cables,

0 °C to 65 °C (+32 °F to 149 °F). Disk media, 10 °C to 40 °C (+50 °F to 104 °F).

80% relative humidity at +40 °C (+122 °F).

10 minutes per axis, ≈0.3 g (rms).

Non-operating: Random vibration 5 to 500 Hz,

10 minutes per axis, ≈ 2.41 g (rms);

and swept sine resonant search, 5 to 500 Hz,

0.75 g (0-peak), 5 minute resonant dwell at 4 resonances per axis.

Dimensions

1–7

General Information

Characteristics (pattern generator)

Product Regulations

Safety IEC 1010-1:1990+A1 / EN 61010-1:1993

UL3111 CSA-C22.2 No. 1010.1:1993

EMC This product meets the requirement of the European

Communities (EC) EMC Directive 89/336/EEC.

Emissions EN55011/CSIPR 11 (ISM, Group1,Class A equipment)

IEC 555-2 and IEC 555-3

Immunity EN50082-1 Code

Notes IEC 801-2 (ESD)4kV CD, 8kV AD 1 IEC 801-3 (Rad.) 3V/m 1 IEC 801-4 (EFT) 1kV 1

Performance Codes: 1 PASS - Normal operations, no effect. 2 PASS - Temporary degradation, self recoverable. 3 PASS - Temporary degradation, operator intervention required. 4 FAIL - Not recoverable, component damage.

1–8

Recommended Test Equipment (logic analyzer)

Equipment Required

General Information

Equipment Critical Specifications Recommended

Use

Model/Part

Pulse Generator 150 MHz, 3.0 ns pulse width,

8133A Option 003 P,T

< 600 ps rise time

Digitizing Oscilloscope ≥ 6 GHz bandwidth, < 58 ps rise time 54750A mainframe with

54751A plugin module 3325B Option 002 P

Function Generator Accuracy ≤ (5)(10

−

) × frequency,

DC offset voltage ±6.3 V

Digital Multimeter 0.1 mV resolution, 0.005% accuracy 3458A P BNC-Banana Cable 11001-60001 P BNC Tee BNC (m)(f)(f) 1250-0781 P Cable BNC (m)(m) 48 inch 8120-1840 P,T SMA Coax Cable (Qty 3) 18 GHz bandwidth 8120-4948 P Adapter (Qty 4) SMA(m)-BNC(f) 1250-1200 P, T Adapter SMA(f)-BNC(m) 1250-2015 P Coupler (Qty 4) BNC (m)(m) 1250-0216 P, T 20:1 Probes (Qty 2) 54006A P BNC Coax Cable BNC(m)(m), >2 GHz bandwidth, >1 meter length 10503A T BNC Test Connector, 17x2

(Qty 1) BNC Test Connector, 6x2

(Qty 4)

P,T

Digitizing Oscilloscope > 100 MHz Bandwidth 54600B T BNC Shorting Cap 1250-0774 T BNC-Banana Adapter 1251-2277 T

*A = Adjustment P = Performance Tests T = Troubleshooting **Instructions for making these test connectors are in chapter 3, "Testing Performance."

1–9

General Information

Recommended test equipment (oscilloscope)

Equipment Required

Equipment Critical Specifications Recommended

Model/Part

Signal Generator Frequency: 1 - 500 MHz at approx.

170 mV RMS

Output Accuracy: ± 1 dB

1 MHz time base accuracy 0.25 ppm

DC Power Supply Range: −35.000 to +35.000 Vdc, ±1 mV 3245A Option 002 P

Digital Multimeter 0.1 mV resolution

Accuracy: better than 0.005% Resistance measurement: better than

0.25% accuracy

Power Meter/Sensor 1 - 250 MHz ±3% accuracy 436/8482A P

Power Splitter Outputs differ by <0.15 dB 11667B P

Blocking Capacitor BNC (m)(f), 0.18 µF, ±200 V 10240B P

BNC Shorting Cap 1250-0074 P

Adapter BNC (f)(f) (UG-914/U) 1250-0080 C

Adapter BNC(f)-to-Dual Banana Plug 1251-2277 P

Adapter Type N(m)-to-BNC(f) 1250-0780 P

BNC Tee BNC (m)(f)(f) 1250-0781 P,C

Cable Type N(m-to-m) 24-inch 11500B P

Cable 50 Ω BNC (m-to-m) 48-inch 10503A P, C Cable (2) 50 Ω BNC (m-to-m) 9 inch 10502A C

*P = Performance Tests C = Calibration

8656B Option 001 P

3458A P

Use*

1–10

Recommended test equipment (pattern generator)

Equipment Required

General Information

Equipment Critical Specifications Recommended

Model/Part

Oscilloscope ≥ 500 MHz Bandwidth 54820A T

Probe 500 MHz Bandwidth 1160A T

Output Data Pod no substitute 10460A - series T

* T = Troubleshooting

Use*

1–11

1–12

To inspect the logic analyzer 2–2 To apply power 2–3 To operate the user interface 2–3 To clean the logic analyzer 2–3 To test the logic analyzer 2–4

Preparing for Use

Preparing For Use

This chapter gives you instructions for preparing the logic analyzer for use.

Power Requirements

The logic analyzer requires a power source of either 115 Vac or 230 Vac, –22 % to +10 %, single phase, 48 to 66 Hz, CAT II pollution degree 2, 200 Watts maximum power.

Operating Environment

The operating environment is listed in chapter 1. The logic analyzer will operate at all specifications within the temperature and humidity range given in chapter 1. However, reliability is enhanced when operating the logic analyzer within the following ranges:

•

Temperature: +20 °C to +35 °C (+68 °F to +95 °F)

•

Humidity: 20% to 80% noncondensing

Note the recommended noncondensing humidity. Condensation within the instrument can cause poor operation or malfunction. Provide protection against internal condensation.

Storage

Store or ship the logic analyzer in environments within the following limits:

•

Temperature: -40 °C to +75 °C

•

Humidity: Up to 90% at 65 °C

•

Altitude: Up to 15,300 meters (50,000 feet)

Protect the logic analyzer from temperature extremes which cause condensation on the instrument.

To inspect the logic analyzer

Inspect the shipping container for damage.

If the shipping container or cushioning material is damaged, keep them until you have checked the contents of the shipment and checked the instrument mechanically and electrically.

Check the supplied accessories.

Accessories supplied with the logic analyzer are listed in "Accessories" in chapter 1.

Inspect the product for physical damage.

Check the logic analyzer and the supplied accessories for obvious physical or mechanical defects. If you find any defects, contact your nearest Agilent Technologies Sales Office. Arrangements for repair or replacement are made, at Agilent Technologies’ option, without waiting for a claim settlement.

2–2

Preparing for Use

To apply power

Check that the line voltage selector, located on the rear panel, is on the correct setting and the correct fuse is installed.

See also, "To set the line voltage" on this page.

Connect the power cord to the instrument and to the power source.

This instrument is equipped with a three-wire power cable. When connected to an appropriate ac power outlet, this cable grounds the instrument cabinet. The type of power cable plug shipped with the instrument depends on the country of destination. Refer to chapter 7, "Replaceable Parts," for option numbers of available power cables and plug configurations.

Turn on the instrument power switch located on the front panel.

To operate the user interface

To select a field on the logic analyzer screen, use the arrow keys to highlight the field, then press the Select key. For more information about the logic analyzer interface, refer to the

Agilent 1670G-Series Logic Analyzers User’s Guide

To set the GPIB address or to configure for RS-232-C, refer to the

Agilent 1670G-Series Logic Analyzer User’s Guide

To clean the logic analyzer

With the instrument turned off and unplugged, use mild soap and water to clean the front and cabinet of the logic analyzer. Harsh soap might damage the water-base paint.

2–3

Preparing for Use

To test the logic analyzer

•

If you require a test to verify the specifications, start at the beginning of chapter 3, "Testing Performance."

•

If you require a test to initially accept the operation, perform the self-tests in chapter 3.

•

If the logic analyzer does not operate correctly, go to the beginning of chapter 5, "Troubleshooting."

2–4

To perform the self-tests 3-3 To make the test connectors (logic analyzer) 3-7 To test the threshold accuracy (logic analyzer) 3-9 To test the single-clock, single-edge, state acquisition (logic analyzer) 3-17 To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) 3-29 To test the single-clock, multiple-edge, state acquisition (logic analyzer) 3-41 To test the time interval accuracy (logic analyzer) 3-53 To test the CAL OUTPUT ports (oscilloscope) 3-59 To test the input resistance (oscilloscope) 3-63 To test the voltage measurement accuracy (oscilloscope) 3-67 To test the offset accuracy (oscilloscope) 3-71 To test the bandwidth (oscilloscope) 3-76 To test the time measurement accuracy (oscilloscope) 3-81 To test the trigger sensitivity (oscilloscope) 3-85 Performance Test Record (logic analyzer) 3-89 Performance Test Record (oscilloscope) 3-92 Performance Test Record (pattern generator) 3-95

Testing Performance

This chapter tells you how to test the performance of the logic analyzer against the specifications listed in chapter 1. To ensure the logic analyzer is operating as specified, you perform software tests (self-tests) and manual performance tests on the analyzer. The logic analyzer is considered performance-verified if all of the software tests and manual performance tests have passed. The procedures in this chapter indicate what constitutes a "Pass" status for each of the tests.

The Logic Analyzer Interface

To select a field on the logic analyzer screen, use the arrow keys to highlight the field, then press the Select key. For more information about the logic analyzer interface, refer to the

Agilent 1670G-Series Logic Analyzers User’s Guide

Test Strategy

For a complete test, start at the beginning with the software tests and continue through to the end of the chapter. For an individual test, follow the procedure in the test. The examples in this chapter were performed using an Agilent 1670G. Other analyzers in the series will have appropriate pods showing on the screen.

With the oscilloscope option, ensure that the operational accuracy calibration has been done before doing the performance verification tests (see chapter 4).

The performance verification procedures starting on page 3–8 are each shown from power-up. To exactly duplicate the setups in the tests, save the power-up configuration to a file on a disk, then load that file at the start of each test.

If a test fails, check the test equipment setup, check the connections, and verify adequate grounding. If a test still fails, the most probable cause of failure would be the acquisition board.

Test Interval

Test the performance of the logic analyzer against specifications at two-year intervals.

Performance Test Record

A performance test record for recording the results of each procedure is located at the end of this chapter. Use the performance test record to gauge the performance of the logic analyzer over time.

Test Equipment

Each procedure lists the recommended test equipment. You can use equipment that satisfies the specifications given. However, the procedures are based on using the recommended model or part number. Before testing the performance of the logic analyzer, warm-up the instrument and the test equipment for 30 minutes.

3–2

To perform the self-tests

The self-tests verify the correct operation of the logic analyzer. Self-tests can be performed all at once or one at a time. While testing the performance of the logic analyzer, run the self-tests all at once.

The performance verification (PV) self-tests consist of system PV tests and analyzer PV tests. For the oscilloscope option there are oscilloscope PV tests, and for the pattern generator option there is a pattern generator test.

These procedures assume the files on the PV disk have been copied to the /SYSTEM subdirectory on the hard disk drive. If they have not already been copied, insert the PV disk in the flexible disk drive before starting this procedure.

Disconnect all inputs, then turn on the power switch. Wait until the power-up tests are complete.

Press the System key. Select External I/O, then select Test in the pop-up menu.

Select the box labeled Load Test System.

Select the Analy PV field. then select SysPV in the pop-up menu. Select the field next to Sys PV, then select System Test in the pop-up menu.

3–3

Testing Performance

To perform the self-tests

Install a formatted disk that is not write protected into the disk drive. Connect an RS-232-C loopback connector onto the RS-232-C port.

Select All System Tests.

You can run all tests at one time, except for the Front Panel Test and Display Test, by running All System Tests. To see more details about each test when troubleshooting failures, you can run each test individually. This example shows how to run all tests at once.

When the tests finish, the status for each test shows PASSED or FAILED, and the status for the All System Tests changes from UNTESTED to TESTED. Note that the Front Panel Test and Display Test remain UNTESTED.

Select the Front Panel Test.

A screen duplicating the front panel appears on the screen.

Press each key on the front panel. The corresponding key on the screen will change from a light to a dark color. Test the knob by turning it in both directions.

Note any failures, then press the Done key a second time to exit the Front Panel Test. The status of the test changes from UNTESTED to TESTED.

Select the Display Test.

A white grid pattern is displayed. Continuously press the Select key to step through the other display screens. When completed, the test screen will again appear, and the Display Test status will indicate Tested.

The six display screens are:

1. white pattern on black background

2. white

3. red

4. yellow

5. green

6. black

3–4

Testing Performance

To perform the self-tests

9 Select Sys PV, then select Analy PV in the pop-up menu. In the Analy PV menu,

select Board Verification. In the Board Verification menu, select All Tests.

You can run all tests at one time by selecting All Tests. To see more details about each test when troubleshooting failures, you can run each test individually. This example shows how to run all tests at once.

When the tests finish, the status for each test shows PASSED or FAILED, and the status for the All Tests changes from UNTESTED to TESTED.

3–5

Testing Performance

To perform the self-tests

10 Select Exit to exit the Board Verification. In the Analy PV menu, select Acquisition

IC Verification. In the Acquisition IC Verification menu, select All Tests.

When the tests finish, the status for each test shows PASSED or FAILED, and the status for the All Tests changes from UNTESTED to TESTED.

11 Record the results of the tests on the performance test record at the end of this

chapter.

12 If you have an oscilloscope, go to step 14. If you have a pattern generator, go to step

17. Otherwise, go to step 18.

13 If you do not have an Agilent 1670G-series logic analyzer with the oscilloscope

option or pattern generator option, exit the tests by pressing the System key. Select the field to the right of the Sys PV field. Select the Exit Test System.

14 If you have the oscilloscope, Select Analy PV, then select Scope PV in the pop-up

menu. In the Scope PV menu, select Functional Tests then select ALL Tests.

You can run all tests at one time, except for the Data Input Inspection, by running All Tests. To see more details about each test when troubleshooting failures, you can run each test individually.

Record the results of the tests on the performance test record at the end of this

chapter.

16 To exit the test system, press the System key, then press the Select key. Select Exit

Test, then select Exit Test System. If you have the pattern generator option, Select Analy PV, then select PattGen in the

pop-up menu. In the PattGen menu select All Tests.

You can run all tests at one time (except the Output Patterns routine) by selecting All Tests. To see more details about each test, you can run each test individually. This example shows how to run all tests at once.

When the tests finish, the status for each test shows Passed or Failed.

Exit the test system.

Select Analy PV, Scope PV, or PattGen depending on what was last tested.

Select Sys PV.

Select System Test, then select Exit Test.

Select Exit Test System to reload the operating system.

3–6

To make the test connectors (logic analyzer)

The test connectors connect the logic analyzer to the test equipment.

Materials Required

Description Recommended Part Qty

BNC (f) Connector 1250-1032 5

100 Ω 1% resistor

Berg Strip, 17-by-2 1

Berg Strip, 6-by-2 4

20:1 Probe 54006A 2

Jumper wire

1 Build four test connectors using BNC connectors and 6-by-2 sections of Berg strip.

Solder a jumper wire to all pins on one side of the Berg strip.

Solder a jumper wire to all pins on the other side of the Berg strip.

Solder two resistors to the Berg strip, one at each end between the end pins.

Solder the center of the BNC connector to the center pin of one row on the Berg strip.

Solder the ground tab of the BNC connector to the center pin of the other row on the Berg strip.

On two of the test connectors, solder a 20:1 probe. The probe ground goes to the same row of pins on the test connector as the BNC ground tab.

0698-7212 8

3–7

Testing Performance

To make the test connectors (logic analyzer)

2 Build one test connector using a BNC connector and a 17-by-2 section of Berg strip.

Solder a jumper wire to all pins on one side of the Berg strip.

Solder a jumper wire to all pins on the other side of the Berg strip.

Solder the center of the BNC connector to the center pin of one row on the Berg strip.

Solder the ground tab of the BNC connector to the center pin of the other row on the Berg strip.

3–8

To test the threshold accuracy (logic analyzer)

Testing the threshold accuracy verifies the performance of the following specification:

• Clock and data channel threshold accuracy.

These instructions include detailed steps for testing the threshold settings of pod 1. After testing pod 1, connect and test the rest of the pods one at a time. To test the next pod, follow the detailed steps for pod 1, substituting the next pod for pod 1 in the instructions.

Each threshold test tells you to record a pass/fail reading in the performance test record located at the end of this chapter.

Equipment Required

Equipment Critical Specifications Recommended Model/Part

Digital Multimeter 0.1 mV resolution, 0.005% accuracy 3458A Function Generator Accuracy ≤ (5)(10

DC offset voltage ±6.3 V BNC-Banana Cable 11001-60001 BNC Tee 1250-0781 BNC Cable 8120-1840 BNC Test Connector, 17x2

−

) × frequency,

3325B Option 002

Set up the equipment

1 Turn on the equipment required and the logic analyzer. Let them warm up for

30 minutes before beginning the test.

2 Set up the function generator.

Set up the function generator to provide a DC offset voltage at the Main Signal output.

Disable any AC voltage to the function generator output, and enable the high voltage output.

Monitor the function generator DC output voltage with the multimeter.

3–9

Testing Performance

To test the threshold accuracy (logic analyzer)

Set up the logic analyzer

1 Press the Config key. 2 Unassign Pods 3 and 4, Pods 5 and 6, and Pods 7 and 8. To unassign the pods, select

the pod field. In the pop-up menu, select Unassigned.

3 Set up the Format menu.

Press the Format key.

Select the field to the right of Pod A1, then select ECL in the pop-up menu.

Move the cursor over the Pod A1 channel selection field. Press the Clear Entry button until all channels are assigned (all ’*’), then press Done.

Move the cursor over the Data on Clocks channel selection field, then press Select. Rotate the RPG knob to move the channel selector to the channel indicated in the following table, then press Select. Press Done.

Pod Channel

A1, A3, A5, A7 0 A2, A4, A6, A8 1

3–10

Testing Performance

To test the threshold accuracy (logic analyzer)

4 Set up the Waveform menu.

Press the Waveform key.

In the Waveform menu, move the cursor to the pod/channel selection field, then press Select. In the pop-up menu, select Delete All, then select Continue.

Again press Select. At the pop-up menu, select Insert, then select Bus1, then select Sequential.

3–11

Testing Performance

To test the threshold accuracy (logic analyzer)

Connect the logic analyzer

1 Using the 17-by-2 test connector, BNC cable, and probe tip assembly, connect the

data and clock channels of pod 1 to one side of the BNC Tee.

2 Using a BNC-banana cable, connect the voltmeter to the other side of the BNC Tee. 3 Connect the BNC Tee to the Main Signal output of the function generator.

3–12

To test the threshold accuracy (logic analyzer)

Test the ECL Threshold

1 Set up the Format menu.

Press the Format key.

Select the field to the right of Pod A1, then select ECL in the pop-up menu.

Testing Performance

Test the high-to-low transition.

On the DC power source, enter -1.438 V.

On the logic analyzer, press Run. The display should show all channels at a logic "0"

3–13

Testing Performance

To test the threshold accuracy (logic analyzer)

3. Test the low-to-high transition

On the DC source, enter -1.162 V

On the logic analyzer, press Run. The display should show all channels at a logic "1".

Record a PASS/FAIL in the performance test record for Threshold Accuracy Pod 1 -

ECL.

3–14

Testing Performance

To test the threshold accuracy (logic analyzer)

Test the 0 V User threshold

1 Set up the Format menu.

Press the Format key.

Select the field to the right of Pod A1, then select User in the pop-up menu, then enter 0 V.

Test the high-to-low transition.

On the DC power source, enter -0.099 V.

On the logic analyzer, press Run. The display should show all channels at a logic "0".

Test the low-to-high transition

On the DC source, enter 0.099 V

On the logic analyzer, press Run. The display should show all channels at a logic "1".

Record a PASS/FAIL in the performance test record for Threshold Accuracy Pod 1 -

0 V.

3–15

Testing Performance

To test the threshold accuracy (logic analyzer)

Test the next pod

1 Using the 17-by-2 test connector and probe tip assembly, connect the data and clock

channels of the next pod to the output of the function generator until all pods have been tested.

2 Unassign the channels just tested.

Press the Format key.

Move the cursor over the channel assignment field for the pod tested. Press Clear Entry until all channels show unassigned (all ’.’).

Move the cursor over the Data on Clocks channel assignment field. Press Clear Entry until all channels show unassigned (all ’.’).

Start with "Set up the logic analyzer" on page 3−10, substituting the next pod to be

tested for pod 1.

3–16

To test the single-clock, single-edge, state acquisition (logic analyzer)

Testing the single-clock, single-edge, state acquisition verifies the performance of the following specifications:

•

Minimum master-to-master clock time

•

Maximum state acquisition speed

•

Setup/Hold time for single-clock, single-edge, state acquisition

This test checks two combinations of data channels using a single-edge clock at two selected setup/hold times.

Equipment Required

Equipment Critical Specifications Recommended Model/Part

Pulse Generator 150 MHz 3.0 ns pulse width, < 600 ps rise time 8133A option 003

Digitizing Oscilloscope ≥ 6 GHz bandwidth, < 58 ps rise time 54750A w/ 54751A

Adapter SMA(m)-BNC(f) 1250-1200 SMA Coax Cable (Qty 3) 18 GHz bandwidth 8120-4948 Coupler BNC(m)(m) 1250-0216 BNC Test Connector, 6x2 (Qty 4)

Set up the equipment

Turn on the equipment required and the logic analyzer. Let them warm up for 30 minutes before beginning the test if you have not already done so.

Set up the pulse generator.

Set up the pulse generator according to the following table.

Pulse Generator Setup

Timebase Channel 2 Period Channel 1

Mode: Int Mode: Pulse Divide: Divide ÷ 2 Mode: Square Period: 6.666 ns Divide: PULSE ÷ 2 Ampl: 0.50 V Delay: 0.000 ns

Width: 3.000 ns Offs: 0.00 V

High: −0.90 V High: −0.90 V Low: −1.70 V Low: −1.70 V

Disable the pulse generator channel 1 COMP (with the LED off).

3–17

Testing Performance

To test the single-clock, single-edge, state acquisition (logic analyzer)

Set up the oscilloscope.

Select Setup, then select Default Setup.

Configure the oscilloscope according to the following table.

Oscilloscope Setup

Acquisition Display Trigger

Averaging: On # of averages: 16

Channel 1 Channel 2 Define meas

Alternate Scale Attenuation: 20.00:1 Scale: 200 mV/div

Offset: −1.300 V

Graticule Graphs: 2

Alternate Scale Attenuation: 20.00:1 Scale: 200 mV/div Offset: -1.300 V

Level: -250 mV Stop src: channel 2 [Enter]

[Shift] ∆ Time

Thresholds: user-defined Units: Volts Upper: -980 mV Middle: -1.30 V Lower: -1.62 V

Set up the logic analyzer

Set up the Configuration menu.

Press the Config key.

In the Configuration menu, assign all pods to Machine 1. To assign the pods, select the pod fields, then select Machine 1 in the pop-up menu.

Select the Type field in the Analyzer 1 box, then select State Compare.

3–18

To test the single-clock, single-edge, state acquisition (logic analyzer)

Set up the Format menu.

Press the Format key.

Select the field to the right of each pod, then select ECL in the pop-up menu. Use the knob to access pods not shown on the screen.

Testing Performance

Set up the Trigger menu.

Press the Trigger key. Select Modify Trigger, then select Clear Trigger, then select All in the pop-up menu.

Select Count Off. Press Select again, then select Time in the pop-up menu. Select Done to exit the menu.

Select Acquisition Control. If the Acquisition Control is "Manual," use the cursor keys to move the cursor to the Acquisition Mode field. Press the "Select" key to toggle this field to "Automatic."

In the Acquisition Control menu, use the knob to set the Memory Length to 4096. Press the Done key.

Select the field labeled 1 under the State Sequence Levels. Select the field labeled "anystate," then select "no state." Select Done to exit the State Sequence Levels menu.

3–19

Testing Performance

To test the single-clock, single-edge, state acquisition (logic analyzer)

Connect the logic analyzer

Using the 6-by-2 test connectors, connect the first combination of logic analyzer clock and data channels listed in one of the following tables to the pulse generator.

If you are testing an Agilent 1670G or Agilent 1671G, you will repeat this test for the second combination.

Using SMA cables, connect the oscilloscope to the pulse generator channel 1 Output,

channel 2 Output, and Trigger Output.

Connect the Agilent 1670G or Agilent 1671G Logic Analyzer to the Pulse Generator

Testing Combinations

1 Pod 1, channel 3

2 Pod 1, channel 11

Connect to 8133A Channel 2 Output

Pod 3, channel 3 Pod 5, channel 3 Pod 7, channel 3

Pod 3, channel 11 Pod 5, channel 11 Pod 7, channel 11

Connect to 8133A Channel 2 Output

Pod 2, channel 3 Pod 4, channel 3 Pod 6, channel 3 Pod 8, channel 3 *

Pod 2, channel 11 Pod 4, channel 11 Pod 6, channel 11 Pod 8, channel 11*

*Agilent 1670G only

Connect to 8133A Channel 1 Output

J-clock

3–20

To test the single-clock, single-edge, state acquisition (logic analyzer)

Connect the Agilent 1672G or Agilent 1673G Logic Analyzer to the Pulse Generator

Testing Performance

Testing Combination

1 Pod 1, channel 3

Connect to 8133A Channel 2 Output

Pod 2, channel 3 Pod 3, channel 3 Pod 4, channel 3

Connect to 8133A Channel 2 Output

Pod 1, channel 11 Pod 2, channel 11 Pod 3, channel 11* Pod 4, channel 11*

*Agilent 1672G only

Connect to 8133A Channel 1 Output

J-clock

Activate the data channels that are connected according to one of the previous tables.

Press the Format key.

Select the field showing the channel assignments for one of the pods being tested, then press the Clear entry key. Using the arrow keys, move the selector to the data channels to be tested, then press the Select key. An asterisk means that a channel is turned on. When all the correct channels of the pod are turned on, press the Done key. Follow this step for the remaining pods.

3–21

Testing Performance

To test the single-clock, single-edge, state acquisition (logic analyzer)

4 Configure the trigger according to the connected channels.

Press the Trigger key.

Select the field next to "a" under the label Bus1. Type the following for your logic analyzer, then press the Select key.

Agilent 1670G – "AA"

Agilent 1672G – "AA"

Agilent 1671G – "2A"

Agilent 1673G – "0A"

Enable the pulse generator channel 1, channel 2, and trigger outputs (with the LEDs

off).

3–22

Testing Performance

To test the single-clock, single-edge, state acquisition (logic analyzer)

Verify the test signal

1 Check the clock period. Using the oscilloscope, verify that the master-to-master

clock time is 6.666 ns, +0 ps or −100 ps.

In the oscilloscope Timebase menu, select Scale: 1.000 ns/div.

In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob, position the clock waveform so that a rising edge appears at the left of the display.

On the oscilloscope, select [Shift] Period: channel 2, then select [Enter] to display the clock period (Period(2)). If the period is not less than 6.666 ns, go to step d. If the period is less than 6.666 ns, go to step 3.

In the oscilloscope Timebase menu, increase Position 6.666 ns. If the period is not less than 6.666 ns, decrease the pulse generator Period in 10 ps increments until one of the two periods measured is less than 6.666 ns.

Check the data pulse width. Using the oscilloscope, verify that the data pulse width

is 3.000 ns, +0 ps or −100 ps.

In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob, position the data waveform so that the waveform is centered on the screen.

On the oscilloscope, select [Shift] + width: channel 1, then select [Enter] to display the data signal pulse width (+ width(1)).

c If the pulse width is outside the limits, adjust the pulse generator channel 2 width until

the pulse width is within limits.

3–23

Testing Performance

To test the single-clock, single-edge, state acquisition (logic analyzer)

Check the setup/hold combination

Select the logic analyzer setup/hold time.

a In the logic analyzer Format menu, select Master Clock.

b Select the Setup/Hold field, then select the setup/hold combination to be tested for all

pods. The first time through this test, use the top combination in the following table.

Setup/Hold Combinations

3.0/0.0 ns

-0.5/3.5 ns

c Select Done to exit the setup/hold combinations.

Disable the pulse generator channel 1 COMP (with the LED off).

Using the Delay mode of the pulse generator channel 1, position the pulses

according to the setup time of the setup/hold combination selected, +0.0 ps or

100 ps

−

b In the oscilloscope timebase menu, select Position. Using the oscilloscope knob,

On the Oscilloscope, select [Define meas] Define ∆ Time - Stop edge: rising.

position the rising edge of the clock waveform so that it is centered on the display.

3–24

Testing Performance

To test the single-clock, single-edge, state acquisition (logic analyzer)

On the oscilloscope, select [Shift] ∆ Time, then select [Enter] to display the setup time (∆ Time(1)-(2)).

d Adjust the pulse generator channel 1 Delay until the pulses are aligned according the

the setup time of the setup/hold combination selected, +0.0 ps or -100 ps.

Disregard the oscilloscope Period(2) value. The settings provided in this procedure measure the period from falling edge to falling edge, which is not a valid measurement.

Select the clock to be tested.

a In the Master Clock menu, select the clock field to be tested, then select the clock

edge as indicated in the table. The first time through this test, use the top clock and edge in the following table.

Clocks

↑

b Connect the clock to be tested to the pulse generator channel 1 output.

c Select Done to exit the Master Clock menu.

3–25

Testing Performance

To test the single-clock, single-edge, state acquisition (logic analyzer)

Note: Do this step only the first time through the test, to create a Compare file. For

subsequent runs, go to step 6.

Use the following to create a Compare file:

a Press Run. The display should show an alternating pattern of "AA" and "55." Verify

the pattern by scrolling through the display.

b Press the List key. In the pop-up menu, use the knob to move the cursor to Compare.

Press Select.

c In the Compare menu, move the cursor to Copy Listing to Reference, then press the

Select key. Select Execute.

d Move the cursor to Specify Stop Measurement and press the Select key. Press Select

again to turn on Compare. At the pop-up menu, select Compare. Move the cursor to the Equal field and press the Select key. At the pop-up menu, select Not Equal. Press Done.

e Move the cursor to the Reference Listing field and select. The field should toggle to

Difference Listing.

Press the blue shift key, then press the Run key. If the analyzer obtains two to four

acquisitions without the "Stop Condition Satisfied" message appearing, then the test passes. Press Stop to halt the acquisition. Record the Pass or Fail results in the performance test record.

Test the next clock.

a Press the Format key, then select Master Clock.

b Turn off and disconnect the clock just tested.

c Repeat steps 4, 6, and 7 for the next clock edge listed in the table in step 4, until all

listed clock edges have been tested.

Enable the pulse generator channel 1 COMP (with the LED on).

Using the Delay mode of the pulse generator channel 1, position the pulses

according to the setup/hold combination selected, +0.0 ps or -100 ps.

On the Oscilloscope, select [Define meas] Define ∆ Time - Stop edge: falling.

On the oscilloscope, select [Shift] ∆ Time. Select Start src: channel 1, then select [Enter] to display the setup time (∆ Time(1)-(2)).

3–26

Testing Performance

To test the single-clock, single-edge, state acquisition (logic analyzer)

c Adjust the pulse generator channel 1 Delay until the pulses are aligned according the

the setup time of the setup/hold combination selected, +0.0 ps or -100 ps.

Disregard the oscilloscope Period(2) value. The settings provided in this procedure measure the period from rising edge to rising edge, which is not a valid measurement.

Select the clock to be tested.

a In the Master Clock menu, select the clock field to be tested, then select the clock

edge as indicated in the table. The first time through this test, use the top clock and edge.

Clocks

↓

b Connect the clock to be tested to the pulse generator channel 1 output.

c Select Done to exit the Master Clock menu.

Press the blue shift key, then press the Run key. If the analyzer obtains two to four

acquisitions without the "Stop Condition Satisfied" message appearing, then the test passes. Press Stop to halt the acquisition. Record the Pass or Fail results in the performance test record.

3–27

Testing Performance

To test the single-clock, single-edge, state acquisition (logic analyzer)

Test the next clock.

a Press the Format key, then select Master Clock.

b Turn off and disconnect the clock just tested.

c Repeat steps 10, 11, and 12 for the next clock edge listed in the table in step 11, until

all listed clock edges have been tested.

Test the next setup/hold combination.

a In the logic analyzer Format menu, press Master Clock.

b Turn off and disconnect the clock just tested.

c Repeat steps 1 through 13 for the next setup/hold combination listed in step 1 on

page 3–24, until all listed setup/hold combinations have been tested.

When aligning the data and clock waveforms using the oscilloscope, align the waveforms

according to the setup time of the setup/hold combination being tested, +0.0 ps or −100 ps.

Test the next channels

Connect the next combination of data channels and clock channels, then test them. Start on page 3–20, "Connect the logic analyzer," connect the next combination, then continue

through the complete test.

3–28

To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)

Testing the multiple-clock, multiple-edge, state acquisition verifies the performance of the following specifications:

Minimum master-to-master clock time

•

Maximum state acquisition speed

•

Setup/Hold time for multiple-clock, multiple-edge, state acquisition

•

This test checks two combinations of data using multiple clocks at two selected setup/hold times.

Equipment Required

Equipment Critical Specifications Recommended

Model/Part

Pulse Generator 150 MHz 3.0 ns pulse width, < 600 ps rise time 8133A option 003 Digitizing Oscilloscope Adapter SMA(m)-BNC(f) 1250-1200 SMA Coax Cable (Qty 3) 18 GHz bandwidth 8120-4948 Coupler BNC(m)(m) 1250-0216 BNC Test Connector, 6x2 (Qty 4)

6 GHz bandwidth, < 58 ps rise time 54750A w/ 54751A

≥

Set up the equipment

Turn on the equipment required and the logic analyzer. Let them warm up for

30 minutes before beginning the test if you have not already done so. Set up the pulse generator.

Set up the pulse generator according to the following table.

Pulse Generator Setup

Timebase Channel 2 Period Channel 1

Mode: Int Mode: Pulse Divide: Divide ÷ 2 Mode: Square

Period: 6.666 ns Divide: PULSE ÷ 2 Ampl: 0.50 V Delay: 0.000 ns

Width: 4.000 ns Offs: 0.00 V

High: −0.90 V High: −0.90 V

Low: −1.70 V Low: −1.70 V

Disable the pulse generator channel 1 COMP (with the LED off).

3–29

Testing Performance

To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)

Set up the oscilloscope. If the oscilloscope was not configured for the previous test,

then do the following steps.

Select Setup, then select Default Setup.

Configure the oscilloscope according to the following table.

Oscilloscope Setup

Acquisition Display Trigger

Averaging: On # of averages: 16

Channel 1 Channel 2 Define meas

Alternate Scale Attenuation: 20.00:1 Scale: 200 mV/div Offset: −1.300 V

Graticule Graphs: 2

Alternate Scale Attenuation: 20.00:1 Scale: 200 mV/div Offset: -1.300 V

Level: -250 mV Stop src: channel 2 [Enter]

[Shift] ∆ Time

Thresholds: user-defined Units: Volts Upper: -980 mV Middle: -1.30 V Lower: -1.62 V

Set up the logic analyzer

Do the following steps if you have not already done them for a previous test.

1 Set up the Configuration menu.

Press the Config key.

In the Configuration menu, assign all pods to Machine 1. To assign pods, select the pod fields, then select Machine 1.

In the Analyzer 1 box, select the Type field, then select State Compare.

3–30

To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)

2 Set up the Format menu.

Press the Format key.

Select the field to the right of each Pod field, then select ECL. The screen does not show all Pod fields at one time. Use the knob to access more Pod fields.

Testing Performance

Set up the Trigger menu.

Press the Trigger key. Select Modify Trigger, then select Clear Trigger, then select All in the pop-up menu.

Select Count Off. Press Select again, then select Time in the pop-up menu. Select Done to exit the menu.

Select Acquisition Control. If the Acquisition Control is "Manual," use the cursor keys to move the cursor to the Acquisition Mode field. Press the "Select" key to toggle this field to "Automatic."

In the Acquisition Control menu, use the knob to set the Memory Length to 4096. Press the Done key.

Select the field labeled 1 under the State Sequence Levels. Select the field labeled "anystate", then select "no state." Select Done to exit the State Sequence Levels menu.

3–31

Testing Performance

To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)

Connect the logic analyzer

1 Using the 6-by-2 test connectors, connect the first combination of logic analyzer

clock and data channels listed in one of the following tables to the pulse generator.

If you are testing an Agilent 1670G or Agilent 1671G, you will repeat this test for the second combination.

Using SMA cables, connect channel 1, channel 2, and trigger of the oscilloscope to

the pulse generator.

Connect the Agilent 1670G or Agilent 1671G Logic Analyzer to the Pulse Generator

Testing Combinations Connect to

8133A Channel 2 Output

1 Pod 1, channel 3

Pod 3, channel 3 Pod 5, channel 3 Pod 7, channel 3

2 Pod 1, channel 11

Pod 3, channel 11 Pod 5, channel 11 Pod 7, channel 11

Connect to 8133A Channel 2

Pod 2, channel 3 Pod 4, channel 3 Pod 6, channel 3 Pod 8, channel 3 *

Pod 2, channel 11 Pod 4, channel 11 Pod 6, channel 11 Pod 8, channel 11 *

*Agilent 1670G only.

Output

Connect to 8133A Channel 1 Output

J-clock K-clock L-clock M-clock

3–32

To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)

Connect the Agilent 1672G or Agilent 1673G Logic Analyzer to the Pulse Generator

Testing Performance

Testing Combination

1 Pod 1, channel 3

Connect to 8133A Channel 2 Output

Pod 2, channel 3 Pod 3, channel 3 Pod 4, channel 3

Connect to 8133A Channel 2 Output

Pod 1, channel 11 Pod 2, channel 11 Pod 3, channel 11 * Pod 4, channel 11 *

*Agilent 1672G only.

Connect to 8133A Channel 1 Output

J-clock K-clock L-clock M-clock

Activate the data channels that are connected according to one of the previous

tables.

Press the Format key.

Select the field showing the channel assignments for one of the pods being tested. Press the Clear entry key. Using the arrow keys, move the selector to the data channels to be tested, then press the Select key. An asterisk means that a channel is turned on. When all the correct channels of the pod are turned on, press the Done key. Follow this step for the remaining pods.

3–33

Testing Performance

To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)

4 Configure the trigger according to the connected channels.

Press the Trigger key.

Select the field next to the pattern recognizer "a" under the label Bus1. Type the following for your logic analyzer, then press Select.

Agilent 1670G – "AA"

Agilent 1672G – "AA"

Agilent 1671G – "2A"

Agilent 1673G – "A"

Enable the pulse generator channel 1, channel 2, and trigger ouputs (with the LEDs

off).

3–34

Testing Performance

To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)

Verify the test signal

Check the clock period. Using the oscilloscope, verify that the master-to-master

clock time is 6.666 ns, +0 ps or −100 ps.

a In the oscilloscope Timebase menu, select Scale: 1.000 ns/div.

b In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob,

position the clock waveform so that a rising edge appears at the left of the display.

c On the oscilloscope, select [Shift] Period: channel 2, then select [Enter] to display the

clock period (Period(2)). If the period is not less than 6.666 ns, go to step d. If the period is less than 6.666 ns, go to step 2.

d In the oscilloscope Timebase menu, increase Position 6.666 ns. If the period is not less

than 6.666 ns, decrease the pulse generator Period in 10 ps increments until one of the two periods measured is less than 6.666 ns.

Check the data pulse width. Using the oscilloscope verify that the data pulse width

is 4.000 ns, +0 ps or −100 ps.

a In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob,

position the data waveform so that the waveform is centered on the screen.

b On the oscilloscope, select [Shift] + width: channel 1, then select [Enter] to display the

data signal pulse width (+ width (1)).

c If the pulse width is outside the limits, adjust the pulse generator channel 2 width until

the pulse width is within limits.

3–35

Testing Performance

To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)

Check the setup/hold with single clock edges, multiple clocks

Select the logic analyzer setup/hold time.

a In the logic analyzer Format menu, select Master Clock.

b Select and activate any two clock edges.

c Select the Setup/Hold field and select the setup/hold to be tested for all pods. The first

time through this test, use the top combination in the following table.

Setup/Hold Combinations

4.0/0.0 ns

-0.5/4.5 ns

d Select Done to exit the setup/hold combinations.

Disable the pulse generator channel 1 COMP (with the LED off).

Using the Delay mode of the pulse generator channel 1, position the pulses

according to the setup time of the setup/hold combination selected, +0.0 ps or

100 ps.

−

On the Oscilloscope, select [Define meas] Define ∆ Time - Stop edge: rising.

b In the oscilloscope timebase menu, select Position. Using the oscilloscope knob,

position the rising edge of the clock waveform so that it is centered on the display.

3–36

Testing Performance

To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)

On the oscilloscope, select [Shift] ∆ Time, then select [Enter] to display the setup time (∆ Time(1)-(2)).

d Adjust the pulse generator channel 1 Delay until the pulses are aligned according the

the setup time of the setup/hold combination selected, +0.0 ps or -100 ps.

Disregard the oscilloscope Period(2) value. The settings provided in this procedure measure the period from falling edge to falling edge, which is not a valid measurement.

Select the clocks to be tested.

a Select the clock field to be tested and then select the clock edges as indicated in the

table.

Clocks

J↑ + K↑ + L

↑ + M↑

b Connect the rising edge clocks to the pulse generator channel 1 output.

c Select Done to exit the Master Clock menu.

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Testing Performance

To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)

Note: Do this step if you have not already created a Compare file for the previous

test (single-clock, single-edge state acquisition), use the following steps to create one. For subsequent passes through this test, skip this step and go to step 6.

Use the following to create a Compare file:

a Press Run. The display should show an alternating pattern of "AA" and "55." Verify

the pattern by scrolling through the display.

b Press the List key. In the pop-up menu, use the knob to move the cursor to Compare.

Press Select.

c In the Compare menu, move the cursor to Copy Listing to Reference, then press the

Select key. Select Execute.

d Move the cursor to Specify Stop Measurement and press the Select key. Press Select

again to turn on Compare. At the pop-up menu, select Compare. Move the cursor to the Equal field and press the Select key. At the pop-up menu, select Not Equal. Press Done.

e Move the cursor to the Reference Listing field and select. The field should toggle to

Difference Listing.

Press the blue shift key, then press the Run key. If the analyzer obtains two to four

acquisitions without the "Stop Condition Satisfied" message appearing, then the test passes. Press Stop to halt the acquisition. Record the Pass or Fail results in the performance test record.

Enable the pulse generator channel 1 COMP (with the LED on).

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