State and Timing Modules
for Agilent Technologies
Logic Analysis Systems
Product Overview
Your design team faces a difficult
challenge: Deliver quality products
to the marketplace faster than
your competitors. Meeting that
challenge depends on your ability
to debug and characterize hardware, design and test firmware
and software, and perform system
integration.
Hardware and software engineers
need a common, scalable system
for testing and debugging digital
systems. Agilent Technologies
offers a variety of measurement
modules for logic analysis systems
to make it easy for you to select
the right solution today then
expand as your needs evolve without relearning or reinvesting in the
platform.
State/Timing General- 8/16 Bit 32/64 Bit High- Timing Deep trace High- Analysis of data
Modules purpose processor processor speed margin capture speed intensive
hardware debug debug or bus analysis or with timing computer systems and
debug channel analysis characterize or state debug performance
intensive setup/hold analysis
systems
16710A √√
16711A √√
16712A √√
16557D √√ √
16715A √√√
16716A √√ √ √ √
16717A √√ √ √√
16718A √√ √ √√ √
16719A √√ √ √√ √
16517/18A √√
A variety of measurement modules allow you to select the optimum combination of performance, features, and price to meet your specific needs now
and in the future.
Choose the Logic Analyzer and Measurement Modules that Best Fit Your Application
TABLE OF CONTENTS
Choose the logic analyzer that best fits your application pg 1
Key specifications and characteristics pg 2
How to evaluate your logic analysis needs pg 4
User interface pg 6
VisiTrigger™ pg 7
2 GHz Timing Zoom pg 8
Acquisition memory pg 9
Probing pg 10
Data processing tools pg 13
Supplemental specifications and characteristics pg 15
Frame compatibility pg 22
Related literature pg 22
Key Specifications* and Characteristics
Model 16715A 16716A 16717A, 16718A, 16719A
Maximum state clock* 167 MHz 167 MHz 333 MHz [1]
Maximum timing sample rate 2 GHz Timing Zoom 2 GHz Timing Zoom
(full/half channel) Conventional: 333/667 MHz Conventional: 333/667 MHz Conventional: 333/667 MHz
Channels/module 68 68 68
Maximum channels on a 340 340 340
single time base and trigger
Maximum channels in a system 680 680 680
Memory depth (full/half channel) 2/4M [2] 512K/1M [2] 16717A 2/4M [2]
16718A 8/16M [2]
16719A 32/64M [2]
Trigger resources Patterns: 16 Patterns: 16 Patterns: 16
Ranges: 15 Ranges: 15 Ranges: 15
Edge & Glitch: 2 Edge & Glitch: 2 Edge & Glitch: 2
Timers: (2 per module) -1 Timers: (2 per module) -1 Timers: (2 per module) -1
Occurrence Counter: [4] Occurrence Counter: [4] Occurrence Counter: [4]
Global Counters: 2 Global Counters: 2 Global Counters: 2
Flags: 8 Flags: 8 Flags: 8
Maximum trigger sequence levels 16 16 16
Maximum trigger sequence speed 167 MHz 167 MHz 333 MHz
Trigger sequence level branching 4-way arbitrary 4-way arbitrary 4-way arbitrary
IF/THEN/ELSE IF/THEN/ELSE IF/THEN/ELSE
branching branching branching
Number of state clocks/qualifiers 444
Setup/hold time* 2.5 ns window adjustable from 4.5/-2.0 ns to -2.0/4.5 ns in 100 ps increments per channel [3]
Threshold range TTL, ECL, user-definable ±6.0 V adjustable in 10-mV increments
[1] State speeds greater than 167 MHz require a trade-off in features. Refer to “Supplemental Specifications and Characteristics” on
page 20 for more information.
[2] Memory depth doubles in half-channel timing mode only.
[3] Minimum setup/hold time specified for a single clock, single edge acquisition. Multi-clock, multi-edge setup/hold window add 0.5 ns.
[4] There is one occurrence counter per trigger sequence level.
2
NEW
NEW
NEW
3
Key Specifications* and Characteristics (cont’d)
Model 16710A, 16711A, 16712A 16557D 16517A/18A
1-4 Modules 5 Modules
Maximum state clock* 100 MHz 140 MHz 100 MHz 1 GHz synchronous state [1]
Maximum timing sample rate Conventional: 250/500 MHz Conventional: 250/500 MHz Conventional: 2/4 GHz
(full/half channel) Transitional: 125 MHz
Channels/module 102 68 16
Maximum channel count 204 272 340 80
on a single time base and trigger
Maximum channels in a system 1020 680 160
Memory depth 16710A 8/16K [2] 2/4M [2] 64/128K [2]
(full/half channel) 16711A 32/64K [2]
16712A 128/256K [2]
Trigger resources Patterns: 10 Patterns: 10 Patterns: 4
Ranges: 2 Ranges: 2 Edge & Glitch: 2
Edge & Glitch: 2 Edge & Glitch: 2 Timers:[3]
Timers: 2 Timers: 2
Trigger sequence levels State mode: 12 State mode: 12 State mode: 4
Timing mode: 10 Timing mode: 10 Timing mode: 4
Maximum trigger sequence speed 125 MHz 140 MHz 500 MHz [1]
Trigger sequence level branching Dedicated next state or single arbitrary branching
Number of state clocks/qualifiers 6 4 1[4]
Setup/hold time* 4.0 ns window adjustable from 3.0 ns window adjustable from 700 ps window adjustable from
4.0/0 ns to 0/4.0 ns 3.0/0 ns to -0.5/3.5 ns 350/350 ps adjustable
in 500 ps increments [6] in 500 ps increments [6] in 50 ps increments [5]
per 34 channels per 34 channels per 8 channels
Threshold range TTL, ECL, user-definable
± 6.0 V adjustable in 50-mV increments TTL, ECL,
user-definable ± 5 V
adjustable
in 10-mV increments
[1] The Agilent Technologies 16517A, 16518A have a maximum trigger sequencer speed of 500 MHz. Triggering on data at speeds faster than
500 MHz requires the data to be valid for a minimum of 2.25 ns.
[2] Memory depth doubles in half-channel timing mode only.
[3] There is one timer or counter per sequence level, which is restarted upon entry into each level.
[4] Requires a periodic clock from 20 MHz to 1 GHz. Clock edge is selectable as positive or negative.
[5] The setup and hold across pods is 750/750 ps without manual adjustment, 350/350 ps with manual adjustment.
[6] Minimum setup/hold time specified for single-clock, single-edge acquisition. Single-clock, multi-edge setup/hold add 0.5 ns.
Multi-clock, multi-edge setup/hold window add 1.0 ns.
4
How to Evaluate Your
Logic Analysis Needs
State Speed
State analysis uses a signal from
your system under test to determine when to sample. Since state
analysis samples are synchronous
with the system under test, it will
provide you with a view of how
your system is executing. You can
use state analysis to capture bus
cycles from a microprocessor or I/O
bus and convert the data into
processor mnemonics or bus
transactions using an Agilent
Technologies inverse assembler.
Select a state acquisition system
that provides the speed you need
without breaking your budget.
Remember that a processor will
specify an internal core frequency
that is normally 2X-5X the speed of
the external bus.
Setup/Hold
Logic analyzers are like any logic
circuitry in that they require time
for the data at the inputs to
become valid (setup time), and
time to capture the data (hold
time). As your target frequencies
increase, the ability of your logic
analyzer to capture accurate data
is limited by its setup and hold. A
lengthy setup and hold can make
the difference between capturing
valid data or data in transition.
Your device under test will ensure
data is valid on the bus for a
defined length of time. This is
known as the data valid window.
Your target’s data valid window
must be large enough to meet the
setup/hold specifications of the
logic analyzer. The data valid window of most devices is generally
less than half of the clock period.
Don’t be fooled by "typical" setup
and hold specifications. To ensure
the capture of valid data, the
maximum setup/hold time for your
logic analyzer must fit within your
target’s data valid window.
Inaccurate measurements can also
result when the logic analyzer’s
setup/hold window cannot be
positioned within the target’s data
valid window. An adjustable
setup/hold with fine position
resolution provides unparalleled
measurement accuracy at
high frequencies.
Figure 2. Make sure your logic
analyzer captures accurate data.
Figure 1. State analysis allows you to track real-time system execution problems.
Target
Clock
Target Data
Target Data Valid
Analyzer S/H
must fit within
the target's data
valid window
Data
Transitions
5
Timing Resolution
Timing analysis uses the logic analyzer’s internal clock to determine
when to sample. Since timing
analysis samples asynchronously
to the system under test, you
should consider what accuracy
you will need to verify your system. Accuracy is made up of two
elements: sample speed and channel-to-channel skew. Remember to
evaluate both of these elements
and be careful of logic analyzers
that have a fast sample speed with
a large channel-to-channel skew.
Transitional Timing
If your system has bursts of
activity followed by times with
little activity, you can use transitional timing to capture a longer
trace. In transitional timing, the
analyzer samples data at regular
intervals, but only stores the data
when there is a transition on one
of the signals.
Channel Count
Determine the number of signals
you want to analyze on your system under test. You will need this
number of channels in your logic
analyzer. Even if you have enough
channels to view all the signals in
your system today, you should
consider logic analysis systems
that allow you to add more channels for your future application
needs.
Memory
Deep memory is an invaluable
resource when you trigger on a
problem symptom that is far
removed from its cause. This is
common in complex systems that
have a significant amount of hardware/software interaction. Software engineers will also appreciate the ability to capture deep
traces to view code execution.
Much of your debug time is spent
analyzing captured data. When
using deep memory,consider a
logic analysis system with the
performance you need to help you
quickly sift through measurement
results.
Triggering
The logic analyzer memory system
is similar to a circular buffer.
When the acquisition is started,
the analyzer continuously acquires
data samples and stores them in
memory. When memory becomes
full, it simply wraps around and
stores each new sample in the
place of the sample that has been
in memory the longest.
This process will continue until
the logic analyzer finds the trigger
point. The logic analyzer trigger
stops the acquisition at the point
you specify and provides a view
into the system under test. The primary responsibility of the trigger is
to stop the acquisition, but it can
also be used to control the selective storage of data. Consider a
logic analyzer with the trigger
resources you need to quickly set
up your measurements.
Figure 3. Evaluate time relationships between signals with timing analysis.
6
Improve your Productivity with an Intuitive User Interface
Measurement configuration and data files can
be loaded directly into the logic analyzer
Menu tabs provide a logical progression
through the setup of your measurement.
State and timing mode selections
specify how data is sampled.
Single location for access to
all state acquisition options.
Convenient color coding helps you
identify the signals in the interface
with the physical connection to
your device under test.
Clocking for state measurements can be
quickly defined using the clock setup menu.
Sampling defines how the logic
analyzer will acquire the data.
Figure 4. Setting up your logic analyzer has never been this easy to understand.
Format allows you
to group signals into buses.
Trigger defines what
data is acquired.
You may not use your logic
analyzer every day, therefore Agilent Technologies has made the
user interface easy to understand.
Now you can spend more time
making measurements and less
time setting up the logic analyzer.
Timing Zoom sample rate and position
configured relative to the trigger
of the main analyzer.
7
Agilent Technologies’ New VisiTrigger™ Technology Allows You To Quickly Locate
Your Most Elusive Problems
Your most commonly used triggers are just a
mouse click away with the built-in trigger
functions. VisiTrigger’s graphical representation shows you how the trigger
condition will be defined. You can use trigger
functions as building blocks to easily
customize a trigger for your specific task.
Sequence levels allow you to develop a
sequence of analyzer instructions to specify a
trigger point or to qualify data and store only
the information that interests you. Each step in
the sequence contains an "IF/THEN/ELSE"
structure that can evaluate up to four logic
events. Each event can specify a combination
of actions such as: store sample, increment
counters, reset timers, trigger, or go to another
step in the sequence level.
Ranges provide a way to monitor program
and data accesses within a specified area
in memory.
Global counters can count events such as
the number of times a function executes or
accesses an I/O port.
Timers can be set up to evaluate when one
event happens too late or too soon with
respect to another event.
In timing mode, edge terms let you
trigger on a rising edge, falling edge,
either edge, or a glitch.
Patterns and their logical combinations
let you identify which states to store, when to
branch and when to trigger.
Save and recall up to ten of your
custom trigger setups without loading
a new configuration file.
View up-to-date information on the
current state of the timers, counters, flags, and
the trigger sequence level.
Flags can be set, cleared and evaluated by
any 16715/16/17/18/19A module in the frame.
This allows you to set up a trigger that is dependent on activity from more than one bus in the
system.
Values can be easily entered directly into the
trigger description.
Figure 5. Set up your trigger in
terms of the measurements you
want to make.
VisiTrigger™ technology available
in the 16715A, 16716A, 16717A,
16718A, and 16719A family of modules is a breakthrough in logic
analysis usability. It combines
increased trigger functionality
with a user interface that is easy to
understand and use. Now with
VisiTrigger™, capturing complex
events is as simple as point-andclick to choose the trigger function
and fill-in-the-blank to customize it
to your specific task.
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