Errata
16500B Users Guide
16500-97007
February 1994
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User’s Guide
Publication number 16500-97007
First Edition, February 1994
For Safety information, Warranties, and Regulatory
information, see the pages behind the index
© Copyright Hewlett-Packard Company 1987, 1990, 1993, 1994
All Rights Reserved
HP 16500B /16501A Logic
Analysis System
ii
HP 16500B—At a Glance
cards with a wide range of state, tim in g,
A system of measurement modules
The HP 16500B is the mainframe of the
Hewlett-Packard Logic Analysis System.
It offers a modular structure for pl ug-i n
oscilloscope, and patter n generator
capabilities.
A powerful, easy-to-use int erface
The touchscreen interfa ce off ers popup menus and color graphics to lead
you through measurement
configurations withou t hav in g to
remember lots of steps. You can add a
keyboard or mouse to speed data input
and measurement confi guration.
The HP 16501A expands mod ule
capacity
connected, they form a single ten-card
The HP 16501A is the add-on mainf ram e
for expanding the module ca paci ty of
the HP 16500B. When the two are
system that is turned on and control l ed
by the HP 16500B.
Intermodule measusu rem ent capability
The HP 16500B offers intermodule
measurement features that allow you to
capture complex system activity.
Modules can
be armed by an external instrument,
•
be armed by another module in the
•
HP16500B or HP16501A frames, or
be used to arm an external
•
instrument.
iii
iv
Install measurement modules in any
slot
Single card analyzers, osc illoscopes,
and other options can go in any slot of
the HP 16500B or HP 1 6501A. You should
generally begin installing cards starting
with the bottom-most slot an d wo rking
up.
Some measurement mo dul es hav e
multiple cards. A multiple-card module
must be installed into adjacent slots in
the same mainframe—that is, you
cannot install one card of the modul e
into the HP 16500B and the other int o
the HP 16501A.
Calibrate measurement modules after
installation
Some measurement mo dul es are
sensitive to temperature and voltage
variations between different
mainframes. Thus, when you install
such a module in the mainfram e, you
should calibrate it before usi ng it to
ensure maximum measurem ent
precision and accuracy .
See the Service Guide for each
measurement module for installation
and calibration procedures.
In This Book
Chapter 1, “Triggering,” shows you how to
v
1
2
File Management
3
Concepts
4
Solving Problems
5
Application Notes
6
Glossary
Index
This User’s Guide shows you how to use
the HP 16500B Logic Analysis System in
your everyday debugging work.
set up the analyzer to trigger on the
various kinds of events present in your
system. Advanced triggering capability
allows you to look at only the program
states of interest when you are solving a
particular problem.
Chapter 2, “Intermodule Measurements,”
shows you how to configure multiple
HP 16500 modules and external
measurement instruments into a single
measurement system in which modules
trigger each other.
Chapter 3, “File Management,” shows you
how to transfer files to and from the
HP 16500B using flexible disks, LAN
interfaces, and other interfaces.
Chapter 4,“Concepts,” gives you a brief
introduction to the ideas underlying the
trigger sequencer and the inverse
assembler, two important components of
sophisticated logic analysis.
Chapter 5, “Solving Problems,” shows you
how to diagnose and correct the more
common types of problems that might
occur while you are making a
measurement.
Chapter 6, “Application Notes,” lists the
various application notes that HP has
published regarding the HP 16500B and
other similar HP logic analyzers. These
Triggering
Intermodule Measure m ents
notes will give you more information about specific application problems and
how to solve them using an HP logic analyzer.
vi
See Also For general information on setup and operation of the HP 16500B, see the
HP 16500B /16501A Logic Analysis System User’s Reference.
For information on programming the HP 16500B using a computer controller
such as a workstation or personal computer, see the HP 16500B/16501A
Logic Analysis System Programmer’s Guide.
For information on logic analyzers, oscilloscopes, preprocessors, and other
logic analysis system options, see the User’s Reference manual for those
options.
Con tents
1Trig ger ing
To cap ture a trace of ac tiv ity as so ci ated with a write of known bad data to a
To ver ify that all stacks and reg is ters are re stored cor rectly bef ore ex it ing a
v
To store and time the exe cu tion of a sub rou tine 1–3
To trig ger on the nth it era tion of a loop 1–5
To trig ger on the nth re cur sive call of a re cur sive func tion 1–7
To trig ger on en try to a func tion 1–9
par ticu lar vari able 1–11
To trig ger on a loop that oc ca sion ally runs too long 1–12
sub rou tine 1–13
To trig ger af ter all status bus lines fin ish tran si tion ing 1–15
To find the nth oc cur rence of as sert ing a chip se lect line 1–16
To ver ify that the chip se lect line of a mem ory chip is strobed af ter the ad dress on the ad dress bus is sta ble 1–17
To trig ger when ex pected data does not ap pear on the data bus from a re mote de vice when re quested 1–18
To test mini mum and maxi mum pulse lim its 1–20
To de tect a hand shake vio la tion 1–22
To de tect bus con ten tion 1–23
Cross- Arming Trig ger Ex am ples 1–24
To ex am ine soft ware exe cu tion when a tim ing vio la tion oc curs 1–25
To look at con trol and status sig nals dur ing exe cu tion of a rou tine 1–26
2In ter mod ule Meas ure ments
In ter mod ule Meas ure ment Ex am ples 2–4
To set up a group run of mod ules within the HP 16500B 2–5
To start a group run of mod ules from an ex ter nal trig ger source 2–7
To start an ex ter nal in stru ment on com mand from a mod ule within the HP
16500 and 16501 main frame 2–9
To see the status of a mod ule within an in ter mod ule meas ure ment 2–11
o see time cor re la tion of each mod ule within an in ter mod ule meas ure ment
2–12
To use a tim ing ana lyzer to de tect a glitch 2–13
ii
To use two state ana lyz ers to moni tor the ac tiv ity of co proc es sors in a tar get
Contents
viii
To cap ture the wave form of a glitch 2–14
o cap ture state flow show ing how your tar get sys tem pro cesses an in ter rupt
2–15
Us ing stimulus- response to test a cir cuit 2–17
To use a state ana lyzer to trig ger tim ing analy sis of a count- down on a set of
data lines 2–19
sys tem 2–20
Spe cial dis plays 2–21
To in ter leave trace lists 2–22
To view trace lists and wave forms to gether on the same dis play 2–24
Skew Ad just ment 2–26
To ad just for mini mum skew be tween two mod ules in volved in an in ter mod -
ule meas ure ment 2–27
3 File Man age ment
Trans fer ring Files Us ing the Flexi ble Disk Drive 3–3
To save a meas ure ment con figu ra tion 3–4
To load a meas ure ment con figu ra tion 3–6
To save a trace list in AS CII for mat 3–8
To save a menu or meas ure ment as a graphic im age 3–10
To load sys tem soft ware 3–12
Us ing the HP 16500L LAN In ter face 3–13
To set up the HP 16500B 3–14
To trans fer data files from the HP 16500B sys tem to your com puter 3–16
To trans fer graph ics files from the HP 16500B sys tem to your com puter
3–18
4Con cepts
The Trig ger Se quencer 4–3
The In verse As sem bler 4–10
Con figu ra tion Trans la tion for Ana lyzer Mod ules 4–13
5 If You Have a Prob lem
Ana lyzer Prob lems 5–3
In ter mit tent data er rors 5–3
Un wanted trig gers 5–3
No Setup/Hold field on for mat screen 5–4
No ac tiv ity on ac tiv ity in di ca tors 5–4
Ca paci tive load ing 5–4
No trace list dis play 5–5
Contents
Pre proc es sor Prob lems 5–6
Tar get sys tem will not boot up 5–6
Slow clock 5–7
Er ratic trace meas ure ments 5–7
In verse As sem bler Prob lems 5–9
No in verse as sem bly or in cor rect in verse as sem bly 5–9
In verse as sem bler will not load or run 5–10
In ter mod ule Meas ure ment Prob lems 5–11
An event was n't cap tured by one of the mod ules 5–11
Mes sages 5–12
“De fault Cali bra tion Fac tors Loaded” (HP 16540, 16541, and 16542) 5–12
“. . . In verse As sem bler Not Found” 5–12
“Meas ure ment Ini tiali za tion Er ror” 5–13
“No Con figu ra tion File Loaded” 5–14
“Se lected File is In com pati ble” 5–14
“Slow or Miss ing Clock” 5–14
“State Clock Vio lates Over drive Speci fi ca tion” 5–15
“Time from Arm Greater Than 41.93 ms” 5–15
ix
Contents
x
“Wait ing for Trig ger” 5–15
6Ap pli ca tion Notes
1
Triggering
Triggering
1
2
As you begin to understand a problem in your system, you may realize
that certain conditions must occur before the problem occurs. You can
use sequential triggering to ensure that those conditions have
occurred before the analyzer recognizes its trigger and captures
information.
You set up sequential triggering as follows:
• Select the Trigger menu for the module you are using.
• In the Trigger menu, define terms and associated values to be used
when searching through the sequence.
• In the Trigger menu, select the number of the state sequence level
you want to modify, and enter the appropriate store qualification,
sequence-advance specification, and sequence-Else specification.
If you aren’t familiar with the trigger menus, try working through the
examples in the Logic Analyzer Training Kit manual, or refer to the
User’s Reference for your analyzer.
Triggering
To store and time the execution of a sub routi ne
To store and time the execution of a subroutine
Most systems software of any kind is composed of a hierarchy of functions
and procedures. During integration, testing, and performance evaluation, you
will want to look at specific procedures to verify that they are executing
correctly and that the implementation is efficient. The analyzer allows you to
do this by triggering on entry to the address range of the subroutine and
counting the elapsed time since the trigger state.
Select the state analyzer Trigger menu.
1
2 Set Count to Time.
Setting the Count to Time causes the state analyzer to store a time stamp for
each data point that is stored in trace memory. The trace list will show these
time stamps next to each state.
Define a range term, such as Range1, to represent the address range
3
of the subroutine of interest.
You may need to examine the structure of your code to help determine this. If
your subroutine calls are really procedure calls, then there is likely to be
some code at the beginning of the routine that adjusts the stack for local
variable allocation. This will precede the address of the first statement in the
procedure. If your subroutine has no local storage and is called by a jump or
branch, then the first statement will also be the entry address.
Under State Sequence Levels, enter the following sequence
4
specification:
While storing “no state” Trigger on “In_range1” 1 time
•
While storing “In_range1” Then find “Out_range1” 1 time
•
Store “no state”
•
Example Suppose you want to trigger on entry to a routine called MY_SUB. You can
define the address of MY_SUB in the Format menu, allowing you to reference
the symbol name when setting up the trace specification. Assume that
MY_SUB extends for 0A hex locations. You can set up the trigger sequencer
as shown in the display.
13
Triggering
To store and time the execution of a subr outi ne
1
4
Trigger Setup for Storing Execution of a Subroutine
For processors that do prefetching of instructions or have pipelin ed
architectures, you may want to add part or all of the depth of the pipeline to the
start address for In_Range 1 to en sure t hat t he anal yzer does not trigger on a
prefetched but unexecuted state.
Triggering
To trigger on the nth iteration of a loop
To trigger on the nth iteration of a loop
Traditional debugging requires print statements around the area of interest.
This is not possible in most embedded systems designs. But, the analyzer
allows you to view the system’s behavior when a particular event occurs.
Suppose that your system behaves incorrectly on the last iteration of a loop,
which, in this instance, happens to be the 10th iteration. You can use the
analyzer’s triggering capabilities to capture that iteration and subsequent
processor activity.
Select the state analyzer Trigger menu.
1
2 Define the terms LP_START and LP_END to represent the start and
end addresses of statements in the loop, and LP_EXIT to represent
the first statement executed after the loop terminates.
3 Under State Sequence Levels, enter the following sequence
specification:
While storing “no state” Find LP_END 1 time
•
While storing “anystate” TRIGGER on LP_START 9 times; Else on
•
“LP_EXIT” go to level 1
Store “anystate”
•
The above sequence specification has some advantages and a potential
problem. The advantages are that a pipelined processor won't trigger until it
has executed the loop 10 times. Requiring LP_END to be seen at least once
first ensures that the processor actually entered the loop; then, 9 more
iterations of LP_START is really the 10th iteration of the loop. Also, no
trigger occurs if the loop executes less than 10 times: the analyzer sees
LP_EXIT and restarts the trigger sequence. The potential problem is that
LP_EXIT may be too near LP_END and thus appear on the bus during a
prefetch. The analyzer will constantly restart the sequence and will never
trigger. The solution to this problem depends on the structure of your code.
You may need to experiment with different trigger sequences to find one that
captures only the data you wish to view.
15
Triggering
1
6
To trigger on the nth iteration of a loop
Trigger Setup for Triggering on the 10th Iteration of a Loop
Triggering
To trigger on the nth recursive call of a recurs ive function
To trigger on the nth recursive call of a recursive
function
1 Select the state analyzer Trigger menu.
2 Define the terms CALL_ADD, F_START, and F_END to represent the
called address of the recursive function, and the start and end
addresses of the function. Define F_EXIT to represent the address of
the first program statement executed after the original recursive call
has terminated.
Typically, CALL_ADD is the address of the code that sets up the activation
record on the stack, F_START is the address of the first statement in the
function, and F_END is the address of the last instruction of the function,
which does not necessarily correspond to the address of the last statement. If
the start of the function and the address called by recursive calls are the
same, or you are not interested in the function initialization code, you can use
F_START for both CALL_ADD and F_START.
Under State Sequence Levels, enter the following sequence
3
specification:
While storing “no state” Find “F_END” 1 time
•
While storing “anystate” Then find “F_START” 1 time
•
While storing “anystate” TRIGGER on “CALL_ADD” 20 times Else on
•
“F_EXIT” go to level 1
Store “anystate”
•
As with the trigger specification for “To trigger on the nth iteration of a loop,”
this specification helps avoid potential problems on pipelined processors by
requiring that the processor already be in the first recursive call before
advancing the sequencer. Depending on the exact code used for the calls, you
may need to experiment with different trigger sequences to find one that
captures only the data you wish to view.
17
Triggering
1
8
To trigger on the nth recursive call of a recurs ive function
Trigger ing on the 22nd Ca ll of a Recursive Function
Triggering
To trigger on entry to a function
To trigger on entry to a function
This sequence triggers on entry to a function only when it is called by one
particular function.
Select the state analyzer Trigger menu.
1
2 Define the terms F1_START and F1_END to represent the start and
end addresses of the calling function. Define F2_START to represent
the start address of the called function.
3 Under State Sequence Levels, enter the following sequence
specification:
While storing “anystate” Find “F1_START” 1 time
•
While storing “anystate” TRIGGER on “F2_START” 1 time Else on
•
“F1_END” go to level 1
Store “anystate”
•
This sequence specification assumes there is some conditional logic in
function F1 that chooses whether or not to call function F2. Thus, if F1 ends
without the analyzer having seen F2, the sequence restarts.
The specification also stores all execution inside function F1, whether or not
F2 was called. If you are interested only in the execution of F1, without the
code that led to its invocation, you can change the storage specification from
“anystate” to “nostate” for the second sequence term.
19
Triggering
1
10
To trigger on entry to a function
Trigger ing on Entry to a Function
Triggering
ith
w
To capture a trace of activity associ ated w
particular variable
To capture a trace of activity associated with a write of known bad data to a particular variable
The trigger specification ANDs the bad data on the data bus, write
transaction on the status bus, and address of the variable on the address bus.
Select the state analyzer Trigger menu.
1
2 Define the terms BAD_DATA, WRITE, and VAR_ADDR to represent
the bad data value, write status, and the address of the variable.
3 Under State Sequence Levels, enter the following sequence
specification:
While storing “anystate” TRIGGER on “BAD_DATA • WRITE •
•
VAR_ADDR” one time (you use the Combination trigger term to do this)
Store “anystate”
•
a write of kno
Capturing a Bad W rite to a Variable
111
Triggering
1
12
To trigger on a loop that occasionall y runs too long
To trigger on a loop that occasionally runs too long
This example assumes the loop normally executes in 14 µs.
1
Select the state analyzer Trigger menu.
2 Define terms LP_START, LP_END, and Timer1 to represent the start
and end addresses of the loop, and the normal duration of the loop.
You can make the sequence specification closer to the problem domain by
renaming Timer1 to LOOP_DUR.
Under State Sequence Levels, enter the following sequence
3
specification:
While storing “anystate” Find “LP_START” 1 time
•
While storing “anystate” TRIGGER on “LOOP_DUR 14.00 µs” 1 time Else
•
on “LP_END” go to level 1
You will need to start the LOOP_DUR timer (Timer1) upon entering
this state. You do this using the Timer Control field in the menu for
sequence level 2.
Store “anystate”
•
Triggering
d
be
To verify that all stacks and registers are restore
subroutine
Triggering on a Loop Overrun
To verify that all stacks and registers are restored correctly before exiting a subroutine
The exit code for a function will often contain instructions for deallocating
stack storage for local variables and restoring registers that were saved
during the function call. Some language implementations vary on these
points, with the calling function doing some of this work, so you may need to
adapt the procedure to suit your system.
Select the state analyzer Trigger menu.
1
2 Define terms SR_START and SR_END to represent the start and end
addresses of the subroutine.
3 Under State Sequence Levels, enter the following sequence
specification:
While storing “anystate” Find “SR_START” 1 time
•
correctly
While storing “anystate” Then find “SR_END” 1 time
•
While storing “anystate” TRIGGER on “≠ SR_START” 1 time Else on
•
“SR_START” go to level 2
113
Store “anystate”
Triggering
1
14
To verify that all stacks and registers are restored correctly before exit ing a
subroutine
•
Verifying Correct Return from a Function Call
Only three sequence term s are sh ow n on the display at a time. You can scroll
through the terms using the knob when the “State Sequence Levels” fiel d is
light blue.
Triggering
To trigger after all status bus lines f ini sh tran si tio ning
To trigger after all status bus lines finish transitioning
In some applications, you will want to trigger a measurement when a
particular pattern has become stable. For example, you might want to trigger
the analyzer when a microprocessor’s status bus has become stable during
the bus cycle.
Select the timing analyzer Trigger menu and define a term called
1
PATTERN to represent the value to be found on the label
representing the status bus lines.
2 Under Timing Sequence Levels, enter the following sequence
specification:
TRIGGER on “PATTERN” > 40 ns
115
Triggering
1
16
To find the nth occurrence of asserting a chip select line
To find the nth occurrence of asserting a chip select
line
1 Select the timing analyzer Trigger menu.
2 Define the glitch/edge1 term to represent the asserting transition on
the chip select line.
You can rename the Edge1 term to make it correspond more closely to the
problem domain, for example, to CHIP_SEL.
Under Timing Sequence Levels, enter the following sequence
3
specification:
TRIGGER on “CHIP_SEL” 10 times
Triggering on the 10th Assertion of a Chip Select Line
Triggering
hip i
b
To verify that the chip select line of a mem ory c
on the address bus is stable
To verify that the chip select line of a memory chip is strobed after the address on the address bus is stable
1 Select the timing analyzer Trigger menu.
2 Define a term called ADDRESS to represent the address in question
and the Edge1 term to represent the asserting transition on the chip
select line.
You can rename the Edge1 term to suit the problem, for example, to
MEM_SEL.
Under Timing Sequence Levels, enter the following sequence
3
specification:
Find “ADDRESS” > 80 ns
•
TRIGGER on “MEM_SEL” 1 time Else on “≠ ADDRESS” go to level 1
•
s stro
Verifying Setup Time for Memory Address
117
Triggering
1
18
To trigger when expected data does not appear on the data bus from a rem ote device when requested
To trigger when expected data does not appear on the
data bus from a remote device when requested
1 Select the timing analyzer Trigger menu.
2 Define a term called DATA to represent the expected data, the Edge1
term to represent the chip select line of the remote device, and the
Timer1 term to identify the time limit for receiving expected data.
You can rename the Edge1 and Timer1 terms to match the problem domain,
for example, to REM_SEL and ACK_TIME.
Under Timing Sequence Levels, enter the following sequence
3
specification:
Find “REM_SEL” 1 time
•
TRIGGER on “ACK_TIME > 16.00 µs” 1 time Else on “DATA” go to level 1
•
You will need to use the Timer Control field in the sequence setup for
sequence level 2 to start the ACK_TIME timer upon entering that sequence
level.
This sequence specification causes the analyzer to trigger when the data does
not occur in 16 µs or less. If it does occur within 16 µs, the sequence restarts.
Specifications of this type are useful in finding intermittent problems. You
can set up and run the trace, then cycle the system through temperature and
voltage variations, using automatic equipment if necessary. The failure will be
captured and saved for later review.
he d
b
device when requested
Triggering
To trigger when expected data does not appear on t
ata
Trigge ri n g W h en I/O D at a N o t Retu rned
119
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