AGERE OR3TP12-6PS240I, OR3TP12-6BA256I, OR3TP12-6BA256, OR3TP12-6PS240, OR3TP12-6BA352I Datasheet

...

Data Sheet March 2000

ORCA

OR3TP12 Field-Programmable System Chip (FPSC)

Embedded Master/Target PCI Interface

Introduction

Lucent Technologies Microelectronics Group has developed a solution for designers who need the many advantages of an FPGA-based design implementation coupled with the high bandwidth of the industry-standard PCI interface. The

ORCA

OR3TP12 FPSC provides a full-featured 33/50/66 MHz, 32-/64-bit PCI interface, fully designed and tested, in hardware, plus FPGA logic for user-programmable functions.

PCI Local Bus

PCI local bus, or simply, PCI bus, has become an industry-standard interface protocol for use in applications ranging from desktop PC busing to highbandwidth backplanes in networking and communications equipment. The PCI bus specification* provides for both 5 V and 3.3 V signaling environments. The PCI interface clock speed is specified in the range from dc to 66 MHz with detailed specifications at 33 MHz and 66 MHz as well as recommendations for 50 MHz operation. Data paths are defined as either 32-bit or 64-bit. These data path and frequency combinations allow for the peak data transfer rates described in Table 1.

Table 1. PCI Local Bus Data Rates

The PCI bus is electrically specified so that no glue logic is required to interface to the bus—PCI devices interface directly to the PCI bus. Other features include registers for device and subsystem identification and autoconfiguration, support for 64-bit addressing, and multimaster capability that allows any PCI bus Master access to any PCI bus Target.

PCI Bus Core Highlights

■

Implemented in an

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Series 3 base array, dis-

placing the bottom four rows of 18 columns.

■

Core is a well-tested ASIC model.

■

Fully compliant to Revision 2.1 of PCI Local Bus Specification (and designed for Revision 2.2).

* PCI Local Bus Specification Rev. 2.1, PCI SIG, June 1, 1995.

Clock

Frequency

(MHz)

Data Path

Width (bits)

Peak Data Rate

(Mbytes)

33 32 132 33 64 264 66 32 264 66 64 528

Table 2.

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PCI FPSC Solutions—Available FPGA Resources

* The embedded core and interface comprise approximately 85K standard-cell ASIC gates in addition to these usable gates. The usable

gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic,

clk

drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32

4 RAM (or

512 gates) per PFU.

Device Usable Gates

Number of

LUTs

Number of

Registers

Max User

RAM

Max User

I/Os

Array

Size

Number of

PFUs

OR3TP12 30K—60K 2016 2636 32K 187 14

18 252

Table of Contents

Contents Page Contents Page

ORCA

OR3TP12 FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

2 Lucent Technologies Inc.

Introduction............................................................... 1

PCI Local Bus........................................................ 1

PCI Bus Core Highlights........................................... 1

FPSC Highlights ....................................................... 6

Software Support............................. ...... ................... 6

Description................................................................ 7

What Is an FPSC?................................................. 7

FPSC Overview..................................................... 7

FPSC Gate Counting............................................. 7

FPGA/Embedded Core Interface .......................... 7

FPSC Design Kit ................................................... 8

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Foundry Development System................... 8

FPGA Logic Overview........................................... 8

PLC Logic.............................................................. 9

PIC Logic............................................................... 9

System Features............. ...... ....... ...... ................... 9

Routing......... ...... ............................................. ......10

Configuration...................................... ....... ...... ......10

More Series 3 Information.....................................10

OR3TP12 Overview..................................................10

Device Layout........................................................10

OR3TP12 PCI Bus Core Overview...........................10

PCI Bus Interface ..................................................10

Embedded Core Options/FPGA Configuration......12

PCI Bus Core Detailed Description ..........................13

PCI Bus Commands..............................................13

PCI Protocol Fundamentals ..................................16

PCI Bus Pin Information........................................18

Embedded Core/FPGA Interface

Signal Descriptions ............................................21

Embedded Core/FPGA Interface

Signal Locations.................................................29

Embedded Core Configuration Options ................31

Embedded Core/FPGA FIFO Interface

Operation Summary...........................................33

PCI Bus Core Master Controller

Detailed Description ..............................................34

FIFO Interface Overview .......................................34

Master Write Operation .........................................35

Master Read Operation.........................................43

PCI Bus Core Target Controller

Detailed Description ..............................................53

Target FIFO Interface ...... ...... ....... ...... ....... ...... ......53

Target Write Operation.............................. ...... ......53

Target Read Operation....................... ....... ...... ......65

Clocking Options at FPGA/Embedded

Core Boundary... ...... ..........................................80

Configuration Space of the PCI Bus Core.............82

FPSC Configuration ..............................................86

FPGA Configuration Target Controller

Data Format ..........................................................88

Using

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Foundry to Generate

Configuration RAM Data ....................................88

FPGA Configuration Data Frame ..........................88

Bit Stream Error Checking........................................90

FPGA Configuration Modes......................................90

Absolute Maximum Ratings......................................91

Recommended Operating Conditions ......................91

Electrical Characteristics ..........................................92

Timing Characteristics..............................................93

Description................................................................93

PFU Timing .......................................................... 94

PLC Timing........................................................... 94

SLIC Timing.......................................................... 94

PIO Timing .................. ....... ...... ....... ...... ....... ........ 94

Special Function Timing........................................94

Clock Timing.............................................................94

Configuration Timing .............................................94

Readback Timing ................................................. 94

Input/Output Buffer Measurement Conditions ..........99

Output Buffer Characteristics .................................100

Estimating Power Dissipation.................................101

Pin Information .......................................................102

......................................................................119

FPGA Maximum Junction Temperature..............119

Package Thermal Characteristics...........................120

Package Coplanarity ..............................................120

Package Parasitics.................................................120

Package Outline Diagrams.....................................122

Terms and Definitions .........................................122

240-Pin SQFP2 ...................................................123

256-Pin PBGA.....................................................124

352-Pin PBGA.....................................................125

Ordering Information...............................................126

Lucent Technologies Inc. 3

Data Sheet

ORCA

OR3TP12 FPSC

Marc h 2000 Embedded Master/Target PCI Interf ace

List of Figures

Figures Page Figures Page

Figure 1. OR3TP12 Array.......................................11

Figure 2.

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OR3TP12 PCI FPSC

Block Diagram .....................................................12

Figure 3. Master Write Single

(FIFO Interface, Dual-Port).................................. 39

Figure 4. Master Write Single

(FIFO Interface, Quad-Port).................................40

Figure 5. Master Write Single

(PCI Bus, 32-Bit)..................................................40

Figure 6. Master Write Burst

(FIFO Interface, Dual-Port).................................. 41

Figure 7. Master Write Burst

(FIFO Interface, Quad-Port).................................42

Figure 8. Master Write Burst

(PCI Bus, 32-Bit)..................................................42

Figure 9. Master Read Single

(FIFO Interface, Dual-Port).................................. 46

Figure 10. Master Read Single

(FIFO Interface, Quad-Port).................................47

Figure 11. Master Read Single

(PCI Bus, 32-Bit)..................................................47

Figure 12. Master Read Burst

(FIFO Interface, Dual-Port).................................. 49

Figure 13. Master Read Burst

(FIFO Interface, Quad-Port).................................50

Figure 14. Master Read Burst

(PCI Bus, 32-Bit)..................................................51

Figure 15. Target Configuration Write

(PCI Bus, 32-Bit)..................................................57

Figure 16. Target I/O Write, Nondelayed

(PCI Bus, 32-Bit)..................................................58

Figure 17. Target Memory Single Write

(PCI Bus, 32-Bit)..................................................59

Figure 18. Target Write Single

(FIFO Interface, Dual-Port).................................. 60

Figure 19. Target Write Single

(FIFO Interface, Quad-Port).................................61

Figure 20. Target Memory Write Burst

(PCI Bus, 32-Bit)..................................................62

Figure 21. Target Write Burst

(FIFO Interface, Dual-Port).................................. 63

Figure 22. Target Write Burst

(FIFO Interface, Quad-Port)...................................64

Figure 23. Target Configur ation Read

(PCI Bus, 32-Bit)....................................................68

Figure 24. Target I/O Read, Delayed

(PCI Bus, 32-Bit)....................................................69

Figure 25. Target I/O Read, Nondelayed

(PCI Bus, 32-Bit)....................................................70

Figure 26. Target Single Memory Read,

Delayed (PCI Bus, 32-Bit)......................................71

Figure 27. Target Read Single

(FIFO Interface, Dual-Port) ....................................72

Figure 28. Target Read Single

(FIFO Interface, Quad-Port)...................................73

Figure 29. Target Memory Read Single,

Nondelayed Transaction (PCI Bus, 32-Bit).............74

Figure 30. Target Burst Memory Read,

Delayed (PCI Bus, 32-Bit)......................................75

Figure 31. Target Read Burst

(FIFO Interface, Dual-Port) ....................................76

Figure 32. Target Read Burst

(FIFO Interface, Quad-Port)...................................77

Figure 33. Target Memory Burst Read,

Nondelayed (PCI Bus, 32-Bit)................................78

Figure 34. FPSC Block Diagram and

Clock Network........................................................81

Figure 35. Serial Configuration Data Format—

Autoincrement Mode..............................................89

Figure 36. Serial Configuration Data Format—

Explicit Mode .........................................................89

Figure 37. ac Test Loads..........................................99

Figure 38. Output Buffer Delays...............................99

Figure 39. Input Buffer Delays..................................99

Figure 40. Sinklim (T

= 25 °C, VDD = 3.3 V)..........100

Figure 41. Slewlim (T

= 25 °C, VDD = 3.3 V).........100

Figure 42. Fast (T

= 25 °C, VDD = 3.3 V) ..............100

Figure 43. Sinklim (T

= 125 °C, VDD = 3.0 V)........100

Figure 44. Slewlim (T

= 125 °C, VDD = 3.0 V).......100

Figure 45. Fast (T

= 125 °C, VDD = 3.0 V) ............100

Figure 46. Package Parasitics................................121

Tables Page Tables Page

ORCA

OR3TP12 FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

4 Lucent Technologies Inc.

List of Tables

Table 1. PCI Local Bus Data Rates ...........................1

Table 2.

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PCI FPSC Solutions—

Av ailable FPGA Resources..................................1

Table 3. PCI Bus Command Descriptions ...............13

Table 4. Timing Budgets..........................................17

Table 5. PCI Bus Pin Descriptions...........................18

Table 6. Embedded Core/FPGA

Interface Signals ................................................21

Table 7. OR3TP12 FPGA/PCI Core

Interface Signal Locations..................................29

Table 8. PCI Bus Core Options Settable

via FPGA Configuration RAM Bits ....................31

Table 9. Index to State Sequence Tables.................33

Table 10. Bit Definitions for Master

Command/Address Phase .................................35

Table 11. Holding Registers,

Examples of Typical Operation..................... ......36

Table 12. Master State Counter (MStateCntr)

Values and the Corresponding Bus Data...........36

Table 13. Dual-Port Master Writes...........................43

Table 14. Quad-Port Master Writes .........................43

Table 15. Dual-Port Master Read,

Specified Burst Length.......................................51

Table 16. Quad-Port Master Read,

Duplicate Burst Length.......................................52

Table 17. Quad-Port Master Read,

Specified Burst Length.......................................52

Table 18. Bit Destinations for Target

Command/Address Phase .................................54

Table 19. Target State Counter (TStateCntr)

Values and the Corresponding Bus Data...........55

Table 20. Dual-Port Target Write..............................64

Table 21. Quad-Port Target Write............................65

Table 22. Dual-Port Target Read .............................79

Table 23. Quad-Port Target Read............................79

Table 24. Configuration Space Layout.....................82

Table 25. Configuration Space Assignment.............83

Table 26. Configuration Frame

Format and Contents .........................................89

Table 27. Configuration Frame Size.........................90

Table 28. Configuration Modes................................90

Table 29. Absolute Maximum Ratings .....................91

Table 30. Recommend Operating Conditions..........91

Table 31. Electrical Characteristics..........................92

Table 32. Derating for Commercial Devices

(I/O Supply V

) ................................................93

Table 33. OR3TP12 PCI and FPGA Interface

Clock Operation Frequencies.............................95

Table 34. OR3TP12 FPGA to PCI, and PCI to

FPGA, Combinatorial Path Delays.....................95

Table 35. OR3TP12 FPGA Side Interface

Combinatorial Path Delay Signals......................96

Table 36. OR3TP12 Interbuf Delays........................96

Table 37. OR3TP12 FPGA Side Interface Clock to

Output Delays, pciclk Synchronous Signals.......97

Table 38. OR3TP12 FPGA Side Interface Clock to

Output Delays, fclk Synchronous Signals ..........97

Table 39. OR3TP12 FPGA Side Interface Input

Setup Delays, pciclk Synchronous Signals ..... ...98

Table 40. OR3TP12 FPGA Side Interface Input

Setup Delays, fclk Synchronous Signals............98

Table 41. FPGA Common-Function

Pin Descriptions ...............................................102

Table 42. OR3TP12 240-Pin SQFP2 Pinout..........105

Table 43. OR3TP12 256-Pin PBGA Pinout............109

Table 44. OR3TP12 352-Pin PBGA Pinout............113

Table 45.

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OR3TP12 Plastic Package

Thermal Guidelines..........................................120

Table 46.

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OR3TP12 Package Parasitics.....121

Table 47. Voltage Options......................................126

Table 48. Temperature Options..............................126

Table 49. Package Options....................................126

Table 50.

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Series 3+ Package Matrix...........126

Table 51. Embedded Core Type.............................126

Table 52. FPSC Base Array...................................126

Lucent Technologies Inc. 5

Data Sheet

ORCA

OR3TP12 FPSC

Marc h 2000 Embedded Master/Target PCI Interf ace

Lucent Technologies Inc.

PCI Bus Core Highlights

(continued)

■

Operates at PCI bus speeds up to 66 MHz.

■

Comprises two independent controllers for Master and Target.

■

Meets/exceeds all requirements for

PICMG

Hot

Swap Friendly silicon, Full Hot Swap model, per the

CompactPCI

Hot Swap Specification,

PICMG

2.1

R1.0.

■

PCI SIG Hot-Plug (R1.0) compliant.

■

Four internal FIFOs individually buffer both directions of both the Master and Target interfaces: — Both Master FIFOs are 64 bits wide by 32 bits

deep.

— Both Target FIFOs are 64 bits wide by 16 bits

deep.

■

Capable of no-wait-state, full-burst PCI transfers in either direction, on either the Master or Target interface. Dual 32-bit data paths extend into the FPGA logic, permitting full-bandwidth, simultaneous bidirectional data transfers of up to 264 Mbytes/s to be sustained indefinitely.

■

Can be configured to provide either two 32-bit buses (one in each direction) to be multiplexed between Master and Target, or four independent 16-bit buses.

■

Provides many hardware options in the PCI bus core that are set during FPGA logic configuration.

■

Operates within the requirements of the PCI 5 V and

3.3 V signaling environments, allowing the same device to be used in 5 V or 3.3 V PCI systems.

■

FPGA is reconfigurable via the PCI interface configuration space (as well as conventionally), allowing the FPGA to be field-updated to meet late-breaking requirements of emerging protocols.

■

Master: — Generates all defined command codes except

interrupt acknowledge and special cycle.

— Capable of acting as the system's configuration

agent by booting up with the Master logic enabled.

— Provides multiple options to increase PCI bus

bandwidth.

■

Target: — Responds legally to most command codes: inter-

rupt acknowledge, special cycle, and reserved commands ignored; memory read multiple and line handled as memory read; memory write and invalidate handled as memory write.

— Implements Target abort, disconnect, retry, and

wait cycles.

— Handles delayed transactions. — Handles fast back-to-back transactions. — Supports programmable latency timer control. — Method of handling wait-states is programmable

to allow tailoring to different Target data access latencies.

— Decodes at medium speed.

■

Supports dual-address cycles (both as Master and Target).

■

Supports all six base address registers (BARs), as either memory (32-bit or 64-bit) or I/O. Any legal page size can be independently specified for each BAR during FPGA configuration.

■

Provides versatile clocking capabilities with FPGA clocks sour ced from PCI bus clock or elsewhere. FIFO interface buffers asynchronous clock domains between the PCI interface and FPGA-based logic.

■

PCI interface timing: meets or exceeds 3 3 MHz, 50 MHz, and 66 MHz PCI requirements.

■

Standard 256-byte PCI configuration space: — Class code, revision ID. — Latency timer. — Cache line size. — Subsystem ID. — Subsystem vendor ID. — Maximum latency, minimum grant. — Interrupt line. — Hot plug/hot swap capability.

CompactPCI

and

PICMG

are registered trademarks of the PCI

Industrial Computer Manufacturers Group.

Parameter 33 MHz 50 MHz 66 MHz

Device clock = > out 11.0 ns 7.5 ns 6.0 ns Device setup time 7.0 ns 4.5 ns 3.0 ns Board prop. delay 10.0 ns 6.5 ns 5.0 ns Board clock skew 2.0 ns 1.5 ns 1.0 ns Total budget 30.0 ns 20.0 ns 15.0 ns

ORCA

OR3TP12 FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

6 Lucent Technologies Inc.

Lucent Technologies Inc.

PCI Bus Core Highlights

(continued)

■

Generates interr upt s on

intan

as directed by the

FPGA.

■

Provisions for 64-bit PCI bus capability in 352-pin PBGA package.

■

Automatically detects 5 V or 3.3 V PCI bus signaling environment and provides appropriate I/O signal clamping.

■

Pinout compatible with the

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PCI Master/Target

Customer Solution Core V2.0 for OR2C/TxxA or

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Series 3 FPGAs.

■

Ideally suited for such applications as: — PCI-based graphics/video/multimedia. — Bridges to ISA/EISA/MCA, LAN, SCSI, Ethernet,

ATM, or other bus architectures.

— High-bandwidth data transfer in proprietary sys-

tems.

FPSC Highlights

■

Implemented as an embedded core into the advanced Series 3+

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FPSC architecture.

■

Allows the user to integrate the core with up to 60K gates of programmable logic, all in one device, and provides up to 187 user I/O pins in addition to the PCI interface pins.

■

FPGA portion retains all of the features of the

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Series 3 FPGA architecture: — High-performance, cost-effective, 0.3 µm

4-level metal technology, with a migration plan to

0.25 µm technology.

— Twin-quad programmable function unit (PFU)

architecture with eight 16-bit look-up tables (LUTs) per PFU, organized in two nibbles for use in nibble- or byte-wide functions. Allows for mixed arithmetic and logic functions in a single PFU.

— Softwired LUTs (SWL) allow fast cascading of up

to three levels of LUT logic in a single PFU for up to 40% speed improvement (-5 speed grade).

— Supplemental logic and interconnect cell (SLIC)

provides 3-statable buffers, up to 10-bit decoder, and

PAL

*-like AND-OR-INVERT (AOI) in each

programmable logic cell (PLC).

— Up to three ExpressCLK inputs allow extremely

fast clocking of signals on- and off-chip plus access to internal general clock routing.

— Dual-use microprocessor interface (MPI) can be

used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA. Glueless interface to

i960

†

and

PowerPC

‡ processors with us er -con fig -

urable address space provided.

— Programmable clock manager (PCM) adjusts

clock phase and duty cycle for input clock rates from 5 MHz to 120 MHz. The PCM may be combined with FPGA logic to create complex functions, such as digital phase-locked loops (DPLL), frequency counters, and frequency synthesizers or clock doublers. Two PCMs are provided perdevice.

— True internal 3-state, bidirectional buses with sim-

ple control provided by the SLIC.

— 32

4 RAM per PFU, configurable as single or dual-port at >170 MHz (-5 speed). Create large, fast RAM/ROM blocks (128

8 in only eight

PFUs) using the SLIC decoders as bank drivers.

— Built-in boundary scan (

IEEE

1149.1 JTAG) and

TS_ALL testability function to 3-state all I/O pins.

■

High-speed on-chip interface provided between FPGA logic and embedded core to reduce bottlenecks typically found when interfacing off-chip.

■

Supported in three packages: 240-pin SQFP2, 256-pin PBGA, and 352-pin PBGA (64-bit PCI in 352-pin PBGA only).

Software Support

■

Supported by

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Foundry software and third-

party CAE tools for implementing

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Series 3+ devices and simulation/timing analysis with embedded PCI bus core.

■

PCI bus core configuration options and simulation models generated by FPSC configuration manager utility in

ORCA

FPSC Design Kit software.

■

Timing constraints provided for interface between PCI bus core and FPGA logic.

PAL

is a trademark of Advanced Micro Devices, Inc.

†

i960

is a registered trademark of Intel Corporation.

‡

PowerPC

is a registered trademark of International Business

Machines Corporation.

IEEE

is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

Lucent Technologies Inc. 7

Data Sheet

ORCA

OR3TP12 FPSC

Marc h 2000 Embedded Master/Target PCI Interf ace

Lucent Technologies Inc.

Description

What Is an FPSC?

FPSCs, or field-programmable system chips, are devices that combine field-programmable logic with ASIC or mask-programmed logic on a single device. FPSCs provide the time to market and flexibility of FPGAs, the design effort savings of using soft intellectual property (IP) cores, and the speed, design density, and economy of ASICs.

FPSC Overview

Lucent’s Series 3+ FPSCs are created from Series 3

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FPGAs. To create a Series 3+ FPSC, several rows of programmable logic cells (see FPGA Logic Overview section for FPGA logic details) are removed from a Series 3

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FPGA, and th e ar ea is re plac ed with an embedded logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 efficiency, none of the FPGA functionality is changed—all of the Series 3 FPGA capability is retained: MPI, PCMs, boundary scan, etc. The rows of programmable logic are replaced at the bottom of the device, allowing pins on the bottom and sides of the replaced rows to be used as I/O pins for the embedded core. The remainder of the device pins retain their FPGA functionality as do special function FPGA pins within the embedded core area.

The embedded cores can take many forms and generally come from Lucent Technologies ASIC libraries. Future offerings will allow customers to supply their own core functions for the creation of custom FPSCs.

FPSC Gate Counting

The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates. Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count is sometimes expressed in the same manner. Standard cell/ASIC gates are, however, 10 to 25 times more silicon area efficient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with a much larger gate count.

FPGA/Embedded Core Interface

The interface between the FPGA logic and the embedded core is designed to look like FPGA I/Os from the FPGA side, simplifying interface signal routing and providing a unified approach with general FPGA design. Effectively, the FPGA is designed as if signals were going off of the device to the embedded core, but the on-chip interface is much faster than going off-chip and requires less power. All of the delays for the interface are precharacterized and accounted for in the

ORCA

Foundry Development System. Clock spines also can pass across the FPGA/embed-

ded core boundary. This allows for f ast, low-ske w clocking between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the FPGA as a system.

For even greater system flexibility , FPGA configuration RAMs are available for use by the embedded core. This allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. Multiple embedded core configurations may be designed into a single device with user-programmable control over which configurations are implemented, as well as the capability to change core functionality simply by reconfiguring the device.

ORCA

OR3TP12 FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

8 Lucent Technologies Inc.

Lucent Technologies Inc.

Description

(continued)

FPSC Design Kit

Development is facilitated by an FPSC Design Kit which, together with

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Foundry and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an FPSC implementation. Included in the kit are the FPSC configuration manager,

V erilog

* and

VHDL

* simulation models, all necessary synthesis libraries, and complete online documentation. The kit's software couples with

ORCA

Foundry under the control of the

ORCA

Foundry Control Center (OFCC) , providing a seamless FPSC design environment. More information can be obtained by visiting the

ORCA

website or contacting a local sales office, both listed on the last page of this document.

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Foundry Development System

The

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Foundry Development System is used to process a design from a netlist to a configured FPSC. This system is used to map a design onto the

ORCA

architecture and then place and route it using

ORCA

Foundry’s timing-driven tools. The development system also includes interfaces to, and libraries for, other popular CAE tools for design entry, synthesis, simulation, and timing analysis.

The

ORCA

Foundry Development System interfaces to front-end design entry tools and provides the tools to produce a configured FPSC. In the design flow, the user defines the functionality of the FPGA portion of the FPSC and embedded core settings at design entry stage. The embedded core options determine the FPSC functionality.

Following design entry, the dev elopment system’s map , place, and route tools translate the netlist into a routed FPSC. A static timing analysis tool is provided to determine design speed, and a back-annotated netlist can be created to allow simulation. Simulation output files from

ORCA

Foundry are also compatible with many third-party analysis tools. Its bit stream generator is then used to generate the configuration data which is loaded into the FPSC’s internal configuration RAM. When using the FPSC configuration manager, the user selects options that affect the functionality of the FPSC. Combined with the front-end tools,

ORCA

Foundry produces configuration data that implements the various logic and routing options discussed in this data sheet.

FPGA Logic Overview

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Series 3 FPGA logic is a new generation of SRAM-based FPGA logic built on the successful Series 2 FPGA line from Lucent Technologies Microelectronics Group, with enhancements and innovations geared toward today’s high-speed designs and tomorrow’s systems on a single chip. Designed from the start to be synthesis friendly and to reduce place and route times while maintaining the compl ete routability of the

ORCA

Series 2 devices, the Series 3 more than doubles the logic available in each logic block and incorporates system-level features that can further reduce logic requirements and increase system speed.

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Series 3 devices contain many new patented enhancements and are offered in a variety of packages, speed grades, and temperature ranges.

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Series 3 FPGA logic consists of three basic elements: PLCs, programmable input/output cells (PICs), and system-level features. An array of PLCs is surrounded by PICs. Each PLC contains a PFU, a SLIC, local routing resourc es, and confi guration RAM . Most of the FPGA logic is performed in the PFU, but decoders,

PAL

-like functions, and 3-state buffering can be performed in the SLIC. The PICs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, and other functions on two output signals. Some of the system-level functions include the new microprocessor interface (

MPI

) and the

PCM

Verilog

and

VHDL

are registered trademarks of Cadance Design

Systems, Inc.

Lucent Technologies Inc. 9

Data Sheet

ORCA

OR3TP12 FPSC

Marc h 2000 Embedded Master/Target PCI Interf ace

Lucent Technologies Inc.

Description

(continued)

PLC Logic

Each PFU within a PLC contains eight 4-input (16-bit) LUTs, eight latches/flip-flops (FFs), and one additional flip-flop that may be used independently or with arithmetic functions.

The PFU is organized in a twin-quad fashion: two sets of four LUTs and FFs that can be controlled independently. LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 × 4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low . The FFs also have programmable clock polarity , clock enables, and local set/reset.

The SLIC is connected to PLC routing resources and to the outputs of the PFU. It contains 3-state, bidirectional buffers and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT AOI to perform

PAL

-like functions. The 3-state drivers in the SLIC and their direct connections to the PFU outputs make fast, true 3-state buses possible within the FPGA logic, reducing required routing and allowing for realworld system performance.

PIC Logic

The Series 3T PIC addresses the demand for everincreasing system clock speeds. Each PIC contains four programmable inputs/outputs (PIOs) and routing resources. On the input side, each PIO contains a fastcapture latch that is clocked by an

ExpressCLK

. This latch is followed by a latch/FF that is clocked by a system clock from the internal general clock routing. The combination provides for very low setup requirements and zero-hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer. Two input signals are available to the PLC array from each PIO, and the

ORCA

Series 2 capability to use any input

pin as a clock or other global input is maintained. On the output side of each PIO, two outputs from the

PLC array can be routed to each output flip-flop, and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals.

The output FF, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The I/O buffer associated with each pad is the same as the

ORCA

Series 3T buffer.

System Features

The Series 3 also provides system-level functionality by means of its dual-use microprocessor interface (MPI) and its innovative PCM. These functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today’s high-speed systems. Since these and all other Series 3T features are available in every Series 3+ FPSC, they can also interface to the embedded core providing for easier system integration.

ORCA

OR3TP12 FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

10 Lucent Technologies Inc.

Lucent Technologies Inc.

Description

(continued)

Routing

The abundant routing resources of

ORCA

Series 3 FPGA logic are organized to route signals individually or as buses with related control signals. Clocks are routed on a low-skew, high-speed distribution network and may be sourced from PLC logic, externally from any I/O pad, or from the very fast

ExpressCLK

pins. ExpressCLKs may be glitchlessly and independently enabled and disabled with a programmable control signal using the new

StopCLK

feature. The improved PIC routing resources are now similar to the patented intraPLC routing resources and provide great flexibility in moving signals to and from the PIOs. This flexibility translates into an improved capability to route designs at the required speeds when the I/O signals have been locked to specific pins.

Configuration

The FPGA logic’s functionality is determined by internal configuration RAM. The FPGA logic’s internal initialization/configuration circuitry loads the configuration data at powerup or under system control. The RAM is loaded by using one of several configuration sources, including serial EEPROM, the microprocessor interface, or the embedded function core.

More Series 3 Information

For more information on Series 3 FPGAs, please refer to the Series 3 FPGA data sheet, available on the

ORCA

worldwide website or by contacting Lucent Technologies as directed on the back of this data sheet.

OR3TP12 Overview

Device Layout

The OR3TP12 FPSC provides a PCI local bus core (with FIFOs) combined with FPGA logic. The device is based on a 3.3 V OR3T55 FPGA. The OR3T55 has an 18

18 array of PLCs. For the OR3TP12, the bottom four rows of PLCs in the array were replaced with the embedded PCI bus core. Figure 1 shows a schematic view of the OR3TP12. The upper portion of the device is a 14

18 array of PLCs surrounded on the left, top,

and right by programmable input/output cells (PICs). At

the bottom of the PLC array are interface cells connecting to the embedded core region. The embedded core region contains the PCI bus functionality of the device. It is surrounded on the left, bottom, and right by PCI bus dedicated I/Os as well as power and special function FPGA pins. Also shown are the interquad routing blocks (hIQ, vIQ) present in the Series 3T FPGA devices. System-level functions (located in the corners of the PLC array), routing resources, and configuration RAM are not shown in Figure 1.

OR3TP12 PCI Bus Core Overview

The OR3TP12 embedded core comprises a PCI bus interface with independent Master and Target controllers, FIFO memories, control logic for data buffering, a dual-/quad-port interface to the FPGA logic which performs data packing and multiplexing, and logic to support the embedded core and FPGA configuration. A detailed description of all of the features and functionality of the OR3TP12 embedded core is provided in the following sections.

PCI Bus Interface

The OR3TP12 PCI bus core is compliant to Revision

2.1 of the PCI Local Bus specification. It is capable of no-wait-state, full-burst operation at all of the rate/data width combinations described in Table 1 as well as at a 50 MHz specification that provides a speed increase over the 33 MHz specification and a larger bus loading capability than the 66 MHz specification. The OR3TP12 operates in either the 3.3 V or 5 V PCI signaling environment and is automatically configured for the appropriate environment by a PCI bus

vio

pin.

Independent Master and Target controllers are provided for use in systems requiring Master/Target or Target only operation. Six 32-bit base address registers (BARs) are provided for decoding the address space of the PCI device, and these six 32-bit registers can be combined in pairs to produce 64-bit BARs. Dualaddress cycles are supported when the PCI bus is either 32 or 64 bits wide. The BARs work in either the I/O or the memory space of the device and can be configured as prefetchable or nonprefetchable.

Lucent Technologies Inc. 11

Data Sheet

ORCA

OR3TP12 FPSC

Marc h 2000 Embedded Master/Target PCI Interf ace

Lucent Technologies Inc.

OR3TP12 Overview

(continued)

5-4489(F).b

Figure 1. OR3TP12 Array

PL9 PL8 PL7 PL6 PL5 PL4 PL3 PL2 PL1PL13 PL12 PL11

PR12PR11PR9PR8PR7PR6PR5PR4PR3PR2PR1 PR13 PR14PR10RMID

PT1 PT2 PT3 PT4 PT5 PT6 PT7 PT8 PT9 PT11 PT12

R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9 R1C10

R1C18R1C17R1C16R1C15R1C14R1C13R1C12R1C11

PT13 PT14 PT15 PT16 PT17 PT18

PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB11 PB12

PL14

PB13 PB14 PB15 PB16 PB17 PB18

PL10

PB10

PT10

R2C1 R2C2 R2C3 R2C4 R2C5 R2C6 R2C7 R2C8 R2C9 R2C10

R3C1 R3C2 R3C3 R3C4 R3C5 R3C6 R3C7 R3C8 R3C9 R3C10

R4C1 R4C2 R4C3 R4C4 R4C5 R4C6 R4C7 R4C8 R4C9 R4C10

R5C1 R5C2 R5C3 R5C4 R5C5 R5C6 R5C7 R5C8 R5C9 R5C10

R6C1 R6C2 R6C3 R6C4 R6C5 R6C6 R6C7 R6C8 R6C9 R6C10

R7C1 R7C2 R7C3 R7C4 R7C5 R7C6 R7C7 R7C8 R7C9 R7C10

R8C1 R8C2 R8C3 R8C4 R8C5 R8C6 R8C7 R8C8 R8C9 R8C10

R9C1 R9C2 R9C3 R9C4 R9C5 R9C6 R9C7 R9C8 R9C9 R9C10

R10C1 R10C2 R10C3 R10C4 R10C5 R10C6 R10C7 R10C8 R10C9 R10C10

R2C18R2C17R2C16R2C15R2C14R2C13R2C12R2C11

R3C18R3C17R13C16R3C15R3C14R3C13R3C12R3C11

R4C18R4C17R4C16R4C15R4C14R4C13R4C12R4C11

R5C18R5C17R5C16R5C15R5C14R5C13R5C12R5C11

R6C18R6C17R6C16R6C15R6C14R6C13R6C12R6C11

R7C18R7C17R7C16R7C15R7C14R7C13R7C12R7C11

R8C18R8C17R8C16R8C15R8C14R8C13R8C12R8C11

R9C18R9C17R9C16R9C15R9C14R9C13R9C12R9C11

R10C18R10C17R10C16R10C15R10C14R10C13R10C12R10C11

R14C18R14C17R14C16R14C15R14C14R14C13R14C12R14C11

R13C18R13C17R13C16R13C15R13C14R13C13R13C12R13C11

R12C18R12C17R12C16R12C15R12C14R12C13R12C12R12C11

R11C18R11C17R11C16R11C15R11C14R11C13R11C12R11C11

R14C10R14C9R14C8R14C7R14C6R14C5R14C4R14C3R14C2R14C1

R13C10R13C9R13C8R13C7R13C6R13C5R13C4R13C3R13C2R13C1

R12C10R12C9R12C8R12C7R12C6R12C5R12C4R12C3R12C2R12C1

R11C10R11C9R11C8R11C7R11C6R11C5R11C4R11C3R11C2R11C1

hIQ

LMID

EMBEDDED CORE AREA

BMIDT

TMID

vIQ

ORCA

OR3TP12 FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

12 Lucent Technologies Inc.

Lucent Technologies Inc.

OR3TP12 Overview

(continued)

Independent data paths exist for the Master and Target FIFO interface. This allows for separate operation of Master and Target functions, and the capability for a Master to transfer data to a Target on the same device.

In dual-port mode, the Master and Target FIFO interfaces share two unidirectional 32-bit data paths between the FIFOs and the FPGA logic. This provides for full-rate transfers in 32-bit PCI bus operation, when operating the FPGA application and PCI bus at the same frequency.

Quad-port mode provides two independent 16-bit data paths for each FIFO interface: one for read data and the other for write data. This mode allows for simultaneous operations on either the Master or Target controller.

Diagrams for dual-port and quad-port operation are shown in Figure 2.

Embedded Core Options/FPGA Configuration

In addition to the Series 3 FPGA configuration modes, the OR3TP12 can also be configured via the PCI bus. Configuration as discussed here covers two operations. There is configuration of the FPGA logic, and there is configuration of the options available in the embedded core. Both are accomplished through the FPGA configuration process. Readback of FPGA and PCI bus core options is also possible using the PCI bus or Series 3T FPGA readback modes. At powerup, the PCI bus core will be functional with a default PCI bus configuration space, as defined in the PCI bus 2.1 specification, even prior to an initial configuration of the FPGA logic.

Figure 2.

ORCA

OR3TP12 PCI FPSC Block Diagram

5-6368.b

5-6368.a

QUAD-PORT MODE

DUAL-PORT MODE

73 USER I/O PADS

OR3T SERIES FPGA

14 ROWS x 18 COLUMNS

USER

I/O PADS

USER

I/O PADS

PCI

MASTER/TARGET

INTERFACE

PCI

BUS

DATA CONTROL

AND

MULTIPLEXING

64-bit x

16 DEEP

FIFO

TARGET

64-bit x

16 DEEP

FIFO

TARGET

64-bit x

32 DEEP

FIFO

MASTER

64-bit x

32 DEEP

FIFO

MASTER

73 USER I/O PADS

OR3T SERIES FPGA

14 ROWS x 18 COLUMNS

USER

I/O PADS

USER

I/O PADS

PCI

MASTER/TARGET

INTERFACE

PCI

BUS

DATA CONTROL

AND

MULTIPLEXING

16 16

64-bit x

16 DEEP

FIFO

TARGET

64-bit x

16 DEEP

FIFO

TARGET

64-bit x

32 DEEP

FIFO

MASTER

64-bit x

32 DEEP

FIFO

MASTER

Lucent Technologies Inc. 13

Data Sheet

ORCA

OR3TP12 FPSC

Marc h 2000 Embedded Master/Target PCI Interf ace

Lucent Technologies Inc.

PCI Bus Core Detailed Description

The following sections describe the operation of the embedded PCI bus core interface.

PCI Bus Commands

The PCI bus core supports all commands required by the PCI Specification. The following table describes each command. Subsequent sections will describe the protocols in which the commands are used.

Table 3. PCI Bus Command Descriptions

Command

Code

(Binary)

Command

OR3TP12

Master

Generates

OR3TP12

Target

Accepts

Description

0000 Interrupt

Acknowledge

— — Only implemented by Master agents that interface to the

system CPU and as Target by agents that incorporate the

system interrupt controller. 0001 Special Cycle — — Target ignores, per PCI Specification Section 3.7.2. 0010 I/O Read √√

Target

: Single accesses only, with bursts disconnected after first data phase. Delayed Mode (

deltrn

= 0): Terminates the initial access with a retry, recording internally the PCI address and byte enables for processing by the FPGA application. Subsequent PCI accesses occurring before the FPGA application loads the Target read FIFO continues to result in retries. After the Target read FIFO is loaded by the FPGA application, the next read access that matches the stored parameters disconnects with the FPGA supplied data and the Target read logic is cleared. Nondelayed Mode (

deltrn

= 1,

trburst pendn

= 0): Accepted access inserts wait-states up to the initial latency count (16 or 32 clocks depending on the option selected in the FPSC configuration manager). During the wait-states, the FPGA application processes the read request and transfers data into the Target read FIFOs. If read data is transferred into the Target read FIFOs before the latency count expires, this read data is transferred to the PCI bus during initial request. If not, the PCI address, byte enables, and Target read data remain stored in the Target controller. The next access that matches the stored address and byte enables disconnects with the FPGA supplied data, and the Target read logic is cleared.

Master:

Single and burst operations are allowed.

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OR3TP12 FPSC Data Sheet

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14 Lucent Technologies Inc.

Lucent Technologies Inc.

0011 I/O Write √√

Target:

Single accesses only, with bursts disconnected after first data phase. Delayed_Mode (

deltrn

= 0): Terminates the initial access with a retry, recording internally the PCI address, byte enables, and write data for processing by the FPGA application. Subsequent PCI accesses occurring before the FPGA application accepts the Target write data will result in retries. After the Target write data is received by the FPGA application, the next I/O write access that matches the stored parameters (PCI address, byte enables, and write data) disconnects with data, and the Target write logic is cleared. Nondelayed Mode (

deltrn

= 1,

trburstpendn

= 0): Access posts write data into the Target write FIFOs and disconnects with data. The FPGA application then processes the I/O write request and transfer data from Target write FIFOs.

Master:

Single and burst operations are allowed. 0100 (reserved) — — Target ignores, per PCI Specification Section 3.1.1. 0101 (reserved) — — Target ignores, per PCI Specification Section 3.1.1. 0110 Memory Read √√

Target

: Single and burst accesses are allowed. The amount of data transferred will depend on either the external PCI Master terminating the read transaction, or the Target read FIFOs becoming empty. Delayed_Mode (

deltrn

= 0): Terminates the initial access with a retry, recording internally the PCI address and byte enables for processing by the FPGA application. Subsequent PCI accesses occurring before the FPGA application loads the Target read FIFO continues to result in retries. After the Target read FIFO is loaded by the FPGA application, the next read access that matches the stored parameters begins transfer of the FPGA supplied data. Nondelayed Mode (

deltrn

= 1,

trburstpendn

= 0): Accepted access inserts wait-states up to the initial latency count (16 or 32 clocks depending on the option selected in the FPSC configuration manager). During the wait-states, the FPGA application processes the read request and transfer data into the Target read FIFOs. If read data is transferred into the Target read FIFOs before the latency count expires, this read data is transferred to the PCI bus during initial request. If not, the PCI address, byte enables, and Target read data are stored in the Target controller. The next access that matches the stored address and byte enables begins transfer of the FPGA supplied data.

Master

: Single and burst operations are allowed.

Command

Code

(Binary)

Command

OR3TP12

Master

Generates

OR3TP12

Target

Accepts

Description

PCI Bus Core Detailed Description

(continued)

Table 3. PCI Bus Command Descriptions

(continued)

Lucent Technologies Inc. 15

Data Sheet

ORCA

OR3TP12 FPSC

Marc h 2000 Embedded Master/Target PCI Interf ace

Lucent Technologies Inc.

0111 Memory Write √√Fully implemented.

Target:

Writes are posted, bursting is allowed, and waitstates generation is controllable. When the Target write FIFO is full, the next data phase will be disconnected without data (

twburstpen dn

= 1), or up to eight wait-states can

be inserted (

twburstpendn

= 0). After the PCI bus transaction completes and the FPGA application empties the Target write FIFO, the Target write logic is cleared.

Master:

Single and burst operations are allowed. 1000 (reserved) — — Target ignores, per PCI Specification Section 3.1.1. 1001 (reserved) — — Target ignores, per PCI Specification Section 3.1.1. 1010 Configuration

Read

√√

Target:

Bursting is disallowed, and no wait-states are generated. Target disconnects with data on first data word. The FPGA portion of the device is not involved in configuration transactions.

Master:

Single and burst operations are allowed.

1011 Configuration

Write

√√Fully implemented.

Target:

Bursting is disallowed, and no wait-states are generated. Target disconnects with data on first data word. The FPGA portion of the device is not involved in configuration transactions.

Master:

Single and burst operations are allowed.

1100 Memory Read

Multiple

√√Fully implemented. Both the Master and the Target treat this

instruction the same as a memory read (4’b0110); the user’s FPGA logic is responsible for ensuring that the Master operation meets the special requirement that the read request ends on a cacheline boundary.

1101 Dual-Access

Cycle

√√Fully implemented. Per PCI Specification 2.1, Section

3.10.1, the PCI bus core (as a Master) automatically converts a 64-bit address to a 32-bit address if the upper 32 bits are all zeros.

1110 Memory Read

Line

√√Fully implemented. Both the Master and the Target treat this

instruction the same as a memory read (0110). The user’s FPGA logic is responsible for ensuring that the Master operation meets the special requirement that the read request continues to the next cacheline boundary.

1111 Memory Write

and Invalidate

√√Fully implemented. Both the Master and the Target treat this

instruction the same as a memory write (0111); the user’s FPGA logic is responsible for ensuring that the Master operation meets the special requirement that writes of complete cachelines, with all byte enables, are performed.

Command

Code

(Binary)

Command

OR3TP12

Master

Generates

OR3TP12

Target

Accepts

Description

PCI Bus Core Detailed Description

(continued)

Table 3. PCI Bus Command Descriptions

(continued)

ORCA

OR3TP12 FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

16 Lucent Technologies Inc.

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

PCI Protocol Fundamentals

Basic Transfer Control

The following paragraphs describe various aspects of the PCI protocol and the way they are handled by the PCI bus core.

Addressing.

The PCI Specification defines three types of address spaces. The first, configuration address space, is a physical address space that is intended as a means for powerup software to identify agents and allocate them address space. The second, I/O address space, is intended for mapping I/O control functions. The third, memory address spaces, is intended for bulk data transfer. It has features to facilitate this, such as special commands for cache implementation, large page sizes, and mechanisms for prefetching. The PCI bus core handles all three address space types as both a Master and a Target.

Byte Alignment.

On all write operations (configuration, I/O, and memory) for both the PCI bus core’s Master and Target functions, byte enables are fully implemented from/to the FPGA interface. Note, however, that even though the PCI bus core implements the ability to control byte enables for the memory write and invalidate instruction, the PCI Specification requires that this instruction assert all byte enables, and this is the FPGA application’s responsibility. On read operations, the utility of byte enables is more dubious since the data must be enroute from the PCI bus Target to Master, at the time that the corresponding byte enables are enroute from the PCI bus Master to Target (unless wait-states are inserted). The PCI bus core, therefore, does not implement full-byte enable control for Target reads, and limited for Master reads.

For the OR3TP12, byte enables on Master read burst operations must always be asserted; nonburst Master reads may manipulate the byte enables. Byte enables on Target read operations are ignored, in accordance with PCI Specification 2.1, Section 3.2.3. All Master burst read and write addresses must be aligned on 64-bit boundaries. Single read and write addresses can be aligned on 32-bit boundaries.

Device Selectio n (devseln)

The Target is responsible for decoding the address of a

aster’s request by asserting the PCI bus signal

devseln. devseln

may be asserted one, two, or three clocks after the address phrase of a transaction, corresponding to fast, medium, or slow decode, respectively. The PCI bus core’s Target is capable of performing a medium-speed decode response. The decode response speed has a significant impact on the overall latency and bandwidth of nonburst PCI transactions. Its impact decreases greatly for burst transactions, particularly for burst lengths of the size of the PCI bus core’s FIFOs.

Address/Data Stepping

Stepping is an optional feature added to the PCI Specification to accommodate agents whose bus drive capability is insufficient to handle large groups of signals changing state in one clock cycle. Continuous stepping allows weak drivers multiple cycles for signal transition. Discrete stepping partitions the bus into two or more groups of bits that transition on successive clock cycles. However, stepping exacts a heavy toll on performance, cutting maximum bandwidth by at least 50% and increasing latency. The PCI core is designed for maximum throughput with high-performance buffers, so stepping is unnecessary and not implemented. The wait cycle control, bit seven of the command register, is therefore hardwired to a 0.

Interrupt Acknowledge

The interrupt acknowledge command is a read by the system CPU implicitly addressed to the system interrupt controller. Other agents, including the PCI bus core, are not required to implement this instruction; the PCI bus core’s Master does not generate it, and its Target ignores it.

Arbitration Parking

The PCI Specification requires that all Master agents properly handle bus parking, which means that when that agent receives an asserted

gntn

without the agent

having asserted its

reqn

, the agent still must drive sig-

nal

par

and buses ad and

c_ben

to a stable value. The

PCI bus core meets this requirement.

Lucent Technologies Inc. 17

Data Sheet

ORCA

OR3TP12 FPSC

Marc h 2000 Embedded Master/Target PCI Interf ace

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

Parity

The PCI bus core implements all required and optional features, including the following:

■

Master generates parity on all addresses placed on the bus.

■

Sending agent generates parity on all data placed on the bus.

■

Target calculates parity on all addresses received from the bus.

■

Receiving agent calculates parity on all data received from the bus.

■

The detected parity error bit in the status register is set whenever an agent calculates corrupted parity.

■

The signal

perrn

is generated whenever an agent calculates corrupted data parity and the parity error response bit is set in the PCI command register.

■

The signal

serrn

is generated whenever an agent

calculates a corrupt address parity.

66 MHz Operation

The PCI bus core is fully compliant to PCI Specification requirements at all clock rates up to 66 MHz. All 33 MHz requirements are also met.

Timing Budget

The PCI bus core’s timing budget is summarized in Table 4. Note that the 66 MHz timing requirements only allow 5 ns for signal proagation (T

PROP

), as compared to 10 ns at 33 MHz. The effect of the reduction is to reduce also the number of agents that the bus can support, although the actual number is not specified in the PCI Specification and is dependent on the design of the hardware components. The four components of the timing budget are T

VAL

(valid output delay), T

PROP

(propagation time), T

(input setup time), and T

SKEW

(clock skew); of these, only T

VAL

and T

are controlled

by the PCI component, and T

PROP

and T

SKEW

are system parameters. Table 4 includes a third column (also shown in the PCI Specification); this column indicates the performance attainable if all 66 MHz requirements are met except T

PROP

= 10 ns, which is the 33 MHz value. In this case, the total budget increases from 15 ns (66 MHz) to 20 ns (50 MHz).

Table 4. Timing Budgets

64-Bit Addressing

The PCI bus core fully supports 64-bit addressing, whether or not the PCI bus core is configured to utilize the 64-bit data extension. When the PCI bus core is a 64-bit Target being addressed by 64-bit Master, the PCI bus core will decode the address one cycle faster so that dual-address operation will have no performance impact; see PCI Specification 2.1, Section 3.10.1 for details.

Section 3.10.1 of the PCI Specification 2.1 also states that a Master that supports 64-bit addressing must nevertheless generate requests utilizing a single address instead of a dual-address when the upper 32 bits are all zeros. This shortens the request time by one cycle when communicating with 32-bit Targets.

FIFO Memories and Control

The OR3TP12 embedded core contains four FIFO memories and supporting control logic. Two FIFOs are for the Master FIFO interface data and two for the Target FIFO interface data. These FIFOs are configured to operate in 64-bit mode and can also carry byte enable bits on a per-byte basis (e.g., a 64-bit FIFO actually carries 64 bits of data and eight byte enable bits for a total of 72 bits). All FIFOs have two relevant flags which extend into the FPGA logic for user application (e.g., a Target read FIFO on the FPGA side has Full and Full-4 flags extending into the FPGA logic). Clocking for the FPGA port of all FIFOs is flexible, with options for different clocks for the Master and Target FIFOs, all sourced by the FPGA logic.

Timing Element 33 MHz 50 MHz 66 MHz Unit

Cycle Time 30.0 20.0 15.0 ns Valid Output

Delay

11.0 7.5 6.0 ns

Propagation Time

10.0 6.5 5.0 ns

Input Setup Time 7.0 4.5 3.0 ns Clock Skew 2.0 1.5 1.0 ns

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OR3TP12 FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

18 Lucent Technologies Inc.

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

PCI Bus Pin Information

This section describes signals on the PCI bus interface and at the embedded core/FPGA interface. Some signal definitions change name and location based on the mode of operation. Modes of operation are described following the signal descriptions. PCI bus signal package pin locations can be found in Table 42 through .

Table 5. PCI Bus Pin Descriptions

Symbol I/O Description

System Pins

clk

Clock.

Provides timing for all transactions on the PCI bus and is an input to the

OR3TP12 device. All PCI signals, except

rstn

and

intan

, are sampled on the rising

edge of

clk

, and all other PCI bus timing parameters are defined with respect to this

edge.

clk

operates up to 66 MHz, and the minimum frequency is dc.

rstn

Reset.

An active-low signal used to reset the entire PCI bus.

rstn

is asynchronous

clk

. When asserted, all PCI output signals are 3-stated.

Address and Data Pins

ad[31:0]

I/O

Address and Data.

Multiplexed on the same PCI pins. A PCI bus transaction con-

sists of an address phase followed by one or more data phases. During data phases,

ad[7:0]

contain the least significant byte and

ad[31:24]

con-

tain the most significant byte. During memory commands, the

ad[31:2]

lines spec-

ify the address and

ad[1:0]

specify the type of bursting sequence to use. The table

below outlines the bursting sequence based on the values of

ad[1:0]

for the Target.

ad[1:0]

Bursting sequence. 00 Linear incrementing accepted by the Target. 01 Target disconnect after first transfer. 10 Target disconnect after first transfer. 11 Target disconnect after first transfer.

c_ben[3:0]

I/O

Bus Command and Byte Enables.

Active-low signals multiplexed on the same

PCI pins. During the address phase of a transaction,

c_ben[3:0]

define the bus

command. During the data phase,

c_ben[3:0]

are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data.

par

I/O

Parity.

Specifies even parity across

ad[31:0]

and

c_ben[3:0]. par

is stable and

valid one clock after the address phase. For data phases,

par

is stable and valid

one clock after

irdyn

is asserted on a write transaction or

trdyn

is asserted on a

read tran sa cti o n. Once

par

is valid, it remains valid until one clock after the comple-

tion of the current data phase. The Master drives

par

for address and write data

phases; the Target drives

par

for read data phases.

Interface Control Pins

framen

I/O

Cycle Frame.

An active-low signal driven by the current Master to indicate the

beginning and duration of an access.

framen

is asserted to indicate a bus transac-

tion is beginning. While

framen

is asserted, data transfers continue. When

framen

is deasserted, the transaction is in the final phase or has completed.

Lucent Technologies Inc. 19

Data Sheet

ORCA

OR3TP12 FPSC

Marc h 2000 Embedded Master/Target PCI Interf ace

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

Table 5. PCI Bus Pin Descriptions

(continued)

Symbol I/O Description

Interface Control Pins

(continued)

irdyn

I/O

Initiator Ready.

An active-low signal indicating the bus Master’s ability to complete

the current data phase of the transaction.

ird yn

is used in conjunction with

trdyn

. A

data phase is completed on any clock cycle during which both

irdyn

and

trdyn

are

asserted. During a write,

irdyn

indicates that valid data from the Master is present

on the

bus. During a read, it indicates that the Master is prepared to accept data.

Wait cycles are inserted until both

irdyn

and

trdyn

are asserted toge ther.

trdyn

I/O

Target Ready.

An active-low signal asserted to indicate the readiness of the Tar-

get’s agent to complete the current data phase of the transaction.

trdyn

is used in

conjunction with

irdyn

. A data phase is completed on any clock where both

trdyn

and

irdyn

are sampled active. During reads,

trdyn

indicates that valid d ata fr om th e

Target is present on t he ad bus. During write cycles,

trdyn

indicates that the T arget

is prepared to accept data.

stopn

I/O

Stop.

Indicates that the current Target is requesting the Master to stop the current

transaction.

idsel

Initialization Device Select.

Used as a chip select during PCI configuration read

and write transactions. Generally, the user ties

idsel

to one of the upper 24 address

lines,

ad[31:8]

devseln

I/O

Device Select.

An active-low signal indicating that a Target device on the bus has been selected. As an output, it indicates that the driving device has decoded its address as the Target of the current access.

Arbitration Pins (for Bus Master Only)

reqn

Request.

An active-low signal that indicates to the arbiter that the asserting agent desires use of the bus. In the OR3TP12, this signal is asserted when the OR3TP12 Master controller needs access to the PCI bus.

gntn

Grant.

An active-low signal that indicates to the OR3TP12 Master that access to

the PCI bus has been granted.

Error Reporting Pins

perrn

I/O

Parity Error.

An active-low signal for the reporting of data parity errors during all

PCI transact i ons except a sp e ci al cy cl e. The

perrn

pin is a sustained 3-state signal and must be driven active by the agent receiving data two clocks following the data when a data parity error is detected. The minimum duration of

perrn

is one clock for each data phase that a data parity error is detected. If sequential data phases each have a data parity error, the

perrn

signal will be asserted for more than a single

clock.

perrn

is driven high for one clock before being 3-stated.

perrn

is not

asserted until it has claimed the access by asserting

devseln

and completed a

data phase.

serrn

System Error.

An active-low signal pulsed by agents to report errors other than

data parity.

serrn

is sampled every

clk

edge, so any agent asserting

serrn

must

ensure it is valid for at least one clock period. For example,

serrn

can be asserted if an abort sequence is detected by the Master, or an address parity error is detected by the Target.

ORCA

OR3TP12 FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

20 Lucent Technologies Inc.

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

Table 5. PCI Bus Pin Descriptions

(continued)

Symbol I/O Description

Interrupt Pins

intan

PCI Interrupt.

The OR3TP12 asserts this active-low signal when it requests an

interrupt from the PCI compliant interrupt controller.

64-Bit Bus Extension Pins

ad[63:32]

I/O

64-Bit Address and Data.

These signals provide the upper 32 bits of address and data when in PCI 64-bit operation. During a 64-bit address phase (when using the dual-address command (DAC) and when

req64n

is asserted), the upper 32-bit

address bits are transferred. During a data phase, the data is valid when

req64n

and

ack64n

are both asserted. Otherwise, these bits are 3-stated.

c_ben[7:4]

I/O

Byte Enables.

These are the upper four, active-low, bus command and byte enables when in PCI 64-bit operation. During a 64-bit address phase (when using the dual-address command (DAC) and when

req64n

is asserted), the bus command is transferred. During a data phase, these bits are the active-low byte enables for data bits

ad[63:32]

. Otherwise, these bits are 3-stated.

req64n

I/O

Request 64-Bit Transfer.

This active-low signal is asserted by the current bus

Master to indicate that it desires to transfer data using 64 bits.

ack64n

I/O

Acknowledge 64-Bit Transfer.

Within its decoded address space (DEVSELN asserted), the Target drives this signal active-low indicating that it can perform 64-bit data transfers, in response to a received active-low

req64n. ack64n

has the

same timing as

devseln

in 32-bit transfers.

par64n

I/O

Upper Double-Word Parity

. The even parity bit that covers

ad[63:32]

and

c_ben[7:4]. par64n

is valid one clock after the initial address phase when

req64n

is asserted and the dual-address command (DAC) is indicated on

c_ben[3:0]

. It is

also valid the clock cycle after the second address phase of a DAC command when

req64n

is asserted. For data phases,

par64n

is stable and valid one clock after

irdyn

is asserted on a write transaction or

trdyn

is asserted on a read transaction.

Once

par64n

is valid, it remains valid until one clock after the completion of the cur-

rent data phase. On 64-bit PCI buses, the Master drives

par64n

for address and

write data phases; the Target drives

par64n

for read data phases.

Hot Swap Function Pins

enumn

Enumeration.

Active-low signal that notifies the system host that the card has been freshly inserted or is about to be extracted. The system host can then either install (for insertion) or deactivate (for extraction) the card’s software driver to adjust for the change in system configuration.

ledn

LED

. Active-low open-drain signal that drives a external blue LED, indicating that removal of the card is permitted. This signal is asserted low whenever the LED ON/ OFF (LOO) bit in the hot swap control and status register (HSSCR) is asserted high.

ejectsw

Eject Switch.

Active-high signal that indicates that the card’s ejector handle is unseated. This signals that the operator has freshly inserted the card, or will extract the card when the blue LED illuminates. If not used, tie high or low.

vio

PCI Bus Signaling Enviro nment Voltage.

This input indicates to the PCI bus core the signaling environment being employed on the PCI bus. The input is tied to the appropriate voltage supply (either 5.0 V or 3.3 V).

Lucent Technologies Inc. 21

Data Sheet

ORCA

OR3TP12 FPSC

Marc h 2000 Embedded Master/Target PCI Interf ace

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

Embedded Core/FPGA Interface Signal Descriptions

In Table 6, an input refers to a signal flowing into the FPGA logic (out of the embedded core) and an output refers to a signal flowing out of the FPGA logic (into the embedded core).

Table 6. Embedded Core/FPGA Interface Signals

Symbol I/O Description

Clock

Domain

Master General Signals

fpga_mbusyn

FPGA Master Is Busy.

The FPGA application asserts this active-low signal to

indicate to the Master to assert the

reqn

signal until

fpga_mbusyn

becomes inactive or the Target disconnects. This is helpful in PCI applications in which Master has multiple high-priority transactions to be performed. Once asserted, this signal needs to remain asserted for a minimum of two

pciclk

cycles.

pciclk

fpga_msyserror

FPGA Master Cycle Aborted by PCI Target.

The Master controller asserts this active-high signal as an indication that the current cycle to the PCI bus has been aborted.

fclk

mstatecntr[3:0]

Master State Counter.

Indicates the current state of the Master FIFO interface. Details of the Master FIFO interface can be found in the PCI Bus Core Master Controller Detailed Description section of this data sheet.

fclk

mfifoclrn

Master FIFO Clear.

This active-low signal is asynchronously asserted by the FPGA application to clear the Master address, read, and write FIFOs, along with

mstatecntr

. This signal does not reset the Master Controllers PCI state machine within the embedded core, and therefore it is not recommended to be used to terminate the current PCI transaction.

—

m_ready

Master Logic Ready.

This active-high signal indicates that the Master FIFO interface to the FPGA logic is ready. This signal will be inactive during PCI bus resets and Master FIFO clears.

fclk

Master FIFO Address and Command Control Signals

maenn

Master Command/Start Address/Read Burst Length Enable.

This is an active-low signal used to register the Master command word, read burst length, and PCI start address into the Master controller registers. The type of data transferred from the FPGA application will depend on the current state of

mstatecntr

and the interface mode (quad-port or dual-port). Further description is provided in the Command/Address Setup section (see page 35) of the PCI Bus Core Master Controller Detailed Description section.

fclk

ma_fulln

Master Address Register Full Flag.

This active-low signal indicates that the Master address register is full and no new PCI Master transactions can be accepted from the FPGA application. This flag is cleared when the Master transaction is completed on the PCI bus. For Master writes,

ma_fulln

is cleared when all write data has been transferred to the external Target. For Master reads,

ma_fulln

is cleared when all read data has been received from the external Target, although all read data may not have been transferred to the FPGA application.

fclk

* The source of the clock (

fclk1

fclk2

) for the FIFO interface (Master or Tar get) is selected in the FPSC configuration manager.

ORCA

OR3TP12 FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

22 Lucent Technologies Inc.

Lucent Technologies Inc.

Symbol I/O Description

Clock

Domain

Master Write Data FIFO Signals

mwlastcycn

Master Write Last Data Cycle.

This active-low signal has two functions:

It is asserted low to indicate that the current Master start address word is the

final portion being sent. It can be asserted prior to any address portion being transferred, indicating to use the previous stored address in the selected Master holding register.

maenn

must be asserted with

mwlastcycn

during

the final address word.

It is asserted low to indicate that the accompanying Master write data is the

final data for this operation.

mwdataenn

must be asserted with

mwlastcycn

during the final data word.

fclk

mwdataenn

Master Write FIFO Data Enable.

This active-low signal enables the registering

of data bus

mwdata

(quad-port mode) or

datafmfpga

(dual-port mode) during

Master write operations into the Master write data FIFOs.

mwdataenn

should

not be asserted when the Master write data FIFOs are full, or data may be lost.

fclk

mwpcihold

Master Write PCI Bus Hold.

For Master write transfers on the PCI bus, this

signal delays the start of the transfer (i.e.,

reqn

asserted) on the PCI bus, allowing the FPGA application to fill the Master write data FIFO. The transaction will begin when

mwpcihold

is deasserted or the Master write data FIFO

becomes full.

mwpcihold

should be deasserted before

mwlastcycn

asserted, and

needs to remain asserted for a minimum of two

pciclk

cycles.

pciclk

mw_afulln

Master Write Data FIFO Almost Full Flag.

This active-low signal indicates that only four more empty 64-bit locations remain in the Master write data FIFO.

fclk

mw_fulln

Master Write Data FIFO Full Flag.

This active-low signal indicates that the

Master write data FIFO is full.

mwdataenn

should never be asserted when

mw_fulln

is active.

fclk

* The source of the clock (

fclk1

fclk2

) for the FIFO interface (Master or Tar get) is selected in the FPSC configuration manager.

PCI Bus Core Detailed Description

(continued)

Table 6. Embedded Core/FPGA Interface Signals

(continued)

Lucent Technologies Inc. 23

Data Sheet

ORCA

OR3TP12 FPSC

Marc h 2000 Embedded Master/Target PCI Interf ace

Lucent Technologies Inc.

Symbol I/O Description

Clock

Domain

Master Write Data FIFO Signals

(continued)

mwdata[17:0]

(quad-port mode)

datafmfp-

gax[3:0]

datafmfpga[31:0]

(dual-port mode)

Depending on the OR3TP12 configuration, only one of these buses will be available to the FPGA application. For Master operations, these buses will carry the same information, but in different sizes and different bit lanes as summarized below:

Quad-Port Mode

Dual-Port Mode

a. Master Command.

Control data decoded by the Master Controller and

FIFO interface

Repeat Burst Length:

mwdata[17] datafmfpgax[3]

Dual-Address Indication:

mwdata[16] datafmfpgax[2]

Unused:

mwdata[15:13] datafmfpga[31:29]

Holding Reg. Selector:

mwdata[12] datafmfpga[28]

Master Rd. Byte Enables:

mwdata[11:4] datafmfpga[27:20]

Master Command Code:

mwdata[3:0] datafmfpga[19:16]

b. Master Start Address: 32- or 64-bit PCI start address.

Unused:

mwdata[17:16] datafmfpgax[3:0]

Address:

mwdata[15:0] datafmfpga[31:0]

c. Master Read Burst Count (18 bits): Number of 64-bit words.

Burst Length[17:16]:

mwdata[17:16] datafmfpgax[1:0]

Burst Length[15:0]:

mwdata[15:0] datafmfpga[15:0]

d. Master Write Data: Write data to PCI bus.

Write Enables:

mwdata[17:16] datafmfpgax[3:0]

Data:

mwdata[15:0] datafmfpga[31:0]

fclk

Master Read Data FIFO Signals

mrdataenn

Master Read FIFO Data Output Enable.

This active-low signal enables data

from the Master read data FIFOs onto bus

mrdata

(quad-port mode) or

datatofpga

(dual-port mode,

fifo_sel

= 0).

mrdataenn

must never be asserted

if the Master read FIFO is empty (

mr_emptyn

= 0)

fclk

mrdata[17:0]

(quad-port mode)

datatofpgax[3:0

datatofpga[31:0]

(dual-port mode)

Quad-Port Mode

Dual-Port Mode (

fifo_sel

= 0)

Master Read Data (16/32 bits)

Unused:

mrdata[17:16] datatofpgax[3:0]

Data:

mrdata[15:0] datatofpga[31:0]

fclk

mr_aemptyn

Master Read Data FIFO Almost Empty.

This active-low signal indicates that only four more 64-bit data locations are available to be read from the Master read data FIFO.

fclk

mr_emptyn

Master Read Data FIFO Empty.

This active-low signal indicates that the Mas-

ter read data FIFO is empty.

mrdataenn

should never be asserted when

mr_emptyn

is active.

fclk

mrlastcycn

Master Read Last Data Cycle.

This active-low signal is asserted to indicate that the accompanying Master read data is the final data word for this operation.

mrdataenn

must be asserted to receive

mrlastcycn

fclk

* The source of the clock (

fclk1

fclk2

) for the FIFO interface (Master or Tar get) is selected in the FPSC configuration manager.

PCI Bus Core Detailed Description

(continued)

Table 6. Embedded Core/FPGA Interface Signals

(continued)

ORCA

OR3TP12 FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

24 Lucent Technologies Inc.

Lucent Technologies Inc.

Symbol I/O Description

Clock

Domain

Master Read Data FIFO Signals

(continued)

mr_stopburstn

Stop Burst Reads.

This active-low signal is used by the FPGA application to terminate Master reads before the read burst length is reached. The Master must be transferring data on the PCI bus for this signal to be effective, and it is recommended to hold this signal until

ma_fulln

is deasserted. Once asserted,

this signal needs to remain asserted for a minimum of two

pciclk

cycles.

pciclk

Target General

tfifoclrn

Target FIFO Clear

. This active-low signal is asynchronously asserted by the FPGA application to clear the Target address, read, and write data FIFOs, along with

tstatecntr

. This signal does not reset the Target controller’s PCI state machine, and it is not recommended to be used to terminate the current PCI transaction.

—

t_ready

Target Logic Ready.

This active-high signal indicates that the Target FIFO interface to the FPGA application is ready. This signal will be inactive during PCI bus resets, Target FIFO clears, and up to 16 clocks after device configuration. This signal can be ignored when transferring data from the Target write data FIFO, if

pci_rstn

is inactive.

fclk

tstatecntr[3:0]

Target State Counter.

Indicates the current state of the Target FIFO interface. Details of the Target FIFO interface can be found in the PCI Bus Core Target Controller Detailed Description section of this data sheet.

fclk

disctimerexpn

Discard Timer Expired.

This active-low signal indicates that the discard timer has expired and the Target controller has deleted the current transaction which was stored as a delayed transaction. The FPGA application should discontinue processing of the current Target transaction. The discard timer is a 15-bit counter which starts its count when the Target transaction is stored.

fclk

t_abort

Target Abort.

This signal is asserted by the FPGA application to abort future PCI Target and Configuration cycles. Once asserted, this signal needs to remain asserted for a minimum of two

pciclk

cycles.

pciclk

t_retryn

Target Retry.

This active-low signal is asserted by an FPGA application to retry future PCI Target and Configuration cycles. Once asserted, this signal needs to remain asserted for a minimum of two

pciclk

cycles.

pciclk

deltrn

Target Read Delayed Transaction

. Active-low signal which indicates to processes certain future PCI Target accesses as delayed transactions. This applies to memory reads, I/O reads, and I/O writes. Further description is provided in Table 3 for each PCI operation.

deltrn

must be asserted if

trburst-

pendn

is deasserted. Once asserted, this signal needs to remain asserted for

a minimum of two

pciclk

cycles and should not be changed while a current Tar-

get transaction is in progress.

pciclk

PCI Bus Core Detailed Description

(continued)

Table 6. Embedded Core/FPGA Interface Signals

(continued)

* The source of the clock (

fclk1

fclk2

) for the FIFO interface (Master or Tar get) is selected in the FPSC configuration manager.

Lucent Technologies Inc. 25

Data Sheet

ORCA

OR3TP12 FPSC

Marc h 2000 Embedded Master/Target PCI Interf ace

Lucent Technologies Inc.

Target FIFO Address and Command Register Control Signals

treqn

Target Request from PCI.

The Target asserts

treqn

as an indication to the FPGA application that a PCI Target operation has been decoded and is pending.

treqn

signal will continue to be active until all data has been transferred between the FPGA application and the Target FIFO interface. The FPGA application should use

treqn

to qualify valid data on following buses:

tcmd, bar

twdata

(quad-port mode), and

datatofpga/datatofpgax

(dual-port mode)

fclk

taenn

Target Address Output Enable.

This active-low signal enables the PCI start address to be transferred from the Target address FIFO to the FPGA application, on either bus

twdata

(quad-port mode) or

datatofpga

(dual-port mode,

fifo_sel

= 1).

treqn

will be asserted to indicate a valid PCI Target address

exists.

fclk

tcmd[3:0]

Target Command Code.

This bus provides the PCI command code for a

pending Target operation, and is valid when

treqn

is asserted active-low.

—

bar[2:0]

Base Address Register Number

. This bus indicates which of the six BARs

decoded the PCI address for the current Target operation, and is valid when

treqn

is active-low. For 64-bit addresses, the BARs pairs will be indicated by

numbers 0, 2, and 4.

—

Target Write Data FIFO Signals

twdataenn

Target Write FIFO Data Enable.

This active-low signal enables data from the

Target write data FIFO onto bus

twdata

(quad-port mode) or

datatofpga

(dual-

port mode,

fifo_sel

= 1).

twdataenn

should not be asserted whenever the Tar-

get write data FIFO is empty (

tw_emptyn

= 0).

fclk

twdata[17:0]

(quad-port mode)

datatofpgax[3:0]

datatofpga[31:0]

(dual-port mode)

Depending on the OR3TP12 configuration, only one of these buses will be available to the FPGA application. For Target operations, these buses will carry the same information, but in different sizes and bit lanes as summarized below:

Quad-Port Mode

Dual-Port Mode (

fifo_sel

= 1)

a. Target Start Address: 32- or 64-bit PCI start address.

Address:

twdata[15:0] datatofpga[31:0]

Dual-Address Indication:

twdata[16] datatofpgax[0]

Burst Indication:

twdata[17] datatofpgax[1]

Unused:

datatofpgax[3:2]

b. Target Write Data: Write data from PCI bus.

Data:

twdata[15:0] datatofpga[31:0]

Write Enables:

twdata[17:16] datatofpgax[3:0]

fclk

tw_aemptyn

Target Write FIFO Almost Empty.

This active-low signal indicates that only four more 64-bit data locations are available to be read from the Target write data FIFO.

fclk

tw_emptyn

Target Write FIFO Empty.

This active-low signal indicates that the Target write

FIFO is empty.

twdataenn

should never be asserted if

tw_emptyn

is asserted.

fclk

* The source of the clock (

fclk1

fclk2

) for the FIFO interface (Master or Tar get) is selected in the FPSC configuration manager.

PCI Bus Core Detailed Description

(continued)

Table 6. Embedded Core/FPGA Interface Signals

(continued)

ORCA

OR3TP12 FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

26 Lucent Technologies Inc.

Lucent Technologies Inc.

Symbol I/O Description

Clock

Domain

Target Write Data FIFO Signals

(continued)

twlastcycn

Targ et Write Last Data Cycle.

This active-low signal has two functions:

a. Indicates that the current Target start address data on

twdata

(quad-port)

datatofpga

(dual-port with

fifo_sel

= 1) is the final transfer of the

address phase.

taenn

is required to be asserted to receive

twlastcycn

b. Indicates that the current Target write data on

twdata

(quad-por t) or

datatofpga

(dual-port with

fifo_sel

= 1) is the final transfer of the data phase. For single data transfers, it will be asserted on the only word of the transfer, whereas on bursts, if will be asserted only on the final word.

twdataenn

is required to be asserted to receive

twlastcycn

fclk

twburstpendn

Burst Write Data Control.

This active-low signal indicates to the Target controller that a write transaction should not be disconnected immediately when the Target write data FIFO is full, but allow up to eight wait-states to be inserted. When desasserted, the Target controller will disconnect when the write FIFOs are full. Once asserted, this signal needs to remain asserted for a minimum of two

pciclk

cycles.

pciclk

Target Read Data FIFO Signals

trdataenn

Target Read FIFO Data Enable.

This active-low signal enables the register-

ing of bus

trdata

(quad-port mode) or

datafmfpga

(dual-port mode) into the

Target read data FIFO.

trdataenn

should not be asserted when the Target

read data FIFO is full (

tr_fulln

= 0).

fclk

trdata[17:0]

(quad-port mode)

datafmfpga[31:0]

datafmfpgax[3:0]

(dual-port mode)

Target Read Data: Read data to the PCI bus.

Data:

trdata[15:0] datafmfpga[31:0]

Unused:

trdata[17:16] datafmfpgax[3:0]

fclk

tr_afulln

Target Read FIFO Almost Full.

This active-low signal indicates that the Tar-

get read data FIFO has only four more 64-bit empty locations available.

fclk

tr_fulln

Target Read FIFO Full.

This active-low signal indicates that the Target read

data FIFO is full and that no more data can be accepted.

trdataenn

must not

be asserted when

tr_fulln

is asserted.

fclk

trlastcycn

Target Read Last Data Cycle

. This active-low signal is asserted to indicate the final cycle of the read data phase. During read bursts, more than one clock is usually required to transfer a complete data phase; therefore, this signal will be asserted only on the last data word. During a read burst,

trlast-

cycn

may remain inactive for longer than it is required by the external Master, leading to transfer of excess data into the Target read data FIFO. All excess data will be cleared when the external Master terminates the transaction.

trlastcycn

will only be active only with an asserted

trdataenn

fclk

* The source of the clock (

fclk1

fclk2

) for the FIFO interface (Master or Tar get) is selected in the FPSC configuration manager.

PCI Bus Core Detailed Description

(continued)

Table 6. Embedded Core/FPGA Interface Signals

(continued)

Lucent Technologies Inc. 27

Data Sheet

ORCA

OR3TP12 FPSC

Marc h 2000 Embedded Master/Target PCI Interf ace

Lucent Technologies Inc.

Symbol I/O Description

Clock

Domain

Target Read Data FIFO Signals

(continued)

trpcihold

Target Read PCI Bus Hold

. For read transfers to the PCI bus, this signal

delays the start of the data transfer (i.e.,

trdyn

assertion). The data transfer

will begin when

trpcihold

is deasserted or the Target read data FIFO becomes full. Once asserted, this signal needs to remain asserted for a minimum of two

pciclk

cycles.

pciclk

trburstpendn

Target Read Burst Control.

This active-low signal directs the Target to insert up to eight wait-states between subsequent read data phases before disconnect. When deasserted, the Target will disconnect immediately when the Target read data FIFO becomes empty. If

deltrn

is inactive,

trburst-

pendn

must be driven active. Once asserted, this signal needs to remain

asserted for a minimum of two

pciclk

cycles.

pciclk

Miscellaneous Signals

pci_intan

PCI Interrupt Request

. This active-low signal is used to generate a PCI bus

interrupt and is forwarded by the embedded core as

intan

onto the PCI bus.

Once asserted, this signal needs to remain asserted for a minimum of two

pciclk

cycles.

—

fclk1 fclk2

O O

FPGA Clock 1 and 2

. Clocks used by the Master and Target FIFO interface

logic.

fclk1

and

fclk2

need to be activated for use by the Master and Target in the FPSC configuration manager. In dual-port mode, only one of these clocks may be active, while the other should be tied low.

—

pciclk

PCI Clock. pciclk

is a buffered version of

clk

for use by the FPGA applica-

tion as the main clock, or for control signals which are in the

pciclk

domain

(such as

t_retryn, mr_stopburstn

, etc.). The FPGA may route

pciclk

to any

of the FPGA reso urces,

fclk1

fclk2

, programmable clock managers, etc.

—

pci_rstn

PCI Reset

. This active-low signal indicates that a PCI bus reset was received

from the PCI bus (

rstn

—

fpga_syserror

System Error

. This pin is used by the FPGA to generate a system error on

the PCI bus. This is passed to the PCI bus as

serrn

. Once asserted, this sig-

nal needs to remain asserted for a minimum of two

pciclk

cycles.

pciclk

* The source of the clock (

fclk1

fclk2

) for the FIFO interface (Master or Tar get) is selected in the FPSC configuration manager.

PCI Bus Core Detailed Description

(continued)

Table 6. Embedded Core/FPGA Interface Signals

(continued)

ORCA

OR3TP12 FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

28 Lucent Technologies Inc.

Lucent Technologies Inc.

Symbol I/O Description

Clock

Domain

Miscellaneous Signals

(continued)

cfgshiftenn

pci_cfg_stat

PCI Error Status Control cfgshiftenn

is an active-low signal that MUXes the output of the PCI device

status register (PCI Specification 2.1: Section 6.2.3) onto signal

pci_cfg_stat

cfgshiftenn

= 1:

pci_cfg_stat

outputs the wired-OR of all status bits below, after being masked by options in the FPSC configuration manager.

cfgshiftenn

= 0:

pci_cfg_stat

outputs each status bit below, shifted one at a time on successive

pciclk

rising edges.

The shift register is reset when

cfgshiftenn

= 1.

Device Status Register bits:

Detected Parity Error, Signaled System Error, Received Master Abort, Received Target Abort, Signaled Target Abort, Master Data Parity Error.

pciclk

pci_64bit

PCI 64-Bit Bus Indication.

This active-high signal indicates that the embedded core detected that it is configured as a 64-bit agent on the PCI bus. This is the result of detecting PCI signal

req64n

as active-low on the rising edge

of PCI signal

rstn

. Note that this does not imply that any particular transaction is 64-bit, since each transaction is individually negotiated using PCI signals

req64n

and

ack64n

. When asserted, all data transfers across the

Master and Target FIFO interface will imply 64-bit data phases.

—

fifo_sel

FIFO Select.

A MUX control signal that is valid in the dual-port mode to

select either Master read data (

fifo_sel

= 0) or Target address/write data

(

fifo_sel

= 1) on the

datatofpga

and

datatofpgax

bus. For quad-port mode,

this signal can be tied to high.

—

PCI Bus Core Detailed Description

(continued)

Table 6. Embedded Core/FPGA Interface Signals

(continued)

* The source of the clock (

fclk1

fclk2

) for the FIFO interface (Master or Target) is selected in the FPSC configuration manager.

Lucent Technologies Inc. 29

Data Sheet

ORCA

OR3TP12 FPSC

Marc h 2000 Embedded Master/Target PCI Interf ace

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

Embedded Core/FPGA Interface Signal Locations

Table 7 lists the physical locations of all signals on the embedded core/FPGA interface. Separate names are provided for dual-port and quad-port bus signals, since their functionality is port mode dependent.

Table 7. OR3TP12 FPGA/PCI Core Interface Signal Locations

Embedded Core /F PGA

Interface Site

FPGA Input Signal FPGA Output Signal

Dual-Port Mode Quad-Port Mode Dual-Port Mode Quad-Port Mode

PB1A

disctimerexpn cfgshiftenn

PB1B

t_ready twburstpendn

PB1C

pci_cfg_stat

(unused)

PB1D

treqn

(unused)

PB2A

datatofpga0 twdata0 datafmfpga0 trdata0

PB2B

datatofpga1 twdata1 datafmfpga1 trdata1

PB2C

datatofpga2 twdata2 datafmfpga2 trdata2

PB2D

datatofpga3 twdata3 datafmfpga3 trdata3

PB3A

datatofpga4 twdata4 datafmfpga4 trdata4

PB3B

datatofpga5 twdata5 datafmfpga5 trdata5

PB3C

datatofpga6 twdata6 datafmfpga6 trdata6

PB3D

datatofpga7 twdata7 datafmfpga7 trdata7

PB4A

datatofpga8 twdata8 datafmfpga8 trdata8

PB4B

datatofpga9 twdata9 datafmfpga9 trdata9

PB4C

datatofpga10 twdata10 datafmfpga10 trdata10

PB4D

datatofpga11 twdata11 datafmfpga11 trdata11

PB5A

datatofpga12 twdata12 datafmfpga12 trdata12

PB5B

datatofpga13 twdata13 datafmfpga13 trdata13

PB5C

datatofpga14 twdata14 datafmfpga14 trdata14

PB5D

datatofpga15 twdata15 datafmfpga15 trdata15

CKTOASB5 (unused)

fclk2

PB6A

datatofpgax

twdata

datafmfpgax

trdata

PB6B

datatofpgax

twdata

datafmfpgax

trdata

PB6C

twlastcycn twdataenn

PB6D

trlastcycn trdataenn

PB7A

bar

fpga_syserror

PB7B

bar

t_abort

PB7C

bar

t_retryn

PB7D

pciclk taenn

PB8A

tstatecntr

0 (unused)

PB8B

tstatecntr

1 (unused)

PB8C

tstatecntr

2 (unused)

PB8D

tstatecntr

3 (unused)

ORCA

OR3TP12 FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

30 Lucent Technologies Inc.

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

Table 7. OR3TP12 FPGA/PCI Core Interface Signal Locations

(continued)

Embedded Core/FPGA

Interface Site

FPGA Input Signal FPGA Output Signal

Dual-Port Mode Quad-Port Mode Dual-Port Mode Quad-Port Mode

PB9A

tw_emptyn trburstpendn

PB9B

tw_aemptyn tfifoclrn

PB9C

tr_fulln trpcihold

PB9D

tr_afulln pci_intan

PB10A

tcmd0 mr_stopburstn

PB10B

tcmd1 mfifoclrn

PB10C

tcmd2 mwpcihold

PB10D

tcmd3 mwlastcycn

PB11A

ma_fulln

(unused)

PB11B

fpga_msyserror

(unused)

PB11C

mrlastcycn

(unused)

PB11D

m_ready

(unused)

PB12A

mw_fulln maenn

PB12B

mw_afulln fifo_sel

PB12C

mr_emptyn fpga_mbusyn

PB12D

mr_aemptynmrdata deltrn

PB13A

pci_rstn mrdataenn

PB13B

pci_64bit mwdataenn

PB13C

datatofpgax2 mrdata16 datafmfpgax2 mwdata16

PB13D

datatofpgax3 mrdata17 datafmfpgax3 mwdata17

CKTOASB13 (unused)

fclk1

PB14A

datatofpga16 mrdata0 datafmfpga16 mwdata0

PB14B

datatofpga17 mrdata1 datafmfpga17 mwdata1

PB14C

datatofpga18 mrdata2 datafmfpga18 mwdata2

PB14D

datatofpga19 mrdata3 datafmfpga19 mwdata3

PB15A

datatofpga20 mrdata4 datafmfpga20 mwdata4

PB15B

datatofpga21 mrdata5 datafmfpga21 mwdata5

PB15C

datatofpga22 mrdata6 datafmfpga22 mwdata6

PB15D

datatofpga23 mrdata7 datafmfpga23 mwdata7

PB16A

datatofpga24 mrdata8 datafmfpga24 mwdata8

PB16B

datatofpga25 mrdata9 datafmfpga25 mwdata9

PB16C

datatofpga26 mrdata10 datafmfpga26 mwdata10

PB16D

datatofpga27 mrdata11 datafmfpga27 mwdata11

PB17A

datatofpga28 mrdata12 datafmfpga28 mwdata12

PB17B

datatofpga29 mrdata13 datafmfpga29 mwdata13

PB17C

datatofpga30 mrdata14 datafmfpga30 mwdata14

PB17D

datatofpga31 mrdata15 datafmfpga31 mwdata15

PB18A

mstatecntr0

(unused)

PB18B

mstatecntr1

(unused)

PB18C

mstatecntr2

(unused)

PB18D

mstatecntr3

(unused)

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