AGERE OR3LP26BA352C, OR3LP26BM680I, OR3LP26BM680C, OR3LP26BA352I Datasheet

Data Sheet March 2000

ORCA

OR3LP26B Field-Programmable System Chip (FPSC

)

Embedded Master/Target PCI Interface

Introduction

Lucent Technologies Microelectronics Group has developed a solution for designers who need the many advantages of an FPGA-based design implementation, coupled with the high bandwidth of an industry-standard PCI interface. The

ORCA

OR3LP26B (a member of the Series 3+ FPSC family) provides a full-featured 33/50/66 MHz, 32-/64-bit PCI interface, fully designed and tested, in hardware, plus FPGA logic for user-programmable functions.

PCI Bus Core Highlights

■

Implemented in an

ORCA

Series 3 OR3L125B base array, displacing the bottom ten rows of 28 columns.

■

Core is a well-tested ASIC model.

■

Fully compliant to Revision 2.2 of PCI Local Bus specification.

■

Operates at PCI bus speeds up to 66 MHz on a 32-/64-bit wide bus.

■

Comprises two independent controllers for Master and Target.

■

Meets/exceeds all requirements for

PICMG

Hot

Swap friendly silicon, full Hot Swap model, per the

CompactPCI

Hot Swap specification,

PICMG

2.1

R1.0.

■

PCI SIG Hot Plug (R1.0) compliant.

■

Four internal FIFOs individually buffer both directions of both the Master and Target interfaces: — Both Master FIFOs are 64 bits wide by 32 bits

deep.

— Both Target FIFOs are 64 bits wide by 16 bits

deep.

■

Capable of no-wait-state, full-burst PCI transfers in either direction, on either the Master or Target interface. The dual 64-bit data paths extend into the FPGA logic, permitting full-bandwidth, simultaneous bidirectional data transfers of up to 528 Mbytes/s to be sustained indefinitely.

■

Can be configured to provide either two 64-bit buses (one in each direction) to be multiplexed between Master and Target, or four independent 32-bit buses.

■

Provides many hardware options in the PCI core that are set during FPGA logic configuration.

■

Operates within the requirements of the PCI 5 V and 3.3 V signaling environments and 3.3 V commercial environmental conditions, allowing the same device to be used in 5 V or 3.3 V PCI systems.

■

FPGA is reconfigurable via the PCI interface's configuration space (as well as conventionally), allowing the FPGA to be field-updated to meet latebreaking requirements of emerging protocols.

PICMG

and

CompactPCI

are registered trademarks of the PCI

Industrial Computer Manufacturers Group.

Table 1.

ORCA

OR3LP26B PCI FPSC Solution—Available FPGA Logic

†The embedded core and interface comprise approximately 85K standard-cell ASIC gates in addition to these usable gates. The usable

gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU.

Device Usable Gates

†

Number of

LUTs

Number of

Registers

Max User

RAM

Max User

I/Os

Array

Size

Number of

PFUs

OR3LP26B 60K—120K 4032 5304 64K 259 18 x 28 504

Table of Contents

Contents Page Contents Page

ORCA

OR3LP26B FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

2 Lucent Technologies Inc.

Introduction ..........................................................................1

PCI Bus Core Highlights ......................................................1

Figures .................................................................................2

Tables ..................................................................................3

FPSC Highlights ...................................................................5

Software Support .................................................................6

Description ...........................................................................7

What Is an FPSC? ............................... ...... ...... ..... ...... ......7

FPSC Overview .......................................... ...... ..... ...... ......7

FPSC Gate Counting ........................................................7

FPGA/Embedded Core Interface ......................................7

ORCA

Foundry Development System ..............................7

FPSC Design Kit ...............................................................8

FPGA Logic Overview .......................................................8

PLC Logic ..........................................................................8

PIC Logic .............................................. .............................9

System Features ...............................................................9

Routing ..............................................................................9

Configuration .....................................................................9

Boundary Scan ..................................................................9

More Series 3 Information .................................................9

OR3LP26B Overview .........................................................10

Device Layout ............................................................. ....10

PCI Local Bus ................................. ..... ...........................10

OR3LP26B PCI Bus Core Overview ...............................12

PCI Bus Interface ............................................................12

Embedded Core Options/FPGA Configuration ...............13

PCI Bus Core Detailed Description ....................................14

PCI Bus Commands .............................................. ...... ....14

PCI Protocol Fundamentals ............................. ...............16

FIFO Memories and Control ............................................17

PCI Bus Pin Information ............................. .....................18

PCI Bus Core Detailed Description Dual Port ....................21

Embedded Core/FPGA Interface Signal Descriptions ....21

Embedded Core/FPGA Interface Signal Locations .........27

Embedded Core Bit Stream Configurable Options .........32

Understanding FIFO Packing/Unpacking ........................33

Embedded Core/FPGA Interface Operation ...................34

Embedded Core/FPGA Interface Operation Summary ...35

Master (FPGA Initiated) Write .........................................36

Master (FPGA Initiated) Read .........................................42

Target (PCI Bus Initiated) Write ......................................49

Target (PCI Bus Initiated) Read ......................................58

PCI Bus Core Detailed Description Quad Port ...................70

Embedded Core/FPGA Interface Signal Descriptions ....70

Embedded Core/FPGA Interface Signal Locations .........76

Embedded Core Bit Stream Configurable Options .........83

Understanding FIFO Packing/Unpacking ........................84

Embedded Core/FPGA Interface Operation ...................86

Embedded Core/FPGA Interface Operation Summary ...87

Master (FPGA Initiated) Write .........................................88

Master (FPGA Initiated) Read .........................................94

Target (PCI Bus Initiated) Write ....................................101

Target (PCI Bus Initiated) Read ....................................110

Configuration Space of the PCI Core ...............................123

PCI Bus Configuration Space Organization ..................123

FPSC Configuration ................................... ...... ..... ...... .....126

Configuration via PCI Bus .............................................126

Readback via PCI interface ..........................................127

Interaction Among Configurat io n Modes ......................127

Clocking Options at FPGA/Core Boundary ..................... 128

PCI Clock as System Clock ..........................................128

Local Clock as System Clock .......................................128

FPGA Configuration Data Format ...................................130

Using

ORCA

Foundry to Generate Configuration

RAM Data ...................................................................130

FPGA Configuration Data Frame ..................................130

Bit Stream Error Checking ...............................................132

FPGA Configuration Modes .............................................132

Powerup Sequencing for Series OR3LP26B Device .......133

Absolute Maximum Ratings .............................................133

Recommended Operating Conditi ons .............................134

Electrical Characteristics .................................................135

Timing Characteristics .....................................................136

Description ....................................................................136

Clock Timing .................................................................137

Input/Output Buffer Measurement Conditions ................. 148

Output Buffer Characteristics ..........................................149

Estimating Power Dissipation ..........................................150

Pin Information ................................................................151

Package Compatibility ..................................................154

Package Thermal Characteristics Summary ................... 178

JA ............................................................................... 178

JC ............................................................................... 178

JC ...............................................................................178

JB ............................................................................... 178

FPGA Maximum Junction Temperature .......................178

Package Coplanarity .......................................................179

Package Parasitics ..........................................................180

Package Outline Diagrams ..............................................181

Terms and Definitions ...................................................181

352-Pin PBGA ..............................................................182

680-Pin PBGA ..............................................................183

Ordering Information ........................................................184

Figures

Figure 1. ORCA OR3LP26B PCI FPSC

Block Diagram...............................................................13

Figure 2. Master Write Single (FPGA Bus, Dual-Port).....38

Figure 3. Master Write Single (PCI Bus, 64-Bit)..............39

Figure 4. Master Write 32-Byte Burst

(FPGA Bus, Dual-Port) .................................................40

Figure 5. Master Write 32-Byte Burst (PCI Bus, 64-Bit)..41 Figure 6. Master Read Single (FPGA Bus, Dual-Port,

Specified Burst Length, 64-Bit Address).......................44

Figure 7. Master Read Single (PCI Bus, 64-Bit)..............45

Figure 8. Master Read 32-Byte Burst (FPGA Bus,

Dual-Port, Burst Length, and 64-Bit Address)..............46

Figure 9. Master Read 32-Byte Burst

(PCI Bus, 64-Bit)...........................................................47

Lucent Technologies Inc. 3

Lucent Technologies Inc.

Table of

Contents

(continued)

Contents Page Contents Page

Data Sheet

ORCA

OR3LP26B FPSC

Marc h 2000 Embedded Master/Target PCI Inte rface

Figure 10. Target Configuration Write

(PCI Bus, 64-Bit)...........................................................52

Figure 11. Target I/O Write, Delayed (PCI Bus, 64-Bit) ...53 Figure 12. Target Write Memory Single

(PCI Bus, 64-Bit)...........................................................54

Figure 13. Target Write Single (FPGA Bus, Dual-Port)....55

Figure 14. Target Memory Write 32-Byte Burst

(PCI Bus, 64-Bit)...........................................................56

Figure 15. Target Write Memory 32-Byte Burst

(FPGA Bus, Dual-Port) ....................................... ...... ....57

Figure 16. Target Configuration Read

(PCI Bus, 64-Bit)...........................................................61

Figure 17. Target I/O Read, Delayed (PCI Bus, 64-Bit)...62 Figure 18. Target I/O Read, Not Delayed

(PCI Bus, 64-Bit)...........................................................63

Figure 19. Target Memory Single Read, Delayed

(PCI Bus, 64-Bit)...........................................................64

Figure 20. Target Read Single (FPGA Bus, Dual-Port)....65

Figure 21. Target Memory Read Single, Not Delayed

(PCI Bus, 64-Bit)...........................................................66

Figure 22. Target Memory Read 32-Byte Burst, Delayed

(PCI Bus, 64-Bit)...........................................................67

Figure 23. Target Read Memory 32-Byte Burst

(FPGA, Dual-Port) ........................................................68

Figure 24. Target Read Memory Burst, No Delayed

(PCI Bus, 32-Bit)...........................................................69

Figure 25. Master Write Single (PCI Bus, 64-Bit)............90

Figure 26. Master Write 32-Byte Burst

(PCI Bus, 64-Bit)...........................................................91

Figure 27. Master Write Single Quadword

(FPGA Bus, Quad-Port, 64-Bit Address)......................92

Figure 28. Master Write 32-Byte Burst

(FPGA Bus, Quad-Port, 64-Bit Address)......................93

Figure 29. Master Read Single (PCI Bus, 64-Bit)............96

Figure 30. Master Read Single Quadword (FPGA Bus,

Quad-Port, Specified Burst Length, 32-Bit Address) ....97

Figure 31. Master Read 32-Byte Burst

(PCI Bus, 64-Bit)...........................................................98

Figure 32. Master Read 32-Byte Burst (FPGA Bus,

Quad-Port, Specified Burst Length, 32-Bit Address) ....99

Figure 33. Target Configuration Write

(PCI Bus, 64-Bit)...........................................................104

Figure 34. Target I/O Write, Delayed (PCI Bus, 64-Bit) ...105 Figure 35. Target Write Memory Single

(PCI Bus, 64-Bit)...........................................................106

Figure 36. Target Write Single Quadword

(FPGA Bus, Quad-Port, 64-Bit Address)......................107

Figure 37. Target Memory Write 32-Byte Burst

(PCI Bus, 64-Bit)...........................................................108

Figure 38. Target Write Memory 32-Byte Burst

(FPGA Bus, Quad-Port, 32-Bit Address)......................109

Figure 39. Target Configuration Read

(PCI Bus, 64-Bit)...........................................................113

Figure 40. Target I/O Read, Delayed

(PCI Bus, 64-Bit)...........................................................114

Figure 41. Target I/O Read, Not Delayed

(PCI Bus, 64-Bit) ......................................................... .115

Figure 42. Target Memory Single Read, Delayed

(PCI Bus, 64-Bit) ......................................................... .116

Figure 43. Target Read Single (FPGA Bus, Quad-Port,

64-Bit Address).............................................................1 17

Figure 44. Target Memory Read Single, Not Delayed

(PCI Bus, 64-Bit) ......................................................... .118

Figure 45. Target Memory Read 32-Byte Burst, Delayed

(PCI Bus, 64-Bit) ......................................................... .119

Figure 46. Target Read Memory 32-Byte Burst

(FPGA Bus, Quad-Port, 32-Bit Address)......................120

Figure 47. Target Read Memory Burst, No Delayed

(PCI Bus, 32-Bit) ......................................................... .121

Figure 48. FPSC Block Diagram and Clock Network......129

Figure 49. Serial Configuration Data Format—

Autoincrement Mode....................................................131

Figure 50. Serial Configuration Data Format—

Explicit Mode................................................................131

Figure 51. ExpressCLK to Output Delay.........................138

Figure 52. Fast Clock to Output Delay ............................139

Figure 53. System Clock to Output Delay.......................140

Figure 54. Input to ExpressCLK Setup/Hold Time..........141

Figure 55. Input to Fast Clock Setup/Hold Time..............142

Figure 56. Input to System Clock Setup/Hold Time........143

Figure 57. ac Test Loads.................................................148

Figure 58. Output Buffer Delays......................................148

Figure 59. Input Buffer Delays.........................................148

Figure 60. Sinklim (TJ = 25 °C, VDD = 3.3 V).................149

Figure 61. Slewlim (TJ = 25 °C, VDD = 3.3 V)................149

Figure 62. Fast (TJ = 25 °C, VDD = 3.3 V)......................149

Figure 63. Sinklim (TJ = 125 °C, VDD = 3.0 V)...............149

Figure 64. Slewlim (TJ = 125 °C, VDD = 3.0 V)..............149

Figure 65. Fast (TJ = 125 °C, VDD = 3.0 V)....................149

Figure 66. Package Parasitics.........................................180

Tables

Table 1. ORCA OR3LP26B PCI FPSC Solution—

Available FPGA Logic...................................................1

Table 2. PCI Local Bus Data Rates................................10

Table 3. OR3LP26B Array..............................................11

Table 4. PCI Bus Command Descriptions......................14

Table 5. Timing Budgets.................................................17

Table 6. FIFO Flags Provided to FPGA Application.......18

Table 7. PCI Bus Pin Descriptions..................................18

Table 8. Embedded Core/FPGA Interface Signals.........21

Table 9. OR3LP26B FPGA/PCI Core Interface Signal

Locations......................................................................27

Table 10. Bit Definitions on FPGA/PCI Core Interface...30 Table 11. Address Cycle Sequences for Various

Operations ................................................................... 31

Table 12. PCI Core Options Settable via FPGA

Configuration RAM Bits................................................32

Table of

Contents

(continued)

Contents Page Contents Page

ORCA

OR3LP26B FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

4 Lucent Technologies Inc.

Table 13. Dual-Port FIFO Packing/Unpacking, Case 1,

PCI Side ........................................................... ..... ......33

Table 14. Dual-Port FIFO Packing/Unpacking, Case 1,

FPGA Side ..................................................................33

Table 15. Dual-Port FIFO Packing/Unpacking, Case 2,

PCI Side...................................................... ...... ..... ......33

Table 16. Dual-Port FIFO Packing/Unpacking, Case 2,

FPGA Side ..................................................................34

Table 17. Index to State Sequence Tables.....................35

Table 18. Dual-Port Master Write ..................................41

Table 19. Dual-Port Master Read, 64-Bit Address

Supplied.......................................................................48

Table 20. Dual-Port Master Read, 32-Bit Address

Supplied ...................................................................... 48

Table 21. Dual-Port Target Write ...................................57

Table 22. Dual-Port Target Read ...................................69

Table 23. Embedded Core/FPGA Interface Signals....... 70

Table 24. OR3LP26B FPGA/PCI Core Interface Signal

Locations......................................................................76

Table 25. Bit Definitions on FPGA/PCI Core Interface...79 Table 26. Address Cycle S equences for Various

Operations ...................................................................82

Table 27. PCI Core Options Settable via FPGA

Configuration RAM Bits................................................83

Table 28. Quad-Port FIFO Packing/Unpacking, Case 1,

PCI Side...................................................... ...... ..... ......84

Table 29. Dual-Port FIFO Packing/Unpacking, Case 1,

FPGA Side ..................................................................84

Table 30. Quad-Port FIFO Packing/Unpacking, Case 1,

PCI Side ........................................................... ..... ......85

Table 31. Quad-Port FIFO Packing/Unpacking,

Case 1, FPGA Side......................................................85

Table 32. Quad-Port FIFO Packing/Unpacking, Case 2,

PCI Side...................................................... ...... ..... ......85

Table 33. Quad-Port FIFO Packing/Unpacking, Case 1,

FPGA Side...................................................................85

Table 34. Holding Registers, Examples of Typical

Operation .....................................................................86

Table 35. Index to State Sequence Tables.....................87

Table 36. Quad-Port Master Write .................................93

Table 37. Quad-Port Master Read, Duplicate Burst

Length and 16-Bit Address...........................................100

Table 38. Quad-Port Master Read, Specified Burst

Length and 64-Bit Address ..........................................100

Table 39. Quad-Port Target Write ..................................109

Table 40. Quad-Port Target Read...................................122

Table 41. Configuration Space Layout............................123

Table 42. Configuration Space Assignment ................... 124

Table 43. Configuration Frame Format and Contents .... 131

Table 44. Configuration Frame Size...............................132

Table 45. Configuration Modes.......................................132

Table 46. Absolute Maximum Ratings............................133

Table 47. Recommended Operating Conditions.............134

Table 48. Electrical Characteristics................................135

Table 49. Derating for Commercial Devices

(I/O Supply VDD) ............................. ..... ...... ...... ...........136

Table 50. .........................................................................Der-

ating for Commercial Devices (I/O Supply VDD2)........136

Table 51. ExpressCLK (ECLK) and Fast Clock (fclk)

TimingCharacteristics...................................................137

Table 52. General-Purpose Clock Timing

Characteristics (Internally Generated Clock)................138

Table 53. OR3LP26B ExpressCLK to Output

Delay (Pin-to-Pin)............................................... ...... ....138

Table 54. OR3LP26B Fast Clock (fclk) to Output

Delay (Pin-to-Pin)............................................... ...... ....139

Table 55. OR3LP26B General System Clock (SCLK)

to Output Delay (Pin-to-Pin)..........................................140

Table 56. OR3LP26B Input to ExpressCLK (ECLK)

Fast-Capture Setup/Hold Time (Pin-to-Pin)..................141

Table 57. OR3LP26B Input to Fast Clock

Setup/Hold Time (Pin-to-Pin)........................................142

Table 58. OR3LP26B Input to General System

Clock (SCLK) Setup/Hold Time (Pin-to-Pin).................143

Table 59. OR3LP26B PCI and FPGA Interface Clock

Operation Frequencies.................................................143

Table 60. OR3LP26B FPGA to PCI, and PCI to FPGA,

Combinatorial Path Delays...........................................144

Table 61. OR3LP26B FPGA Side Interface

Combinatorial Path Delay Signals ................................144

Table 62. OR3LP26B Interbuf Delays.............................145

Table 63. OR3LP26B FPGA Side Interface Clock to

Output Delays, pciclk Synchronous Signals.................145

Table 64. OR3LP26B FPGA Side Interface Clock to

Output Delays, fclk Synchronous Signals.....................146

Table 65. OR3LP26B FPGA Side Interface Input

Setup Delays, pciclk Synchronous Signals...................147

Table 66. OR3LP26B FPGA Side Interface Input

Setup Delays, fclk Synchronous Signals ......................147

Table 67. PCI Core Internal Power Dissapation .............150

Table 68. FPGA Common-Function Pin Descriptions.....151

Table 69. ORCA OR3LP26B I/Os Summary ..................154

Table 70. Pinout Information ..........................................155

Table 71. ORCA OR3LP26B Plastic Package Thermal

Guidelines.....................................................................178

Table 72. Package Coplanarity.......................................179

Table 73. Package Parasitics..........................................180

Table 74. Voltage Options...............................................184

Table 75. Package Options.............................................184

Table 76. ORCA Series 3+ Package Matrix....................184

Table 77. Embedded Core Type......................................184

Table 78. FPSC Base Array............................................184

Lucent Technologies Inc. 5

Data Sheet

ORCA

OR3LP26B FPSC

Marc h 2000 Embedded Master/Target PCI Inte rface

Lucent Technologies Inc.

PCI Bus Core Highlights

(continued)

■

Master: — Generates all defined command codes except

interrupt acknowledge and special cycle. — Capable of accessing its own local Target. — Capable of acting as the system's configuration

agent by booting up with the Master logic

enabled. — Supports multiple options for Master bus requests,

to increase PCI bus bandwidth. — Supports single-cycle I/O space accesses. — Provides option to delay PCI access until FIFO is

full on Master writes to increase PCI bandwidth. — Supports programmable latency timer control.

■

Target: — Responds legally to all command codes: interrupt

acknowledge, special cycle, and reserved com-

mands ignored; memory read multiple and line

handled as memory read; memory write and

invalidate handled as memory write. — Implements Target abort, disconnect, retry, and

wait cycles. — Handles delayed transactions. — Handles fast back-to-back transactions. — Method of handling retries is programmable at

FPGA configuration to allow tailoring to different

Target data access latencies. — Decodes at medium speed. — Provides option to delay PCI access until FIFO is

full on Target reads to increase PCI bandwidth.

■

Supports dual-address cycles (both as Master and Target).

■

Supports all six base address registers (BARs), as either memory (32-bit or 64-bit) or I/O. Any legal page size can be independently specified for each BAR during FPGA configuration.

■

Independent Master and Target clocks can be supplied to the PCI FIFO interface from the FPGA-based logic.

■

Provides vers atile clocking capabilities with FPGA clocks sourced from PCI bus clock or elsewhere. FIFO interface buffers asynchronous clock domains between the PCI interface and FPGA-based logic.

■

PCI interface timing: meets or exceeds 33 MHz, 50 MHz, and 66 MHz PCI requirements.

■

Configuration options: — Class code, revision ID. — Latency timer. — Cache line size. — Subsystem ID. — Subsystem vendor ID. — Maximum latency, minimum grant. — Interrupt line. — Hot Plug/Hot Swap capability.

■

Generates interrupts on

intan

as directed by the

FPGA.

■

PCI I/O output drivers can be programmed for fast or slew-limited operation.

■

Automatically detects 5 V or 3.3 V PCI bus signaling environment and provides appropriate I/O signaling, under 3.3 V commercial conditions.

■

Ideally suited for such applications as: — PCI-based graphics/video/multimedia. — Bridges to ISA/EISA/MCA, LAN, SCSI, Ethernet,

ATM, or other bus architectures.

— High-bandwidth data transfer in proprietary sys-

tems.

FPSC Highlights

■

Implemented as an embedded core into the advanced Series 3+

ORCA

FPSC architecture.

■

Allows the user to integrate the core with up to 120K gates of programmable logic, all in one device, and provides up to 259 user I/O pins in addition to the PCI interface pins.

■

FPGA portion retains all of the features of the

ORCA

3 FPGA architecture: — High-performance, cost-effective, 0.25 µm

5-level metal technology.

— Twin-quad programmable function unit (PFU)

architecture with eight 16-bit look-up tables (LUTs) per PFU, organized in two nibbles for use in nibble- or byte-wide functions. Allows for mixed arithmetic and logic functions in a single PFU.

Parameter 33 MHz 50 MHz 66 MHz

Device Clock = > Out 11.0 ns 7.5 ns 6.0 ns Device Setup Time 7.0 ns 4.5 ns 3.0 ns Board Prop. Delay 10.0 ns 6.5 ns 5.0 ns Board Clock Skew 2.0 ns 1.5 ns 1.0 ns Total Budget 30.0 ns 20.0 ns 15.0 ns Load Capacitance 50 pF 50 pF 10 pF

66 Lucent Technologies Inc.

ORCA

OR3LP26B FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

Lucent Technologies Inc.

FPSC Highlights

(continued)

— Softwired LUTs (SWL) allow fast cascading of up

to three levels of LUT logic in a single PFU.

— Supplemental logic and interconnect cell (SLIC)

provides 3-statable buffers, up to 10-bit decoder, and

PAL

*-like AND-OR-INVERT (AOI) in each

programmable logic cell (PLC).

— Up to three ExpressCLK inputs allow extremely

fast clocking of signals on- and off-chip plus access to internal general clock routing.

— Dual-use microprocessor interface (MPI) can be

used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA. Glueless interface to

i960

†

and

PowerPC

‡ processors w ith use r-co nf ig-

urable address space provided.

— Programmable clock manager (PCM) adjusts

clock phase and duty cycle for input clock rates from 5 MHz to 120 MHz. The PCM may be combined with FPGA logic to create complex functions, such as digital phase-locked loops (DPLL), frequency counters, and frequency synthesizers or clock doublers. Two PCMs are provided per device.

— True internal 3-state, bidirectional buses with sim-

ple control provided by the SLIC.

— 32 x 4 RAM per PFU, configurable as single or

dual port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the SLIC decoders as bank drivers.

— Built-in boundary scan (

IEEE

1149.1 JTAG) and

TS_ALL testability function to 3-state all I/O pins.

■

High-speed on-chip interface provided between FPGA logic and embedded core to reduce bottlenecks typically found when interfacing off-chip.

■

Supported in two packages: 352-pin PBGA and 680-pin PBGAM.

PAL

is a trademark of Advanced Micro Devices, Inc.

†

i960

is a registered trademark of Intel Corporation.

‡

PowerPC

is a registered trademark of International Business

Machines Corporation.

IEEE

is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

Note

: This document will conform to the nomenclature

of the PCI Local Bus Specification, as follows:

Software Support

■

Supported by

ORCA

Foundry software and third-

part

CAE tools for implementing

ORCA

Series 3+

devices and simulation/timin

analysis with embed-

ded PCI bus core.

■

PCI core configuration options and simulati on netlists

enerated by FPSC Configuration Manager

utility in

ORCA

Foundry software.

■

Preference files provided for timing interface between PCI bus core and FPGA logic.

Term Meaning

byte 8 bits

word 16 bits

DWORD 32 bits

Quadword 64 bits

Lucent Technologies Inc. 7

Data Sheet

ORCA

OR3LP26B FPSC

Marc h 2000 Embedded Master/Target PCI Inte rface

Lucent Technologies Inc.

Description

What Is an FPSC?

FPSCs, or field-programmable system chips, are devices that combine field-programmable logic with ASIC or mask-programmed logic on a single device. FPSCs provide the time to market and flexibility of FPGAs, the design effort savings of using soft intellectual property (IP) cores, and the speed, design density, and economy of ASICs.

FPSC Overview

Lucent’s Series 3+ FPSCs are created from Series 3

ORCA

FPGAs. To create a Series 3+ FPSC, several rows of programmable logic cells (see FPGA Logic Overview section for FPGA logic details) are removed from a Series 3

ORCA

FPGA, and the area is replaced with an embedded logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 efficiency, none of the FPGA functionality is changed—all of the Ser ies 3 FPGA ca pabi li ty is retained: MPI, PCMs, boundary scan, etc. The rows of programmable logic are replaced at the bottom of the device, allowing pins on the bottom and sides of the replaced rows to be used as I/O pins for the embedded core. The remainder of the device pins retain their FPGA functionality as do special function FPGA pins within the embedded core area.

The embedded cores can take many forms and generally come from Lucent Technologies ASIC libraries. Future offerings will allow customers to supply their own core functions for the creation of custom FPSCs.

FPSC Gate Counting

The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates. Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count is sometimes expressed in the same manner. Standard-cell/ASIC gates are, however, 10 to 25 times more silicon area efficient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with a much larger gate count.

FPGA/Embedded Core Interface

The interface between the FPGA logic and the embedded core is designed to look like FPGA I/Os from the FPGA side, simplifying interface signal routing and providing a unified approach with general FPGA design. Effectively, the FPGA is designed as if signals were going off of the device to the embedded core, but the on-chip interface is much faster than going off-chip and requires less power. All of the delays for the interface are precharacterized and accounted for in the

ORCA

Foundry Development System. Clock spines also can pass across the FPGA/embed-

ded core boundary. This allows for fast, low-ske w clocking between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the FPGA as a system.

For even greater system flexibility, FPGA configuration RAMs are available for use by the embedded core. This allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. Multiple embedded core configurations may be designed into a single device with user-programmable control over which configurations are implemented, as well as the capability to change core functionality simply by reconfiguring the device.

ORCA

Foundry Development System

The

ORCA

Foundry Development System is used to process a design from a netlist to a configured FPSC. This system is used to map a design onto the

ORCA

architecture and then place and route it using

ORCA

Foundry’s timing-driven tools. The development system also includes interfaces to, and libraries for, other popular CAE tools for design entry, synthesis, simulation, and timing analysis.

The

ORCA

Foundry Development System interfaces to front-end design entry tools and provides the tools to produce a configured FPSC. In the design flow, the user defines the functionality of the FPGA portion of the FPSC and embedded core settings at two points in the design flow: at design entry and at the bit stream generation stage.

88 Lucent Technologies Inc.

ORCA

OR3LP26B FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

Lucent Technologies Inc.

Description

(continued)

Following design entry, the dev elopment system’s map , place, and route tools translate the netlist into a routed FPSC. A static timing analysis tool is provided to determine device speed and a back-annotated netlist can be created to allow simulation. Timing and simulation output files from

ORCA

Foundry are also compatible with many third-party analysis tools. Its bit stream generator is then used to generate the configuration data which is loaded into the FPSC’s internal configuration RAM. When using the bit stream generator, the user selects options that affect the functionality of the FPSC. Combined with the front-end tools,

ORCA

Foundry produces configuration data that implements the various logic and routing options discussed in this data sheet.

FPSC Design Kit

Development is facilitated by an FPSC Design Kit which, together with

ORCA

Foundry and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an FPSC implementation. Included in the kit are the FPSC Configuration Manager,

Verilog

* and

VHDL

* gate-level structural netlists, all necessary synthesis libraries, and complete online documentation. The kit's software couples with

ORCA

Foundry under the control of the

ORCA

Foundry Control Center (OFCC), providing a seamless FPSC design environment. More information can be obtained by visiting the

ORCA

website or contacting a local sales office, both listed on the last page of this document.

FPGA Logic Overview

ORCA

Series 3 FPGA logic is a new generation of SRAM-based FPGA logic built on the successful Series 2 FPGA line from Lucent Technologies Microelectronics Group, with enhancements and innovations geared toward today’s high-speed designs and tomorrow’s systems on a single chip. Designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the

ORCA

Series 2 devices, the Series 3 more than doubles the logic available in each logic block and incorporates system-level features that can further reduce logic requirements and increase system speed.

ORCA

Series 3 devices contain many new patented enhancements and are offered in a variety of packages, speed grades, and temperature ranges.

ORCA

Series 3 FPGA logic consists of three basic elements: programmable logic cells (PLCs), programmable input/output cells (PICs), and system-level features. An array of PLCs is surrounded by PICs. Each PLC contains a programmable function unit (PFU), a supplemental logic and interconnect cell (SLIC), local routing resources, and configuration RAM. Most of the FPGA logic is performed in the PFU, but decoders,

PAL

-like functions, and 3-state buffering can be performed in the SLIC. The PICs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, and other functions on two output signals. Some of the system-level functions include the new microprocessor interface (

MPI

) and the programmable clock manager

(

PCM

PLC Logic

Each PFU within a PLC contains eight 4-input (16-bit) look-up tables (LUTs), eight latches/flip-flops (FFs), and one additional flip-flop that may be used independently or with arithmetic functions.

The PFU is organized in a twin-quad fashion: two sets of four LUTs and FFs that can be controlled independently. LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset.

The SLIC is connected to PLC routing resources and to the outputs of the PFU. It contains 3-state, bidirectional buffers and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT (AOI) to perform

PAL

-like functions. The 3-state drivers in the SLIC and their direct connections to the PFU outputs make fast, true 3-state buses possible within the FPGA logic, reducing required routing and allowing for real-world system performance.

Verilog

and

VHDL

are registered trademarks of Cadance Design

Systems, Inc.

Lucent Technologies Inc. 9

Data Sheet

ORCA

OR3LP26B FPSC

Marc h 2000 Embedded Master/Target PCI Inte rface

Lucent Technologies Inc.

Description

(continued)

PIC Logic

The Series 3 PIC addresses the demand for everincreasing system clock speeds. Each PIC contains four programmable inputs/outputs (PIOs) and routing resources. On the input side, each PIO contains a fastcapture latch that is clocked by an

ExpressCLK

. This latch is followed by a latch/FF that is clocked by a system clock from the internal general clock routing. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer. Two input signals are available to the PLC array from each PIO, and the

ORCA

Series 2 capability to use any input

pin as a clock or other global input is maintained. On the output side of each PIO, two outputs from the

PLC array can be routed to each output flip-flop, and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals.

The output FF, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The I/O buffer associated with each pad is the same as the

ORCA

Series 3 buffer.

System Features

The Series 3 also provides system-level functionality by means of its dual-use microprocessor interface (MPI) and its innovative programmable clock manager (PCM). These functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today’s high-speed systems. Since these and all other Series 3 features are available in every Series 3+ FPSC, they can also interface to the embedded core providing for easier system integration.

Routing

The abundant routing resources of

ORCA

Series 3 FPGA logic are organized to route signals individually or as buses with related control signals. Clocks are routed on a low-skew, high-speed distribution network and may be sourced from PLC logic, externally from any I/O pad, or from the very fast

ExpressCLK

pins.

ExpressCLKs may be glitchlessly and independently enabled and disabled with a programmable control signal using the new

StopCLK

feature. The improved PIC routing resources are now similar to the patented intraPLC routing resources and provide great flexibility in moving signals to and from the PIOs. This flexibility translates into an improved capability to route designs at the required speeds when the I/O signals have been locked to specific pins.

Configuration

The FPGA logic’s functionality is determined by internal configuration RAM. The FPGA logic’s internal initialization/configuration circuitry loads the configuration data at powerup or under system control. The RAM is loaded by using one of several configuration modes, including serial EEPROM, the microprocessor interface, or the embedded function core.

Boundary Scan

Boundary scan is implemented in the OR3LP26B device as with any of the OR3LXXB family of parts. The PCI core side of the device contains the same boundary-scan registers. After performing a boundary-scan test, it is highly recommended that the device be reset through the PCI

rstn

pin. This reset will clear out any PCI core internal registers that may have been set during the boundary-scan tests.

More Series 3 Information

For more information on Series 3 FPGAs, please refer to the Series 3 FPGA data sheet, available on the

ORCA

worldwide website or by contacting Lucent Technologies as directed on the back of this data sheet.

1010 Lucent Technologies Inc.

ORCA

OR3LP26B FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

Lucent Technologies Inc.

OR3LP26B Overview

Device Layout

The OR3LP26B FPSC provides a PCI local bus core (with FIFOs) combined with FPGA logic. The device is based on a 2.5 V OR3L125B FPGA. The OR3L125B has a 28 x 28 array of programmable logic cells (PLCs). For the OR3LP26B, the bottom ten rows of PLCs in the array were replaced with the embedded PCI bus core. Table 3 shows a schematic view of the OR3LP26B. The upper portion of the device is an 18 x 28 array of PLCs surrounded on the left, top, and right by programmable input/output cells (PICs). At the bottom of the PLC array are the core interface cells (CICs) connecting to the embedded core region. The embedded core region contains the PCI bus functionality of the device. It is surrounded on the left, bottom, and right by PCI bus dedicated I/Os as well as power and special function FPGA pins. Also shown are the interquad routing blocks (hIQ, vIQ) present in the Series 3 FPGA devices. System-level functions (located in the corners of the PLC array), routing resources, and configuration RAM are not shown in Figure 1.

PCI Local Bus

PCI local bus, or simply, PCI bus, has become an industry-standard interface protocol for use in applications ranging from desktop PC busing to high-bandwidth backplanes in networking and communications equipment. The PCI bus specification* provides for both 5 V and 3.3 V signaling environments. The interface clock speed is specified in the range from dc to 66 MHz with detailed specifications at 33 MHz and 66 MHz as well as recommendations for 50 MHz operation. Data paths are defined as either 32-bit or 64-bit. These data path and frequency combinations allow for the peak data transfer rates described in Table 2.

* PCI Local Bus Specification Rev. 2.2, PCI SIG, December 18,

1998.

The PCI bus is electrically specified so that no glue logic is required to interface to the bus—PCI devices interface directly to the PCI bus. Other features include registers for device and subsystem identification and autoconfiguration, support for 64-bit addressing, and multi-Master capabilit y that allows any PCI bus Master access to any PCI bus Target.

Table 2. PCI Local Bus Data Rates

Clock

Frequency

(MHz)

Data Path

Width (bits)

Peak Data Rate

(Mbytes)

33 32 132 33 64 264 66 32 264 66 64 528

Lucent Technologies Inc. 11

Data Sheet

ORCA

OR3LP26B FPSC

Marc h 2000 Embedded Master/Target PCI Inte rface

Lucent Technologies Inc.

OR3LP26B Overview

(continued)

Table 3. OR3LP26B Arra y

IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII

PT1 PT2 PT3 PT4 PT5 PT6 PT7 PT8 PT9 PT10 PT11 PT12 PT13 PT14 PT15 PT16 PT17 PT18 PT19 PT20 PT21 PT22 PT23 PT24 P T25 PT2 6 PT2 7 PT28

IIII

PL1

R1C1R1C2R1C3R1C4R1C5R1C6R1C7R1C8R1C9R1

C10R1C11R1C12R1C13R1C14R1C15R1C16R1C17R1C18R1C19R1C20R1C21R1C22R1C23R1C24R1C25R1C26R1C27R1C28

PR1

IIII

PL2

R2C1R2C2R2C3R2C4R2C5R2C6R2C7R2C8R2C9R2

C10R2C11R2C12R2C13R2C14R2C15R2C16R2C17R2C18R2C19R2C20R2C21R2C22R2C23R2C24R2C25R2C26R2C27R2C28

PR2

IIII

PL3

R3C1R3C2R3C3R3C4R3C5R3C6R3C7R3C8R3C9R3

C10R3C11R3C12R3C13R3C14R3C15R3C16R3C17R3C18R3C19R3C20R3C21R3C22R3C23R3C24R3C25R3C26R3C27R3C28

PR3

IIII

PL4

R4C1R4C2R4C3R4C4R4C5R4C6R4C7R4C8R4C9R4

C10R4C11R4C12R4C13R4C14R4C15R4C16R4C17R4C18R4C19R4C20R4C21R4C22R4C23R4C24R4C25R4C26R4C27R4C28

PR4

IIII

PL5

R5C1R5C2R5C3R5C4R5C5R5C6R5C7R5C8R5C9R5

C10R5C11R5C12R5C13R5C14R5C15R5C16R5C17R5C18R5C19R5C20R5C21R5C22R5C23R5C24R5C25R5C26R5C27R5C28

PR5

IIII

PL6

R6C1R6C2R6C3R6C4R6C5R6C6R6C7R6C8R6C9R6

C10R6C11R6C12R6C13R6C14R6C15R6C16R6C17R6C18R6C19R6C20R6C21R6C22R6C23R6C24R6C25R6C26R6C27R6C28

PR6

IIII

PL7

R7C1R7C2R7C3R7C4R7C5R7C6R7C7R7C8R7C9R7

C10R7C11R7C12R7C13R7C14R7C15R7C16R7C17R7C18R7C19R7C20R7C21R7C22R7C23R7C24R7C25R7C26R7C27R7C28

PR7

IIII

PL8

R8C1R8C2R8C3R8C4R8C5R8C6R8C7R8C8R8C9R8

C10R8C11R8C12R8C13R8C14R8C15R8C16R8C17R8C18R8C19R8C20R8C21R8C22R8C23R8C24R8C25R8C26R8C27R8C28

PR8

IIII

PL9

R9C1R9C2R9C3R9C4R9C5R9C6R9C7R9C8R9C9R9

C10R9C11R9C12R9C13R9C14R9C15R9C16R9C17R9C18R9C19R9C20R9C21R9C22R9C23R9C24R9C25R9C26R9C27R9C28

PR9

IIII

PL10

R10C1R10C2R10C3R10C4R10C5R10C6R10C7R10C8R10C9R10

C10

R10 C11

R10 C12

R10 C13

R10 C14

R10 C15

R10 C16

R10 C17

R10 C18

R10 C19

R10 C20

R10 C21

R10 C22

R10 C23

R10 C24

R10 C25

R10 C26

R10 C27

R10 C28

PR10

IIII

PL11

R11C1R11C2R11C3R11C4R11C5R11C6R11C7R11C8R11C9R11

C10

R11 C11

R11 C12

R11 C13

R11 C14

R11 C15

R11 C16

R11 C17

R11 C18

R11 C19

R11 C20

R11 C21

R11 C22

R11 C23

R11 C24

R11 C25

R11 C26

R11 C27

R11 C28

PR11

IIII

PL12

R12C1R12C2R12C3R12C4R12C5R12C6R12C7R12C8R12C9R12

C10

R12 C11

R12 C12

R12 C13

R12 C14

R12 C15

R12 C16

R12 C17

R12 C18

R12 C19

R12 C20

R12 C21

R12 C22

R12 C23

R12 C24

R12 C25

R12 C26

R12 C27

R12 C28

PR12

IIII

PL13

R13C1R13C2R13C3R13C4R13C5R13C6R13C7R13C8R13C9R13

C10

R13 C11

R13 C12

R13 C13

R13 C14

R13 C15

R13 C16

R13 C17

R13 C18

R13 C19

R13 C20

R13 C21

R13 C22

R13 C23

R13 C24

R13 C25

R13 C26

R13 C27

R13 C28

PR13

IIII

PL14

R14C1R14C2R14C3R14C4R14C5R14C6R14C7R14C8R14C9R14

C10

R14 C11

R14 C12

R14 C13

R14 C14

R14 C15

R14 C16

R14 C17

R14 C18

R14 C19

R14 C20

R14 C21

R14 C22

R14 C23

R14 C24

R14 C25

R14 C26

R14 C27

R14 C28

PR14

IIII

PL15

R15C1R15C2R15C3R15C4R15C5R15C6R15C7R15C8R15C9R15

C10

R15 C11

R15 C12

R15 C13

R15 C14

R15 C15

R15 C16

R15 C17

R15 C18

R15 C19

R15 C20

R15 C21

R15 C22

R15 C23

R15 C24

R15 C25

R15 C26

R15 C27

R15 C28

PR15

IIII

PL16

R16C1R16C2R16C3R16C4R16C5R16C6R16C7R16C8R16C9R16

C10

R16 C11

R16 C12

R16 C13

R16 C14

R16 C15

R16 C16

R16 C17

R16 C18

R16 C19

R16 C20

R16 C21

R16 C22

R16 C23

R16 C24

R16 C25

R16 C26

R16 C27

R16 C28

PR16

IIII

PL17

R17C1R17C2R17C3R17C4R17C5R17C6R17C7R17C8R17C9R17

C10

R17 C11

R17 C12

R17 C13

R17 C14

R17 C15

R17 C16

R17 C17

R17 C18

R17 C19

R17 C20

R17 C21

R17 C22

R17 C23

R17 C24

R17 C25

R17 C26

R17 C27

R17 C28

PR17

IIII

PL18

R18C1R18C2R18C3R18C4R18C5R18C6R18C7R18C8R18C9R18

C10

R18 C11

R18 C12

R18 C13

R18 C14

R18 C15

R18 C16

R18 C17

R18 C18

R18 C19

R18 C20

R18 C21

R18 C22

R18 C23

R18 C24

R18 C25

R18 C26

R18 C27

R18 C28

PR18

IIII

ASB1 ASB2 ASB3 ASB4 ASB5 ASB6 ASB7 ASB8 ASB9 ASB10 ASB11 ASB12 ASB13 ASB14 ASB15 ASB16 ASB17 ASB18 ASB19 ASB20 ASB21 ASB22 ASB23 ASB24 ASB25 ASB26 ASB27 ASB28

IIII

EMBEDDED CORE AREA

IIII

IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII III IIII IIII IIII IIII

1212 Lucent Technologies Inc.

ORCA

OR3LP26B FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

Lucent Technologies Inc.

OR3LP26B Overview

(continued)

OR3LP26B PCI Bus Core Overview

The OR3LP26B embedded core comprises a PCI bus interface with independent Master and Target controllers, FIFO memories and control logic for data buffering, a dual-/quad-port interface to the FPGA logic which performs data packing and multiplexing, and logic to support embedded core and FPGA configuration. Each of these areas is briefly described in the following paragraphs. A detailed description of all of the features and functionality of the OR3LP26B embedded core is provided in the next section.

PCI Bus Interface

The OR3LP26B PCI bus interface is compliant to Revision 2.2 of the PCI Local Bus specification. It is capable of no-wait-state, full-burst operation at all of the rate/data width combinations described in Table 2 as well as at a 50 MHz specification that provides a speed increase over the 33 MHz specification and a larger bus loading capability than the 66 MHz specification. The OR3LP26B operates in either the 3.3 V or 5 V PCI signaling environment and is automatically configured for the appropriate environment by a PCI bus

vio

pin.

Independent Master and Target controllers are provided for use in systems requiring Master/Target or Target only operation. Six 32-bit base address registers (BARs) are provided for choosing the address space of the PCI device, and these six registers can be combined in pairs to produce 64-bit BARs. Dual address cycles are supported in both 32-bit and 64-bit addressing modes. The BARs work in either the I/O or the memory space of the device, and can be configured as prefetchable or nonprefetchable.

Lucent Technologies Inc. 13

Data Sheet

ORCA

OR3LP26B FPSC

Marc h 2000 Embedded Master/Target PCI Inte rface

Lucent Technologies Inc.

OR3LP26B Overview

(continued)

Independent data paths exist for the Master and Target controllers. This allows for separate operation of Master and Target functions, and the capability for a Master to talk to a Target on the same device.

In dual-port mode, the Master and T arget controllers share two 64-bit data paths, one in each direction, between the FIFOs and the FPGA logic. This provides for full-rate transfers in both 32- and 64-bit PCI bus operation.

Quad-port mode provides two 32-bit data paths for each controller: one in each direction. This mode allows for simultaneous reads and writes on either the Master or Target controller.

Diagrams for dual-port and quad-port operation are shown in Figure 1.

5-6368(F).e

Note: User I/O pin count includes three ExpressCLK pins.

Figure 1.

ORCA

OR3LP26B PCI FPSC Block Diagram

Embedded Core Options/FPGA Configuration

In addition to the Series 3 FPGA configuration modes (less Master parallel), the OR3LP26B can also be configured via the PCI bus. Configuration as discussed here has two meanings. There is configuration of the FPGA logic, and there is configuration of the options available in the embedded core. Both are accomplished through the FPGA configuration process (some PCI configuration options may also be set via registers within the PCI bus core). Readback of FPGA and PCI core options is also possible using the PCI bus or Series 3 FPGA readback modes. The PCI bus core will be functional in the default PCI bus configuration space, as defined in the PCI bus 2.2 specification, prior to an initial configuration of the FPGA logic or the embedded core options.

113 USER I/O PADS

OR3T SERIES FPGA

18 ROWS x 28 COLUMNS

USER

I/O PADS

USER

I/O PADS

PCI

MASTER/TARGET

INTERFACE

PCI BUS

DATA CONTROL

AND

MULTIPLEXING

32 32

64-bit x

16 DEEP

FIFO

TARGET

64-bit x

16 DEEP

FIFO

TARGET

64-bit x

32 DEEP

FIFO

MASTER

64-bit x

32 DEEP

FIFO

MASTER

113 USER I/O PADS

OR3T SERIES FPGA

18 ROWS x 28 COLUMNS

USER

I/O PADS

USER

I/O PADS

64-bit x

32 DEEP

FIFO

PCI

MASTER/TARGET

INTERFACE

PCI

BUS

DATA CONTROL

AND

MULTIPLEXING

MASTER

64-bit x

32 DEEP

FIFO

MASTER

64-bit x

16 DEEP

FIFO

TARGET

64-bit x

16 DEEP

FIFO

TARGET

ORCA

OR3LP26B FPSC Data Sheet

Embedded Master/Target PCI Interface

March 2000

14 Lucent Technologies Inc.

Lucent Technologies Inc.

PCI Bus Core Detailed Description

The following sections describe the operation of the embedded core PCI bus interface.

PCI Bus Commands

The PCI core supports all commands required by the PCI specification. The following table describes each command. Subsequent sections will describe the protocols in which the commands are used.

Table 4. PCI Bus Command Descriptions

Command

Code

(Binary

)

Command

Master

Generates

Target

Accepts

Description

0000 Interrupt

Acknowl-

edge

— — Only implemented as Master by agents that interface to the sys-

tem CPU and as Target by agents that incorporate the system interrupt controller.

0001 Special

Cycle

— — Target ignores, per PCI Specification section 3.6.2.

0010 I/O Read

√√

Fully implemented.

Target:

Bursting is prevented by disconnecting with data on the

first data phase. If signal

deltrn

is asserted low, I/O (and memory) reads are handled as delayed transactions; no wait-states are generated. If signal

deltrn

is deasserted high, the unit waits for the data from the FPGA application, inserting wait-states (up to the maximum allowed, after which a retry is issued).

Master:

Bursting is allowed, and no wait-states are generated.

0011 I/O Write

√√

Fully implemented.

Target:

Bursting is prevented by disconnecting with data on the

first data phase. If signal

deltrn

is asserted low, I/O writes are

handled as delayed transactions; no wait-states are generated.

Master:

Bursting is allowed, and no wait-states are generated. 0100 (reserved) — — Target ignores, per PCI Specification section 3.1.1. 0101 (reserved) — — Target ignores, per PCI Specification section 3.1.1. 0110 Memory

Read

√√

Fully implemented.

Target:

Bursting is allowed. If signal

deltrn

is asserted low, mem-

ory (and I/O) reads are handled as delayed transactions. If signal

deltrn

is deasserted high, the unit waits for the data from the FPGA application, inserting wait-states (up to the maximum allowed, after which a retry is issued). If signal

trburstpendn

is asserted low and the Target Read FIFO is empty, wait-states are inserted (up to the maximum allowed, after which a retry is issued).

Master:

Bursting is allowed, and no wait-states are generated.

Lucent Technologies Inc. 15

Data Sheet

ORCA

OR3LP26B FPSC

Marc h 2000 Embedded Master/Target PCI Inte rface

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

Table 4. PCI Bus Command Descriptions

(continued)

Command

Code

(Binary

)

Command

Master

Generates

Target

Accepts

Description

0111 Memory

Write

√√

Fully implemented.

Target:

Writes are posted, bursting is allowed, and no wait-states

are generated.

Master:

Bursting is allowed, and no wait-states are generated. 1000 (reserved) — — Target ignores, per PCI Specification section 3.1.1. 1001 (reserved) — — Target ignores, per PCI Specification section 3.1.1. 1010 Configura-

tion Read

√√

Fully implemented.

Target:

Bursting is disallowed, and no wait-states are generated. Target disconnects with data on first data word. The FPGA portion of the device is not involved in Target configuration transactions.

Master:

Bursting is allowed, and no wait-states are generated.

1011 Configura-

tion Write

√√

Fully implemented.

Target:

Bursting is disallowed, and no wait-states are generated. Target disconnects with data on first data word. The FPGA portion of the device is not involved in Target configuration transactions.

Master:

Bursting is allowed, and no wait-states are generated.

1100 Memory

Read

Multiple

√√

Fully implemented. Both the Master and the Target treat this instruction the same as a memory read (0110); the user’s FPGA logic is responsible for ensuring that the Master operation meets the special requirement that the read request ends on a cacheline boundary.

1101 Dual

Access

Cycle

√√

Fully implemented. Per PCI Specification section 3.9, the PCI core will automatically convert a 64-bit address to a 32-bit address if the upper 32 bits are all zeros.

1110 Memory

Read Line

√√

1111 Memory

Write and Invalidate

√√

Fully implemented. Both the Master and the Target treat this instruction the same as a memory write (0111); the user’s FPGA logic is responsible for ensuring that the Master operation meets the special requirement that writes of complete cachelines, with all byte enables, are performed.

1616 Lucent Technologies Inc.

ORCA

OR3LP26B FPSC Data Sheet

Embedded Master/Target PCI Interface March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

PCI Protocol Fundamentals

Basic Transfer Control

The following paragraphs describe various aspects of the PCI protocol and the way they are handled by the PCI core.

Addressing.

The PCI Specification defines three types of address spaces. The first, configuration address space, is a physical address of space and is intended as a means for powerup software to identify agents and configure them before other address spaces have allocated. The second, I/O address space, is intended for mapping control functions. Control function page sizes in configuration space should be no more than 256 bytes. The third, memory address space, is intended for bulk data transfer. It has features to facilitate this, such as special commands for cache implementation, large page sizes, and mechanisms for prefetching. The PCI core handles all three address space types as both a Master and a Target.

Byte Alignment.

On all write operations (configuration, I/O, and memory space, and including the memory write and invalidate instruction), for both the PCI core’s Master and Target functions, byte enables are fully implemented from/to the FPGA interface. Note, however, that even though the PCI core implements the ability to control byte enables for the memory write and invalidate instruction, the PCI Specification requires that this instruction assert all byte enables, and this is the FPGA application’s responsibility. On read operations, the utility of byte enables is more dubious since the data must be enroute from the PCI bus from Target to Master, at the time that the corresponding byte enables are enroute on the PCI bus Master to Target (unless wait-states are inserted). The PCI core, therefore, does not implement byte enable control for Master or Target reads. Byte enables on master read operations are always asserted, and target ignores the byte enables that are sent, in accordance with PCI Specification requirements.

Device Selectio n (devseln)

The target is responsible for responding to a master’s request by asserting the PCI bus signal

devseln

may be asserted one, two, or three clocks after the address phrase of a transaction, corresponding to fast, medium, or slow decode, respectively. The PCI core’s target is capable of preforming a mediumspeed decode response. The decode response speed has a significant impact on the overall latency and bandwidth of nonburst PCI transactions, but its impact decreases greatly for burst transactions, particularly for burst lengths of the size of the PCI core’s FIFOs.

Address/Data Stepping

Stepping is an optional feature added to the PCI Specification to accommodate agents whose bus drive capability is insufficient to handle large groups of signals changing state in one clock cycle. Continuous stepping allows weak drivers multiple cycles for signal transition. Discrete stepping partitions the bus into two or more groups of bits that transition on successive clock cycles. However, stepping exacts a heavy toll on performance, cutting maximum bandwidth by at least 50% and increasing latency. The PCI core is designed for maximum throughput with high-performance buffers, so stepping is unnecessary and not implemented. The wait cycle control, bit 7 of the command register, is therefore hardwired to a zero.

Reset Operation

The PCI bus contains a signal,

rstn

, that performs a PCI reset function. When the reset occurs, all state machines in the ASIC are placed in their idle state, the configuration space BARs are reset to their mask values, and the command registers are reset. The reset does not reset the FPGA logic. The PCI reset signal is fed from the ASIC to the FPGA logic to be used by the designer.

Interrupt Acknowledge

The interrupt acknowledge command is a read by the system CPU implicitly addressed to the system interrupt controller. Other agents, including the PCI core, are not required to implement this instruction; the PCI core’s Master does not generate it and its Target ignores it.

Lucent Technologies Inc. 17

Data Sheet

ORCA

OR3LP26B FPSC

Marc h 2000 Embedded Master/Target PCI Inte rface

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

Arbitration Parking

The PCI Specification requires that all master agents properly handle bus parking, which means that when that agent receives an asserted

gntn

without the agent

having asserted

reqn

, the agent still must drive signal

par

and buses AD and c_ben. The PCI core meets this

requirement.

Parity

The PCI core implements all required and optional features, including the following:

■

Master generates parity on all addresses placed on the bus.

■

Sending agent generates parity on all data placed on the bus.

■

Target calculates parity on all addresses received from the bus.

■

Receiving agent calculates parity on all data received from the bus.

■

The detected parity error bit in the status register is set whenever an agent calculates corrupted parity.

■

The signal

perrn

is generated whenever an agent calculates corrupted parity and the parity error response bit is set in the command register.

66 MHz Operation

The PCI core is fully compliant to PCI Specification requirements at all clock rates up to 66 MHz. All 33 MHz requirements are also met.

Timing Budget

The PCI core’s timing budget is summarized in Table 5. Note that the 66 MHz timing requirements only allow 5 ns for signal propagation (T

PROP

), as compared to 10 ns at 33 MHz. The effect of the reduction is to also reduce the number of agents that the bus can support, although the actual number is not specified in the PCI Specification and is dependent on the design of the hardware components. The four components of the timing budget are T

VAL

(valid output delay), T

PROP

(propagation time), T

(input setup time), and T

SKEW

(clock sk ew); o f these, only T

VAL

and T

are controlled

by the PCI component, and T

PROP

and T

SKEW

are system parameters. Table 5 includes a third column (also shown in the PCI Specification). This column indicates the performance attainable if all 66 MHz requirements are met except T

PROP

= 10 ns, which is the 33 MHz

value. In this case, the total budget increases from 15 ns (66 MHz) to 20 ns (50 MHz).

Table 5. Timing Budgets

64-Bit Addressing

The PCI core fully supports 64-bit addressing, whether or not the PCI core is configured to utilize the 64-bit data extension. When the PCI core is a 64-bit target being addressed by 64-bit master, the PCI core will decode the address one cycle faster so that dualaddress operation will have no performance impact; see PCI Specification section 3.9 for details.

Section 3.9 of the PCI Specification also states that a Master that supports 64-bit addressin g must nevertheless generate requests utilizing a single address instead of a dual address when the upper 32 bits are all zeros. This shortens the request time by one cycle when comm unicati ng wit h 32-bit Targets. It is the FPGA application’s responsibility to ensure that this requirement is met.

FIFO Memories and Control

The OR3LP26B embedded core contains four FIFO memories and supporting control logic. Two FIFOs are for the master interface data and two for the target interface data. These FIFOs are always configured to operate in 64-bit mode and also carry byte enable bits on a per-byte basis (e.g., the 64-bit FIFO actually carries 64 bits of data and 8 byte enable bits for a total of 72 bits). During 32-bit transactions, the FPSC will pack the data to fully utilize the memories. All FIFOs have four flags: Full, Almost Full (Full-4), Empty, and Almost Empty (Empty+4). (See Table 6.) The FPGA application is provided with the Full/Empty signal and Almost Full/Empty signal associated with the FPGA side of the FIFO. In addition, the FPGA application is provided with the PCI side's Full/Empty signal (but not the Almost Full/Empty signal), to enable checking for operation completion. Clocking for the FPGA side of all FIFOs is flexible, with options for different clocks f or the Master and Target FIFOs, sourced by the FPGA logic, or by the PCI bus clock.

Timing Element 33 MHz 50 MHz 66 MHz Unit

Cycle Time 30.0 20.0 1 5.0 ns Valid Output

Delay

11.0 7.5 6.0 ns

Propagation Time

10.0 6.5 5.0 ns

Input Setup Time 7.0 4.5 3.0 ns Clock Skew 2.0 1.5 1.0 ns

ORCA

OR3LP26B FPSC Data Sheet

Embedded Master/Target PCI Interface

March 2000

18 Lucent Technologies Inc.

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

Table 6. FIFO Flags Provided to FPGA Application

PCI Bus Pin Information

This section describes signals on the PCI bus interface and at the embedded core/FPGA interface. Some signal definitions change name and location based on the mode of operation. Modes of operation are described following the signal descriptions. PCI bus signal package pin locations can be found in Table 70.

Table 7. PCI Bus Pin Descriptions

Write Operation Read Operation

FPGA Side PCI Side FPGA Side PCI Side

Master Operation

mw_fulln mw_emptyn mr_emptyn mr_fulln

mw_afulln mr_aemptyn

Target Operation

tw_emptyn tw_fulln tr_fulln tr_emptyn

tw_aemptyn tr_afulln

mbol

I/O

Description

System Pins

clk

Clock.

Provides timing for all transactions on the PCI bus and is an input to the

OR3LP26B device. All PCI signals, except

rstn

and

intan

, are sampled on the ris-

ing edge of

clk

, and all other PCI bus timing parameters are defined with respect to

this edge. The signal

clk

operates up to 66 MHz, and the minimum frequency is dc.

rstn I

Reset.

An active-low signal used to reset the entire PCI bus.

rstn

is asynchronous

clk

. During

rstn

, all PCI output signals are 3-stated.

Address and Data Pins

ad[31:0] I/O

Address and Data.

Multiplexed on the same PCI pins. A PCI bus transaction con-

sists of an address phase followed by one or more data phases. During data phases,

ad[7:0]

contain the least significant byte and

ad[31:24]

con-

tain the most significant byte. During memory commands, the

ad[31:2]

lines spec-

ify the address and

ad[1:0]

specify the type of bursting sequence to use. The table

below outlines the bursting sequence based on the values of

ad[1:0]

Bursting sequence.

00 Linear incrementing.

01 Disconnect after first transfer. 10 Disconnect after first transfer. 11 Disconnect after first transfer.

c_ben[3:0] I/O

Bus Command and Byte Enables.

Active-low signals multiplexed on the same

PCI pins. During the address phase of a transaction,

c_ben[3:0]

define the bus

command. During the data phase,

c_ben[3:0]

are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data.

par I/O

Parity.

Specifies even parity across

ad[31:0]

and

c_ben[3:0]. par

is stable and

valid one clock after the address phase. For data phases,

par

is stable and valid

one clock after

irdyn

is asserted on a write transaction or

trdyn

is asserted on a

read tran sa cti o n. Once

par

is valid, it remains valid until one clock after the comple-

tion of the current data phase. The Master drives

par

for address and write data

phases; the Target drives

par

for read data phases.

Lucent Technologies Inc. 19

Data Sheet

ORCA

OR3LP26B FPSC

Marc h 2000 Embedded Master/Target PCI Inte rface

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

Table 7. PCI Bus Pin Descriptions

(continued)

mbol

I/O

Description

Interface Control Pins

framen I/O

Cycle Frame.

An active-low signal driven by the current Master to indicate the beginning and duration of an access. The signal framen is asserted to indicate a bus transaction is beginning. While

framen

is asserted, data transfers continue.

When

framen

is deasserted, the transaction is in the final phase or has completed.

irdyn I/O

Initiator Ready.

An active-low signal indicating the bus Master’s ability to complete

the current data phase of the transaction. The signal

irdyn

is used in conjunction

with

trd

. A data phase is completed on any clock cycle during which both

irdyn

and

trd

are asserted. Duri ng a write ,

irdyn

indicates that valid data is present on

ad[31:0]

. During a read, it indicates the Master is prepared to accept data. Wait

cycles are inserted until both

irdyn

and

trd

are asserted together.

trd

I/O

Target Ready.

An active-low signal asserted to indicate the readiness of the Tar-

get’s agent to complete the current data phase of the transaction. The signal

trd

is used in conjunction with

irdyn

. A data phase is completed on any clock where

both

trd

and

irdyn

are sampled active. During reads,

trdyn

indicates that valid

data is present on

ad[31:0]

lines. During write cycles,

trd

indicates that the Tar-

get is prepared to accept data.

stopn

I/O

STOPn.

Indicates that the current Target is requesting the Master to stop the cur-

rent transaction.

idsel I

Initialization Device Select.

Used as a chip select during PCI configuration read

and write transactions. Generally, the user ties

idsel

to one of the upper 24 address

lines,

ad[31:8]

devseln I/O

Device Select.

An active-low input indicating that a device on the bus has been selected. As an output, it indicates that the driving device has decoded its address as the Target of the current access.

Arbitration Pins (for Bus Master Only)

reqn O

Request.

An active-low signal that indicates to the arbiter that the asserting agent desires use of the bus. In the OR3LP26B, this signal is asserted when the OR3LP26B Master controller needs access to the PCI bus.

gntn I

Grant.

An active-low signal that indicates to the OR3LP26B that access to the PCI

bus has been granted.

Error Reporting Pins

perrn I/O

Parity Error.

An active-low signal for the reporting of data parity errors during all

PCI transact i ons except a sp e ci al cy cl e. The

perrn

pin is a sustained 3-state signal and must be driven active by the agent receiving data two clocks following the data when a data parity error is detected. The minimum duration of

perrn

is one clock for each data phase that a data parity error is detected. If sequential data phases each have a data parity error, the

perrn

signal will be asserted for more than a single

clock.

perrn

is driven high for one clock before being 3-stated. The signal

perrn

not asserted until it has claimed the access by asserting

devseln

and completed a

data phase.

ORCA

OR3LP26B FPSC Data Sheet

Embedded Master/Target PCI Interface

March 2000

20 Lucent Technologies Inc.

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

Table 7. PCI Bus Pin Descriptions

(continued)

mbol

I/O

Description

serrn

System Error.

An active-low open drain signal pulsed by agents to report errors

other than parity.

serrn

is sampled every

clk

edge, so any agent asserting

serrn

must ensure it is valid for at least one clock period. The OR3LP26B asserts

serrn

if a Master abort sequence is asserted when the Master controller is accessing the PCI bus.

Interrupt Pins

intan O

PCI Interrupt.

The OR3LP26B asserts this active-low open drain signal when it

requests an interrupt from the PCI compliant interrupt controller.

64-Bit Bus Extension Pins

ad[63:32] I/O

64-Bit Address and Data.

These signals provide the upper 32 bits of address and data when in PCI 64-bit operation. During an address phase (when using the DAC command and when

req64n

is asserted), these address bits are transferred. Dur-

ing a data phase, the data is valid when

req64n

and

ack64n

are both asserted.

Otherwise, these bits are 3-stated.

c_ben[7:4] I/O

Byte Enables.

These are the upper four, active-low, bus command and byte enables when in PCI 64-bit operation. During an address phase (when using the DAC command and when

req64n

is asserted), the bus command is transferred. During a data phase, these bits are the active-low byte enables for data bits 64:32. Otherwise, these bits are 3-stated.

req64n I/O

Request 64-Bit Transfer.

This active-low signal is asserted by the current bus

Master to indicate that it desires to transfer data using 64 bits. The signal

req64n

has the same meaning as

framen

for 32-bit transfers.

ack64n I/O

Acknowledge 64-Bit Transfer.

The Target drives this signal low to indicate that it has decoded its own address as the Target of the current access and that it can do 64-bit transfers. The signal

ack64n

has the same timing as

devseln

in 32-bit trans-

fers.

par64 I/O

Upper Double-Word Parity.

The even parity bit that covers

ad[63:32]

and

c_ben[7:4]

. PAR64 is valid one clock after the initial address phase when

req64n

asserted and the DAC command is indicated on

c_ben[7:4]

. It is also valid the

clock cycle after the second address phase of a DAC command when

req64n

asserted.

Hot Swap Function Pins

enumn O Active-low open drain signal that notifies the system host that the card has been

freshly inserted or is about to be extracted. The system host can then either install (for insertion) or quiesce (for extraction) the card’s driver to adjust for the change in system configuration.

ledn O Active-low open-drain signal that drives a blue LED, indicating that removal of the

card is permitted. This signal is asserted low whenever the LED ON/OFF (LOO) bit in the hot swap control and status register (HSSCR) is asserted high.

ejectsw I Active-high signal that indicates that the card’s ejector handle is unseated. This sig-

nals that the operator has freshly inserted the card, or will extract the card when the blue LED illuminates. If not used, tie high or low.

vio I

PCI Bus Signaling Environment Voltage.

This input indicates to the PCI core the signaling environment being employed on the PCI bus. The input is tied to the appropriate voltage supply (either 5.0 V or 3.3 V).

Lucent Technologies Inc. 21

Data Sheet

ORCA

OR3LP26B FPSC

Marc h 2000 Embedded Master/Target PCI Inte rface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port

Pages 21—69 will refer to the dual-port mode of the OR3LP26B device. For quad-port mode, please refer to pages 70—122.

Embedded Core/FPGA Interface Signal Descriptions

In Table 8, an input refers to a signal flowing into the FPGA logic (out of the embedded core) and an output refers to a signal flowing out of the FPGA logic (into the embedded core).

Table 8

. Embedded Core/FPGA Interface Si

nals

Symbol I/O Description

Data FIFO Signals

datafmfpga[63:0] datafmfpgax[7:0]

Main data bus into the master write FIFO and target read FIFO. Refer to Table 10 on page 30 for bus usage and bit descriptions. These signals must be synchronous to

fclk

datatofpga[63:0] datatofpgax[7:0]

Main data bus out of the master read FIFO and target write FIFO. Refer to Table 10 on page 30 for bus usage and bit descriptions. These signals are synchronous to

fclk

Master General Signals

fpga_mbusyn

FPGA Master Is Busy .

This signal is used in modes currently not implemented in the

core. Tie off this signal to a 1.

fpga_msyserror

FPGA Master Cycle Aborted by PCI Target.

The PCI Master controller in the PCI core asserts this active-high as an indication that the current cycle to the PCI bus has been aborted. This signal is synchronous to

fclk

mcfgshiftenn

pci_mcfg_stat

OImcfgshiftenn is an active-low si gnal that determines the data that is output by the PCI

core onto signal

pci_mcfg_stat

mcfgshiftenn

= 1:

pci_mcfg_stat

= wired-OR of all bits below, after being

masked by FPGA configuration RAM bits;

mcfgshiftenn

= 0:

pci_mcfg_stat

= each bit below, one at a time on succes-

sive

pciclk

rising edges (unmasked), reset when

mcfgshiftenn

= 1;

Status bits: Data parity error detected, Target abort received, and

Master abort received.

Both signals are synchronous to

fclk

Master FIFO Address and Command Register Control Signals

mbol I/O Description

maenn O

Master Command/Address/Burst Length Enable.

This is an active-low signal and is used to enable registering commands , burst length, and start address into the Master address register of the PCI core. On each rising edge of the clock that this signal is sampled low, command, burst length, and address will be registered. This signal must be synchronous to

fclk

ma_fulln

Master Address Register Full Flag.

This active-low signal indicates that the Master address register is full and no more addresses can be registered. This signal is synchronous to

fclk

mstatecntr[2:0]

Internal State Counter.

Used for Master reads and writes. Details of the Master state machine operation can be found in tables at the end of each operation section. This signal is synchronous to

fclk

mfifoclrn

Master FIFO Clear.

This active-low signal i s asserted by the FPGA Master to clear all Master FIFOs. This signal must be synchronous to

fclk

ORCA

OR3LP26B FPSC Data Sheet

Embedded Master/Target PCI Interface

March 2000

22 Lucent Technologies Inc.

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port

(continued)

Table 8. Embedded Core/FPGA Interface Si

nals

(continued)

mbol

I/O

Description

m_ready

Master Logic Ready.

This active-high signal indicates that the Master logic interfacing to the FPGA logic is ready. This signal will be inactive during PCI bus reset or Master FIFO clears. This signal is synchronous to

fclk

mcmd[3:0]

Master Command Code.

Command code for the current Master read/write operation. Refer to Table 10 on page 30. This signal must be synchronous to

fclk

Master Write Data FIFO Signals

mwdataenn

Master Write FIFO Data Enable.

This active-low signal enables the registering

of bus

datafmfpga

during Master write operations into the PCI core Master

write data FIFOs on the rising edge of the Master FIFO clock signal. The signal

mwdataenn

should not be asserted when the Master write data FIFOs are full, or data may be lost. This signal must be synchronous to

fclk

mwpcihold

Master Write PCI Bus Hold.

During burst transfers on the PCI bus, this signal delays the start of the transfer on the PCI bus, allowing the FPGA application to fill the FIFO. The transaction will begin when

mwpcihold

is deasserted or the

FIFO becomes full. When asserted,

mwpcihold

must be held low for a mini-

mum of two

pciclk

periods.

This signal must be synchronous to

pcilk

mw_fulln

Master Write Data FIFO Full Flag.

This active-low signal indicates that the Master write data FIFOs are full. This signal is synchronous to

fclk

mw_afulln

Master Write Data FIFO Almost Full Flag.

This active-low signal indicates that only four more empty locations remain in the Master write data FIFOs. This signal is synchronous to

fclk

mw_emptyn

Master Write Data FIFO Empty Flag.

This active-low signal indicates that the Master write data FIFO is empty. Refer to Master write description on signal usage. This signal is synchronous to

pciclk

mwlastcycn O

Master Write Last Data Cycle.

This active-low signal has two functions:

a. It is asserted low to indicate that the accompanying 32/64 bits of Master read

or write address information is the final portion being sent. It can also be asserted prior to any address portion being sent, indicating that the previous address is to be used.

b. It is asserted low to indicate that the accompanying master write data is the

final data for this operation. When more than one cycle is required to transfer a complete data word, this signal is only valid on the last cycle. This signal must be synchronous to

fclk

Master Read Data FIFO Signals

mrdataenn O

Master Read FIFO Data Output Enable.

This active-low signal enables the

data from the PCI core Master read data FIFOs onto bus

datatofpga

during Master read operations on the rising edge of the Master FIFO clock signal. Valid data will be read from the FIFO whenever it is not empty. This signal must be synchronous to

fclk

mr_emptyn I

Master Read Data FIFO Empty.

This active-low signal indicates that the Master read data FIFOs of the PCI core are empty. This signal is synchronous to

fclk

Lucent Technologies Inc. 23

Data Sheet

ORCA

OR3LP26B FPSC

Marc h 2000 Embedded Master/Target PCI Inte rface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port

(continued)

Table 8. Embedded Core/FPGA Interface Si

nals

(continued)

mbol

I/O

Description

mr_aemptyn I

Master Read Data FIFO Almost Empty.

This active-low signal indicates that only four more data locations are available to be read from the Master read data FIFOs of the PCI core. This signal is synchronous to

fclk

mr_fulln I

Master Read Data FIFO Full Flag.

This active-low signal indicates that the Master read data FIFO is full. Refer to Master read description on signal usage. This signal is synchronous to

pciclk

fpga_mstopburstn O

Stop Burst Reads.

This active-low signal is used by the FPGA Master to terminate burst reads before completion. When asserted, it must stay asserted for a minimum of two

pciclk

periods. When asserted,

fpga_mstopburstn

must stay

asserted until

ma_fulln

goes inactive (high).

This signal must be synchronous to

pciclk

mrlastcycn I

Master Read Last Data Cycle.

This active-low signal is asserted to indicate that the accompanying Master read data is the final data for this operation. When more than one cycle is required to transfer a complete data word, this signal is only valid on the last cycle (1

fclk

period).

This signal is synchronous to

fclk

Target General Signals

disctimerexpn I

Discard Timer Expired.

This active-low signal, when asserted, indicates that the discard timer has expired and the core will now treat the retried delayed transaction as a new transaction. The discard timer is a 15-bit counter which starts its count when a delayed transaction is started. This signal is synchronous to

fclk

fpga_tabort O

Target Abort.

This active-high signal is asserted by the FPGA Target application to abort all future PCI cycles. Once asserted, this signal needs to remain asserted for a minimum of two

pciclk

cycles.

This signal must be synchronous to

pciclk

fpga_tretryn O

Assert Retry.

This active-low signal is asserted by an FPGA Target to the PCI core to send a retry to the PCI bus. Once asserted, this signal needs to remain asserted for a minimum of two

pciclk

cycles.

This signal must be synchronous to

pciclk

deltrn O

Target Delayed Transaction.

Used for Target I/O write (page 50) and Target read operations (page 59). Target memory writes are always posted. Once asserted, this signal needs to remain asserted for a minimum of two

pciclk

cycles. This signal must be synchronous to

pciclk

tcfgshiftenn

pci_tcfg_stat

tcfgshiftenn

is an active-low signal that determines the data that is output by

the PCI core onto signal

pci_tcfg_stat

tcfgshiftenn

= 1:

pci_tcfg_stat

= wired-OR of all bits below, after being

masked by FPGA configuration RAM bits;

tcfgshiftenn

= 0:

pci_tcfg_stat

= each bit below, one at a time on suc-

cessive pciclk rising edges (unmasked), reset when

tcfgshiftenn

= 1;

Status bits: Target abort signaled, system error signaled,

and parity error detected.

Both signals are synchronous to

fclk

ORCA

OR3LP26B FPSC Data Sheet

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March 2000

24 Lucent Technologies Inc.

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port

(continued)

Table 8. Embedded Core/FPGA Interface Si

nals

(continued)

mbol

I/O

Description

Target FIFO Address and Command Register Control Signals

tfifoclrn O

Target FIFO Clear.

This active-low signal is asserted by the FPGA Target to clear all Target FIFOs. This signal must be synchronous to

fclk

treqn I

Target Request from PCI.

This active-low signal is synchronous to the Target

FIFO clock signal. The PCI core asserts

treqn

as an indication to the Target that a transfer request (either read or write) is pending to the target. As long as there are valid target addresses present in the address FIFO, the treqn signal will continue to be active. This signal is synchronous to

fclk

t_ready I

T a rget Logic Ready.

This active-high signal indicates that the T arget logic interfacing to the FPGA logic is ready. This signal will be inactive during PCI bus reset or Target FIFO clears. This signal is synchronous to

fclk

taenn O

Target Address and Command Register Output Enable.

This active-low signal enables PCI addresses to be read from the Target address register of the PCI core, and PCI commands to be read from the Target command register. The PCI core will only execute enough address cycles to transfer the address within the matched page (higher-order bits are not stripped). This signal must be synchronous to

fclk

tcmd[3:0] I

Target Command Code.

This bus provides the command code for a new Tar-

get operation, and is valid when the FPGA senses

treqn

active-low.

Because it is synchron ous to

pciclk

, it must be qualified with

treqn

bar[2:0] I

Base Address Register Number.

This bus indicates which of the six BARs matched the address for the current Target operation, and is valid when the FPGA senses

treqn

active-low. The three 64-bit BARs are designated as numbers 0, 2, and 4. Because it is synchron ous to

pciclk

, it must be qualified with

treqn

tstatecntr[2:0] I

Internal State Counter.

Used for target reads and writes. Details of the target state machine operation can be found in tables at the end of each operation section. This signal is synchronous to

fclk

Target Write Data FIFO Signals

twdataenn O

Target Write FIFO Data Enable.

This active-low signal enables data from the

PCI core Target write da t a F I FOs on t o bus

datatofpga

during Target write operations on the rising edge of the Target FIFO clock signal. Valid data will be read from the FIFO whenever it is not empty. This signal must be synchronous to

fclk

tw_emptyn I

Target Write FIFO Empty.

This signal active indicates that the Target write FIFO is empty. This signal is synchronous to

fclk

tw_aemptyn I

Target Write FIFO Almost Empty.

This active-low signal indicates that only four more empty locations are available in the Target write FIFOs. This signal is synchronous to

fclk

tw_fulln I

Target Write Data FIFO Full Flag

. This active-low signal indicates that the target write data FIFO is full. Refer to target write description on signal usage. This signal is synchronous to

pciclk

Lucent Technologies Inc. 25

Data Sheet

ORCA

OR3LP26B FPSC

Marc h 2000 Embedded Master/Target PCI Inte rface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port

(continued)

Table 8. Embedded Core/FPGA Interface Signals

(continued)

mbol

I/O

Description

twlastcycn I

Target Write Last Data Cycle.

This active-low signal has two functions:

a. It is asserted low to indicate that the accompanying 32/64 bits of Target read or

write address information is the final portion being sent. It can also be asserted prior to any address portion being sent, indicating that the previous address is to be used.

b. It is asserted low to indicate that the accompanying T arget write data is the final

data for this operation. When more than one cycle is required to transfer a complete data word, this signal is only valid on the last cycle. This signal is synchronous to

fclk

Target Read Data FIFO Signals

twburstpendn O

Target Write Burst Data Availability Pending Flag.

This active-low signal directs the PCI core not to immediately disconnect when the Target write FIFO becomes full, but rather to insert PCI bus wait-states (up to the maximum allowed, and then disconnect). Once asserted, this signal needs to remain asserted for a minimum of two

pciclk

periods.

This signal must be synchronous to

pciclk

trdataenn O

Target Read FIFO Data Enable.

This active-low signal enables the registering of

bus

datafmfpga

during Target read operations into the PCI core Target read data

FIFOs on the rising edge of the Target FIFO clock signal. The signal

trdataenn

should not be asserted when the Target read data FIFOs are full, or data may be lost. This signal must be synchronous to

fclk

tr_fulln I

Target Read FIFO Full.

This signal is active-low and synchronous to the rising edge of the Target FIFO clock signal. The PCI core asserts this signal to indicate that the Target read FIFOs are full and that no more data can be clocked in. This signal is synchronous to

fclk

tr_afulln I

Target Read FIFO Almost Full.

This active-low signal indicates that the Target read FIFO has only four more empty locations available in the FIFOs. This signal is synchronous to

fclk

tr_emptyn I

Target Read Data FIFO Empty Flag.

This active-low signal indicates that the target read data FIFO is empty. Refer to target read description on signal usage. This signal is synchronous to

pciclk

trpcihold O

Target Read PCI Bus Hold

. During burst transfers on the PCI bus, this signal delays the start of the transfer on the PCI bus, allowing the FPGA application to fill the FIFO. The transaction will begin when

trpcihold

is deasserted or the FIFO becomes full. Once asserted, this signal needs to remain asserted for a minimum of two

pciclk

periods.

This signal must be synchronous to

pciclk

trlastcycn I

Target Read Last Data Cycle.

This active-low signal is asserted to indicate that the accompanying Target read data is the final data for this operation. When more than one cycle is required to transfer a complete data word, this signal is only valid on the last cycle. During a read burst,

trlastcycn

may remain inactive for longer than it is required to complete the data transfer. If this occurs, the FPGA Target should continue to write data into the Target read FIFOs unless the incremented address crosses the address decode space of the FPGA Target. The address should be incremented by a double word as long as

trlastcycn

is inactive. This signal is synchronous to

fclk

ORCA

OR3LP26B FPSC Data Sheet

Embedded Master/Target PCI Interface

March 2000

26 Lucent Technologies Inc.

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port

(continued)

Table 8. Embedded Core/FPGA Interface Signals

(continued)

mbol

I/O

Description

trburstpendn O

Target Read Burst Data Availability Pending Flag.

This active-low signal directs the PCI core not to immediately disconnect when the Target read FIFO becomes empty, but rather to insert PCI bus wait-states (up to the maximum allowed, and then disconnect). Once asserted, this signal needs to remain asserted for a minimum of two

pciclk

periods.

This signal must be synchronous to

pciclk

Miscellaneous Signals

pci_intan O

PCI Interrupt Request

. This active-low signal is used to generate a PCI bus

interrupt and is forwarded by the PCI core as

intan

onto the PCI bus. Once

asserted, this signal needs to remain asserted for a minimum of two

pciclk

cycles. This signal must be synchronous to

pciclk

fclk1 fclk2

O O

FPGA Clock 1 and 2

. Clocks for use by the PCI core for Master and Target FIFOs. When the PCI clock domain extends into the FPGA, the FPGA may reroute the PCI clock back into

fclk1

fclk2

. External or user-defined clocks may

also be used. The signals

fclk1

and

fclk2

must be the same clock in dual-port

mode.

pciclk I

PCI Clock

. The signal

pciclk

is synchronous to

clk

and may be used by the

FPGA logic.

pci_rstn I

PCI Reset for Use by the FPGA Logic

. This active-low signal indicates that a

PCI bus reset was received from the PCI bus (

rstn

fpga_syserror O

System Error

. This active-high signal is used by the FPGA to generate a system

error on the PCI bus. This is passed to the PCI bus as

serrn

This signal must be synchronous to

pciclk

pci_64bit I

PCI Bus in 64-Bit Mode

. This active-high signal indicates that the PCI core detected that it is connected as a 64-bit agent to the PCI bus. This is the result of detecting PCI signal

req64n

as active (low) on the inactive-going (rising) edge of

PCI signal

rstn

. Note that this does not imply that any particular transaction is

64-bit, since each transaction is individually negotiated using PCI signals

req64n

and

ack64n

This signal is synchronous to

pciclk

fifo_sel O

FIFO Select.

An active-high signal that is valid in the dual-port modes to select

either Master read data (

fifo_sel

= 0) or Target write data (

fifo_sel

= 1).

This signal must be synchronous to

fclk

Lucent Technologies Inc. 27

Data Sheet

ORCA

OR3LP26B FPSC

Marc h 2000 Embedded Master/Target PCI Inte rface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port

(continued)

Embedded Core/FPGA Interface Signal Locations

Table 9 lists the physical locations of all signals on the PCI core/FPGA interface. Separate names are provided for dual-port and quad-port bus signals, since their functionality is port mode dependent.

Table 9. OR3LP26B FPGA/PCI Core Interface Signal Locations

PCI Core/FPGA Interface Site FPGA Input Signal Name FPGA Output Signal Name

ASB1A pci_rstn pci_intan ASB1B pci_64bit (unused) ASB1C (unused) fpga_syserror ASB1D (unused) fpga_mbusyn ASB2A datatofpga31 datafmfpga31 ASB2B datatofpga30 datafmfpga30 ASB2C datatofpga29 datafmfpga29 ASB2D datatofpga28 datafmfpga28 ASB3A datatofpga27 datafmfpga27 ASB3B datatofpga26 datafmfpga26 ASB3C datatofpga25 datafmfpga25 ASB3D datatofpga24 datafmfpga24 ASB4A datatofpga23 datafmfpga23 ASB4B datatofpga22 datafmfpga22 ASB4C datatofpga21 datafmfpga21 ASB4D datatofpga20 datafmfpga20 ASB5A datatofpga19 datafmfpga19 ASB5B datatofpga18 datafmfpga18 ASB5C datatofpga17 datafmfpga17 ASB5D datatofpga16 datafmfpga16 ASB6A datatofpgax3 datafmfpgax3 ASB6B datatofpgax2 datafmfpgax2 ASB6C datatofpgax1 datafmfpgax1 ASB6D datatofpgax0 datafmfpgax0 ASB7A datatofpga15 datafmfpga15 ASB7B datatofpga14 datafmfpga14 ASB7C datatofpga13 datafmfpga13 ASB7D datatofpga12 datafmfpga12 ASB8A datatofpga11 datafmfpga11 ASB8B datatofpga10 datafmfpga10 ASB8C datatofpga9 datafmfpga9 ASB8D datatofpga8 datafmfpga8 ASB9A datatofpga7 datafmfpga7 ASB9B datatofpga6 datafmfpga6 ASB9C datatofpga5 datafmfpga5 ASB9D datatofpga4 datafmfpga4

CKTOASB9 (unused) fclk1

ORCA

OR3LP26B FPSC Data Sheet

Embedded Master/Target PCI Interface

March 2000

28 Lucent Technologies Inc.

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port

(continued)

Table 9. OR3LP26B FPGA/PCI Core Interface Signal Locations

(continued)

PCI Core/FPGA Interface Site FPGA Input Signal Name FPGA Output Signal Name

ASB10A datatofpga3 datafmfpga3

ASB10B datatofpga2 datafmfpga2 ASB10C datatofpga1 datafmfpga1 ASB10D datatofpga0 datafmfpga0

ASB11A tstatecntr0 (unused)

ASB11B tstatecntr1 (unused) ASB11C tstatecntr2 (unused) ASB11D pci_tcfg_stat tcfgshiftenn

ASB12A tcmd0 (unused)

ASB12B tcmd1 (unused) ASB12C tcmd2 (unused) ASB12D tcmd3 twburstpendn

ASB13A bar0 trburstpendn

ASB13B bar1 fpga_tabort ASB13C bar2 fpga_tretryn ASB13D disctimerexpn deltrn

ASB14A treqn taenn

ASB14B twlastcycn twdataenn ASB14C tw_emptyn fifo_sel ASB14D tw_aemptyn (unused)

CKFMASB14 pciclk (unused)

ASB15A t_ready tfifoclrN

ASB15B trlastcycn trdataenn ASB15C tr_fulln (unused) ASB15D tr_afulln (unused)

ASB16A tw_fulln trpcihold

ASB16B tr_emptyn mwpcihold ASB16C mw_emptyn fpga_mstopburstn ASB16D mr_fulln (unused)

ASB17A ma_fulln maenn

ASB17B mw_fulln mwdataenn ASB17C mw_afulln mwlastcycn ASB17D m_ready mrdataenn

ASB18A mrlastcycn mcmd0

ASB18B mr_emptyn mcmd1 ASB18C mr_aemptyn mcmd2 ASB18D fpga_msyserror mcmd3

ASB19A datatofpga32 datafmfpga32

ASB19B datatofpga33 datafmfpga33 ASB19C datatofpga34 datafmfpga34 ASB19D datatofpga35 datafmfpga35

CKTOASB19 (unused) fclk2

ASB20A datatofpga36 datafmfpga36

Lucent Technologies Inc. 29

Data Sheet

ORCA

OR3LP26B FPSC

Marc h 2000 Embedded Master/Target PCI Inte rface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port

(continued)

Table 9. OR3LP26B FPGA/PCI Core Interface Signal Locations

(continued)

PCI Core/FPGA Interface Site FPGA Input Signal Name FPGA Output Signal Name

ASB20B datatofpga37 datafmfpga37 ASB20C datatofpga38 datafmfpga38 ASB20D datatofpga39 datafmfpga39 ASB21A datatofpga40 datafmfpga40 ASB21B datatofpga41 datafmfpga41 ASB21C datatofpga42 datafmfpga42 ASB21D datatofpga43 datafmfpga43 ASB22A datatofpga44 datafmfpga44 ASB22B datatofpga45 datafmfpga45 ASB22C datatofpga46 datafmfpga46 ASB22D datatofpga47 datafmfpga47 ASB23A datatofpgax4 datafmfpgax4 ASB23B datatofpgax5 datafmfpgax5 ASB23C datatofpgax6 datafmfpgax6 ASB23D datatofpgax7 datafmfpgax7 ASB24A datatofpga48 datafmfpga48 ASB24B datatofpga49 datafmfpga49 ASB24C datatofpga50 datafmfpga50 ASB24D datatofpga51 datafmfpga51 ASB25A datatofpga52 datafmfpga52 ASB25B datatofpga53 datafmfpga53 ASB25C datatofpga54 datafmfpga54 ASB25D datatofpga55 datafmfpga55 ASB26A datatofpga56 datafmfpga56 ASB26B datatofpga57 datafmfpga57 ASB26C datatofpga58 datafmfpga58 ASB26D datatofpga59 datafmfpga59 ASB27A datatofpga60 datafmfpga60 ASB27B datatofpga61 datafmfpga61 ASB27C datatofpga62 datafmfpga62 ASB27D datatofpga63 datafmfpga63 ASB28A mstatecntr0 mfifoclrn ASB28B mstatecntr1 (unused) ASB28C mstatecntr2 (unused) ASB28D pci_mcfg_stat mcfgshiftenn

ORCA

OR3LP26B FPSC Data Sheet

Embedded Master/Target PCI Interface

March 2000

30 Lucent Technologies Inc.

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port

(continued)

Table 10. Bit Definitions on FPGA/PCI Core Interface

* Command Codes (codes correspond to PCI bus command codes): 0000 Not Used (interrupt acknowledge not implemented) 0001 Not Used (special cycle not implemented) 0010 I/O Read 0011 I/O Write 0100 Reserved (per PCI specification) 0101 Reserved (per PCI specification) 0110 Memory Read 0111 Memory Write 1000 Reserved (per PCI specification) 1001 Reserved (per PCI specification) 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Not Used (dual address operation is indicated via separate signal) 1110 Memory Read Line 1111 Memory Write and Invalidate

Bits Name Description

Dual-Port Master Write, Command and Address mstatecntr = 0

datafmfpgax[7:3] — Unused

datafmfpgax[2] DA Dual address indicator (active-high)

datafmfpgax[1:0] — Unused

datafmfpga[63:32] A3 & A2 Address words 3 and 2 (if DA = 1; else must set

all bits to 0s)

datafmfpga[31:0] A1 & A0 Address words 1 and 0

mcmd[3:0] mcmd Master command opcode*

B. Dual-Port Master Write, Data mstatecntr = 4

datafmfpgax[7:0] BE7—BE0 Byte enables (active-low)

datafmfpga[63:0] D7—D0 Data bytes 7 to 0

C. Dual-Port Master Read (Burst Length Cycle) mstatecntr = 0

datafmfpgax[7:3] — Unused

datafmfpgax[2] DA Dual address indicator (active-high)

datafmfpgax[1:0] — Unused datafmfpga[63:56] mrd_benn Byte enables (active-low) datafmfpga[55:50] — Unused datafmfpg a[49:32] BL Burst length (in Quadwords)

datafmfpga[31:0] A1 & A0 Address words 1 and 0 (set to all 0s if 64-bit

address required—A1 & A0 supplied in next

cycle)

mcmd[3:0] mcmd Master command opcode*

D. Dual-Port Master Read (64-Bit Address Cycle) mstatecntr = 1

datafmfpgax[7:0] — Unused datafmfpga[63:32] A3 & A2 Address words 3 and 2

datafmfpga[31:0] A1 & A0 Address words 1 and 0

mcmd[3:0] — Unused

E. Dual-Port Master Read, Data mstatecntr = 4

datatofpgax[7:0] — Unused datatofpga[63:0] D7—D0 Data bytes 7 to 0

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