AGERE LU3X54FTL-HS208-DB Datasheet
Data Sheet
July 2000
QUAD-FET for 10Base-T/100Base-TX/
Introduction
Configuration
The LU3X54FTL is a four-channel, single-chip complete transceiver designed specifically for dual-speed
10Base-T, 100Base-TX, and 100Base-FX repeaters
and switches. It supports simultaneous operation in
three separate
100Base-TX, and 100Base-FX. The LU3X54FTL
provides a 3.3 V or 5.0 V MII interface logic level.
Each channel implement s:
IEEE
standard modes: 10Base-T,
LU3X54FTL
■
Autopolarity detection and correction
■
Adjustable squelch level for extended line length
capability (two levels)
■
Interfaces with
interface (MII) or a serial 10 Mbits/s 7-pin interface
■
On-chip filtering eliminates the need for external
filters
■
Half- and full-duplex operations
100 Mbits/s TX Transceiver
IEEE
802.3u media independent
FX
■
10Base-T transceiver function of
■
Physical coding sublayer (PCS) of
■
Physical medium attachment (PMA) of
IEEE
IEEE
802.3.
802.3u.
IEEE
802.3u.
■
Autonegotiation of
■
MII management of
■
Physical medium dependent (PMD) of
IEEE
IEEE
802.3u.
802.3u.
IEEE
802.3.
The LU3X54FTL supports operations over two pairs
of unshielded twisted-pair (UTP) cable (10Base-T
and 100Base-TX), and over fiber-optic cable
(100Base-FX).
It has been designed with a flexible system interface
that allows configuration for optimum performance
and effortless design. The individual per-port interface can be configured as 100 Mbits/s MII, 10 Mbits/s
MII, 7-pin 10 Mbits/s serial, or bused mode.
Features
10 Mbits/s Transceiver
■
Compatible with
IEEE
802.3u MI I (cl ause 22), P CS
(clause 23), PMA (clause 24), autonegotiation
(clause 28), and PMD (clause 25) specifications
■
Scrambler/descrambler bypass
■
Encoder/decoder bypass
■
3-statable MII in 100 Mbits/s mode
■
Selectable carrier sense signal generation (CRS)
asserted during either transmission or reception in
half duplex (CRS asserted during reception only in
full duplex)
■
Selectable MII or 5-bit code group interface
■
Full- or half-duplex operations
■
Optional carrier integrity monitor (CIM)
■
On-chip filtering and adaptive equalization that
eliminates the need for external filters
100 Mbits/s FX Transceiver
■
Compatible with
dard
IEEE
802.3U 100Base-FX stan-
■
Compatible with
IEEE
* 802.3 10Base-T standard
for twisted-pair cable
*
IEEE
is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact
your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.
LU3X54FTL Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000
Table of Contents
Contents Page
Introduction................................................................................................................................................................1
Configuration...........................................................................................................................................................1
Features ....................................................................................................................................................................1
10 Mbits/s Transceiver ............................................................................................................................................1
100 Mbits/s TX Transceiver.....................................................................................................................................1
100 Mbits/s FX Transceiver.....................................................................................................................................1
General ...................................................................................................................................................................4
Description ................................................................................................................................................................4
Bused MII Mode......................................................................................................................................................4
Clocking ..................................................................................................................................................................5
FX Mode .................................................................................................................................................................6
Functional Block Diagrams .....................................................................................................................................7
Application Diagrams ............. ....... ............................................. ....... ...... ...... .................................................... ......9
Block Diagrams.....................................................................................................................................................11
Pin Information ........................................................................................................................................................13
Pin Diagram for Normal MII Mode.........................................................................................................................13
Pin Diagram for Bused MII Mode..........................................................................................................................14
Pin Maps....................................... ...... ....... ...... ....... ...... ....... ...... ....... ...... ................................ ....... ...... ....... ...... ....15
Pin Descriptions......................................................................... ....... ...... ...... ....................................... ....... ...... ....16
MII Station Management ................. ...... ....... ...... ....... ...... ....... ...... ....... ............................................. ...... ....... ...... ....29
Basic Operations...................................................................................................................................................29
MII Management Frames......................................................................................................................................29
Management Registers (MR)................................................................................................................................30
Unmanaged Operations........................................................................................................................................40
Mode Select.................................. ...... ....... ...... ....... ...... ....... ...... ...........................................................................40
Absolute Maximum Ratings (TA = 25 °C)................................................................................................................41
Electrical Characteristics.........................................................................................................................................41
Timing Characteristics (Preliminary) .......................................................................................................................42
Outline Diagram.......................................................................................................................................................51
208-Pin SQFP.......................................................................................................................................................51
Ordering Information................................................................................................................................................52
Tables Page
Table 1. LU3X54FTL Crystal Specifications ............................................................................................................ 6
Table 2. LU3X54FTL Pin Maps.............................................................................................................................. 15
Table 3. MII/Serial Interface Pins in Normal MII Mode (Four Separate MII Ports)................................................. 16
Table 4. MII/Serial Interface Pins in Bused MII Mode............................................................................................ 18
Table 5. MII Management Pins .............................................................................................................................. 22
Table 6. 10/100 Mbits/s Twisted-Pair (TP) Interface Pins....................................................................................... 22
Table 7. Miscellaneous Pins .................................................................................................................................. 23
Table 8. MII Management Frame Format............................................................................................................... 29
Table 9. MII Management Frames Field Descriptions............................................................................................ 29
Table 10. MII Management Registers (MR)........................................................................................................... 30
Table 11. MR0—Control Register Bit Descriptions................................................................................................ 31
Table 12. MR1—Status Register Bit Descriptions ................................................................................................. 32
Table 13. MR2, 3—PHY Identifier Registers (1 and 2) Bit Descriptions................................................................ 33
Table 14. MR4—Autonegotiation Advertisement Register Bit Descriptions........................................................... 33
Table 15. MR5—Autonegotiation Link Partner (LP) Ability Register (Base Page) Bit Descriptions....................... 34
Table 16. MR5—Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Descriptions........................ 34
2 Lucent Technologies Inc.
Data Sheet LU3X54FTL
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX
Table of Contents
(continued)
Tables Page
Table 17. MR6—Autonegotiation Expansion Register Bit Descriptions..................................................................35
Table 18. MR7—Next-Page Transmit Register Bit Descriptions.............................................................................35
Table 19. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions...................................................36
Table 20. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions............................................37
Table 21. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions..............................................38
Table 22. MR31—Device-Specific Register 4 (Quick Status) Bit Descriptions.......................................................39
Table 23. Output Pins.............................................................................................................................................40
Table 24. LU3X54FTL Modes.................................................................................................................................40
Table 25. Absolute Maximum Ratings ....................................................................................................................41
Table 26. Operating Conditions ..............................................................................................................................41
Table 27. dc Characteristics ...................................................................................................................................41
Table 28. MII Management Interface Timing (25 pF Load).....................................................................................42
Table 29. MII Data Timing (25 pF Load).................................................................................................................43
Table 30. Serial 10 Mbits/s Timing for TPIN, CRS, and RX_CLK...........................................................................45
Table 31. Serial 10 Mbits/s Timing for TX_EN, TPOUT, CRS, and RX_CLK..........................................................45
Table 32. Serial 10 Mbits/s Timing for TX_EN, TPIN, and COL .............................................................................46
Table 33. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD (25 pF Load)................47
Table 34. Serial 10 Mbits/s Timing for RX_CLK and TX_CLK (25 pF Load)..........................................................48
Table 35. 100 Mbits/s MII Transmit Timing.............................................................................................................49
Table 36. 100 Mbits/s MII Receive Timing..............................................................................................................50
Figures Page
Figure 1. LU3X54FTL Device Overview...................................................................................................................7
Figure 2. LU3X54FTL Single-Channel Detail Functions ..........................................................................................8
Figure 3. Typical Single-Channel Twisted-Pair (TP) Interface ..................................................................................9
Figure 4. Typical Single-Channel Fiber-Optic Interface..........................................................................................10
Figure 5. Smart 10/100 Mbits/s Bused MII Mode...................................................................................................11
Figure 6. Separate 10/100 Mbits/s Bused MII Mode..............................................................................................12
Figure 7. LU3X54FTL Pinout for Normal MII Mode................................................................................................13
Figure 8. LU3X54FTL Pinout for Bused MII Mode.................................................................................................14
Figure 9. MDIO Input Timing..................................................................................................................................42
Figure 10. MDIO Output Timing.............................................................................................................................42
Figure 11. MDIO During TA (Turnaround) of a Read Transaction ..........................................................................43
Figure 12. MII Timing Requirements for LU3X54FTL ............................................................................................44
Figure 13. Serial 10 Mbits/s Timing for TPIN, CRS, and RX_CLK.........................................................................45
Figure 14. Serial 10 Mbits/s Timing for TX_EN, TPOUT, CRS, and RX_CLK........................................................45
Figure 15. Serial 10 Mbits/s Timing for TX_EN, TPIN, and COL ...........................................................................46
Figure 16. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD ...................................47
Figure 17. Serial 10 Mbits/s Timing Diagram for RX_CLK and TX_CLK ...............................................................48
Figure 18. 100 Mbits/s MII Transmit Timing ...........................................................................................................49
Figure 19. 100 Mbits/s MII Receive Timing............................................................................................................50
Lucent Technologies Inc. 3
LU3X54FTL Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000
Features
■
Reuses existing twisted-pair I/O pins for compatible
(continued)
fiber-optic transceiver pseudo-ECL (PECL ) data:
— No additional data pins required
— Reuses existing LU3X54FTL pins for fiber-optic
signal detect (FOSD) inputs
■
Fiber mode automatically configures port:
— Disables autonegotiation
— Disables 10Base-T
— Enables 100Base-FX remote fault signaling
— Disables MLT-3 encoder/decoder
— Disables scrambler/descrambler
■
FX mode enable is pin- or register-selectable on an
individual per-port basis
General
■
Autonegotiation (
— Fast link pulse (FLP) burst generator
— Arbitration function
■
Bused interfaces:
— Supports either separate 10 Mbits/s and
100 Mbits/s multiport repeaters (100 Mbits/s
MII and 10 Mbits/s serial data stream), or singlechip multispeed repeaters
— Connects ports to either the 10 Mbits/s or
100 Mbits/s buses controlled by autonegotiation
— Separate TX_EN, RX_EN, CRS, and COL pins for
each port
— Drivers on bused signal can drive up to eight
LU3X54FTLs (32 ports )
■
Supports the station management protocol and
frame format (clause 22):
— Basic and extended registers
— Supports next-page function
— Operates up to 12.5 MHz
— Accepts preamble suppression
— Maskable status interrupts
■
Supports the following management functions via
pins if MII station management is unavailable:
— Speed select
— Carrier integrity enable
— Encoder/decoder bypass
— Scrambler/descrambler bypass
— Full duplex
— No link pulse mode
— Carrier sense select
— Autonegotiation
IEEE
802.3u, cl ause 28):
— 10 Mbits/s repeater reference select
— Internal 20 MHz clock synthesizer
— FX mode select
■
Single 25 MHz crystal input or 25 MHz clock input,
optional 20 MHz clock input
■
Supports half- and full-duplex operations
■
Provides six status signals:
— Receive activity
— Transmit activity
— Full duplex
— Collision/jabber
— Link integrity
— Speed indication
■
Optional LED pulse stretching
■
Per-channel powerdown mode for 10 Mbits/s and
100 Mbits/s operation
■
Loopback for 10 Mbits/s and 100 Mbits/s operation
■
Internal pull-up or pull-down resistors to set default
powerup mode
■
0.35 µm low-power CMOS technology
■
208-pin SQFP
Description
Bused MII Mode
The LU3X54FTL has been designed for operation in
two basic system interface modes of operation:
Normal MII Mode (Four Separate MII Ports).
■
separate mode provides four independent RJ-45 to
MII ports and is similar to having four independent
10/100 transceivers.
Bused MII Mode.
■
This mode is designed specifically
for repeater applications to save pins. In bused
mode:
— Data from all of the ports operating at 100 Mbits/s
will be internally bused to system interface port A
(100 Mbits/s MII interface).
— Data from all of the ports operating at 10 Mbits/s
will be internally bused to system interface port B
(7-pin 10 Mbits/s serial interface).
The LU3X54FTL will automatically detect the speed of
each port (10 Mbits/s or 100 Mbits/s) and route the
data to the appropriate port.
The
4 Lucent Technologies Inc.
Data Sheet LU3X54FTL
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX
Description
(continued)
The bused mode has two additional submodes of
operation:
Separate Bused MII Mode.
■
This mode is designed
to operate with two independent repeater ICs, one
repeater operating at 100 Mbits/s and the other operating at 10 Mbits/s.
Figure 6 shows a block diagram of this mode in
which separate pins (four of each) are used for
COL_10(4), COL_100(4), CRS_10(4), CRS_100(4),
RX_EN10(4), RX_EN100(4), TX_EN10 (4), and
TX_EN100(4).
The signals RX_CLK10, RXD_10, TX_CLK10, and
TXD_10 (all from ports A, B, C, and D) are internally
bused together and connected to MII port B.
The signals TX_CLK25, TXD_100[3:0], TX_ER,
RX_CLK25, RXD_100[3:0], RX_DV, and RX_ER (all
from ports A, B, C, D) are internally bused together
and connected to MII port A.
The repeater ICs will enable the particular port to
which it will communicate by enabling the port with
TX_EN 10, TX_EN100, RX_EN10, or RX_EN100.
Smart Bused MII Mode.
■
This mode is used when
the LU3X54FTL is communicating with a single
(smart) 10/100 Mbits/s repeater IC, and allows the
use of the security feature.
Figure 5 shows a block diagram of the smart bused
mode of operation. In this mode, a common set of
pins is used for CRS_10/100[D:A],
RX_EN10/100[D:A], TX_EN10/100, and
COL_10/100.
The 10 Mbits/s (7-pin 10 Mbits/s serial interface) signals are still routed to port B (RX_CLK10, RXD_10,
TX_CLK10, and TXD_10).
The bused interface allows each of the four transceivers to be connected to one of two system interfaces:
■
Port A: 100 Mbits/s MII interface.
■
Port B: 7-pin 10 Mbits/s serial interface.
This configuration allows 10/100 Mbits/s segment segregation or port switching with conventional multiport
shared-media repeaters.
The port speed configuration and connection to the
appropriate bused output is done automatically and is
controlled by autonegotiation.
Figure 1 gives a functional overview of the LU3X54FTL
while Figure 2 details its single-channel functions.
Figure 3 shows how the LU3X54FTL sing le-channel
interfaces to the twisted pair (TP).
Clocking
The LU3X54FTL requires an internal 25 MHz clock and
a 20 MHz clock to run the 100Base-TX transceiver and
10Base-T transceiver.
These clocks can be supplied as follows:
■
As separate clock inputs: 25 MHz and 20 MHz.
■
The 20 MHz clock can be internally synthesized from
the 25 MHz clock.
■
The 25 MHz clock can also be internally generated
by an on-chip oscillator if an external crystal is supplied.
The LU3X54FTL will automatically detect if a 25 MHz
clock is supplied, or if a crystal is being used to generate the 25 MHz clock.
The 100 Mbits/s signals are still routed to port A
(TX_CLK25, TXD_100[3:0], TX_ER, RX_ CLK 25,
RXD_100[3:0], RX_DV, and RX_ER).
Lucent Technologies Inc. 5
LU3X54FTL Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000
Description
(continued)
Either the on-chip 20 MHz clock synthesizer (default
clock) can be used, or H-DUPLED[A]/CLK20_SEL
(pin 198) can be pulled high (sensed on powerup and
reset) to select the external 20 MHz clock input.
The crystal specifications for the device are listed in
Table 1, an d the crysta l circu it is sh ow n in Fig ure 3 an d
Figure 4.
Table 1. LU3X54FTL Crystal Specifications
Parameter Requirement
Type Quartz Fundamental Mode
Frequency 25 MHz
Stability ±25 ppm, 0—70 °C
Shunt Capacitor 7 pF
Load Capacitor 20 pF
Series Resistance <30 Ω
FX Mode
Each individual port of the LU3X54FTL can be operated in 100Base-FX mode by selecting it through the
pin program option RXLED[D:A]/FX_MODE_EN[D:A],
or through the register bit (register 29, bit 0).
When operating in FX mode, the twisted-pair I/O pins
are reused as the fiber-optic transceiver I/O data pins,
and the fiber-optic signal detect (FOSD) inputs are
enabled.
Figure 4 shows a typical FX port interface. Note that no
additional external components, excluding those
needed by the fiber transceiver, are required.
When a port is placed in FX mode, it will automatically
configure the port for 100Base-FX operation (and the
register bit control will be ignored) such that:
■
The far-end fault signaling option will be enabled.
■
The MLT-3 encoding/decoding will be disabled.
■
Scrambler/descrambler will be disabled.
■
Autonegotiation will be disabled.
■
The signal detect inputs will be activated.
■
10Base-T will be disabled.
6 Lucent Technologies Inc.
Data Sheet LU3X54FTL
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX
Description
(continued)
Functional Block Diagrams
Device Overview
MII/SERIAL
INTERFACE
MII/SERIAL
INTERFACE
MII/SERIAL
INTERFACE
MANAGEMENT
PCS
MANAGEMENT
PCS
MANAGEMENT
PCS
PMA
AUTONEGOTIATION
10 Mbits/s TRANSCEIVER
DRIVER AND FILTERS
PMA
AUTONEGOTIATION
10 Mbits/s TRANSCEIVER
DRIVER AND FILTERS
PMA
AUTONEGOTIATION
TX PMD/
FX PORT
DRIVER AND
FILTERS
MUX
TX PMD/
FX PORT
DRIVER AND
FILTERS
MUX
TX PMD/
FX PORT
DRIVER AND
FILTERS
FX_MODE_EN
FX_MODE_EN
FX_MODE_EN
TP
MAGNETICS
INTERFACE
LSCLK
25 MHz
25 MHz
CRYSTAL
MII/SERIAL
INTERFACE
DPLL
25 MHz
125 MHz
20 MHz
10 Mbits/s TRANSCEIVER
DRIVER AND FILTERS
MANAGEMENT
PMA
PCS
AUTONEGOTIATION
10 Mbits/s TRANSCEIVER
DRIVER AND FILTERS
10 MHz
20 MHz
Figure 1. LU3X54FTL Device Overview
MUX
TX PMD/
FX PORT
DRIVER AND
FILTERS
MUX
FX_MODE_EN
5-5137(F).fr2
Lucent Technologies Inc. 7
LU3X54FTL Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000
Description
(continued)
Single-Channel Detail Functions
100 OFF
RX_ER/RXD[4]
MII
INTERFAC E
TX_ER/TXD[4]
SERIAL
INTERFAC E
CRS
COL
RXD[3:0]
RX_DV
RX_CLK
TX_CLK
TXD[3:0]
TX_EN
REF10
RX_CLK
RXD[0]
TX_CLK
TX_EN
TXD[0]
CLK20
TXD[3:0]
MII
4B/5B
ENCODER
TX STATE
MACHINE
CIM
5B/4B
DECODER
FAULT DETECT
100 Mbits/s TRANSCEIVER
FAR-END
FAULT GEN
SD
COLLISION
DETECT
CAR_STAT
RXERR_ST
FAR-END
10 Mbits/s TRANSCEIVER
CARRIER
DETECT
ALIGNER
LC10 LS10
SCRAMBLER
RX STATE
MACHINE
SD
DESCRAMBLER
LC100
LS100
SD
PDT
DCRU
PDR
FX_MODE_EN
PMD
TX/
FIBER PORT
FX_MODE_EN
PMD
RX/
FIBER
PORT
SD
TPOUT
FOSD
±
TPIN
±
MANAGEMENT
INTERFACE
LSCLK
25 MH
MDC
MDIO
DPLL
Z
25 MHz
CRYSTAL
MII
MANAGEMENT
25 MHz
125 MHz
20 MHz
AUTONEGOTIATION
AND LINK MONITOR
Figure 2. LU3X54FTL Single-Channel Detail Functions
5-5136(F).j
8 Lucent Technologies Inc.
Data Sheet LU3X54FTL
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX
Description
(continued)
Application Diagrams
Single-Channel Twisted-Pair Interface
LU3X54FTL
88 87
XTALOUT
33 pF 33 pF
25 MHz
TPOUT+
50
50
TPOUT–
TPIN+
50
50
TPIN–
XTALIN
Ω
Ω
Ω
Ω
DDO
V
0.01 µF
220
220
RJ-45
1:1
Ω
Ω
0.01 µF
1:1
0.01 µF
Ω
75
0.01 µF
Ω
75
0.01 µF
75
Ω
Ω
75
0.01 µF
1
2
3
4
5
6
7
8
Figure 3. Typical Single-Channel Twisted-Pair (TP) Interface
5-5433(F).r9
Lucent Technologies Inc. 9
LU3X54FTL Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000
Description
(continued)
Single-Channel Fiber-Optic Interface
LU3X54FTL
88 87
TPOUT+
50
50
TPOUT–
FOSD
TPIN+
TPIN–
Ω
Ω
DDO
V
Ω
220
Ω
220
0.01 µF
82
130
DDA
V
0.01 µF
TD
Ω
Ω
Ω
82
130
Ω
Ω
Ω
82
0.01 µF
Ω
130
50
50
Ω
TDN
SD
RD
RDN
XTALOUT
33 pF 33 pF
25 MHz
XTALIN
Figure 4. Typical Single-Channel Fiber-Optic Interface
5-5433(F).dr2
10 Lucent Technologies Inc.
Data Sheet LU3X54FTL
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX
Description
(continued)
Block Diagrams
Smart Bused MII Mode
10/100 Mbits/s
SMART
REPEATER
RX_CLK10
RXD_10
TX_CLK10
TXD_10
CRS_10/100
RX_EN10/100
TX_EN10/100
COL_10/100
SECURITY10/100
TX_CLK25
TXD_100[3:0]
TX_ER
RX_CLK25
RXD_100[3:0]
RX_DV
RX_ER
MDC
MDIO
RX_CLK10
RXD_10
TX_CLK10
TXD_10
4
4
4
4
4
CRS_100
RX_EN100
TX_EN100
COL_100
TX_EN10/SECURITY_10/100
TX_CLK25
TXD_100[3:0]
TX_ER
RX_CLK25
RXD_100[3:0]
RX_DV
RX_ER
MDC
MDIO
LU3X54FTL
SMART_MODE_SELECT
BUSED_MII_MODE
Figure 5. Smart 10/100 Mbits/s Bused MII Mode
5-5599.gr1
Lucent Technologies Inc. 11
LU3X54FTL Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000
Description
(continued)
Separate Bused MII Mode
10 Mbits/s
REPEATER
100 Mbits/s
REPEATER
RX_CLK10
RXD_10
TX_CLK10
TXD_10
COL_10
CRS_10
RX_EN10
TX_EN10
CRS_100
TX_EN100
TX_CLK25
TXD_100[3:0]
TX_ER
RX_CLK25
RXD_100[3:0]
RX_DV
RX_ER
COL_100
RX_EN100
RX_CLK10
RXD_10
TX_CLK10
4
4
4
4
4
4
4
4
TXD_10
COL_10
CRS_10
RX_EN10
TX_EN10
CRS_100
TX_EN100
TX_CLK25
TXD_100[3:0]
TX_ER
RX_CLK25
RXD_100[3:0]
RX_DV
RX_ER
COL_100
RX_EN100
LU3X54FTL
MANAGEMENT
MDC
MDIO
SMART_MODE_SELECT
BUSED_MII_MODE
MDC
MDIO
Figure 6. Separate 10/100 Mbits/s Bused MII Mode
5-5599.ar7
12 Lucent Technologies Inc.
Data Sheet LU3X54FTL
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX
Pin Information
Pin Diagram for Normal MII Mode
RXD[1][B]
RXD[2][B]
RXD[3][B]
VDD3
MII_EN[B]
TXLED[A]/REF_SEL
VSS
TXLED[B]/SCRAM_DESC_BYPASS
TXLED[C]/ENC_DEC_BYPASS
TXLED[D]/CARIN_EN
VDD167
RXLED[A]/FX_MODE_EN[A]
RXLED[B]/FX_MODE_EN[B]
RXLED[C]/FX_MODE_EN[C]
RXLED[D]/FX_MODE_EN[D]
VDD
COLED[A]
COLED[B]
COLED[C]
COLED[D]
VSS
GNDC
VDDC
VDDC
GNDC
GNDA
ATEST[A]
ATEST[B]
VDDA
VSS
LINKLED[A]/NO_LP
LINKLED[B]/PHYADD[0]
LINKLED[C]PHYADD[1]
LINKLED[D]/PHYADD[2]
SPEEDLED[A]/ISOLATE_MODE
SPEEDLED[B]/BUSED_MII_MODE
SPEEDLED[C]/SMART_MODE_SELECT
SPEEDLED[D]/SPEED
VDD
3ST_EN
AUTO_EN
H_DUPLED[A]/CLK20_SEL
H_DUPLED[B]/CRS_SEL
H_DUPLED[C]/SERIAL_SEL
H_DUPLED[D]/FULL_DUP
VDD
RESET
MODE[0]
MODE[1]
MODE[2]
MODE[3]
VSS
157
158
159
160
161
162
163
164
165
166
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
GNDA
FOSD[C]
FOSD[D]
VDDA
TPIN+/FOIN+[D]
TPIN–/FOIN–[D]
GNDA
VDDA
TPIN+/FOIN+[C]
TPIN–/FOIN–[C]
GNDA
VDDA
BGREF[0]
GNDA
VDDA
TPIN+/FOIN+[B]
TPIN–/FOIN–[B]
GNDA
VDDA
TPIN+/FOIN+[A]
TPIN–/FOIN–[A]
GNDA
VDDA
GNDA
BGREF[1]
GNDD
CLK20
VDDD
GNDAA
VDDAA
TPOUT+/FOOUT+[D]
TPOUT–/FOOUT–[D]
TPOUT+/FOOUT+[C]
TPOUT–/FOOUT–[C]
TPOUT+/FOOUT+[B]
TPOUT–/FOOUT–[B]
TPOUT+/FOOUT+[A]
TPOUT–/FOOUT–[A]
GNDO
VDDO
GNDO
VDDO
GNDM
VDDM
GNDAP
ISET_10
ISET_100
VDDAP
GNDO
VDDO
GNDO
VDDO
208
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
56
55NC54
53
61
60
59
58
57
66
65
64
63
62
71
70
69
68
67
73
72
LU3X54FTL
77
74
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
84
83
82
81
80
79
78
103
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
VSS
RXD[0][B]
RX_CLK[B]
RX_ER[B]/RXD[4][B]
VDD3
RX_DV[B]
COL[B]
CRS[B]
TX_CLK[B]
VSS
TX_EN[B]
TX_ER[B]/TXD[4][B]
VDD
TXD[3][B]
TXD[2][B]
VSS
TXD[1][B]
TXD[0][B]
MII_EN[A]
VDD3
RXD[3][A]
RXD[2][A]
RXD[1][A]
VSS
RXD[0][A]
RX_CLK[A]
RX_ER[A]/RXD[4][A]
VDD3
RX_DV[A]
COL[A]
CRS[A]
TX_CLK[A]
VSS
TX_EN[A]
TX_ER[A]/TXD[4][A]
VDD3
TXD[3][A]
TXD[2][A]
VSS
TXD[1][A]
TXD[0][A]
VSS
REF10
MDC
MDIO
VDD
MII_EN[D]
RXD[3][D]
RXD[2][D]
RXD[1][D]
VSS
RXD[0][D]
VDD
TXD[3][D]
TX_ER[D]TXD[4][D]
TX_EN[D]
VSS
VDD3
COL[D]
CRS[D]
RX_DV[D]
TX_CLK[D]
RX_CLK[D]
RX_ER[D]/RXD[4][D]
5-5616(F).cr3
VDD3
TXD[3][C]
TX_EN[C]
TX_ER[C]/TXD[4][C]
VSS
COL[C]
CRS[C]
RX_DV[C]
TX_CLK[C]
VSS
MODE[4]
TXD[2][C]
TXD[1][C]
TXD[0][C]
MASK_STAT_INT
VDD3
RX_CLK[C]
RX_ER[C]/RXD[4][C]
VSS
RXD[0][C]
VSS
VDD
CKREF
VDDPLL
RXD[3][C]76RXD[2][C]75RXD[1][C]
MII_EN[C]
VSSPD
VDDPD
VSSPLL
FOSD[B]85FOSD[A]
VSS
TXD[2][D]
TXD[1][D]
TXD[0][D]
XTALOUT
LSCLK/XTALIN
Figure 7. LU3X54FTL Pinout for Normal MII Mode
Lucent Technologies Inc. 13
LU3X54FTL Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000
Pin Information
(continued)
Pin Diagram for Bused MII Mode
VDD
3ST_EN
AUTO_EN
H_DUPLED[A]/CLK20_SEL
H_DUPLED[B]/CRS_SEL
195
196
197
198
199
66NC65
64
63NC62
GNDA
FOSD[C]
FOSD[D]
VDDA
TPIN+/FOIN+[D]
TPIN–/FOIN–[D]
GNDA
VDDA
TPIN+/FOIN+[C]
TPIN–/FOIN–[C]
GNDA
VDDA
BGREF[0]
GNDA
VDDA
TPIN+/FOIN+[B]
TPIN–/FOIN–[B]
GNDA
VDDA
TPIN+/FOIN+[A]
TPIN–/FOIN–[A]
GNDA
VDDA
GNDA
BGREF[1]
GNDD
CLK20
VDDD
GNDAA
VDDAA
TPOUT+/FOOUT+[D]
TPOUT–/FOOUT–[D]
TPOUT+/FOOUT+[C]
TPOUT–/FOOUT–[C]
TPOUT+/FOOUT+[B]
TPOUT–/FOOUT–[B]
TPOUT+/FOOUT+[A]
TPOUT–/FOOUT–[A]
GNDO
VDDO
GNDO
VDDO
GNDM
VDDM
GNDAP
ISET_10
ISET_100
VDDAP
GNDO
VDDO
GNDO
VDDO
VSS
MODE[3]
207
208
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
VDD
RESET
MODE[0]
MODE[1]
MODE[2]
206
55NC54
H_DUPLED[D]/FULL_DUP
H_DUPLED[C]/SERIAL_SEL
200
201
202
203
204
205
61
59
58
56
COLED[D]
176
COLED[C]
175
COLED[B]
174
COLED[A]
173
VDD
172
VSS
ATEST[A]
ATEST[B]
LINKLED[A]/NO_LP
LINKLED[B]/PHYADD[0]
SPEEDLED[D]/SPEED
194
LINKLED[C]PHYADD[1]
LINKLED[D]/PHYADD[2]
SPEEDLED[A]/ISOLATE_MODE
SPEEDLED[B]/BUSED_MII_MODE
SPEEDLED[C]/SMART_MODE_SELECT
183
184
185
186
187
188
189
190
191
192
193
182
GNDC
180
181
179
GNDC
177
178
VSS
VDDC
VDDC
GNDA
VDDA
LU3X54FTL
89
88
87
86
84
83
82
81
80
79
78
77
75
74
73
72NC71NC70
69NC68
67
RXLED[D]/FX_MODE_EN[D]
171
VDD167
TXLED[D]/CARIN_EN
RXLED[A]/FX_MODE_EN[A]
RXLED[B]/FX_MODE_EN[B]
RXLED[C]/FX_MODE_EN[C]
168
169
170
94
92
91
TXLED[A]/REF_SEL
TXLED[C]/ENC_DEC_BYPASS
TXLED[B]/SCRAM_DESC_BYPASS
162
163
164
165
166
99NC98
97
96NC95
RX_EN100[B]/RX_EN10/100[B]
161
100
VDD3
160
102NC101
NC
157NC158NC159
VSS
156
RXD_10
155
RX_CLK10
154
NC
153
VDD3
152
NC
151
COL_100[B]/COL_10/100[B]
150
CRS_100[B]/CRS_10/100[B]
149
TX_CLK10
148
VSS
147
TX_EN100[B]/TX_EN10/100
146
NC
145
VDD
144
NC
143
NC
142
VSS
141
NC
140
TXD_10
139
RX_EN100[A]/RX_EN10/100[A]
138
VDD3
137
RXD_100[3]
136
RXD_100[2]
135
RXD_100[1]
134
VSS
133
RXD_100[0]
132
RX_CLK25
131
RX_ER
130
VDD3
129
RX_DV
128
COL_100[A]/COL_10/100[A]
127
CRS_100[A]/CRS_10/100[A]
126
TX_CLK25
125
VSS
124
TX_EN100[A]/TX_EN10/100
123
TX_ER
122
VDD3
121
TXD_100[3]
120
TXD_100[2]
119
VSS
118
TXD_100[1]
117
TXD_100[0]
116
VSS
115
REF10
114
MDC
113
MDIO
112
VDD
111
RX_EN100[D]/RX_EN10/100[D]
110
CRS_10[D]
109
CRS_10[C]
108
CRS_10[B]
107
VSS
106
CRS_10[A]
105
104NC103
VSS
VDD3
VSS
COL_10[B]
COL_10[A]
RX_EN10[D]60RX_EN10[C]
VDD3
VSS
TX_EN100[C]/TX_EN10/100
COL_100[C]/COL_10/100[C]
CRS_100[C]/CRS_10/100[C]
VSS
MODE[4]
RX_EN10[B]57RX_EN10[A]
MASK_STAT_INT
VSS
VDD
CKREF
VDDPLL
COL_10[D]76COL_10[C]
RX_EN100[C]/RX_EN10/100[C]
VSSPLL
VDDPD
VSSPD
FOSD[B]85FOSD[A]
VSS
XTALOUT
LSCLK/XTALIN
TX_EN10[B]/SECURITY_10/10090TX_EN10[A]/SECURITY_10/100
VSS
VDD
TX_EN100[D]/TX_EN10/100
CRS_100[D]/CRS_10/100[D]
TX_EN10[D]/SECURITY_10/10093TX_EN10[C]/SECURITY_10/100
NC
VDD3
COL_100[D]/COL_10/100[D]
5-5616(F).dr2
Figure 8. LU3X54FTL Pinout for Bused MII Mode
14 Lucent Technologies Inc.
Data Sheet LU3X54FTL
July 2000 QUAD-FET for 10Base-T/100Base-TX/FX
Pin Information
(continued)
Pin Maps
Table 2. LU3X54FTL Pin Maps
Normal Mode Pins Bused Mode Pins 10/100 Mbits/s Smart Mode Pins Separate Mode Pins
RXD[3:0][D] CRS_10[D:A] Not used CRS_10
CRS[D:A] CRS_100[D:A] CRS_10/100 CRS_100
TXD[3:0][C] RX_EN10/100 Not used RX_EN10
MII_EN[D:A] RX_EN100[D:A] RX_EN10/100 RX_EN100
TXD[3:0][D] TX_EN10[D:A] SECURITY_10/100 TX_EN10
TX_EN[D:A] TX_EN100[D:A] TX_EN10/100 TX_EN100
RXD[3:0][C] COL_10[D:A] Not used COL_10
COL[D:A] COL_100[D:A] COL_10/100 COL_100
SPEEDLED[C] SMART_MODE_SELECT SMART_MODE_SELECT SMART_MODE_SELECT
SPEEDLED[B] BUSED_MII_MODE BUSED_MII_MODE BUSED_MII_MODE
TX_CLK[A] TX_CLK25 TX_CLK25 TX_CLK25
TX_CLK[B] TX_CLK10 TX_CLK10 TX_CLK10
RX_CLK[B] RX_CLK10 RX_CLK10 RX_CLK10
RX_CLK[A] RX_CLK25 RX_CLK25 RX_CLK25
RXD[0][B] RXD_10 RXD_10 RXD_10
RXD[3:0][A] RXD_100[3:0] RXD_100 RXD_100
RX_DV[A] RX_DV RX_DV RX_DV
RX_ER[A] RX_ER RX_ER RX_ER
TXD[0][B] TXD_10 TXD_10 TXD_10
TXD[3:0][A] TXD_100[3:0] TXD_100 TXD_100
TX_ER[A]/TXD[4][A] TX_ER TX_ER TX_ER
Lucent Technologies Inc. 15
LU3X54FTL Data Sheet
QUAD-FET for 10Base-T/100Base-TX/FX July 2000
Pin Information
(continued)
Pin Descriptions
This section describes the LU3X54FTL signal pins. Note that any register bit referenced includes the register number and bit position. For example, register bit [29.8] is register 29, bit 8.
Table 3. MII/Serial Interface Pins in Normal MII Mode (Four Separate MII Ports)
Pin Signal Type Description
100
67
150
127
99
66
149
126
104
71
154
131
109
76
159
136
108
75
158
135
107
74
157
134
105
72
155
132
101
68
151
128
103
70
153
130
COL[D:A] O
CRS[D:A] O
RX_CLK[D:A] O
RXD[3:0][D:A] O
RX_DV[D:A] O
RX_ER[D:A]/
RXD[4][D:A]
Collision Detect.
This signal signifies in half-duplex mode that a collision
has occurred on the network. COL is asserted high whenever there is
transmit and receive activity on the UTP media. COL is the logical AND of
TX_EN and receive activity, and is an asynchronous output. When
SERIAL_SEL is high and in 10Base-T mode, this signal indicates the jabber timer has expired.
Carrier Sense.
When CRS_SEL is low, this signal is asserted high when
either the transmit or receive medium is nonidle. This signal remains
asserted throughout a collision condition. When CRS_SEL is high, CRS is
asserted on receive activity only . CRS_SEL is set via the MII management
interface or the CRS_SEL pin.
Receive Clock.
25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output
in 10 Mbits/s nibble mode, 10 MHz in 10 Mbits/s serial mode. RX_CLK has
a worst-case 45/55 duty cycle. RX_CLK provides the timing reference for
the transfer of RX_DV, RXD, and RX_ER signals.
Receive Data
. 4-bit parallel data outputs that are synchronous to RX_CLK.
When RX_ER[D:A] is asserted high in 100 Mbits/s mode, an error code will
be presented on RXD[3:0][D:A] where appropriate. The codes are as follows:
■
Packet errors: ERROR_CODES = 2h.
■
Link errors: ERROR_CODES = 3h. (Packet and link error codes will only
be repeated if registers [29.9] and [29.8] are enabled.)
■
Premature end errors: ERROR_CODES = 4h.
■
Code errors: ERROR_CODES = 5h.
When SERIAL_SEL is active-high and 10 Mbits/s mode is selected, RXD[0]
is used for data output and RXD[3:1] are 3-stated.
Receive Data Valid.
When this pin is high, it indicates the LU3X54FTL is
recovering and decoding valid nibbles on RXD[3:0], and the data is synchronous with RX_CLK. RX_DV is synchronous with RX_CLK. This pin is
not used in serial 10 Mbits/s mode.
Receive Error.
O
When high, RX_ER indicates the LU3X54FTL has detected
a coding error in the frame presently being transferred. RX_ER is synchronous with RX_CLK.
Receive Data[4].
When encoder/decoder bypass (ENC_DEC_BYP ASS) is
selected through the MII management interface, this output serves as the
RXD[4] output. This pin is only valid when the LU3X54FTL is in 100 Mbits/s
mode.
16 Lucent Technologies Inc.
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