AGERE 2417J4A Datasheet

Data Sheet, Rev. 1

August 2001

NetLight

®

2417J4A 1300 nm Laser

Gigabit Transceiver

Available in a smal l form-factor, RJ-45 size, plastic packa ge,
the 2417J4A Transceiver is a high-perf ormance, cost­effective optic al transceiv er for Gigabit Ethern et 1000Base-LX
applications.

Features

■

Gigabit Ethernet 1000Base-LX compliant

■

Small form factor (SFF), RJ-45 size, multisourced
10-pin package

■

LC duplex receptacle

■

Uncooled 1300 nm laser transmitter with automatic
output power control

■

Transmitter disable input

■

TTL signal-detect output

■

Low power dissipation

■

Single 3.3 V power supply

■

Raised ECL (LVPECL) logic data interfaces

■

Operating temperature range: 0 °C to
70 °C

■

Agere Systems Inc. Reliability and Qualification
Program for built-in quality and reliability

Description

The 2417J4A transceiver is a high-speed, cost-effec­tive optical transceiver that is compliant with the

®

IEEE

802.3z Gigabit Ethernet Physical Medium
Dependent (PMD) 1000Base-LX spe cifications usi ng
a long-wav elength laser. The transceiver featur es the
latest generation of Agere Systems optics and is
packaged in a narrow-width plastic housing with an
LC duplex receptacle. This receptacle fits into an
RJ-45 form-factor outline. The 10-pin package and
pinout conform to a multisource transceiver agree­ment.

The transmitter features differential LVPECL logic
level data inputs and an LVTTL logic level disable
input. The receiver f eatu res differential L VPECL logic
level data outputs and an LVTTL logic level signal­detect output.

■

Wide dynamic range receiver with InGaAs PIN
photodetector

NetLight

2417J4A 1300 nm Laser Data Sheet, Rev. 1

Gigabit Transceiver August 2001

Absolute Maximum Rat ings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso­lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations s ections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.

Parameter Symbol Min Max Unit

Supply Voltage V
Operating Temperature Range T
Storage Case Temperature Range T

CC

stg

03.6V

C

070°C

–40 85 °C
Lead Soldering Temperature/Time — — 250/10 °C/s
Operating Wavelength Range λ 1.1 1.6 µm

Pin Information

Figure 1. 2417J4A Transceiver, 10-Pin Configuration, Top View

Table 1. Transceiver Pin Descriptions

Pin

Number

MS MS

Symbol Name/Description

Mounting Studs.

cal attachment to the circuit board. They may also provide an optional con-

nection of the transceiver to the equipment chassis ground.
1V
2V

EER
CCR

3SD

Receiver Signal Ground

Receiver Power Supply.

Signal Detect.

Normal operation: logic one output.

Fault condition: logic zero output.
4RD–
5RD+

6V
7V
8T

CCT
EET

DIS

9TD+

Received DATA

Received DATA Out.

Transmitter Power Supply.

Transmitter Signal Ground

Transmitter Disable.

Transmitter DATA In.

100 Ω resistor between the TD+ and TD– pins.

10 TD–

Transmitter DATA

12345

109876

RX

TX

Receiver

The mounting studs are provided for transceiver mechani-

.NA

Out.

Transmitter

.NA

An internal termination is provided, consisting of a

In.

See TD+ pin for terminations. LVPECL

3

0

1

-

1

Logic

Family

NA

NA

LVTTL

LVPECL
LVPECL

NA

LVTTL

LVPECL

F

)

(

1

2 Agere Systems Inc.

Data Sheet, Rev. 1

NetLight

2417J4A 1300 nm Laser

August 2001 Gigabit Transceiver

Electrostatic Discharge

Caution: This device is susceptible to damage as

a result of electrostatic discharge (ESD).
Take proper precautions during both
handling and testing. Follow
dard

EIA

-625.

Although protection circuitry is designed into the
device, take proper precautions to avoid exposure to
ESD.

Agere Systems employs a human-body model (HBM)
for ESD susceptibility testing and protection-design
evaluation. ESD voltage thresholds are dependent on
the critical parameters used to define the model. A
standard HBM (resistance = 1.5 kΩ, capacitance = 100
pF) is widely used and, therefore, can be used for com­parison purposes. The HBM ESD threshold estab­lished for the 2417J4A is ±1500 V.

EIA

®

Stan-

Application Information

The 2417 receiver section is a highly sensitive fiber­optic receiver. Although the data outputs are digital
logic lev e ls (PEC L) , the device should be thought of as
an analog component. When laying out system appli­cation boards, the 2417 transceiver should receive the
same type of consideration one would give to a sensi­tive analog component.

Printed-Wiring Board Layout Consider­ations

A fiber-optic receiver employs a very high gain, wide
bandwidth transimpedance amplifier. This amplifier
detects and amplifies signals that are only tens of nA in
amplitude when the receiver is operating near its sensi­tivity limit. Any unwanted signal currents that couple
into the receiver circuitry cause a decrease in the
receiver's sensitivity and can also degrade the perfor­mance of the receiver's signal detect (SD) circuit. To
minimize the coupling of unwanted noise into the
receiver, careful attention must be given to the printed­wiring board layout.

Multilayer construction also permits the routing of sen­sitive signal traces away from high-level, high-speed
signal lines. To minimize the possibility of coupling
noise into the receiver section, high-level, high-speed
signals such as transmitter inputs and clock lines
should be routed as far away as possible from the
receiver pins.

Noise that couples into the receiver through the power
supply pins can also degrade performance. It is
recommended that the pi filter, shown in Figure 2, be
used for both the transmitter and receiver power
supplies.

Data and Signal Detect Outputs

The data and signal detect outputs of the 2417 trans­ceiver are driven by open-emitter NPN transistors,
which have an outpu t impedance of appr o xima tely 7 Ω.
Each output can provide approximately 50 mA maxi­mum current to a 50 Ω. load terminated to V

Due to the high switching speeds of ECL outputs,
transmission line design must be used to interconnect
components. To ensure optimum signal fidelity, both
data outputs (RD+/RD–) should be terminated identi­cally. The signal lines connecting the data outputs to
the next device should be equal in length and have
matched impedances. Controlled impedance stripline
or microstrip construction must be used to preserve the
quality of the signal into the next component and to
minimize reflections bac k int o the receiver, which could
degrade its performance. Excessive ringing due to
reflections caused by improperly terminated signal
lines makes it difficult for the component receiving
these signals to decipher the proper logic levels and
can cause transitions to occur where none we re
intended. Also, by minimizing high-frequency ringing,
possible EMI problems can be avoided.

The signal-detect output is positiv e LVTTL logic. A logic
low at this output indicates that the optical signal into
the receiver has been interrupted or that the light level
has fallen below the minimum signal detect threshold.
This output should not be used as an error rate indica­tor since its switching threshold is determined only by
the magnitude of the incoming optical signal.

– 2.0 V.

CC

At a minimum, a double-sided printed-wiring board
(PWB) with a large component-side ground plane
beneath the transceiver must be used. In applications
that include many other high-speed devices, a multi­layer PWB is highly recommended. This permits the
placement of power and ground on separate layers,
which allows them to be isolated from the signal lines.

Agere Systems Inc. 3