AGERE 1417K4A Datasheet
®
NetLight
1417K4A 1300 nm Laser
2.5 Gbits/s Transceiver
Advance Data Sheet
January 2000
■
Wide dynamic range receiver with InGaAs PIN
photodetector
■
TTL signal-detect output
■
Low power dissipation
■
Single 3.3 V power supply
■
LVPECL/CML compatible data inputs and CML
compatible data outputs
■
Operating temperature range: 0 °C to 70 °C
Avail a ble in a small form factor, RJ-45 size, plastic package,
the 1417K4A Transceiver is a high-performance, cost-effective, optical transceiver for SONET applications.
Features
■
SONET SR OC-48, SDH I-16 applications
■
High-speed, optical data interface for shelf-to-shelf
interconnect
■
Small form factor, RJ-45 size, 10-pin package
■
LC duplex receptacle
■
Uncooled 1300 nm laser transmitter with automatic
output power control
■
Transmitter disable input
■
Agere Systems Inc. Reliability and Qualification
Program for built-in quality and reliability
Description
The 1417K4A transceiver is a high-speed, cost-effective optical transceiver intended for 2.488 Gbits/s
shelf-to-shelf optical interconnect applications as well
as SONET SR OC-48 and SDH I-16. The transceiver
features proven Agere Systems’ optics and is packaged in a narrow-width plastic housing with an LC
duplex receptacle. The receptacle fits into an RJ-45
form factor outline. The 10-pin package pinout conforms to a multisource transceiver agreement.
The transmitter features the ability to interface to both
LVPECL and CML differential logic level data inputs.
It also features a TTL logic level disable input. The
receiver features differential CML logic level outputs
and a TTL logic level signal-detect output.
Advance Data Sheet
NetLight
1417K4A 1300 nm Laser
January 2000 2.5 Gbits/s Transceiver
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter Symbol Min Max Unit
Supply Voltage V
Operating Temperature Range* T
Storage Temperature Range T
CC
A
stg
05V
070°C
–40 85 °C
Lead Soldering Temperature/Time — — 250/10 °C/s
Operating Wavelength Range λ 1.1 1.6 µm
* Under conditions of 2 m/s forced airflow .
Pin Information
Figure 1. 1417K4A Transceiver, 10-Pin Configuration, Top View
Table 1. Transceiver Pin Descriptions
Pin
Number
MS MS
Symbol Name/Description
Mounting Studs.
cal attachment to the circuit board. They may also provide an optional con-
nection of the transceiver to the equipment chassis ground.
1V
2V
EER
CCR
3SD
Receiver Signal Ground.
Receiver Power Supply.
Signal Detect.
Normal operation: logic one output.
Fault condition: logic zero output.
4RD–
5 RD+
6V
7V
8T
CCT
EET
DIS
9TD+
Received
Received DATA Out.
Transmitter Power Supply.
Transmitter Signal Ground.
Transmitter Disable.
Transmitter DATA In
DATA
a 100 Ω resistor between the TD+ and TD– pins.
10 TD–
Transmitter
12345
109876
RX
TX
Receiver
The mounting studs are provided for transceiver mechani-
Out.
Transmitter
. An internal 50 Ω termination is provided, consisting of
In
DATA
. See TD+ pin for terminations. LVPECL
1-967
Logic
Family
NA
NA
NA
LVTTL
CML
CML
NA
NA
LVTTL
LVPECL
or CML
or CML
2
Agere System s Inc.
NetLight
DATA
SINGLE ENDED
V
OH
V
OL
DATA
V
OH
V
OL
DIFFERENTIAL
1417K4A 1300 nm Laser Advance Data Sheet
2.5 Gbits/s Transceiver January 2000
Electrostatic Discharge
Caution: This device is susceptible to damage as
a result of electrostatic discharge (ESD).
Take proper precautions during both
handling and testing. Follow
dard
EIA
-625.
EIA
®
Stan-
Although protection circuitry is designed into the
device, take proper precautions to avoid exposure to
ESD .
Agere Systems employs a human-body model (HBM)
for ESD susceptibility testing and protection-design
evaluation. ESD voltage thresholds are dependent on
the critical parameters used to define the model. A
standard HBM (resistance = 1.5 kΩ, capacitance =
100 pF) is widely used and, therefore, can be used for
comparison purposes. The HBM ESD threshold established for the 1417K4A transceiver is ±1000 V.
Application Information
The 1417 receiver section is a highly sensitive fiberoptic receiver. Although the data outputs are digital
logic levels (CML), the device should be thought of as
an analog component. When laying out system application boards, the 1417 transceiver should receive the
same type of consideration one would give to a sensitive analog component.
Printed-Wiring Board Layout Considerations
A fiber-optic receiver employs a very high gain, widebandwidth transimpedance amplifier. This amplifier
detects and amplifies signals that are only tens of nA in
amplitude when the receiver is operating near its sensitivity limit. Any unwanted signal currents that couple
into the receiver circuitry cause a decrease in the
receiver's sensitivity and can also degrade the performance of the receiver's signal detect (SD) circuit. To
minimize the coupling of unwanted noise into the
receiver, careful attention must be given to the printedwiring board.
Multilayer construction also permits the routing of sensitive signal traces away from high-level, high-speed
signal lines. To minimize the possibility of coupling
noise into the receiver section, high-level, high-speed
signals such as transmitter inputs and clock lines
should be routed as far away as possible from the
receiver pins.
Noise that couples into the receiver through the power
supply pins can also degrade performance. It is recommended that a pi filter, shown in Figure 3, be used for
both the transmitter and receiver power supplies.
Data and Signal Detect Outputs
Due to the high switching speeds of CML outputs,
transmission line design must be used to interconnect
components. To ensure optimum signal fidelity, both
data outputs (RD+/RD–) should be terminated identically. The signal lines connecting the data outputs to
the next device should be equal in length and have
matched impedances. Controlled impedance stripline
or microstrip construction must be used to preserve the
quality of the signal into the next component and to
minimize reflections back into the receiver, which could
degrade its performance. Excessive ringing due to
reflections caused by improperly terminated signal
lines makes it difficult for the component receiving
these signals to decipher the proper logic levels and
can cause transitions to occur where none were
intended. Also, by minimizing high-frequency ringing,
possible EMI problems can be avoided.
The signal-detect output is positive LVTTL logic. A logic
low at this output indicates that the optical signal into
the receiver has been interrupted or that the light level
has fallen below the minimum signal-detect threshold.
This output should not be used as an error rate indicator, since its switching threshold is determined only by
the magnitude of the incoming optical signal.
At a minimum, a double-sided printed-wiring board
(PWB) with a large component-side ground plane
beneath the transceiver must be used. In applications
that include many other high-speed devices, a multilayer PWB is highly recommended. This permits the
placement of power and ground on separate layers,
which allows them to be isolated from the signal lines.
Agere Systems Inc.
Figure 2. Data Input/Output Logic Level Definitions
3
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