AGERE 1417H4A, 1417G4A Datasheet

®

NetLight

1417G4A and 1417H4A

ATM/SONET/SDH Transceivers

Data Sheet

January 2000

■

Signal-detect output

■

Low power dissipation

■

Raised ECL (PECL) logic data interfaces

■

Operating case temperature range: –40 °C to
+85 °C

■

Agere Systems Inc. Reliability and Qualification
Program for built-in quality and reliability

Avail a ble in a small form factor, RJ-45 size, plastic package,
the 1417G4A and 1417H4A are high-performance, cost-effec­tive transceivers for ATM/SONET/SDH applications at
155 Mbits/s and 622 Mbits/s.

Features

■

ATM/SONET/SDH Compliant (ITU-T G.957 Speci­fications):
— IR-1/S1.1, S4.1

■

Small form factor, RJ-45 size, multisourced 10-pin
package

■

Requires single 3.3 V power supply

■

LC duplex receptacle

■

Uncooled 1300 nm laser transmitter with automatic
output power control

■

Transmitter disable input

■

Wide dynamic range receiver with InGaAs PIN
photodetector

Description

The 1417G4A and 1417H4A transceivers are high­speed, cost-effective optical transceivers that are
compliant with the International Telecommunication
Union Telecommunication (ITU-T) G.957 specifica­tions for use in ATM, SONET, and SDH applications.
The 1417G4A operates at the OC-3/STM-1 rate of
155 Mbits/s, and the 1417H4A operates at the
OC-12/STM-4 rate of 622 Mbits/s. The transceivers
feature Agere Systems’ high-reliability optics and are
packaged in a narrow-width plastic housing with an
LC duplex receptacle. This receptacle fits into an RJ­45 form factor outline. The 10-pin package and
pinout conform to a multisource transceiver agree­ment.

The transmitter features differential PECL logic level
data inputs and a TTL logic level disable input. The
receiver features differential PECL logic level data
and a PECL logic level signal-detect output for the
1417G4A, and a TTL logic level signal-detect output
for the 1417H4A.

Data Sheet

NetLight

1417G4A and 1417H4A

January 2000 ATM/SONET/SDH Transceivers

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso­lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.

Parameter Symbol Min Max Unit

Supply Voltage V
Operating Case Temperature Range T
Storage Case Temperature Range T

CC

C

stg

03.6V
–40 85 °C
–40 85 °C

Lead Soldering Temperature/Time — — 250/10 °C/s
Operating Wavelength Range λ 1.1 1.6 µm

Pin Information

TX

RX

Figure 1. 1417G4A and 1714H4A Transceivers, 10-Pin Configuration, Top View

Table 1. Transceiver Pin Descriptions

Pin

Number

MS MS

Symbol Name/Description Logic Family

Mounting Studs.

mechanical attachment to the circuit board. They may also provide an
optional connection of the transceiver to the equipment chassis

ground.
1V
2V

EER
CCR

3SD

Receiver Signal Ground.

Receiver Power Supply.

Signal Detect.

Normal operation: logic one output.

Fault condition: logic zero output.

4 RD–
5 RD+

6V
7V
8T

CCT
EET

DIS

9TD+

10 TD–

Received

Received DATA Out.

Transmitter Power Supply.

Transmitter Signal Ground.

Transmitter Disable.

Transmitter DATA In

Transmitter

DATA

DATA

109876

10-PIN MODULE - TOP VIEW

12345

Receiver

The mounting studs are provided for transceiver

Out.

Transmitter

. LVPECL

In

. LVPECL

1-967.a

NA

NA
NA

LVTTL

(1417H4A);

LVPECL

(1417G4A)

LVPECL
LVPECL

NA
NA

LVTTL

2

Agere System s Inc.

NetLight

1417G4A and 1417H4A Data Sheet

ATM/SONET/SDH Transceivers January 2000

Electrostatic Discharge

Caution: This device is susceptible to damage as

a result of electrostatic discharge (ESD).
Take proper precautions during both
handling and testing. Follow
dard

EIA

-625.

Although protection circuitry is designed into the
device, take proper precautions to avoid exposure to
ESD .

Agere Systems employs a human-body model (HBM)
for ESD susceptibility testing and protection-design
evaluation. ESD voltage thresholds are dependent on
the critical parameters used to define the model. A
standard HBM (resistance = 1.5 kΩ, capacitance =
100 pF) is widely used and, therefore, can be used for
comparison purposes. The HBM ESD threshold estab­lished for the 1417G4A and 1417H4A transceivers is
±1000 V.

EIA

®

Stan-

Application Information

The 1417 receiver section is a highly sensitive fiber­optic receiver. Although the data outputs are digital
logic levels (PECL), the device should be thought of as
an analog component. When laying out system appli­cation boards, the 1417 transceiver should receive the
same type of consideration one would give to a sensi­tive analog component.

Printed-Wiring Board Layout Considerations

A fiber-optic receiver employs a very high gain, wide
bandwidth transimpedance amplifier. This amplifier
detects and amplifies signals that are only tens of nA in
amplitude when the receiver is operating near its sensi­tivity limit. Any unwanted signal currents that couple
into the receiver circuitry cause a decrease in the
receiver's sensitivity and can also degrade the perfor­mance of the receiver's signal detect (SD) circuit. To
minimize the coupling of unwanted noise into the
receiver, careful attention must be given to the printed­wiring board layout.

Multilayer construction also permits the routing of sen­sitive signal traces away from high-level, high-speed
signal lines. To minimize the possibility of coupling
noise into the receiver section, high-level, high-speed
signals such as transmitte r inputs and clock lines
should be routed as far away as possible from the
receiver pins.

Noise that couples into the receiver through the power
supply pins can also degrade performance. It is recom­mended that the pi filter, shown in Figure 2, be used for
both the transmitter and receiver power supplies.

Data and Signal Detect Outputs

The data and signal detect outputs of the 1417 trans­ceiver are driven by open-emitter NPN transistors,
which have an output impedance of approximately 7 Ω.
Each output can provide approximately 50 mA maxi­mum current to a 50 Ω load terminated to V

Due to the high switching speeds of ECL outputs,
transmission line design must be used to interconnect
components. To ensure optimum signal fidelity, both
data outputs (RD+/RD–) should be terminated identi­cally. The signal lines connecting the data outputs to
the next device should be equal in length and have
matched impedances. Controlled impedance stripline
or microstrip construction must be used to preserve the
quality of the signal into the next component and to
minimize reflections back into the receiver, which could
degrade its performance. Excessive ringing due to
reflections caused by improperly terminated signal
lines makes it difficult for the component receiving
these signals to decipher the proper logic levels and
can cause transitions to occur where none were
intended. Also, by minimizing high-frequency ringing,
possible EMI problems can be avoided.

The signal-detect output is positive ECL (PECL) logic
for the 1417G4A and TTL for the 1417H4A. A logic low
at this output indicates that the optical signal into the
receiver has been interrupted or that the light level has
fallen below the minimum signal detect threshold. This
output should not be used as an error rate indicator,
since its switching threshold is determined only by the
magnitude of the incoming optical signal.

– 2.0 V.

CC

At a minimum, a double-sided printed-wiring board
(PWB) with a large component-side ground plane
beneath the transceiver must be used. In applications
that include many other high-speed devices, a multi­layer PWB is highly recommended. This permits the
placement of power and ground on separate layers,
which allows them to be isolated from the signal lines.

Agere Systems Inc.

3