Aeroflex UTMC UTR50, UTR75, UTR100, UTR25, UTR150 Datasheet

Semicustom Products

UTR 0.8µ Gate Array Family

Preliminary Data Sheet

Jan. 2000

FEATURES

q Up to 200,000 usable equivalent gates
q Clock rates up to 180 MHz
q Advanced 0.8µ radiation-hardened silicon gate CMOS
q Operating voltage of 5V
q QML Class Q & V compliant
q Designed specifically for high reliability applications
q Radiation-hardened to 1.0E6 rads(Si) total dose

(functional) and SEU-immune cells to less than 1.0E-10
errors/bit-day

q JTAG (IEEE 1149.1) boundary-scan registers built into

I/O cells

q Low noise package technology for high speed circuits
q Design support using Mentor Graphics®, SynopsysTM and

VHDL tools on HP® and Sun® workstations

q Standard Microcircuit Drawing pending

PRODUCT DESCRIPTION

The high-performance UTR 0.8µ gate array family
features densities of up to 200,000 equivalent gates and is avail­able in MIL-PRF-38535 QML Q and V quality levels and
radiation-hardened.

For those designs requiring stringent radiation hardness,
UTR’s 0.8µ process employs a special processing module that
enhances the total dose radiation hardness of the field and gate
oxides while maintaining circuit density and reliability. In ad­dition, for both greater transient radiation-hardness and latchup
immunity, the UTR 0.8µ process is built on epitaxial substrate
wafers.

Developed from UTMC’s patented architectures, the
UTR 0.8µ array family uses a highly efficient continuous tran­sistor architecture for the internal cell construction. Combined
with state-of-the-art placement and routing tools, the
utilization of available transistors is maximized using three lev­els of metal interconnect.

The UTR 0.8µ family of gate arrays is supported by an exten­sive cell library that includes SSI, MSI, and 54XX equivalent
functions, as well as, configurable RAM and other megafunc­tions. UTMC’s megacell library includes the following
functions:

• Intel 80C31® equivalent

• MIL-STD-1553 functions (BRCTM, RTI, RTMP)

• MIL-STD-1750 microprocessor

• RISC microcontroller

• Configurable RAM

2

Table 1. Gate Densities

Notes:

1.The "R" denotes radiation-hardened.

2.Based on NAND2 equivalents. Actual usable gate count is design-dependent. Estimates reflect a mix of functions including RAM.

3.Includes five pins that may or may not be reserved for JTAG boundary-scan, depending on user requirements.

4.Reserved for dedicated VDD/VSS and V

DDQ/VSSQ

.

Low-noise Device and Package Solutions

The UTR 0.8µ output drivers feature programmable slew rate
control for minimizing noise and switching transients. This fea­ture allows the user to optimize edge characteristics to match
system requirements. Separate on-chip power and ground buses
are provided for internal cells and output drivers which further
isolate internal design circuitry from switching noise.

In addition, UTMC offers advanced low-noise package technol­ogy with multi-layer, co-fired ceramic construction featuring
built-in isolated power and ground planes. These planes provide
lower overall resistance/inductance through power and ground

paths which minimize voltage drops during periods of heavy
switching. These isolated planes also help sustain supply volt­age during dose rate events, thus preventing rail span collapse.

Flatpacks are available with up to 304 leads; PGAs are available
with up to 280 leads. UTMC’s flatpacks feature a non-conduc­tive tie bar that helps maintain lead integrity through test and
handling operations. In addition to the packages listed in Table
2, UTMC offers custom package development and package tool­ing modification services for individual requirements.

Table 2. Packages

Notes:

1. The number of device I/O pads available may be restricted by the selected package.

2. PGA packages have one additional non-connected index pin (i.e., 144 + 1 index pin = 145 total package pins for the 144 PGA).
Contact UTMC for specific package drawings.

DEVICE PART NUMBERS1EQUIVALENT USABLE GATES2SIGNAL I/O3POWER & GROUND PADS

4

UTR25 5,000 - 25,000 175 40
UTR35 35,000 175 40
UTR50 50,000 175 40

UTR75 75,000 256 80
UTR100 125,000 256 80
UTR150 150,000 256 80
UTR200 200,000 256 80

PACKAGE TYPE/LEADCOUNT

1

UTR25 UTR35 UTR50 UTR75 UTR100 UTR150 UTR200

Flatpack

84 X X X
132 X X X
172 X X X X X X X
196 X X X X X X X
224 X X X X
256 X X X X
304 X X X X

PGA

2

84 X X X
120 X X X X
144 X X X
208 X X X X X X X
280 X X X X

3

Extensive Cell Library

The UTR 0.8µ family of gate arrays is supported by an extensive
cell library that includes SSI, MSI, and 54XX-equivalent func­tions, as well as, RAM and other megafunctions. User-
selectable options for cell configurations include scan for all
register elements, as well as output drive strength. UTMC’s
megacell library includes the following functions:

• Intel® 80C31 equivalent

• MIL-STD-1553 functions (BCRTM, RTI, RTMP)

• MIL-STD-1750 microprocessor

• Standard microprocessor peripheral functions

• Configurable RAM

Refer to UTMC’s UTR 0.8µ Design Manual for complete cell
listing and details.

I/O Buffers

The UTR 0.8µ gate array family offers up to 342 device pad
locations (note: device pad availability is affected by package
selection and pinout.) The I/O cells can be configured by the
user to serve as input, output, bidirectional, three-state, or addi­tional power and ground pads. Output drive options range from
2 to 8mA. To drive larger off-chip loads, output drivers can be
combined in parallel to provide additional drive up to 12mA.

Other I/O buffer features and options include:

• Slew rate control

• Pull-up and pull-down resistors

• TTL, CMOS, and Schmitt levels

• Built-in boundary-scan

JTAG Boundary-Scan

The UTR 0.8µ arrays include a test access port and boundary­scan architecture that conforms to the IEEE Standard 1149.1
(JTAG). Some of the benefits this capability offers include the
following:

• Allows easy test of complex assembled printed circuit

boards

• Can be used to gain access to and control internal

scan paths

• Can be used to initiate Built-In Self Test

Clock Driver Distribution

UTMC design tools provide methods for balanced clock distri­bution that maximize drive capability and minimize relative
clock skew between clocked devices.

Speed and Performance

UTMC specializes in high-performance circuits designed to op­erate in harsh military and radiation environments. Table 3
presents a sampling of typical cell delays.

Note that the propagation delay for a CMOS device is a function
of its fanout loading, supply voltage, operating temperature, and
processing tolerance. In a radiation environment, additional per­formance variances must be considered. The UTR 0.8µ
simulation models account for all of these effects to accurately
determine circuit performance for its particular set of use
conditions.

Power Dissipation

Each internal gate or I/O driver has an average power consump­tion based on its switching frequency and capacitive loading.
The radiation-hardened processes exhibit power dissipation that
is typical of CMOS processes. For a rigorous power estimating
methodology, refer to the UTMC UTR 0.8µ Design Manual or
consult with a UTMC Applications Engineer.