Aeroflex UTMC UT54ACTS220 Datasheet
UT54ACTS220
Clock and Wait-State Generation Circuit
FEATURES
• 1.2µ radiation-hardened CMOS
- Latchup immune
• High speed
• Low power consumption
• Single 5-volt supply
• Available QML Q or V processes
• Flexible package
- 14-pin DIP
- 14-lead flatpack
DESCRIPTION
The UT54ACTS220 is designed to be a companion chip to
UTMC’s UT69151 SµMMIT family for the purpose of generating clock and wait-state signals. The device contains a divide
by two circuit that accepts TTL input levels and drives CMOS
output buffers. The chip accepts a 48MHz clock and generates
a 24MHz clock. The 48MHz clock can have a duty cycle that
varies by ± 20%. The UT54ACT220 generates a 24MHz clock
with a ± 5% duty cycle variation. The wait-state circuit generates
a single wait-state by delaying the falling edge of DTACK into
the SµMMIT. The clock/timing device generates DTACK from
the falling edge of input RCS which is synchronized by the
falling edge of 24MHz. The SµMMIT drives inputs RCS and
DMACK.
The devices are characterized over full military temperature
range of -55°C to +125°C.
LOGIC SYMBOL
PINOUTS
CLKOUT
CLKOUT
CLKIN
48MHz
V
NC
NC
SS
NC
CLKOUT
CLKOUT
CLKIN
NC
48MHz
V
14-Pin DIP
Top View
1 14
2 13
3 12
4 11
5 10
6 9
7 8
SS
14-Lead Flatpack
Top View
1 14
2 13
3 12
4 11
5 10
6 9
7 8
V
DD
24MHz
DTACK
TEST
MRST
RCS
DMACK
V
DD
24MHz
DTACK
TEST
MRST
RCS
DMACK
(10)
MRST
RCS
CLKIN
(6)
(9)
(8)
(4)
48MHz
DMACK
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
S
1D
S
CTR1
SRG2
(13)
(12)
(11)
(2)
(3)
24MHz
DTACK
TEST
CLKOUT
CLKOUT
145 RadHard MSI Logic
PIN DESCRIPTION
Pin Number Pin Name Description
2 CLKOUT Buffered version of CLKIN.
3 CLKOUT Inverted version of CLKIN.
4 CLKIN Clock Input. This signal can be any arbitrary signal that the user wishes to buffer.
6 48MHz 48MHz Clock. The 24MHz clock is created by dividing this signal by two.
8 DMACK DMA Acknowledge. This input is generated by the SµMMIT. When high, this signal
will cause DTACK output to be forced high.
9 RCS RAM Chip Select. This input is generated by the SµMMIT.
UT54ACTS220
10 MRST Master Reset. This input can be used to preset 24MHz, DTACK and TEST. For normal
11 TEST Test output signal.
12 DTACK Data Transfer Acknowledge. This signal can be used to drive the DTACK signal of the
13 24MHz 24MHz Clock. This output runs at half the frequency of the 48MHz input. The falling
FUNCTIONAL TIMING: Single SµMMIT Wait-State
For both read and write memory cycles, DTACK is an input to the SµMMIT E and SµMMIT LXE/DXE. A non-wait state mem-
ory requires two clock cycles, T1 and T2 of figure 1. For accessing slower memory devices, the UT54ACTS220 holds DTACK to
a logical “1”. This results in the stretching of memory cycles by one clock to three clock cycles, TW of figure 1. The SµMMIT E
and SµMMIT LXE/DXE samples the DTACK on the rising edge of the 24 MHz clock. If DTACK is not generated before the ris-
ing edge of the clock, the SµMMIT E and SµMMIT LXE/DXE extends the memory cycle.
48MHz
24MHz
operation tie MRST to VDD through a resistor.
SµMMIT if the user requires one wait state during the memory transfer.
edge of 24MHz is the signal that latches the DTACK outputs. 24MHz is forced high
whenever MRST is low. Properly loaded, 24MHz will have a 50% duty cycle ± 5%.
T
1
T
W
T
2
DMACK
RCS
DTACK
Figure 1. Functional Timing
RadHard MSI Logic 146
UT54ACTS220
LOGIC DIAGRAM
24MHz
D
Q
Q
D
DTACK
48MHz
MRST
RCS
DMACK
CLKIN
CK
RST
Q
CK
PRE
Q
Q
D
CK
Q
PRE
TEST
CLKOUT
CLKOUT
147 RadHard MSI Logic
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