Aeroflex UTMC UT54ACTS191, UT54ACS191 Datasheet
123 Rad-Hard MSI Logic
UT54ACS191/UT54ACTS191
Radiation-Hardened
Synchronous 4-Bit Up-Down Binary Counters
FEATURES
Single down/up count control line
counters
Fully synchronous in count modes
Asynchronously presetable with load control
radiation-hardened CMOS
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
DESCRIPTION
The UT54ACS191 and the UT54ACTS191 are synchronous 4bit reversible up-down binary counters. Synchronous counting
operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other
when so instructed. Synchronous operation eliminates the output counting spikes associated with asynchronous counters.
The outputs of the four flip-flops are triggered on a low-to-highlevel transition of the clock input if the enable input (CTEN) is
low. A logic one applied to CTEN inhibits counting. The direction of the count is determined by the level of the down/up
(D/U) input. When D/U is low, the counter counts up and when
D/U is high, it counts down.
The counters feature a fully independent clock circuit. Changes
at control inputs (CTEN and D/U) that will modify the operating
mode have no effect on the contents of the counter until clocking
occurs.
The counters are fully programmable. The outputs may be
preset to either logic level by placing a low on the load input
and entering the desired data at the data inputs. The output will
change to agree with the data inputs independently of the level
of the clock input. The asynchronous load allows counters to
be used as modulo-N dividers by simply modifying the count
length with the preset inputs.
Two outputs have been made available to perform the cascading
function: ripple clock and maximum/minimum (MAX/MIN)
count. The MAX/MIN output produces a high-level output
pulse with a duration approximately equal to one complete cycle
of the clock while the count is zero (all outputs low) counting
down or maximum (15) counting up.
PINOUTS
16-Pin DIP
Top View
16-Lead Flatpack
Top View
The ripple clock output (RCO) produces a low-level output
pulse under those same conditions but only while the clock input
is low. The counters easily cascade by feeding the RCO to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. Use the
MAX/MIN count output to accomplish look-ahead for highspeed operation.
The devices are characterized over full military temperature
range of -55 C to +125
1
3
5
6
15
13
10
B
B
A
D/
Q
Q
V
A
RCO
C
9
SS
LOAD
2
4
7
16
14
12
11
DD
9
Q
Q
CTEN
U
C
D
CLK
MAX/MIN
C
SS
Rad-Hard MSI Logic 124
UT54ACS191/UT54ACTS191
FUNCTION TABLE LOGIC SYMBOL
LOGIC DIAGRAM
FUNCTION LOAD CTEN D/U CLK
Count Up H L L
Count Down H L H
Asynchronous
Reset
L X X X
No Change H H X X
(4)
CTEN
(5)
D/U
M3 (UP)
G1
CTRDIV 16
(14)
CLK
(15)
A
(1)
B
(10)
C
(9)
D
(12)
MAX/MIN
(3)
Q
A
(7)
Q
D
1,2 -/1,3+
(6)
Q
C
(2)
Q
B
5D
(1)
(2)
(4)
(8)
2(CT=0)Z6
M2 (DWN)
G4
3(CT=9)Z6
(11)
LOAD C5
(13)
RCO
6,1,4
7
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
CLK
D/U
CTEN
LOAD
(11)
(9)
(10)
(1)
(4)
S
R
1J
C1
1K
(7)
(6)
(2)
(3)
(13)
(12)
Q
D
Q
C
Q
B
Q
A
MAX/MIN
RCO
A
B
C
D
(15)
(5)
(14)
S
R
1J
C1
1K
S
R
1J
C1
1K
R
1J
C1
1K
S
Q
Q
Q
Q
Q
Q
Q
Q
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