
MT70003
SINGLE CHANNEL ARINC DECODER
• 16/24 bit parallel interface
• Automatic address recognition option on
8/10 bits
• Single 5V supply with low power
consumption < 50mW
• Full MIL operating range
• Built in parity and word length error
detection
• HIGH/LOW speed programmable
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
1

MT70003
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature - 65ºC to +150ºC
Temperature (Ambient) under Bias - 55ºC to +125ºC
Supply Voltage VDD -0.3V to + 7V
DC Input Voltage -0.3 to VDD +0.3V
Output Current (Single O/P) 10mA
Output Current (Total O/P) 20mA
ELECTRICAL CHARACTERISTICS over operating range
PARAMETER DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS
IOH Output High Current VOH=2.8V VDD= 4.5V 1.0
IOL Output Low Current VOL=0.4V 3.2
VIH Input High Voltage 2.4 VCC
VIL Input Low Voltage -0.3 0.8
IIL Input Load Current VSS 0.45
IOZ Output Leakage Current
CI Input Capacitance
0.4V<VO<VCC Output Disabled
Test Frequency = 1.0 MHZ
-40 40
2 2.6
CI/O I/O Capacitance 7 9
ICC Supply Current
VCC = MAX. All inputs
HIGH, All outputs open.
1.5
mA
mA
Volts
Volts
mA
uA
pF
pF
mA
Switching Characteristics
Note Unless otherwise stated output loading assumes 50 pF capacitive plus static
current within the limits of IOH
PARAMETER DESCRIPTION MIN MAX UNITS
tRI & tFI
tHI
tLO
tLO
tRO; tFO
tAZ
tAZ
tPLH
tLO
Input rise and fall times
Clock Ø period
Clock Ø HI time
NOT RESET LO time
NOT RESET DATA READY LO time
Output rise and fall times
Output Tristates delays relative to changes on NOT TAG EN
or NOT DATA ENABLE.
Tristate OFF from NOT ENABLE ↑
Tristate ON from NOT ENABLE ↓ (includes worst case
output edge time).
DATA READY from NOT RESET DATA READY ↓.
DATA READY ↑ from DATA READY ↓.
and IOL
MIN
MAX
0.9
0.45
200
100
+0.05
2 -0.1
50
1.0
0.55
200
300
500
2 +0.2
2 +0.1
ns
us
us
ns
ns
ns
ns
ns
us
us
16 bit bus option; data access incomplete; NOT DATA
ENABLE LO; LO pulse on NOT RESET DATA READY
< )
2 +0.2
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
2