Aeroflex Circuit Technology MT34013 Datasheet

MT34013

EIGHT CHANNEL ARINC DECODER

• 8/16 bit parallel interface

• 3 channels programmable to HIGH/LOW

speed data

• Single 5V supply with low power

consumption < 50mW

• Full MIL operating range

• Programmable test I/P to all channels

• Built in parity and word length error

detection

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

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MT34013

MAXIMUM RATINGS (Above which the useful life may be impaired)

Storage Temperature - 65ºC to +150ºC
Temperature (Ambient) under Bias - 55ºC to +125ºC
Supply Voltage VDD -0.3V to + 7V
DC Input Voltage -0.3 to VDD +0.3V
Output Current (Single O/P) 10mA
Output Current (Total O/P) 20mA

ELECTRICAL CHARACTERISTICS over operating range

PARAMETER DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS
IOH Output High Current VOH=2.8V VDD= 4.5V 1.0
IOL Output Low Current VOL=0.4V 3.2
VIH Input High Voltage 2.4 VCC
VIL Input Low Voltage -0.3 0.8
IIL Input Load Current VSS 40
IOZ Output Leakage Current
CI Input Capacitance
CI/O I/O Capacitance 7 9
ICC Supply Current

0.4V<VO<VCC Output Disabled

Test Frequency = 1.0 MHZ

VCC = MAX. All inputs
HIGH, All inputs open.

-40 40
2 2.6

10

mA
mA
Volts
Volts
uA
uA
pF
pF
mA

ARINC 429 SERIAL INPUT INTERFACE

Interfaces are provided for 8 independent Arinc 429 serial input channels with sufficient digital storage to guarantee
no data is lost provided all 8 channels can be accessed within 230µS.

Channels 0,1 & 2 can be programmed for either high or low speed operation. Channels 3 to 7 are configured for
interfacing to low speed Arinc buses only.

Digital Filtering is incorporated on each decoder input port to prevent word corruption due to noise spikes. (The
duration of reject noise spikes is a function of the basic clock period).

Arinc have suggested that the number of labels available to the user can be increased by either using SDI bits 9 and 10
as extra label bits or by using port identification. Both of these techniques have been accommodated in the design.

DATA DETECTION AND WORD TESTS

Each channel is provided with a 32 bit shift register to hold one complete word. The three channels which are
selectable for either high or low speed operation are additionally provided with a 32 bit buffer register.

Each channel contains hardware to test the following parameters:-

(1) Word length of 32 bits.

(2) Parity:- odd on good words.

(3) Gap:- the presence of a 33rd bit is checked for and the output processing is achieved during the remaining

gap for a valid word.

(4) Interconnection fault (both I/P’s high).

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

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MT34013

Prioritised error information for each channel is latched into a 3 bit register with the format indicated in Table 1 and
made available at the user output port.

Channel servicing is carried out on a rotating priority basis, where the last channel serviced is given the lowest
priority, in order to allow full access for each channel.

A facility is provided on the decoder chip to enable individual channels to be tested, which consists of a multi-plexer
on the input to each channel to allow test messages (generated external to the chip) to be injected.

TABLE 1

Prioritorised coded error data.

Bit position relative to first output word see fig.2.

15 14 13
1 1 1 ) Unused
1 1 0 )

1 0 1 Interconnection fault (highest priority)

1 0 0 Channel overrun (causes corruption of following word in that channel.

0 1 1 Word length error (number of bits not equal to 32).

0 1 0 Parity error (word received with even parity).

0 0 1 Service overrun (not all words or bytes accessed) - lowest priority.

0 0 0 Good word.

USER INTERFACE

Arinc 429 data is read from the decoder chip via an 8 or 16 bit parallel data bus.

Fig 2 illustrates the formatting of the output data relative to the generalised Arinc 429 word format.

Control of the chip is achieved via a four bit control port which provides the user with the facilities outlined in Table

2. The control word is strobed into the chip using the leading edge of the NOT CSTR input providing the required set
up and hold times are met.
N.B. NOT CSTR must be high before NOT RESET is removed.

DATA READY signifies to the user that a word is available and can be accessed by pulling NOT CHIP ENABLE low
and strobing the NOT OUTPUT SELECT line as illustrated in fig .3.

NOT RESET provides the user with a simple means of asynchronously inhibiting the chip. Activating NOT RESET
disables the output buffers and clears DATA READY asynchronously. The internal counters are cleared by holding
NOT RESET low for 2 clock periods. Default options are selected which can be overwritten using the control input
port. The default options are shown below and are selected by pulsing RESET low or by selecting software reset (see
table 2).

• Channel sequencer set to channel 0 for highest priority.

• All channels are set for low speed operation.

• All channels are set for normal reception with no end around test mode.

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

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