Advanced Linear Devices Inc ALD1103SB, ALD1103PB Datasheet

ADVANCED
LINEAR
DEVICES, INC.

DUAL N-CHANNEL AND DUAL P-CHANNEL MATCHED MOSFET PAIR

ALD1103

GENERAL DESCRIPTION

The ALD1103 is a monolithic dual N-channel and dual P-channel matched
transistor pair intended for a broad range of analog applications. These
enhancement-mode transistors are manufactured with Advanced Linear
Devices' enhanced ACMOS silicon gate CMOS process. It consists of an
ALD1101 N-channel MOSFET pair and an ALD1102 P-channel MOSFET
pair in one package.

The ALD1103 offers high input impedance and negative current temperature
coefficient. The transistor pair is matched for minimum offset voltage and
differential thermal response, and it is designed for precision signal
switching and amplifying applications in +2V to +12V systems where low
input bias current, low input capacitance and fast switching speed are
desired. Since these are MOSFET devices, they feature very large (almost
infinite) current gain in a low frequency, or near DC, operating environment.
When used in pairs, a dual CMOS analog switch can be constructed. In
addition, the ALD1103 is intended as a building block for differential
amplifier input stages, transmission gates, and multiplexer applications.

The ALD1103 is suitable for use in precision applications which require
very high current gain, beta, such as current mirrors and current sources.
The high input impedance and the high DC current gain of the Field Effect
Transistors result in extremely low current loss through the control gate.
The DC current gain is limited by the gate input leakage current, which is
specified at 50pA at room temperature. For example, DC beta of the device
at a drain current of 5mA at 25°C is = 5mA/50pA = 100,000,000.

FEATURES

• Thermal tracking between N-channel and P-channel pairs

• Low threshold voltage of 0.7V for both N-channel &
P-channel MOSFETS

• Low input capacitance

• Low Vos -- 10mV

• High input impedance -- 10

13

Ω typical

• Low input and output leakage currents

• Negative current (I

• Enhancement mode (normally off)

• DC current gain 10

) temperature coefficient

DS

9

• Matched N-channel and matched P-channel in one package

APPLICATIONS

• Precision current mirrors

• Complementary push-pull linear drives

• Analog switches

• Choppers

• Differential amplifier input stage

• Voltage comparator

• Data converters

• Sample and Hold

• Analog inverter

• Precision matched current sources

PIN CONFIGURATION

DN1

GN1

SN1

V

DP1

GP1

SP1

1

2

3

-

4

5

6

7

DB, PB, SB PACKAGE

14

13

12

11

10

DN2

GN2

SN2

+

V

DP2

GP2

9

8

SP2

BLOCK DIAGRAM

N GATE 1 (2)

N DRAIN 1 (1)

N DRAIN 2 (14)

N SOURCE 1 (3)
SUBSTRATE (4)

N SOURCE 2 (12)

N GATE 2 (13)

ORDERING INFORMATION

Operating Temperature Range*

-55°C to +125°C0°C to +70°C0°C to +70°C
14-Pin 14-Pin 14-Pin

CERDIP Plastic Dip SOIC
Package Package Package

ALD1103 DB ALD1103 PB ALD1103 SB

* Contact factory for industrial temperature range.

© 1998 Advanced Linear Devices, Inc. 415 T asman Drive, Sunnyvale, California 94089 -1706 Tel: [phone] Fax: [phone] http://www .aldinc.com

P DRAIN 1 (5)

P DRAIN 2 (10)

P GATE 1 (6)

P SOURCE 1 (7)
SUBSTRATE (11)

P SOURCE 2 (8)

P GATE 2 (9)

ABSOLUTE MAXIMUM RATINGS

Drain-source voltage, V
Gate-source voltage, V

DS

GS

Power dissipation 500 mW
Operating temperature range PB, SB package 0°C to +70°C

DB package -55°C to +125°C
Storage temperature range -65°C to +150°C
Lead temperature, 10 seconds +260°C

13.2V

13.2V

OPERATING ELECTRICAL CHARACTERISTICS
T

= 25°C unless otherwise specified

A

N - Channel Test P - Channel Test

Parameter Symbol Min Typ Max Unit Conditions Min Typ Max Unit Conditions

Gate Threshold V
Voltage

0.4 0.7 1.0 V IDS = 10µA VGS = V

T

-0.4 -0.7 -1.2 V IDS = -10µA VGS = V

DS

DS

Offset Voltage V
V

- V

GS1

GS2

OS

10 mV IDS = 100µA VGS = V

Gate Threshold
Temperature TC
Drift

On Drain I
Current

DS (ON)

Trans-. G
conductance

Mismatch ∆G
Output G

Conductance
Drain Source R

ON Resistance

VT

fs

fs

OS

DS(ON)

-1.2 mV/°C -1.3 mV/°C

25 40 mA VGS = V

5 10 mmho VDS = 5V IDS= 10mA 2 4 mmho VDS = -5V IDS= -10mA

0.5 % 0.5 %

200 µmho VDS = 5V I

50 75 Ω VDS = 0.1V V

Drain Source
ON Resistance
Mismatch

∆R

DS(ON)

0.5 % VDS = 0.1V V

Drain Source
Breakdown BV
Voltage

Off Drain I
Current 4 µAT

Gate Leakage I
Current 10 nA T

Input C
Capacitance

DS(OFF)

GSS

ISS

12 V IDS = 10µA V

DSS

0.1 4 nA VDS =12V I

150pA VDS = 0V V

610pF 610pF

= 125°C4µAT

A

= 125°C10nAT

A

DS

= 5V -8 -16 mA VGS = V

DS

= 10mA 500 µmho VDS = -5V I

DS

= 5V 180 270 Ω VDS = -0.1V V

GS

= 5V 0.5 % VDS = -0.1V V

GS

=0V -12 V IDS = -10µA V

GS

= 0V 0.1 4 nA VDS = -12V V

GS

=12V 1 50 pA VDS = 0V V

GS

10 mV IDS = -100µA VGS = V

DS

= -5V

DS

= -10mA

DS

= -5V

GS

= -5V

GS

=0V

GS

= 0V

GS

GS

=-12V

= 125°C

A

= 125°C

A

ALD1103 Advanced Linear Devices 2