Advanced Hardware Architectures AHA4210A-062PJC Datasheet

Product Specification

AHA4210 RSVP

Viterbi with

Reed-Solomon Decoder

Advanced Hardware

Architectures, Inc.

2365 NE Hopkins Court

Pullman, WA 99163-5601

509.334.1000

Fax: [phone]

e-mail: [e-mail]

http://www.aha.com

TM

Advanced Hardware

Architectures

The Data Coding Leader

PS4210-1099

Advanced Hardware Architectures, Inc.

Notes to Customers of AHA4210

1) Patent(s) pending. One or more patent(s) have been applied for this product.

2

2) Purchase of I
Patent Rights to use these components in an I
system conforms to the I

C components of AHA conveys a license under the Philips I2C

2

C Standard Specification as defined by Philips.

2

C system, provided that the

PS4210-1099

Advanced Hardware Architectures, Inc.

Table of Contents

1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.3 Conventions and Notations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.4 Definition of Terms and Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.1 Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.1.1 Explanation of Clocking Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.2 Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2.2.1 Depuncture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2.3 Deinterleaver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2.4 RS Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.5 Derandomize/Energy Dispersal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.6 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.7 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2.7.1 Parallel 80C188 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2.7.2 Serial I

2.8 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2

C Protocol Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3.0 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.1 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.2 ERRSTAT: Error Count Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.3 ERRSIZE: Error Block Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.4 VRSSIZE: Total Block Count for VRSTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.5 VSYNCP: Sync Decoder Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.6 VRSTH: RS Uncorrectable Blocks Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.7 VERTH: Sync Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 0

3.8 VCON: Viterbi Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.9 MSGBYTES2: Message Bytes K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.10 RSEED0: Derandomizer Seed LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.11 RSEED1: Derandomizer Seed MSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.12 IOCNTRL: Input/Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.13 NJL: Block Length Times Interleave Depth LSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.14 NJM: Block Length Times Interleave Depth MSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.15 BLKLEN2: RS Block Length N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.16 JDEPTH: Interleave Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.17 RSCONTROL: Reed-Solomon Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.0 Signal Descriptions and Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4.1 Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4.2 Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.3 Bidirectional Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.4 Input Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.5 Output Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.6 Bidirectional Pin Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.7 Power & Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.8 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

5.0 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

6.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

7.0 Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

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Advanced Hardware Architectures, Inc.

8.0 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

8.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

8.2 Part Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

9.0 AHA Related Technical Publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

10.0 Other Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

ii PS4210-1099

Advanced Hardware Architectures, Inc.

Figures

Figure 1: AHA4210 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2

Figure 2: I
Figure 3: I

Figure 4: Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 5: Start and Stop Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 6: Clock Timing - SCLK and VCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 7: Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 8: DATAFLUSH Timing - Byte Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 9: Microprocessor Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 10: Microprocessor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 11: I

Figure 12: Input - Serial Mode: IOCNTRL[2:1] = 0x Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 13: Input - Byte Mode: IOCNTRL[2:1] = 10 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 14: Input - Byte Mode IOCNTRL[2:1] = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 15: Output - BCLK Mode: IOCNTRL[4:3] = 10, [2:1] = 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 16: Output - Byte Mode: IOCNTRL[4:3] = 10, IOCNTRL[2:1] ≠11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 17: IOCNTRL[4:3] = 00, Serial Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 5

Figure 18: IOCNTRL[4:3] = 01, Serial Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 5

Figure 19: IOCNTRL[4:3] = 10, Byte Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 20: IOCNTRL[4:3] = 11, Byte Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 21: Power vs. VCLK Rate, Estimated for Modes 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 22: Max Ambient Temperature (Ta) vs. VCLK Rate, Estimated for Modes 1 and 3. . . . . . . . . . . . . . . . . . .27

C Internal Register Increment Example, Writing the Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2

C Reading Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2

C Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

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Tables

Table 1: Various Modes Supported by the AHA4210 Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 2: Register Settings for Functional Block Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 3: Maximum Latency in VCLK Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

iv PS4210-1099

Advanced Hardware Architectures, Inc.

1.0 INTRODUCTION

The AHA4210, referred to as the RSVP, is a
single-chip Forward Error Correction LSI device
combining a Viterbi decoder, a Reed-Solomon
decoder, a descrambler (energy dispersal) and a
deinterleav er. The de vice c onforms to the MPEG-II
transport layer protocol specified by ISO/IEC
standard and FEC requirements of Digital Video
Broadcasting (DVB) DT/8622/DVB and DT/8610/
III-B specif ication. These documen ts are referr ed to
as the DVB specification.

The Viterbi decoder supports selectable code
rates of 1/2, 2/3, 3/4, 5/6, 6/7 or 7/8 using industry
standard puncturing algorithms. Viterbi decoded
data rate is up to 62 Mbits/second at all code rates.
The chip also performs byte alignment and block/
packet synchron ization detecti ng sync bytes use d in
transmission. The descrambling function is
selectable with a programmable seed or performed
externally. Each fun ctional block may be bypassed
giving more flexibility to a system designer.

Block size programmability, several code rate
choices and programmable RS error correction
capability allows flexibility to a digital
communications system designer incorporating
Forward Error Correction into a receiver. Intel
80C188 multiplexed parallel or serial I
interface allows the system microprocessor to
program internal registers and monitor channel
performance.

This document contains ke y featu re s,
correction terms, functional description, signal
functions, Related Technical Publications, DC and
AC characteristics, pinout, package dimension and
ordering information.

1.1 APPLICATIONS

• Satellite communications/VSAT

• DBS

• Military Communications

1.2 FEATURES

GENERAL:

• Conforms to the ISO/IEC-CD 13818-1 MPEG-II

transport layer protocol and Digital Video
Broadcasting (DVB)FEC specification

• Viterbi decoded data rates up to 62 Mbits/sec at

any code rate

• Programmable block size from 34 to 255 bytes

• Multiplexed parallel Intel 80C188 or serial I

protocol microprocessor interface

• Byte or serial data output

• On-Chip err or rate monitor

2

C protocol

2

C

• Programmable bypass modes for each of the
major blocks

• Configured to DVB mode of operation on
power-up

• 68 pin PLCC

VITERBI DECODER:

• Selectable decoder rates 1/2, 2/3, 3/4, 5/6, 6/7
and 7/8 or automatic acquire mode

• 3-Bit soft-decision decoder inputs

• Constraint length k=7

SYNCHRONIZATION CONTROL:

• Automatic synchronization capability for QPSK
based demodulator

• Up to one sync byte per block

• Responds to inverted sync byte

REED-SOLOMON:

• t=1 through 8 in increments of 0.5

• Correction capability of up to 8 bytes

• Internal FIFOs

DEINTERLEAVER:

• Programmable convolutional deinterleaving
(Ramsey II, Ramsey II modified or Forney) to
depth I=16

• No externa l RAM required

ENERGY DISPERSAL:

• Selectable on-chip DVB specification Energy
Dispersal

• Optional bypass mode

• Programmable seed

1.3 CONVENTIONS AND NOTATIONS

- Cert ain signals are logically true at a voltage
defined as “low” in the data sheet. All such
signals have an “N” appended to the end of the
signal name. For example, RSTN and RDYON.

- “Signal assertion” means the signal is logically true.

- Hex values are defined with a prefix of “0x”,
such as “0x10”.

- A range of signal names is denoted by a set of
colons between the numbe rs . Most signi f ican t b it
is always shown first, followed by least
significant bit. For example, ERRSTAT[6:0]
represents number of bytes corrected by the
Reed-Solomon decoder.

- A product of two variables is expressed with an
“x”, for example, BLKLEN2 x JDEPTH
represents Block Length mu ltip lied b y Int erle a ve
Depth.

- Megabytes per second is referred to as MBytes/
sec or MB/sec. Megabit s per second i s referred as
Mbits/sec or Mb/sec.

- Frequency of a clock signal is referred to as
F(name). For example, F(VCLK) specifies
frequency of VCLK.

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1.4 DEFINITION OF TERMS AND PROGRAMMABILITY

VITERBI

TERM

k Constraint Length

NAME

(other references)

Number of input bits over which convolutional
code is computed.
Length of path through the trellis over which the

Traceback Depth

Viterbi decoder computes the likelihood of a
decoded bit value.

Puncturing

Puncture Pattern
Convolutional Code

Rate (Puncture Rate)

Process of deriving a higher rate code from a basic
rate code.
Mapping between 1/2 rate encoded bits and new
higher rate encoded bits.
Ratio of input to output bits for convolutional
code.

DEINTERLEAVER

TERM

Ramsey or Forney Convolutional interleave techniques. N/A

J Interleave Depth Minimum separation in th e interleaved stream. 1 through 16

NAME

(other references)

DEFINITION RANGE

7

minimum=115

N/A

N/A
1/2, 2/3, 3/4, 5/6, 6/

7, 7/8

DEFINITION RANGE

TERM

K

R

N

Message Length (user
data or message bytes)

Check symbols
(parity or redundancy)

Codeword Length
(block length)

NAME

(other references)

t Error Corrections

e Number of Errors

RS Code Rate Ratio of message to block length, . 0.67 through 0.99

TERM

NAME

(other references)

Bypass

Block

Packet MPEG-II transport layer packet size.

REED-SOLOMON

DEFINITION RANGE

Number of user data symbols in one message
block. Size of a symbol in AHA4210 is 8-bits.
Message length is .

KNR–=

Symbols appended to the user data to detect and
correct errors. The number of check symbols
required in a sys te m is . Every 2 ch ec k bytes

R 2e≥

correct 1 error byte.
Sum of message and check symbols. .

NKR+=

Maximum number of error corrections performed
by the device. The value is t=Integer .

NK–

-------------­2

An error is defined as an erroneous byte whose
correct value and position within the message
block are both unknown.

K

--- -

GENERAL

DEFINITION RANGE

Processing data either through or around a
functional block.

An entity of both message and Reed-Solomon check
bytes. The number of message bytes is equal to the
length of the MPEG-II packet for a DVB system.

32 thru 253 bytes
(32, 33, 34 . . . 253)

2 thru 16 bytes in
increments of 1
(2, 3, 4 . . . 16)

34 thru 255 bytes
(34, 35, 36 . . . 255)

1 thru 8 bytes in
increments of 0.5
(1, 1.5, 2, 2.5 . . . 8)

minimum 0

N/A

(34, 35, . . . 255)
bytes

188 including one
sync mark byte

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2.0 FUNCTIONAL DESCRIPTION

This section presents an architectural overview of the chip and its many functions, features and

operating modes. Block diagram of the chip shows the Viterbi and Reed-Solomon decoder modules.

Figure 1: AHA4210 Block Diagram

BYTE[1:0]

MUX

I[2:0]

IQSTRB

Q[2:0]

SCLK

DATAFLUSH

INPUT

INTERFACE

DEPUNCTURING

LOGIC

VITERBI

DECODER

DEINTERLEAVER

&

RAM

REED-SOLOMON

DECODER

&

ENGERY DISPERSAL

(DESCRAMBLER)

BLKNEW
DO[7:0]
RDYON

BLKERR

MD[7:0]

SYNC CONTRO L

MAL

MCSN

RSTN

MICROPROCESSOR INTERFACE

DECODER CONTROL

SCL

SDA

MRDN

MWRN

2.1 SYNCHRONIZATION

This module synchronizes data received from
Viterbi to byte and packet boundaries. The
synchronization alg ori thm is summarized below.

Bit-to-byte mapping is performed while
looking for sync marks specified in register
VSYNCP . Ev ery bit posit ion is examine d for a sync
mark byte. If no sync mark is d etected af ter looking
for a minimum of two block lengths, then the phase
is incremented and the process is repeated. Carrier
and depuncture phases are cycled through
searching for sync marks. This process terminates
when sync is achieved.

After a sync mark is detected, additional sync
marks as specified in SYNCON[2:0] are searched.
Detection of additional sync completes the block
sync process and da ta is out put on th e ne xt in v er ted
sync (or regular sync if VCON[7] = 0). Once the
output data flow starts, cons ecu tive sync marks are
required if enabled by the VCON[6] to remain in
sync. In this case if SYNCOFF[2:0] consecutive
sync marks are missed, then the block goes out of
the sync condition.

The block may also go out of sync if the Reed­Solomon uncorrectable blocks threshold is
exceeded over a programmable number of blocks.
This feature is enabled by VCON [5]. Total Block
Count and Threshold are programmed by
VRSSIZE and VRSTH registers.

DECODER

CLOCK CONTR OL

VCLK

READY

BCLK

2.1.1 EXPLANATION OF CLOCKING SCHEMES

The Viterbi block has two clock inputs: SCLK
and VCLK. VCLK runs the actual Viterbi decoder
block while SCLK simply d riv es the in put stage for
V iterbi. The data inp uts I[2:0], Q[2:0] and IQSTRB
are synchronous to SCLK.

There are two approaches to using this
interface. Approa ch one involves tying IQSTRB to
VDD (active) and assuring that:

VCLK



Frequency SCLK()Frequency

≤

Where CR is defined as the code ra te. Note that
this is a strict requi re me nt and the chi p will enter a
state requiring a hard reset if this is not met.

One advantage to this approach is that in some
designs SCLK is already available and I and Q are
already synchronous to this signal.

The other method is to tie SCLK and VCLK
together and throttle the data with IQSTRB. For

X

any given code rate , where Y is even, IQSTRB
would be held high (clocking in I[2:0] and Q[2:0]

---

Y

on that cycle) for no more than out of every X
clocks. If Y is odd then IQSTRB woul d be held high
for no more than Y out of every 2X clocks and no

Y 1+

more than in every X clock cycles.

In the final approach it is not necessary to

-----------­2

supply a separate clock (SCLK), however, the
customer must supply the circuitry to drive
IQSTRB appropriately.

---------------- -



2 CR×

Y

-- ­2

PS4210-1099 Page 3 of 30

Advanced Hardware Architectures, Inc.

F SCLK()

F VCLK()

2 CR×

------------------------

≤

The Viterbi decoder can be set up to cycle
through all convolutional code rates. In this case,
use convolutional code rate ≥ 7/8 in the equation:

2.2 VITERBI DECODER

The Viterbi decoder takes the data from an I
and a Q channel and decode s these using a 3 bit sof t
decision. The V i terbi d ecoder is bas ed on a 1/2 rate
code, but also sup ports punctu red cod es with ra tes:
2/3, 3/4, 5/6, 6/7 and 7/8.

The generator polynomials are:

g1 171(octal) and g2 133(octal)==

The minimum trace back depth is 115.

The output of the Viterbi decoder is converted
to 8 bit bytes, sync bytes are det ected and after
which the data is run through the deinterleaver to
restore the ECC blocks.

The V iterbi deco der can be bypass ed by bit 2 of
the IOCNTRL and disabled by bit 4 of the VCON
register.

The latency of th e Viterbi block is measured in
two ways. First, there is a latency associated with

“synching” to the incoming signal. Assuming that
there is no valid sync byte patterns in the data the
worst case sync time is given by:

8 block length 384+×()4 # of puncture phases()512+××

This assumes that SCLK runs fast enough to
keep the data pi peline full. Once the V iterbi block is
synched up, the maximum latency from input to
output is 258 VCLK cycles.

2.2.1 DEPUNCTURE

The Viterbi module can be programmed to
depuncture according to a specified code rate or
automatically find the code rate used in the channel.
Follo wing i s a lis t of punc ture p att erns a nd number
of phases that are cycled through in an attempt to
align the puncture phase.

RATE PATTERN: X:Y # OF PHASES

1/2

2/3

3/4

5/6

6/7

7/8

X
Y
X
Y
X
Y

X
Y
X
Y
X
Y

1000101
1111010

10

11
101
110

10101

11010
100101
111010

1
1

1

3

2

3

7

4

During the encoding process, X and Y are
mapped into I and Q b y taking the nond eleted terms
in order of X1, Y1, X2, Y2, etc. Deleted terms are
simply skipped. The decodi ng process is si mply the
reverse of this procedure. Erasures are inserted on
the pattern locations with zeroes. For example, the
rate 5/6 I and Q have values:

I = X1, Y2, Y4, X1, Y2, Y4, . . .

Q = Y1, X3, X5, Y1, X3, X5, . . .

The chip is capable of supporting a limited
number of depuncture codes not included in this
specification. The procedure for supporting these
codes are beyond the scope of this specification.
Please contact AHA Applications Engineering for
these codes.

The Viterbi core can be configured to self
synchronize to the appropriate depuncture pattern
phase and correct for phase ambiguity. If
VRSSIZE[6] is set, Viterbi sync does not cycle

pi

---- ­2

through carrier phases. If the code rate is not
known, the core can also be con figured to cycle
through 1/2, 2/3, 3/4, 5/6, 6/7 and 7/8 code rates
looking for a valid pattern.

2.3 DEINTERLEAVER

The deinterleaver supports a variety of

programmed options:

TECHNIQUE TYPE

WITH

VITERBI

Ramsey II No Yes
Forney/Ramsey III Yes Yes
Modified Ramsey II Yes Yes

A Ramsey type II interlea ver is spe cified in J .L.
Ramsey, “Realization of Optimal Interleavers,”
IEEE Transaction on Information Theory, May
1970, pp. 338-345. A F orne y/Ramse y ty pe III int er­leaver is specified in DVB DT/8622/DVB
specifica tion. The interleave dept h is programmable
up to 16 packets and the bl ock size is programmable
up to 255 bytes. However, the product of the inter­leave depth and block length cannot be larger than
2688 bytes. In a ddi ti on t o t hi s, t he following co ndi ­tions must be satisfied for various applications.

APP INTERLEAVE CONSTRAINT

Forney/

DVB

Ramsey III
Ramsey II
Ramsey II

modified

Maximum processing latency =

8 NJM[3:0] & NJL[7:0]()× VCLKS

Note that the “&” is a concatenation symbol.

BLKLEN2/JDEPTH[3:0]
must be an integer
BLKLEN a nd JD EPTH [3:0 ]
must be relati vely prime

Same as Ramsey II

WITHOUT

VITERBI

Page 4 of 30 PS4210-1099

Advanced Hardware Architectures, Inc.

px() x8x4x3x21++++=

α1primitive element=

2.4 RS DECODER

The RS block performs the ou ter decoding. The
Reed-Solomon decoder conforms to the DVB
specificati on. Th e RS bl ock can be programmed to
decode t=1, 1.5, 2, . . . 7.5, 8.

2t 1–

gx() x α0+()x α1+(). . . x α

The block length of the code is programmable
up to 255 bytes. Block length is 204 with 16 check
bytes and a correction power of 8 bytes per block
for the DVB specification. Maximum latency
through the RS Decoder Block is:

N 1–()81202RN2.67×+++×

()

+()=

2.5 DERANDOMIZE/ENERGY

DISPERSAL

The derandomizer is specified in the DVB
specification. It is built as a 15 stage pseudo­random binary sequence generator with
initialization sequence specified by RSEED0 and
RSEED1 registers. The randomization occurs over
8 blocks of MGSBYTES2 (188 bytes for DVB
specification). Randomization does not occur over

Reed-Solomon parity bytes nor sync bytes.
However, the pseudo-random binary sequence
generator continue s to run during non-in verted sync
bytes. Maximum latency = 10 VCLKs.

2.6 MODES OF OPERATION

The FEC decoder has been designed with a
modular approach so that each of the four major
functions: Viterbi deco ding, deinterle aving, RS
decoding and derandomization can be individually
enabled or disabled. Five operating modes are
supported by the device. These are:

1) Normal mode. All functions enabled. Inputs

clocked with SCLK.

2) Byte Input mode. All functions except Viterbi

enabled. Inputs clocked with VCLK. Tie

SCLK to VCLK. Use Byte [1:0], I[2:0] and

Q[2:0] as byte wide data path. Bytes must

arrive on packet boundaries.

3) Viterbi decode mode. Inputs clocked with

SCLK.

4) Reed-Solomon decode mode. Same input

constraints as byte input mode.

5) Deinterleave mode. Same input constraints as

byte input mode.

These modes may be operated with or without
the derandomizer enabled.

Table 1: Various Modes Supported by the AHA4210 Device

FUNCTIONAL BLOCK

MODE

VITERBI DEINTERLEAVER RS DECODER DERANDOMIZER

1) Normal Enabled Enabled Enabled Either

2) Byte Input Disabled Enabled Enabled Either

3) Viterbi Decode Enabled Disabled Disabled Either

4) RS Decode Disabled Disabled Enabled Either

5) Deinterleaver Disabled Enabled Disabled Either

Ta ble 2: Register Settings for Functional Block Bypass

FUNCTIONAL BLOCK ENABLED DISABLED

Viterbi
Deinterleaver JDEPTH[4]=1 JDEPTH[4]=0

Reed-Solomon RSCONTROL=0C RSCONTROL=1C
Derandomizer IOCNTRL[7]=1; VCON[7]=1 IOCNTRL[7]=0; VCON[7]=0

VCON[4]=1
IOCNTRL[2]=0

VCON[4]=0
IOCNTRL[2]=1

PS4210-1099 Page 5 of 30