Advanced Hardware Architectures AHA4013B-050PJC Datasheet

Product Specification

AHA4013B

12.5 MBytes/sec Reed-Solomon
Error Correction Device

2365 NE Hopkins Court

Pullman, WA 99163-5601

tel: [phone]

fax: [phone]

e-mail: [e-mail]

www.aha.com

advancedhardwarearchitectures

PS4013B-0600

Advanced Hardware Architectures, Inc.

Table of Contents

1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.2 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.2.1 Definition of Correction Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2.2 Correcting Capability and Polynomials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2.4 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2.5 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.5.1 Shortened Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.6 Reset and Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.6.1 Initialization Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2.7 Encode, Decode or Pass-Through Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.8 Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2.9 Data Rates and Latencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2.9.1 Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2.9.2 Continuous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2.10 Reed-Solomon (ECC) Module and Error Rate Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.11 Determining Decoder Performance Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2.12 Erasures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.0 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.3 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.4 Data Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4.0 Signal Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.1 Input Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.2 Output Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.3 Power & Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.4 AC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.0 Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

6.0 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

6.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

6.2 Part Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

7.0 Related Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 0

Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

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Figures

Figure 1: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Figure 2: Typical Applications Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Figure 3: Data Input and Output Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 4: Burst and Continuous Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 5: Symbol (Byte) Error Rate Performance Curves for Codeword Length = 255 Bytes . . . . . . . . . . . . . . . . .11

Figure 6: CLK Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 7: Initialization and Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 8: Data Input - Buffer Always Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 9: Data Input - Buffer Not Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 10: Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 11: CRTN Timing - Reverse Order Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

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Tables

Table 1: Initialization Register Settings for Encode, Decode and Pass-Through Operations . . . . . . . . . . . . . . . . . .7

Table 2: Burst Operation Using 50 MHz Clock and 1 Clock/Byte, Forward Order Output. . . . . . . . . . . . . . . . . . . . .9

Table 3: Continuous Operation Using 50 MHz Clock and Specified Clocks/Byte, Forward OutputOrder. . . . . . . .10

Table 4: Continuous Operation for IESS-308 Codes Using 50 MHz Clock and Specified Clocks/Byte,

Forward Output Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

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Advanced Hardware Architectures, Inc.

1.0 INTRODUCTION

The AHA4013B is a single chip integrated
circuit that implemen ts a high speed Reed-Solomon
Forward Error Correction algorithm. The
AHA4013B is a member of the AHA PerFEC
family of high speed for ward error correction (FEC)
devices conforming to the Intelsat IESS-308
specification.

The device supports several programmable
parameters, including, block size, error threshold,
number of check bytes, order of out put and mode of
operations. Shortened blocks are suppor ted without
requirement of zero padding typically required in
Reed-Solomon decoders . The data input port is used
to initialize the programmable parameters and the
two on-chip buffers are used to input and output
data. Discontinu ities in data flow may b e controlled
by dedicated control pins.

High operating frequenc y, in put and output data
rate flexibility, low processing latency and various
programmable parameters make this device ideal
for many applications including: DTV, DBS,
ADSL, Satellite Communications, ISDN, High
Performance Modems and networks.

This specification provi des ful l ele ct ri cal and
mechanical information to help a system engineer
develop a system usi ng AHA4013B. This document
contains descriptions on correction terms, pinout,
functions and featu res , DC and AC ch ar act eristics,
package and mechanical specifications, ordering
information and Related Technical Publications.
Software simulatio n of the RS code as implemented
in the device is al so available. Please co nta ct AHA
or its authorized sales repr esentative s worldwide or
visit our web site a t http:/ /www.aha.com for copies
of Related Technical Publications and software
simulation.

1.1 FEATURES

HIGH PERFORMANCE

• Polynomial complies to Intelsat IESS-308;

RTCA DO-217 Appendix F, Revision D and
proposed ITU-TS SG-18 (Formerly CCITT SG-

18) standards

• 50 MBytes/sec burst trans fe r rate with a 50 MHz

clock for all block lengths

• Sustained data transfer rate of 12.5 MBytes/sec

for block lengths from 54 bytes through 255
bytes using a 50 MHz clock

• Processing latency time less than 12.2 µsec in

continuous operation for block lengths of 100
bytes

FLEXIBILITY

• Programmable to correc t fro m 1 to 10 error by tes
or 20 erasure bytes per block

• Block lengths programmable from 3 to 255 bytes

• Encode, decode or pass-through capabi li ty in­line with data flow

• Outputs corrected data or correction vectors in
forward or reverse order

• Continuous or burst data transfer

• Programmable error threshold to help determine
channel performance

SYSTEM INTERFACE

• Byte wide synchronous I/O ports with internal
buffering on both ports

• Dedicated control pins permit discontinuities in
system data flow

OTHERS

• 44 pin PLCC; 50 mil lead pitch

• Pin compatible with lower performance
AHA4011/12

• Plug compatible with AHA4011/12 excep t for an
initialization register setting

• Software emulation of the algorithm available

1.2 CONVENTIONS, NOTATIONS AND

DEFINITIONS

– Certain signals are logically true at a voltage

defined as “low” in the dat a sheet. All such signals
have an “N” appended to the end of the signal
name. For example, RSTN and DSON.

– “Signal assertion” means the output signal is

logically true.

– Hex values are defined with a prefix of “0x”, such

as “0x10”.

– A range of signal names is denoted by a set of

colons between the numbers. Most significant bit
is always shown first, followed by least significant
bit. For example, DI[7:0] represents Data Input
Bus 7 through 0.

– A product of two variables is expressed with an

“×”, for example, N × C
Length multiplied by Input clocks/byte.

– Mega Bytes per second is referred to as MBytes/

sec or MB/sec.

represents Codeword

i

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1.2.1 DEFINITION OF CORRECTION TERMS

TERM

K

R

N

Message Length (user
data or message bytes)

Check Symbols
(parity or redundancy)

Codeword Length
(block length)

NAME

(other references)

t Error Correcti ons

P Error Threshold

e Number of Errors

E Number of Erasures

G Burden of Correction

DEFINITION

Number of user data symbol s in one message block.
Size of a symbol in AHA4013B is 8-bits. Message
length is K = N − R. The first message byte is
referred to as X
Symbols appended to the user data to detect and
correct errors. The number of check symbols
required in a sys tem is R ≥ E + 2e.* The f irst check
symbol is referred to as Y
is Y

.

0

Sum of message and check symbols. N = K + R.
Maximum number of error corrections performed

by the device. The value is t = Integer .
The threshold limit to determine uncorrectability of

a Codeword and the number of check bytes
allocated for correction-only purposes (not for
detection).

An error is defined as an erroneous byte whose
correct value and positi on within the message block
are both unknown.
An erasure is defined as an error whose position is
known within the message block.**
A measure of the burden of correct ion being placed
on the capabilities of the device for that message
block. The value G = 2e + E.

; the last message byte is X0.

K−1

; the last check symbol

R−1

NK–

--------------

2

RANGE

(number of bytes)

1 through 253
(1, 2, 3, 4... 253)

2 through 20 in
increments of 1
(2, 3, 4... 20)

3 through 255
(3, 4, 5, 6... 255)

1 through 10
(1, 2, 3... 10)

2 through 20
(2, 3, 4... 20)

0 through N

0 through N

0 through R

* For every 2 check bytes, the AHA4013B can correct either 2 erasures or 1 error.
** An erasure is detected by a parity detector or a signal dropout detector. The presence of an erasure is indicated

by asserting the ERASE signal when the erased byte is clocked into the AHA4013B.

2.0 FUNCTIONAL DESCRIPTION

The ECC core has three phases of operation:

Data In, Calculation and Data Out. Data to be

This sectio n describes a n architectural
overview of the chip and its many functions,
features and operations. The block diagram for the
chip shows the Reed-Solomon ECC module, the
Input and Output Buffers, and their associated
control. All input an d output data are cl ocked on the
rising edge of CLK.

2.1 FUNCTIONAL OVERVIEW

processed is first input into a single ported Input
Buffer using a control signal DSIN. ECC core
arbitrates for the inpu t data out of the Input Buffer.
ECC core has access to the Input Buffer on clock
edges where DSIN is not asserted.

Each block is processed within the ECC core
and calculations are made. The entire block is
processed through the ECC core, and transferred
into the Output Buf fer. The device asserts RDYON
signal and holds active until the Output Buffer is
completely emptied.

The AHA4013B Reed-Solomon codec (coder/

decoder) is a member of the AHA PerFEC™ family
of high speed forward error cor rection (FEC) devices.
This single chip, three-layer metal, CMOS device can
operate in encode, decode or pas s-t hrough modes.

The ECC core implements a full error

The ECC core loads the Output Buffer in
reverse order for either operation. Data may be
strobed out of the de vice in forward or revers e order.
If forward order is desired, output data cannot be
strobed out of the device until the entire block has
been loaded into the Outpu t Buffer.

correcting Reed-Solomon decoder. This code is
capable of correct ing up t o 10 (t =10) byte- error s or
20 (t=10) erasures in a RS block.

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Gx() x αi–()

i 120=

119 R+

∏

=

The use of internal buffers is restricted per the
rules defined in Section 2.9 Data Rates and
Latencies.

Maximum delay required for each block of a
given length t o pass through the device is fixed, and
does not vary with the location or the number of
errors received. This delay (or latency), expressed
in the number of clocks i s discussed in a later
section.

2.2 CORRECTING CAPABILITY AND

POLYNOMIALS

Compared with other codes, RS codes require
relatively few “overhead” check bytes to be added
to the data stream t o ac hie ve a high degree of error
detection and correction. Since the AHA4013B
deals with bytes (or symbols) rather than with
individual bits, when a byte is in error it does not
matter how many bits within the byt e are corrupted;
it is counted as one error.

The Reed-Solomon code is defined over the
finite field GF(2
polynomial is:

and the generator polynomial, dependent on the
variable R, is given by:

8

). The field defining primitive

8

P(x) = x

+ x7 + x2 + x + 1

Correcting “erasures” takes only half as much
of the correction capa bility of the RS code as it takes
to correct “errors”, since the position information is
already known for “erasures”. The correction ab ility
of the code is bounded as:

R ≥ # erasures + 2(# errors)

Valid block length (N) is defined by the
relationship:

R + 1 ≤ N ≤ 255

where R ranges from 2 to 20.

A complete codeword can therefore ra nge from
a minimum of 3 bytes to a maximum of 255 bytes.

For further discussion on error rate
performance, refer to Section 2.10 Reed-Solomon
(ECC) Module and Error Rate Performance.

Figure 1: Block Diagram

RDYIN

RDYIN

ERASE DI[7:0] CLK

DI

REGISTER

INPUT BUFFER

367x9

CLK

where R ∈ {2, 3, 4, 5,... 20} for the AHA4013B. This
polynomial is specified in international standards ,
Intelsat IESS 308; R TCA DO-2 17 Appendix F (Rev
D) and the proposed CCITT SG-18.

For every 2 check bytes, the decoder corrects
either 2 erasures or 1 error. An erasure can be
determined with a parity detector or a signal dropout
detector external to the chip. An erasure is indicated
by the ERASE signal when the erased byte is
clocked in the device.

Figure 2: Typical Applications Diagram

ENCODER COMMUNICATIONS DECODER

DATA SOURCE

SYSTEM

CONTROLLER

8 8 8 8

A

AHA4013B

ECC COPROCESSOR

BLOCK FORMAT AT:

B C

A

KDATA PLUS R “DUMMY” BYTES

B

KDATA PLUS R CHECK BYTES

C

KDATA BYTES

CHANNEL

1 TO x BITS WIDE

RSTN

DSIN

DSON

RSTN

DSIN

DSON

CONTROL

RDYON

RDYON CRTN DO[7:0] ERR

ECC COPROCESSOR

CRTN

AHA4013B

ECC CORE

OUTPUT BUFFER

256x9

REGISTER

GND

VDD

DO

DATA SINK

SYSTEM

CONTROLLER

GND

VDD

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2.3 SIGNAL DESCRIPTIONS

Input Pins

DI[7:0] Data Input Bus. The input byte and ERASE

are latched on the rising edge of the clock
when both DSIN and RDYIN are activ e. If
either DSIN or RDYIN are inactive, the DI
and ERASE are ignored.

DSIN Data In put Strobe. Enables dat a from DI to

be loaded into the chip. When RDYIN is
active, DSIN being active on the rising
edge of the clock loads the input data in the
device. DSIN must be activ e f or one c lock
edge only per each input byte. DSIN is
ignored if RDYIN is inactive. Signal is
active low.

DSON Data Output Strobe. This input strobe

acknowledges to the chip that data
available on the Outpu t Bus, DO, has be en
received by the system. The device uses
this strobe to increment its internal address
counter to the next data location. DSON
must be active for one clo ck edge on ly per
each output byte. DSON is ignored if
RDYON is inactive. Active low.

ERASE Erasure input f la g fo r symbol currently on

DI. Signal is active hi gh. ERASE signal is
used for marking all check Bytes as
erasures (dummy check Bytes) during
encode operation. It is also used to mark
input symbols that contain errors during
decoding. If not used , connect this signal to
ground.

RSTN Reset. Input pin. When RSTN is active and

DSIN and DSON are inactive, the device
forces all internal control circuitry into a
known state and initializes all data path
elements. RSTN is active during
Initializat ion Phase. In this phase, intern al
registers are progr ammed by usi ng DI a nd
DSIN. Signal is active low.

CLK Clock. System clock input. Refer to

Section 4.4 AC Electrical Characteristics
for clock requirements.

Output Pins

RDYIN Ready Input. Indicate s th e chi p’s ability to

accept data input on DI. If ac ti ve, DSI N is
allowed to enable the loading of input data
on DI. When inactive, DSIN is ignored.
Signal is active low.

DO[7:0] Data Output. The output byte is available

on this bus. The val ue of the ou tpu t byte is
undefined if RDYON is inactive. Requir es
an acknowledge strobe, DSON, at a rising
edge of the clock to incre ment internal
address counter and output the next
location in the buffer. DO bus is always
driven and is not tristated by the device.

R DY O NReady Output. This output pin indicates the

chip’s ability to generate output data. If
active, DSON is allowed to increment the
internal address count er for the next data
byte. When inactive DSON i s i gnored and
DO is undefined. Signal is active low.

CRTN Correctable. The output pin when active

indicates the blo ck did not exceed th e error
threshold programmed by P. Error
threshold must be programmed with the
same value as the number of chec k symbols
R if erasures are not used. This signal is
valid when the first m essage byte, X

K−1

, of
the block is available out of the chip.
During all other times the signal is
undefined. Signal is valid for at least one
clock. Active low.

ERR Error. Output pin indicates the current

value on DO[7:0] is a corrected byte.
Active high.

2.4 PINOUT

INPUT

CLK

DI6

DI7

DISN

4443424140

GND

39

VDD

38

VDD

37

GND

36

VDD

35

RSTN

34

ERASE

33

DSON

32

RDYIN

31

RDYON

30

GND

29

GND

VDD

GND

VDD
GND
GND

VDD

*NC
*NC

VDD
GND
GND

DI0

DI1

DI2

DI3

DI4

DI5

65432

7
8
9

AHA4013B-050 PJC

10
11
12
13
14
15
16
17

1819202122232425262728

1

DO0

DO1

DO2

DO3

DO4

DO5

DO6

DO7

VDD

ERR

CRTN

OUTPUT

*NC = No connect, reserv e d for fu tur e cons i de r ati o ns .

Page 4 of 24 PS4013B-0600

Advanced Hardware Architectures, Inc.

ECC
Core

Data Available
Reverse Order Forward Order

Data Available

.

.

.

.

.

.

X

0

Y

0

R-1

Y

K-1

X

.

.

.

.

.

.

Y

0

X

0

R-1

Y

K-1

X

Last Byte Out

First Byte Out

First
Byte

In

Last
Byte

In

. . . . . .

X

1

Y1Y

0

X

0R-2YR-1

Y

K-2XK-1

X

INPUT

BUFFER

OUTPUT
BUFFER

2.5 DATA FLOW

The device is first initialized for various
programmable parameters including: Erasure
Multiplier, Error Threshold, Number of Check
bytes, Number of Message bytes per block, Block
Length and a Control byte. Follo wing t his six-byte
initialization, the device may be used to encode,
decode or pass-through multiple blocks of data. The
device requires reinitialization when the parameters
are changed or a reset is required.

The device processes data as “blocks”
containing Message and Check Bytes. Order of
input bytes must be first mess age byte X
last messa ge byte X
Y

through last check byte Y0. The device

R−1

, followed by first check byte

0

processes the block in this manner:

- a block is clocked into the Input Buffer;

- transferred into the ECC module;

- passed to the Output Buffer in th e reverse order
from what was received at the Input Port; and

Figure 3: Data Input and Output Order

through

K−1

- clocked out through the Output Port via the
Output Buffer. Consecutive blocks may be
input into the Input Buffer while the Output
Buffer is being emptied.
Data is available through the Output Port in

forward or reverse order. Forward order clocks out
the block the same as in put and reverse order c locks
the check byte Y

through check bytes Y

0

followed by message byte X
X

.

K−1

through message byte

0

R−1

2.5.1 SHORT ENED BLOCKS

This device allows for shortened RS blocks,

thus not requiring zero padding when decoding.
During encoding, conversely, zero padding is not
performed. When the device is programmed to
decode a block of less than 255 Bytes, only the
message bytes followed by check bytes are sent.
Prepending with zero value bytes to fill out the
block to 255 Bytes is not required.

2.6 RESET AND INITIALIZATION SEQUENCE

The chip must b e r es et and initiali ze d a ny time

a reset is necessary.
Caveat: All six regist ers must be initialized

Reset and initialization first requires pulling the
RSTN low signal for at least two clocks while the
DSIN and DSON signals are held inact ive, i.e., high

Following this sequence, the six internal
registers, referred to as “Initialization Registers” are
strobed by DSIN. These bytes are loaded in order of

correctly for proper operation of the chip. The
device has no provisions for reading back
Initialization Regi ster sett ings. This seq uence must
be used if the device needs to be reset or any one
register needs updating, i.e., all registers must be
reinitialized for a change to any one register.

1 through 6.

The RSTN must be active low for at least two
clocks before the first initialization byte is strobed
in and remain active for at le ast o ne cl ock af ter the
final byte. RSTN must be high for at least two
clocks before the fi rst message byte can be strobed
into the device. For a deta iled timing diagram, see
Figure 7: Initializatio n and Reset Timing.

PS4013B-0600 Page 5 of 24