Advanced Hardware Architectures AHA3520A-040PQC Datasheet

PS3520-1098

The Data Coding Leader

Advanced Hardware

Architectures

TM

Advanced Hardware

Architectures, Inc.

2365 NE Hopkins Court

Pullman, WA 99163-5601

509.334.1000

Fax: [phone]

e-mail: [e-mail]

http://www.aha.com

Product Specification

AHA3520

20 MBytes/sec ALDC Data

Compression Coprocessor IC

Advanced Hardware Architectures, Inc.

PS3520-1098

i

Table of Conte n ts

1.0 Introduction

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.4.1 Port A and Port B Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

1.4.2 FIFO Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

1.4.3 Data Expansion During Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2.0 Compression Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.1 Compression Pass Through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.2 Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

3.0 Decompression Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3.1 Decompression Pass Through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3.2 Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3.3 Decompression Output Disabled Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

4.0 Microprocessor Interface and Register Access

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

4.1 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

4.1.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

4.1.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

4.2 Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

4.3 Pausing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

5.0 Port A and Port B Configuration

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

6.0 Register Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

6.1 Status 0 (STAT0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

6.2 Port A Configuration 0 (ACNF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

6.3 Port A Configuration 1 (ACNF1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

6.4 Port B Configuration 0 (BCNF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

6.5 Port B Configuration 1 (BCNF1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

6.6 Identification (ID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

6.7 Port A Polarity (APOL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

6.8 Port B Polarity (BPOL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

6.9 Port A Transfer Count (ATC0, ATC1, ATC2, ATC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

6.10 Port B Transfer Count (BTC0, BTC1, BTC2, BTC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

6.11 Error Status (ERRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1

6.12 Interrupt Status (INTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

6.13 Command (CMND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

6.14 Transfer Size (TS0, TS1, TS2, TS3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

6.15 Data Disabled Count (DDC0, DDC1, DDC2, DDC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

6.16 error mask (EMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

6.17 Interrupt Mask (IMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

7.0 Signal Descriptions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

7.1 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

7.2 Port A Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

7.3 Port B Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

8.0 Pinout

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 8

9.0 Electrical Specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

9.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

9.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

9.3 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Advanced Hardware Architectures, Inc.

ii

PS3520-1098

10.0 Timing Specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

11.0 Packaging

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

12.0 Ordering Information

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

12.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

12.2 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

13.0 AHA Related Technical Publications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Advanced Hardware Architectures, Inc.

PS3520-1098

iii

Figures

Figure 1: Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Figure 2: Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 3: Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 4: Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 5: Almost Full/Almost Empty Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 6: Processor Read Timing, MMODE = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 7: Processor Write Timing, MMODE = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 3

Figure 8: Processor Read Timing, MMODE = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 9: Processor Write Timing, MMODE = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 5

Figure 10: Port A/B Timing, Four Edge, Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 11: Port A/B Timing, Four Edge, Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 12: Port A/B Timing, Burst, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 13: Port A/B Timing, Burst, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 14: Peripheral Access Read Timing, MMODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 15: Peripheral Access Write Timing, MMODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 16: Peripheral Access Read Timing, MMODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 17: Peripheral Access Write Timing, MMODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 18: AHA3520 PQFP Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Advanced Hardware Architectures, Inc.

iv

PS3520-1098

Tables

Table 1: Microprocessor Interface Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Table 2: Port A Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 3: Port B Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 4: Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 5: Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 6: Almost Full/Almost Empty Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 7: Processor Read Timing, MMODE = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 8: Processor Write Timing, MMODE = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 3

Table 9: Processor Read Timing, MMODE = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 10: Processor Write Timing, MMODE = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 5

Table 11: Port A/B Timing, Four Edge, Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 12: Port A/B Timing, Four Edge, Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 13: Port A/B Timing, Burst, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 14: Port A/B Timing, Burst, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 15: Peripheral Access Read Timing, MMODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 16: Peripheral Access Write Timing, MMODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 17: Peripheral Access Read Timing, MMODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 18: Peripheral Access Write Timing, MMODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 19: PQFP (Plastic Quad Flat Pack) 14 mm × 20 mm Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . .34

PS3520-1098 Page 1 of 35

Advanced Hardware Architectures, Inc.

1.0 INTRODUCTION

AHA3520 is a single chip lossless compr ession
and decompression integ rated circuit implemen ting
the industry standard adaptive lossless data
compression algorithm, al so known a s ALDC. The
device compresses, decompresses or passes
through data unchanged depending on the operat ing
mode selected. This device achieves an average
compression ratio of 2:1 on typical computer files.
The flexible hardware interface makes this part
suitable for many applicat ions.

AHA 3520 is algorithm and pi nout co mp ati bl e
to the IBM ALDC device. Compressed files
between AHA and IBM’s implementation of the
algorithm do not always produce the same
compressed code stream. However, the
decompressed results are always the same. Files
compressed on either device can be interchanged
and decompressed on either device.

Content Addressable Memory (CAM) within
the compression/decompression engine eliminates
the need for external SRAMS. This part connects
directly to industry standard peripheral chips.

Included in this specification is a functional
overview, operation modes, register descriptions,
DC and AC Electrical characteristics, ordering
information, and a listing of related technical
publications. It is intended for hardware and
software engineer s designing a compres sion system
using AHA3520.

AHA designs and develops lossless
compression, forward error correction and data
storage formatter/controller ICs. Other ALDC
product offering includes AHA3521. This is a pin
and firmware compatible device that includes
additional features. Technical publications are
available upon request.

1.1 CONVENTIONS, NOTATIONS AND

DEFINITIONS

- Active low signals have an “N” appended to the

end of the signal name. For example, CSN and
WRITEN.

- “Signal assertion” means the output signal is

logically true.

- Hex values are represented with a prefix of “0x”,

such as Register “0x00”. Binary values do not
contain a prefix, for example, MMODE = 1.

- A prefix or suffix of “x” indicates a letter missing

in a register name or signal name. For example,
xCNF0 refers to the ACNF0 or BCNF0 register.

- A range of signal names or register bits is denoted

by a set of colons between the numbers. Most
significant bit is always shown first, followed by

least significant bit. For example, MDATA[7:0]
indicates signal names MDATA7 through
MDATA0.

- Mega Bytes per second is referred to as MBytes/
sec or MB/sec.

- Reserved bits in registers are referred as “

res

”.

1.2 FEATURES

PERFORMANCE:

• 20 MB/s data compression, decompression or
pass-through rate with a single 40 MHz clock

• 2:1 average compression ratio

• A four byte

Transfer Size

register allows block

transfers up to 4 gigabytes

• Error checking in decompression mode
reportable via an interrupt

FLEXIBILITY:

• In-line and Look-aside architectures supported

• Polled or interrupt driven I/O

• T wo independent DMA ports programma ble for 8
or 16-bit transfers, handshaking modes and
master or slave operation

• Programmable polarity for DMA control signals

SYSTEM INTERFACE:

• Single chip data compression solution

• Two selectable microprocessor interfaces

• Programmable Interrupts

• Interfaces directly with the AHA5140 tape
formatter and industry standard SCSI chips

OTHERS:

• Open standard ALDC adaptive lossless
compression algorithm

• Complies to QIC-154, ECMA 222, ANSI
X3.280-1996 and ISO 15200 standard
specifications

• Compatible to IBM ALDC1-20S-HA
specification

• 100 pin package in 14 × 20 mm PQFP

1.3 APPLICATIONS

• QIC or 8 mm tape drives

1.4 FUNCTIONAL DESCRIPTION

AHA3520 is a compression/decompression
device residing between the host interface, usually
SCSI, and the buffer manager ASIC. Major blocks
in this device are the Micropr ocessor Interfac e, Port
A Interface, Port B Interface, and the Compression /
Decompression Engine. The Micropro cessor
Interface provides status and control information by
register access. Port A and Port B Interfaces are
DMA ports configurable for bus width, polarity,
handshaking modes, and other options. The

Page 2 of 35 PS3520-1098

Advanced Hardware Architectures, Inc.

operating mode establishe s the direction of both the
Port A and Port B Interfaces. Compression or
Compression Pass Through sets the Port A Interface
as an input and the Port B Interface as an output.
Conversely Decompression or Decompression Pass
Through sets the Port A Interface as an output and
the Port B Interface as an input. Decompression
Output Disabled mode allows the device to
decompress a block of data up to a predetermined
point while dumping the uncompressed data, then
automatically begin outputting the remaining
uncompressed data in that block or record.

A four byte Tr ansfer Size counter allows the use r
to partition the data into bl ocks of four gigabytes or
less to process. Compression Pas s Through mode and
Decompression Pass Through modes al low data
transfers through the devi ce wi thout cha nging the
data. Both the Port A Interfac e and Po rt B I nte rface
have a 16-byte FIFO with Almost Empty and Almost
Full signal pins and progr ammable t hre shol ds. Bot h
DMA interfaces, Port A and Port B, have
programmable wait states in add it ion t o fou r
selectable DMA transfer modes: a synch ronou s
request/acknowledge pair , asynchronous burst mode,
and two peripheral acces s modes t hat correlate with
the two microprocesso r modes.

1.4.1 PORT A AND PORT B INTERFACES

Both Port A and Port B Interfaces are
independently configurable via the

Port A

Configuration

registers (ACNFx), the

Port A

Polarity

register (APOL), the

Port B Configuration

registers (BCNFx), and the

Port B Polarity

register

(BPOL). Both operate in four DMA modes.

Four-edge mode is an asynchronous dat a transfer
requiring a request and ackn owledge pul se f or each
transfer of one or two bytes, depending on th e width
configuration of the Inte rfa ce. A f our e dge transfer
begins by asserting the request signal, followed by
the acknowledge in response to t he r eque st, whi ch
causes the request to dea ssert, and final ly this causes
the acknowledge to deassert. Dat a i s tr ans fer red o n
the trailing edge of the a cknowl edge s igna l.

Burst mode is similar to four -edge mode except
there may be many acknowledges whil e the request
is held asser ted . Th e advantage of this mode i s that
it requires fewer clocks per transfer.

Two peripheral access modes exist and are
selected via the MMODE pin. Peripheral access
allows the microprocessor to write to and read from
a peripheral device connected to the Port A
Interface or P ort B Interface. This mode is a
relatively slow , asynchronous transfer. This mode is
not allowed during a data transfer operation.

1.4.2 FIFO OPERATION

Port A and Port B Interfaces both contain
sixteen-byte FIFOs with progr ammable th resholds.
AHA3520 has an Almost Full and an Almos t Empty
signal pin associated with each of the Data
Interfaces. The FIFO thres holds are programmed in
the configuration regist ers (ACNF0 and BCNF0). If
the Data Interface is configured for either four-edge
or burst mode of operation the FIFO threshold
determines when request gets asserted and
deasserted. During an output transfer the request
signal asserts when the number of bytes in the FIFO
is greater than or equal to the programmed FIFO
threshold. The interface continues to request data
transfers until the FIFO becomes empty.

When transferring data into either the Port A or
Port B Interfaces, the request signal asserts when
the number of empty byte locations in the FIFO is
greater than or equal to the programmed FIFO
threshold. The interface continues to request data
transfers until the FIFO is full.

The almost full (xAF) and almost empty (xAE)
signals are always ava ilable to the user . Almost Ful l
can be used as an early warning indicator to stop
transferring d ata i nto th e Po rt B I nterf ace or Po rt A
Interface. The xAE signal can be used to stop
transfers out of the Port A Interface or Port B
Interface

The xAF signal deasserts when a transfer
operation begins. It asserts the clock after the
number of empty byte locat ions in the FIFO is less
than or equal to the FIFO thre shold. The xAF s ignal
deasserts the clock after the number of empty byte
locations in the FIFO is greater than the FIFO
threshold.

The xAE signal asserts when a transfer
operation begins. It deasserts the clock after the
number of available bytes in the FIFO is greater than
the FIFO threshold. The xAE signal asserts after the
clock when the number of available bytes in the
FIFO is less than or equal to the FIFO threshold.

1.4.3 DATA EXPANSION DURING

COMPRESSION

Data expansion occurs when the size of the data
increases during a compressi on oper at ion. Th is
typically occurs when t he data is compressed prior to
input into the chip.The EXPAND status bit is set if
the Port B Trans fer Count is lar ger than th e

Tr ansfer

Size

register. If data expansion caused the Port B
Transfer Count t o ex ceed it s maximum 4-byte value
then the BTC Overflow Error status get s set . Worst
case expansion allowable by the algorithm is 12.5%
or (9/8 times the uncompressed t ran sfe r si ze) .

PS3520-1098 Page 3 of 35

Advanced Hardware Architectures, Inc.

Figure 1: Functional Block Diagram

2.0 COMPRESSION OPERATION

2.1 COMPRESSION PASS THROUGH

Compression Pass Through mode allows data to
enter the Port A Interface, transfer through the device
unchanged and exit through the Port B Interface. Pass
through mode uses the Port A Transfer counter, Port
B Trans f er c ounter and

Transfer Size

register. The
DONE status bit and i nterrup t (if not mask ed) are se t
when the tran sf er c ompletes.

2.2 COMPRESSION

During compression operation, uncompressed
data flows into the Port A Interface, is compressed
by the compression engin e and the compressed dat a
transferred out of the Port B Interface.

The device contains a Content Addressable
Memory (CAM). The CAM is the history buffer
during compression operation. The compressor
appends an end marker control code to the end of the
compressed data. It also pads the end of a transfer t o a
byte boundary with zeroes. End marker control

codewords are monitored during decompression, to
determine Decompression End errors.

The compression engine constantly monitors
the performance of compression for expansion
during compression operat ion. The EXPAND bit is
set if the Port B Transfer Count is larger than the
transfer size at the end of a compressi on o peration.
When the Port B Transfer Count is higher than the
Port A Transfer Count the EXPAND bit in the

Status 0

register is set indicating data expansion

during compression operation.

Port A Interface count increments with each
byte received and when this count equals the
transfer size, all bytes in this transfer have been
received into Port A.

A compression operati on is c omplete when t he
last byte transfer s out of the Port B Int erface and the
Port B Interface count is zero, thus setting the
DONE status bit and generati ng a Done Inter rupt if
it is not masked.

PORT B

TRANSFER

COUNTER

PORT A

DMA

STATE

PORT A

TRANSFER

COUNTER

MACHINE

CLOCK

GENERATION

PORT B

DMA

STATE

MACHINE

INTERRUPT

LOGIC

PROCESSOR INTERFACE

STATE MACHINE

PASS THROUGH

CONTROLLER

PROCESSOR

INTERFACE

ALDC

ENGINE

APARITY[1:0]

ADATA[15:0]

CLOCK

MDATA[7:0]

PORT A

INTERFACE

PORT B

INTERFACE

AHA3520 Compression Chip

ACOUT

ARD

APCS

AAF

BPARITY[1:0]

BDATA[15:0]

BCOUT

BCIN

BPCS

BAF

MCIN[1:0]

WAITN

ADDR[4:0]

MMODE

RESETN

IREQN

IREQ

AWR

ACIN

AAE

BAE

BRD

BWR

Page 4 of 35 PS3520-1098

Advanced Hardware Architectures, Inc.

3.0 DECOMPRESSION OPERATION

3.1 DECOMPRESSIO N PAS S THROU GH

Decompression Pass Through mode allows data
to enter the Port B Interface, transfer through the
device unchanged and exit through the Port A
Interface. Pass through mode uses the Port A Transfer
counter, Port B Transfer counter and

Transfer Size

register. The DONE status bit and interrupt (if not
masked) are set when the transfer completes.

3.2 DECOMPRESSION

During Decompression mode, compressed data
flows into the Port B Interface and is decompress ed.
The resulting uncompressed data is transfer red out of
the Port A Interface.

The number of compressed bytes in the transfer
is programmed into the four byte

Transfer Size

register. A decompression operation is complete
when the last byte transfers out of the Po rt A
Interface, thus setting the DONE status bit and
generating a Done Interrupt if it is not maske d.

Two types of errors are detected and reported
during decompression. Decoder Control Coder
Errors are caused by detection of invalid control
codes in the compress ed data stream. Decoder End
Errors are detected when either the decompressor
encountered an end control code before the
expected end of record indicated by the

Transfer

Size

register, or the end of record was reached
according to the

Transfer Size

register but no end
control code was detected. The se errors are reported
in the

Error Status

register.

3.3 DECOMPRESSION OUTPUT

DISABLED MODE

Decompressed output disabl ed mode allows the
user to decompress to a point in the record or bl ock
and rebuild the history buffer while discarding the
uncompresse d data. After the point in the file is

reached where the user wants the data (Port A
Transfer Count is equal or greater than the Data
Disable Count), the device switches to normal
decompression mode and th e rema inder of that fi le
is decompressed and transferred out of the Port A
Interface. Removal of CBG hea der s also applies to
this mode.

4.0 MICROPR OCESSOR INTER­FACE AND REGISTER ACCESS

4.1 MICROPROCESSOR INTERFACE

Microprocessor Interface configuration is
determined by the MMODE pin. If MMODE is t ied
high transfers are controlled by a chip sele ct si gnal
(CSN) and a read/write signal (RWN), otherwise
transfers are controll ed by separate read (READN),
write (WRITEN) signals. Refer to Section 10.0

Timing Specifications

for timing diagrams.

4.1.1 INTERRUPTS

IREQ and IREQN are two hardware interrupt
signals. IREQN is a negative active open-drain
output that requires a pull-up resistor if it is used.
IREQ is a standard TTL output. When active they
indicate an interrupt is set in the device. The
microprocessor can determine the cau se of the
interrupt by reading the

Interrupt Status

register.

Masking individual interrupts with the

Interrupt Mask

register disables particular
interrupts from causing the interrupt signal pins to
assert (IREQ and IREQN). Th ey do not disa ble bits
in the

Interrupt Status

register.

The interrupt signals are reset to their inactive
state when either a hardware or software reset
occurs, when a data transfer operation resumes, or
when a data transfer operation begins. In addition,
disabling Interrup t Mas k bit s aft er the In terr upt pi n
is asserted, clears the interrupt and deasserts the
Interrupt pin.

Table 1: Microprocessor Interface Control Signals

PIN NAME MMODE TIED LOW MMODE TIED HIGH

MCIN[0] READN CSN
MCIN[1] WRITEN RWN
WAITN WAITN WAITN

ADDR[0]

ADDR[0] = 0 selects register bits 7:0
ADDR[0] = 1 selects register bits 15:8

ADDR[0] = 0 selects register bits 15:8
ADDR[0] = 1 selects register bits 7:0

PS3520-1098 Page 5 of 35

Advanced Hardware Architectures, Inc.

4.1.2 RESETS

The AHA3520 has one hardware reset signal
and a software reset. When the RESETN signal is
asserted all registers except the

Identification

registers are r eset, current oper ations a re cance lled,
and the history buf fer is cleared . The s oftware reset
via the

Command

register does not affect the

Configuration

registers (ACNFx or BCNFx),

Identification

registers (IDx), either of the

Polarity

registers (APOL or BPOL), or the

Command

register (CMND). All other registers are reset,
current operations cancelled and the history buffer
cleared.

4.2 REGISTER ACCESS

MMODE determines whether ADDR[0]
selects even or odd addressed registers. When
MMODE is high and ADDR[0]=0, odd addressed
registers are accessible. MMODE=1 causes
ADDR[0] input signal to be inverted.

The following registers may not be stable if
BUSY is set:

Status 0, Status 1, Port A Transfer

Count, Port B Transfer Count, Error Status

,

Interrupt Status

and

FIFO Access

.

4.3 PAUSING

When a Pause command is issued, the device
pauses at the next break in the DMA handshaking.
When a port is in slave mode, it pauses after
xCOUT (DACKx) deasserts. When a port is in
master mode and xCOUT (DREQx) is asserted, the
port does not pause until xCIN (DACKx) is
recieved from the external DMA device. The
AHA3520 waits until both ports are paused, at
which time the BUSY status bit clears and the
PAUSED status bit and interrupt are set.

5.0 PORT A AND PORT B

CONFIGURATION

Port A and Po rt B operate identically. They
both are 16-bit bidirectional data ports with parity
checking and generation. There are three
configuration registers associated with each port
and a polarity register that determines the polarity
of all of the control signals for that port.

The function of the contro l pin is determined by
either xCNF0[13, 12] bits or

Command

register
programmed for peripheral access. The polarity of
control signals are c ontro lled b y s pecif ic bit s in the

Polarity

registers.

Table 2: Port A Interface Signals

Table 3: Port B Interface Signals

SIGNAL

NAME

MASTER

SLAVE=0

SLAVE

SLAVE=1

APOL

bit

DIRECTION

ACIN DACKA DREQA 7 I

ACOUT DREQA DACKA 5 O

AWR deasserted AWR 4 O

ARD d easserted ARD 3 O

APCS APCS APCS 2 O

AAF AAF AAF 1 O
AAE AAE AAE 0 O

SIGNAL

NAME

MASTER

SLAVE=0

SLAVE

SLAVE=1

BPOL

bit

DIRECTION

BCIN DACKB DREQB 7 I

BCOUT DREQB DACKB 5 O

BWR deasserted BWR 4 O

BRD deasserted BRD 3 O

BPCS BPCS BPCS 2 O

BAF BAF BAF 1 O

BAE BAE BAE 0 O

Page 6 of 35 PS3520-1098

Advanced Hardware Architectures, Inc.

6.0 REGISTER DESCRIPTION

Notes:

1) When CMND is not a Selection Command.

2) When CMND is a Select Port A Configuration Command.

3) When CMND is a Select Port B Configuration Command.

4) When CMND is any Transfer Command or Select Port A Configuration Command.

5) When CMND is any Transfer Command or Select Port B Configuration Command.

ADDR[4:0]

MNEMONIC REGISTER NAME R/W NOTES

REGISTER RESET VALUE

MMODE=0 MMODE=1

HARDWARE

RESET

RESET

COMMAND

NEW

TRANSFER

COMMAND

0x00 0x01 STAT0 Stat us 0 R 1 0x00 0x00 0x80
0x01 0x00

res Reserved

0x00 0x01 ACNF0 Por t A Confi g u ration 0 R/W 2 0x00 unchanged unchanged
0x01 0x00 ACNF1 Por t A Confi g u ration 1 R/W 2 0x00 unchanged unchanged
0x00 0x01 BCNF0 Port B C o n f igura tion 0 R/W 3 0x00 unchanged unchanged
0x01 0x00 BCNF1 Port B C o n f igura tion 1 R/W 3 0x00 unchanged unchanged
0x02 0x03 ID Identificati on R 1 0xC1 0xC1 0xC1
0x03 0x02

res Reserved

0x02 0x03 APOL Port A P o l a rity R/W 2 0xFF unchanged unchanged
0x03 0x02

res Reserved

0x02 0x03 BPOL Port B Po l arity R/W 3 0xFF unchanged unchanged
0x03 0x02

res Reserved

0x04 0x05 A TC2 Port A Transfer Count, Byte 2 R 4 0x00 0x00 0x00
0x05 0x04 A TC3 Port A Transfer Count, Byte 3 R 4 0x00 0x00 0x00
0x06 0x07 A TC0 Port A Transfer Count, Byte 0 R 4 0x00 0x00 0x00
0x07 0x06 A TC1 Port A Transfer Count, Byte 1 R 4 0x00 0x00 0x00
0x08 0x09 BTC2 Port B Transfer Count, Byte 2 R 5 0x00 0x00 0x00
0x09 0x08 BTC3 Port B Transfer Count, Byte 3 R 5 0x00 0x00 0x00

0x0A 0x0B BTC0 Port B Transfer Count, Byte 0 R 5 0x00 0x00 0x00
0x0B 0x0A BTC1 Port B Transfer Count , Byte 1 R 5 0x00 0x00 0x00
0x0C 0x0D ERRS Er r o r S tatus R 1 0x00 0x00 0x00
0x0D 0x0C

res Reserved

1

0x0E 0x0F INTS Inte r r u p t S tatus R 1 0x00 0x00 0x00

0x0F 0x0E

res Reserved

0x10 0x11

res Reserved

0x11 0x10 CMND Command R/W 0x00 0x00 0x00
0x12 0x13

res Reserved

0x13 0x12

res Reserved

0x14 0x15 TS2 Tra n s f e r Size , B y te 2 R/W 0x00 0x00 unchanged
0x15 0x14 TS3 Tra n s f e r Size , B y te 3 R/W 0x00 0x00 unchanged

0x16 0x17 TS0 Tra n s f e r Size , B y te 0 R/W 0x00 0x00 unchanged
0x17 0x16 TS1 Tra n s f e r Size , B y te 1 R/W 0x00 0x00 unchanged
0x18 0x19 DDC2 Data Disabled Count, Byte 2 R/W 0x00 0x00 unchanged

0x19 0x18 DDC3 Data Disabled Count, Byte 3 R/W 0x00 0x00 unchanged
0x1A 0x1B DDC0 Data Disabled Count, Byte 0 R/W 0x00 0x00 unchanged
0x1B 0x1A DDC1 Data Disabled Count, Byte 1 R/W 0x00 0x00 unchanged
0x1C 0x1D EMSK Err o r M a s k R/W 0x00 0x00 unchanged
0x1D 0x1C

res Reserved

0x1E 0x1F IMSK Inte r ru pt Mas k R/W 0x00 0x00 unchanged

0x1F 0x1E

res Reserved

PS3520-1098 Page 7 of 35

Advanced Hardware Architectures, Inc.

6.1 STATUS 0 (STAT0)

Read Only
Reset Value = 0x00
Software Reset Value = 0x00

BUSY - Busy. This bit is set when a data transfer operation begins. It is cleared when the data transfer

operation completes successfully, when an unmasked error occurs, when a reset occurs, or
when a paused command is issued by the microprocessor.

PAUSED - Paused. This bit is set when a data transfer operation is currently paused. It is cleared when a

paused dat a transfer operation is resum ed or when a reset occurs.

OUTDIS - Output Disabled. This bit i s set when Port A Interfac e output is disabled. I t is cleared when Port

A Interface output is re-enabled or when a reset occurs.

BYP ASS - Bypass. This bit is set after a Start Compression Bypass or a Start Decompression Bypass

command is written to the

Command

register. It is cleared after a Start Compression, Start

Decompression or when a reset occurs.

EXP AND - Expansion. This bit is set when the

Port B Transfer Count

register is larger than the

Transfer

Size

register at the end of a compression operation. It is cleared when another data transfer

operation begins or when a reset occurs.

ANYINT - Any Interrupt. This bit is set while an unmasked interrupt is active. This signal mirrors the

Interrupt signal pin.

ANYERR - Any Error. This bit is set when an unmasked error occurs. It is cleared when a data transfer

operation begins or when a reset occurs.

DONE - Done. This bit is set when the current data transfer operation is complete. It is cleared when a

data transfer operation begins or when a reset occurs.

6.2 PORT A CONFIGURATION 0 (ACNF0)

Read/Write
Reset Value = 0x00
Software Reset Value = unchanged

WAITST[2:0]-Wait State. These bits configure the number of wait states used during a Port A Interface

peripheral access. The values 011 through 111 are valid.

FIFOTH[3:0]-FIFO Threshold. These bits configure the Port A FIFO threshold value. Values from 0000

through 1111 are valid.

MMODE =

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

01

0x00 0x01 BUSY PAUSED OUTDIS BYP ASS EXPAND ANYINT ANYERR DONE

MMODE =

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

01

0x00 0x01 reserved WAITST[2:0] FIFOTH[3:0]