Advanced Hardware Architectures AHA3422A-033PQC Datasheet

Product Specification

AHA3422 StarLite

16 MBytes/sec Lossless

Decompressor IC

TM

2365 NE Hopkins Court

Pullman, WA 99163-5601

tel: [phone]

fax: [phone]

e-mail: [e-mail]

www.aha.com

advancedhardwarearchitectures

PS3422-0600

Advanced Hardware Architectures, Inc.

Table of Contents

1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2.0 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.1 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.1 Data Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.2 DMA Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.3 Pad Word Handling in BurstMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3.4 DMA Request Signals andStatus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3.4.1 FIFO Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3.4.2 Request During an End-of-Record. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.4.3 Request Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.5 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.6 Odd Byte Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.6.1 Input, Pad Bytes and Error Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.6.2 Output and Pad Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.7 Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.7.1 Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.8 Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.9 Decompression Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.10 Prearming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.11 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.12 Duplex Printing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.13 Blank Bands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.14 Low Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.15 Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4.0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 3

4.1 System Configuration 0, Address 0x00 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.2 System Configuration 1, Address 0x01 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.3 Input FIFO Thresholds, Address 0x02 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.4 Output FIFO Thresholds, Address 0x03 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.5 Decompression Ports Status, Address 0x05 - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.6 Port Control, Address 0x06 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.7 Interrupt Status/Control 0, Address 0x07 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.8 Interrupt Mask 0, Address 0x09 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.9 Version, Address 0x0A - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.10 Decompression Record Length, Address 0x0C, 0x0D, 0x0E, 0x0F - Read/Write. . . . . . . . . . . . . . . . . . . .18

4.11 Decompression Control, Address 0x18 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.12 Decompression Reserved, Address 0x1A, 0x3A - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.13 Decompression Line Length, Address 0x1C, 0x1D - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.14 Interrupt Status/Control 1, Address 0x27 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.15 Interrupt Mask 1, Address 0x29 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.16 Decompression Record Count, Address 0x2C, 0x2D - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.17 Pattern, Address 0x35 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.18 Decompression Control Prearm, Address 0x38 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.19 Control, Address 0x3F - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

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5.0 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

5.1 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

5.2 Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5.3 Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5.4 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

6.0 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

7.0 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 7

7.1 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

7.2 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

8.0 AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 8

9.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

10.0 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

10.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

10.2 Part Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

11.0 Related Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Appendix A: Additional Timing Diagrams for DMA Mode Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Appendix B: Sequential Register Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

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Figures

Figure 1: Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 3: Microprocessor Port Read (PROCMODE[1:0]=“01”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 4: Microprocessor Port Write (PROCMODE[1:0]=“11”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 5: Microprocessor Port Read (PROCMODE[1:0]=“11”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100 . . . . . . . . . . . . . . . . . . . . . . .6

Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100 . . . . . . . . . . . . . . . . . . . . . . .6

Figure 8: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition ofDSC=100. . . . . . . .6

Figure 9: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=100 . . . . . . .7

Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition ofDSC=100. . . . . . .7

Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=100. . . . . . .7

Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 14: Timing Diagram, Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 15: Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 16: Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 17: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=0. . . . . . . . . . . . . . . . . . . . . . .28

Figure 18: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=1. . . . . . . . . . . . . . . . . . . . . . .29

Figure 19: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0 . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 20: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1 . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 21: Output Enable Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 22: Video Output Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 23: Microprocessor Interface Timing (PROCMODE[1]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 24: Microprocessor Interface Timing (PROCMODE[1]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 25: Interrupt Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 26: Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 27: Power On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure A1: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000 . . . . . . . . . . . . . . . . . . . . . .37

Figure A2: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000 . . . . . . . . . . . . . . . . . . . . . .37

Figure A3: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition ofDSC=000. . . . . . .37

Figure A4: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=000 . . . . . .38

Figure A5: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition ofDSC=000. . . . . .38

Figure A6: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=000. . . . . .38

Figure A7: DMA Mode Timing for Single Word Writes, Strobe Condition ofDSC=010 . . . . . . . . . . . . . . . . . . . . . .39

Figure A8: DMA Mode Timing for Single Word Reads, Strobe Condition ofDSC=010 . . . . . . . . . . . . . . . . . . . . . .39

Figure A9: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition ofDSC=010. . . . . . .39

Figure A10: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=010 . . . . . .40

Figure A11: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition ofDSC=010. . . . . .40

Figure A12: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=010. . . . . .40

Figure A13: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=011 . . . . . . . . . . . . . . . . . . . . . .41

Figure A14: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011 . . . . . . . . . . . . . . . . . . . . . .41

Figure A15: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=011. . . . . . .4 1

Figure A16: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=011 . . . . . .42

Figure A17: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition ofDSC=011. . . . . .42

Figure A18: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=011. . . . . .42

Figure A19: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=111 . . . . . . . . . . . . . . . . . . . . . .43

Figure A20: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=111 . . . . . . . . . . . . . . . . . . . . . .43

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Tables

Table 1: Data Bus and FIFO Sizes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 2: Connection to Host Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3: Microprocessor Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Table 4: Internal Strobe Conditions for DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 5: Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 6: Data Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 7: Request vs. EOR Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 8: Output Enable Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 0

Table 9: Video Output Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 10: Microprocessor Interface Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 11: Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 12: Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 13: Power On Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

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1.0 INTRODUCTION

AHA3422 is a lossless decompression
coprocessor IC for hardcopy systems on many
standard platforms. The device is targeted for high
throughput and high resolution hardcopy systems.

Multiple record counters, higher clock
frequency, advanced banding and duplex printing
features enhance this product from the first
StarLite introduction, AHA3410. Identical
decompression algorithm and similar firmware
considerations ease migration to this second
generation device.

Blank band generation in real time and
prearming registers between records enable
advanced banding techniqu es. Bands may be in raw
uncompressed, compressed or blank format in the
frame buffer. The device processes all three formats
and outputs the raster data to the printer engine.
Appropriate register s are prearmed when switch ing
from one type to t he next. Byt e order ing allows full
reversal of the image data for duplex printing
support. A system may use mult iple record counters
and End-of-Transfer interrupts to easily handle
pages partitioned into smaller records or bands.

This document contains f unctional des cription,
system configurations, register descriptions,
electrical characteristics and ordering information.
It is intended for system de signers considering a
decompression coprocessor in their embedded
applications. Software simulation and an analysis of
the algorithm for printer and copier images of
various com plexity are also available for
evaluation. A comprehensive Designer’s Guide
complements this document to assist with the
system design. Section 1 1.0 contains a list of related
technical publications.

1.1 CONVENTIONS, NOTATIONS AND

DEFINITIONS

– Active low signals h ave an “N” appended to the

end of the signal name. For example, CSN and
RDYN.

– A “bar” over a signal name indicates an i nverse of

the signal. For example, SD
of SD. This terminology is used only in logic
equations.

–“Signal assertion” means the output signal is

logically true.

– Hex values are represented with a prefix of “0x”,

such as Register “0x00”. Binary values do not
contain a prefix, for example, DSC=000.

indicates an inverse

– A rang e of signal names or re gister bits is denoted

by a set of colons between the numbers. Most
significant bit i s always shown first, followed by
least significant bit. For example, VOD[7:0]
indicates signal names VOD7 through VOD0.

– A logical “AND” function of two signals is

expressed with an “&” between variables.

– Mega Bytes per second is referred to as MBytes/

sec or MB/sec.

– In re ferencing micropr ocessors, an x, xx or xxx is

used as suffix to indicate more than one
processor. For example, Motorola 68xxx
processor family includes various 68000
processors from Motorola.

– Reserved bits in registers are referred as “
– REQN or ACKN refer to either DI, or DO

Request or Acknowledge signals, as applicable.

– NC in pinout description means “no connect”.

res”.

1.2 FEATURES

PERFORMANCE:

• 16 MBytes/sec maximum sustained data
throughput

• 132 MBytes/sec burst data rate over a 32-bit data bus

• 33 MBytes/sec synchronous 8-bit video out port

• Maximum clock speeds up to 33 MHz

• Average 15 to 1 compression ratio for 1200 dpi

bitmap image data

• Advanced banding support: blank ba nds,
prearming

FLEXIBILITY:

• Big Endian or Little Endian; 32 or 16-bit bus
width and data byte reord ering for duplex printing
support

• Prearmab le registers

• Scan line length up to 2K bytes

• Interfaces directly with various MIPS, Motorola

68xxx and Cold FIRE, Intel i960 embedded
processors

• Pass-through mode passes raw data through the
decompression engine

• Counter checks errors in decompression

SYSTEM INTERFACE:

• Single chip decompression sol ution – no exte rnal
SRAM required

• Two 16 × 32-bit FIFOs with programmable
threshold counters facilitate burst mode transfers

OTHERS:

• Low power modes

• Software emulation program available

• 128 pin quad flat package

• Test pin tristates outpu ts

PS3422-0600 Page 1 of 44

Advanced Hardwar e Architectures, Inc.

Figure 1: Functional Block Diagram

32

D[31:0]

DRIVEN

DATA

PORT

32 32

DI

FIFO

16x32

DIREQN

SD

DOACKN

DIACKN

DATA PORT CONTROL

DECOMPRESSOR

DOREQN

(To Printer)

VOEOTN

DO

FIFO

16x32

888

VOD

PORT

VOEORN
VOREQN
VOD[7:0]
VOACKN

CLOCK

MICROPROCESSOR INTERFACE

AHA3422
StarLiteTM

8

6

TEST

CLK

RSTN

1.3 FUNCTIONAL OVERVIEW

PROCMODE[1:0]

PD[7:0]

CSN

DIR

RDYN

PA[5:0]

INTRN

is made available on the 32-bit data port via the
Decompression Output FIFO (DO FIFO) or the 8-

The coprocessor device has two external high
speed synchronous data ports capable of transferring
once every clock cycle. These are a 32-bit
bidirectional data port and a V ideo Output Data
(VOD) port. The 32-bit port is capable of
transferring up to 4 bytes per clock. The VOD is
capable of up to one byte per clock.

Decompression data is acc epted through the 32­bit data port, buffered in the Decompression Input

bit Video Output port. The decompression engine
runs on the 33 MHz clock and is capable of
processing an uncompresse d byte every other cloc k.

The two FIFOs are organized as 16×32 each.
For data transfers through the two ports, the
“effective” FI FO sizes dif fer according to their data
bus widths. The table below shows the size of the
data port and the “effective” FIFO size for the
various configurations supported by the device.

FIFO (DI FIFO) and decompre ssed. The output data

Table 1: Data Bus and FIFO Sizes Supported

OPERATION DATA BUS WIDTH PORT EFFECTIVE FIFO SIZE

Decompression Data In/Out 32 Data Port 16 x 32
Decompression Data In/Out 16 Data Port 16 x 16
Decompressed Data Out 8 Video Out 16 x 8

Table 2: Connection to Host Microprocessors

PIN NAME i960Cx i960Kx IDT3081

PA A LAD Latched Address Latched Address

CSN

DIR

CS

W/R

CS

W/R WR R/W

PD D LAD A/D A/D[7:0]
SD

RDYN No Connect

DRIVEN

WAIT

DEN

READY
READY

System Dependent

CLOCK PCLK No Connect

Page 2 of 44 PS3422-0600

System Dependent

System Dependent

ACK TA

System Dependent System Dependent

SYSCLK

Motorola

MCFS102(ColdFIRE)

Decoded Chip Select

System Dependent

BCLOCK

Advanced Hardware Architectures, Inc.

Movement of data for decompression is
performed using sync hronous DMA over the 32- bit
data port. The Video port also supports synchronous
DMA mode transfers. The DMA strobe conditions
are configurable for the 32-bit data port depending
upon the system processor and the available DMA
controller.

Data transfer for dec ompression is synchronous
over the two data ports functioning as DMA
masters. To initiate a transfer out of the Video port,
the device asserts VORE QN, the external device
responds with VOACKN and begins to transfer data
over the VOD bus on each succeedi ng rising edge of
the clock until VOREQN is deasserted. The 32-bit
port relies on the FIFO Threshold settings to
determine the transfer.

The sections below describe the various
configurations, programming and other special
considerations in developing a decompression
system using AHA3422.

2.0 SYSTEM CONFIGURATION

This section provides information on
connecting the device to various microprocessors.

Data throughput is internally controlled by
writing a control code to the Control register . If this
feature is not used, the system must control data
throughput to remain within the specified limit of 16
MBytes/sec. The control code for this device is 0x0E.

2.1 MICROPROCESSOR INTERFACE

The device is capable of interfacing directly to
various processors for embedde d application. T able 2
and Table 3 show how to connect t o var iou s host
microprocessors.

All register accesse s are performed on the 8-bit
PD bus. The PD bus is the lowest byte of the 32-bit
microprocessor bus. During reads of th e internal
registers, the upper 24 bits are not driven. System
designers should terminate these lines with Pullup
resistors.

The part provides four modes of operation for
the microprocesso r port. Both active high and a ctive
low write enable si gnals are al lowed a s well as two
modes for chip select. T he mode of oper atio n is set
by the PROCMODE[1:0] pins. The
PROCMODE[1] signal selects when CSN must be
active and also how long an access lasts.

When PROCMODE[1] is high, CSN
determines the le ngth of the acces s. CSN must be at
least 5 clocks in length. On a read, valid data is
driven onto PD[7:0] during th e 5th clock. If CSN is
longer than 5 clocks, t hen valid data c ontinues to be
driven out onto PD[7:0]. When CSN goes inactive
(high), PD[7:0] goes tristate (asynchronously) and
RDYN is driven high as ynchronously . CSN must be
high for at least t wo clocks. RDYN is always drive n
(it is not tristated when P RO CM OD E [1 ] is high). The
mode is typical of processors such as the Motorola
68xxx.

When PROCMODE[1] is low, accesses are
fixed at 5 clocks, PD[7:0] is onl y driven dur ing the
fifth clock, and RDYN is driven high for the first 4
clocks and low during the fifth clock. RDYN is
tristated at all other times. Write data must be driven
the clock after CSN is sampled low. Accesses may
be back to back with no delays in between. This
mode is typical of RISC p rocessors such as the i960.

PROCMODE[0] determines the polarity of the
DIR pin. If PROCMODE[0] is high, then the DIR
pin is an active low write enable. If PROCMODE[0]
is low, then the DIR pin is an active high write
enable. Figure 2 through Figure 5 illustrate the
detailed timing diagrams for the microprocessor
interface.

For additional notes on interfacing to various
micropro cessors, refer to AHA Application Note
(ANDC16), Designer’ s Guid e for StarLite
Products. AHA Applications Engineering is
available to supp ort with other pr ocessors not i n the
Designer’s Guide.

TM

Family

Table 3: Microprocessor Port Configuration

PROCMODE[1:0] DIR CYCLE LENGTH EXAMPLE PROCESSOR

00 Active high write fixed i960
01 Active low write fixed
10 Active high write variable
11 Active low write variable 68xxx, MIPS R3000

PS3422-0600 Page 3 of 44

Advanced Hardwar e Architectures, Inc.

Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”)

CLOCK

PA[5:0]

CSN

DIR

PD[7:0]

RDYN

A0

D0 D1

Figure 3: Microprocessor Port Read (PROCMODE[1:0]=“01”)

CLOCK

PA[5:0]

CSN

DIR

A0

A1

A1

A2

PD[7:0]

RDYN

D0

Figure 4: Microprocessor Port Write (PROCMODE[1:0]=“11”)

CLOCK

PA[5:0]

CSN

DIR

PD[7:0]

RDYN

A0

D0

D1

A1

Page 4 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

ACKN()& SD()

ACKN()& SD()

ACKN

delayed

()& SD

delayed

()

ACKN

delayed

()& SD

delayed

()

ACKN()& ACKN

delayed

()

ACKN()& ACKN

delayed

()

Figure 5: Microprocessor Port Read (PROCMODE[1:0]=“11”)

CLOCK

PA[5:0]

CSN

DIR

PD[7:0]

RDYN

A0

3.0 FUNCTIONAL DESCRIPTION

This section describes the var ious data ports,

special handling, data formats and cl ocking structure.

3.1 DATA PORTS

The device contains one data input port, DI, and
one data output port, DO, on the same 32-bit data bus,
D[31:0]. Data transfers are controlled by external
DMA control. The logical conditions under which data
is written to the input FIFO or read from the output
FIFO are set by the DSC (Data Strobe Condition) field
of the

System Configuration 1 register.

A strobe condition defines under what logical
conditions the input FIFO is written or the output
FIFO read. DIACKN, DOACKN, and SD pins
combine to strobe data in a manner similar to DMA
controllers. The DMA Mode
the various data strobe options.

sub-section describes

A1

D0

3.2 DMA MODE

On the rising edge of CLOCK when the strobe
condition is met, the port with the active
acknowledge either strobes data into or out of the
chip. No more than one port may assert acknowledge
at any one time. T able 4 shows the various conditions
that may be programmed into register DSC.

Figure 6 through Figure 11 illustrate the DMA
mode timings for single, four word and eight word
burst transfers for DSC=100 selection. For other
DSC settings, please refer to Appe ndix A. Note that
the only differe nce between odd and eve n values of
DSC is the polarity of SD. Waveforms are only
shown for polari ties of SD correspondi ng to specific
systems.

Table 4: Internal Strobe Conditions for DMA Mode

PS3422-0600 Page 5 of 44

DSC[2:0] LOGIC EQUATION SYSTEM CONFIGURATION

000
001 No specifi c system

ACKN()& ACKN
ACKN()& ACKN

()& SD()
()& SD()

delayed

delayed

010 General purpose DMA controller

011

100 No specifi c system
101 No specifi c system

110 No specific sy stem
111 No specific syst em

CKN

SD

i960Cx with internal DMA contro ller. SD is connected to
WAITN.

i960Kx with external, bus master type DMA controller.
SD is connected to RDYN.

delayed
delayed

ACKN delayed 1 clock=
SD delayed 1 clock=

Advanced Hardwar e Architectures, Inc.

Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D0 D1

Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D1D0

Figure 8: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition

of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3

Page 6 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

Figure 9: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition

of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D1D0 D2 D3

Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition

of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wa it State, Strobe Condition

of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

PS3422-0600 Page 7 of 44

Advanced Hardwar e Architectures, Inc.

3.3 PAD WORD HANDLING IN
BURST MODE

A method is available to delete pad words during
decompression. Pad words may be deleted by using
the Decompression Pause on Record Boundaries bit
(DPOR), in the Decompression Control register.
After the part is paused, the DI FIFO must be reset by
asserting the DIRST bit in the Port Control register.
Decompressor must also be reset by asserting DDR
bit in Decompression Control register.

3.4 DMA REQUEST SIGNALS

AND STATUS

The part requests data using request pins
(DIREQN, DOREQN) . The req ues ts a re co nt rol le d
by programmable FIFO thresholds. Both input and
output FIFOs have programmable empty and full
thresholds set in the Input FIFO Threshol d
Output FIFO Threshold registers. By requesting
only when a FIFO can sustain a certain burst size, the
bus is used more efficiently.

Operation of these request signals should not be
confused with the request signals on the video port.
DIREQN active indicates space available in the input
FIFO and DOREQN active indicates data is available
in the output FIFO. These request signals being
inactive do not prevent data transfers. The data
transfers are controlled solely with the particular
acknowledge signal being active.

The input request, DIREQN, ope rates under the
following prioritized rules, listed in order of highest
to lowest:

1) If the FIFO re set in the
register is active, the requ est is inactive.

2) If a FIFO overflow interrupt is active, the
request is inactive.

3) If the FIFO is at or below the empty
threshold, the request remains active.

4) If the FIFO is a t or above the fu ll threshold,
the request stays inactive.

Port Control

and

The output request, DOREQN, operates under
the following prioritized rules, listed in order of
highest to lowest:

1) If the FIFO reset in the
register is active, the request is inactive.

2) If the output FIFO underflow interrupt is
active, the request is inactive.

3) If an EOR is pres ent in the output FIFO, th e
request goes active.

4) If the output FIFO is at or above the full
threshold, the request goes acti ve.

5) If an EOR is read (strobed) out of the FI FO,
the request goes inactive during the same
clock as the strobe (if ERC=0), otherwi se it
goes inactive on the next clock.

6) If the output FIFO i s at or below the empt y
threshold, the request goes inact ive.

Port Control

3.4.1 FIFO THRESHOLD

For maximum efficiency, the FIFO t hreshold
should be set in such a way that the decompressor
seldom runs out of data from the DI FIFO or
completely fills the output FIFO. The FIFO is 16
words deep.

For example, in a system with fixed 8-word
bursts, good values for the thresholds are:

IET=3, IFT=4, OFT=D, OET=C

Setting the input full threshold to one higher
than the input empty threshold simply guarantees
that the request deasserts as soon as possible. The
latency between a word being strobed in and the
request changing due to a FIFO threshold condition
is 3 clocks. This should be ke p t in mi nd wh e n
programming threshold values. Refer to Section 4.0
of AHA Applicat i o n Not e ( AND C1 6) , Designer’s

Guide for StarLite

thorough discussion of FIFO thresholds. The
following figure shows an example of an input FIFO
crossing its full threshold.

TM

Family Products for a more

Page 8 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO)

CLOCK

3

234

45

6

5

7

6

8

78

CIACKN

CIREQN

Threshold

Counter

D

1

1

2

Note: DIREQN deasserted when threshold counter exceeded IFT=4, but additional words are read as long as

ACKN is asserted.

Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010

CLOCK

CIACKN

D

EOR-2

EOR-1

EOR

9

REQN

(ERC=0)

REQN

(ERC=1)

EORN

3.4.2 REQUEST DURING AN END-OF-RECORD

The request deasserts at an EOR in one of two
ways. If ERC bit in System Conf igurati on 1 is zero,
the request deasserts as ynchronously during the
clock where the EOR is strobed out of the FIFO.
This leads to a lo ng output delay for REQN, but may
be necessary in some systems. For DSC values of 4
or 5, the request deasserts the first clock after the
acknowledge pulse for the EOR. If ERC is set to
one, then the request deasserts synchronously the
clock after the EOR is strobed out. The minimum
low time on the request in this case is one clock.

The request delay varies between the different
strobe conditions. See Section 8.0 AC Electrical
Specifications for further details.

3.4.3 REQUEST STATUS BITS

An externa l microproc essor can also read the
value of each requ est using the DIREQ and DOREQ
bits in the Decompression Port Status register.
Please note the request status bits are active high
while the pins are active low.

3.5 DATA FORMAT

The width of the D bus is selected with the
WIDE bit in System Configuration 0. If WIDE=1,
then D is a 32-bit bus. If WIDE=0, D is a 16-bit bus.
If the bus is configured to be 16-bits wide
(WIDE=0), all data transfers occur on D[15:0] and
the upper 16 bits of the bus, D[31:16], should be
terminated with Pullup res istors. If WIDE=0, the
FIFO is sixteen words deep.

PS3422-0600 Page 9 of 44

Advanced Hardwar e Architectures, Inc.

Since the compression algorithm is byte
oriented, it is necessary for AHA3422 to know the
ordering of the bytes within the word. The
DECOMP BIG bit in System Co nfiguration 0 selects
between big endian and little endian b yte or der in g.
Little endian stores the first byte in the lower eight
bits of a word (D[7:0]). Big endian stores the first
byte in the uppe rmost eight bi ts of a word ( D[3 1: 24 ]
for WIDE=1, D[15:8] for WIDE=0).

3.6 ODD BYTE HANDLING

All data transfers to or from the device are
performed on the D bus on wo rd bounda ries . Since
no provision is made for single byte transfers,
occasionally words will contain pad bytes.
Following is a descriptio n of when t hese pad bytes
are necessary for each of the data interfaces.

3.6.1 INPUT, PAD BYTES AND ERROR

CHECKING

The device reco gnizes the end of a record by the
appearance of a special End-of- Record sequence in
the data stream. Once this is seen, the remaining
bytes in the current word are treated as pad bytes
and discarded. The word following the end of the
record is the beginning of the next record.

The Decompression Record Length (DRLEN)
register can be used to provide er ror c hecking. The
expected length of the decompressed record is
programmed into the DRLEN register. The
decompressor then counts down from the value in
DRLEN to zero.

A DERR interrupt is issued if an EOR is not
read out of the decompressor when the counter
expires or if an EOR occurs before the counter
expires (i.e., when th e record lengths do not match).
If the DERR interrupt is masked, us e of the DRLEN
register is optional.

When operating in pass-thr ough mode, there is
no End-of-Record codeword for the decompressor
to see. In pass-through mode, the user must set the
record length in the DRLEN register.

Figure 14: Timing Diagram, Video Output

3.6.2 OUTPUT AND PAD BYTES

When the decompressor detects an End-of­Record codeword, it will add enough pad bytes of
value 0x00 to complete the current word as defined
by the WIDE bit in the System Configuration 0
register. For example, if a record ends on a byte
other than the last byte in a word, the final word
contains 1, 2 or 3 pad bytes. This applies to the 32­bit data port only, not the VOD port. The VOD port
never outputs pad bytes since it is 8-bits wide.

3.7 VIDEO INTERFACE

3.7.1 VIDEO OUTPUT

The video output por t i s enabled by the VDOE
bit in the System Configurat ion 1 regi st er. The port
uses VORE QN to indicate that the byte on
VOD[7:0] is valid. An 8-bit word is re ad each clock
when both VOREQN and VOACKN are sampled
low on a rising edge of CLOCK. Pad bytes at an end
of record are discarde d by the video outp ut port and
do not appear on VOD[7:0]. When the byte on
VOD[7:0] is the last by te in a record, the VOEORN
signal goes low . Unlike a DMA transfer , there are no
pad bytes after an End-of-Record.

VOEOTN operates similar to VOEORN. It flags
the end of an output transfer of one or more
decompressed records. VOEOTN is asserted when the
End-of-Record is at the output of the DO FIFO and the
decompression record count has decremented to zero.

The port requests whenever a valid byte is
present on the output. The values in OET and OFT
are all ignored. The decompression output FIFO is
16 bytes
can output up to one byte per clock. The DMA
interface cannot access the decompression output
FIFO when VDOE is set.

deep in this mode. The video output port

CLOCK

VOREQN

VOACKN

VOD[7:0]

VOEORN/

VOEOTN

Page 10 of 44 PS3422-0600

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