Datasheet AHA3422A-033PQC Datasheet (Advanced Hardware Architectures)

Product Specification

AHA3422 StarLite

16 MBytes/sec Lossless

Decompressor IC

TM

2365 NE Hopkins Court

Pullman, WA 99163-5601

tel: [phone]

fax: [phone]

e-mail: [e-mail]

www.aha.com

advancedhardwarearchitectures

PS3422-0600

Advanced Hardware Architectures, Inc.

Table of Contents

1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2.0 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.1 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.1 Data Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.2 DMA Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.3 Pad Word Handling in BurstMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3.4 DMA Request Signals andStatus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3.4.1 FIFO Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3.4.2 Request During an End-of-Record. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.4.3 Request Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.5 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.6 Odd Byte Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.6.1 Input, Pad Bytes and Error Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.6.2 Output and Pad Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.7 Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.7.1 Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.8 Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.9 Decompression Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.10 Prearming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.11 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.12 Duplex Printing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.13 Blank Bands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.14 Low Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.15 Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4.0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 3

4.1 System Configuration 0, Address 0x00 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.2 System Configuration 1, Address 0x01 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.3 Input FIFO Thresholds, Address 0x02 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.4 Output FIFO Thresholds, Address 0x03 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.5 Decompression Ports Status, Address 0x05 - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.6 Port Control, Address 0x06 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.7 Interrupt Status/Control 0, Address 0x07 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.8 Interrupt Mask 0, Address 0x09 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.9 Version, Address 0x0A - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.10 Decompression Record Length, Address 0x0C, 0x0D, 0x0E, 0x0F - Read/Write. . . . . . . . . . . . . . . . . . . .18

4.11 Decompression Control, Address 0x18 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.12 Decompression Reserved, Address 0x1A, 0x3A - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.13 Decompression Line Length, Address 0x1C, 0x1D - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.14 Interrupt Status/Control 1, Address 0x27 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.15 Interrupt Mask 1, Address 0x29 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.16 Decompression Record Count, Address 0x2C, 0x2D - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.17 Pattern, Address 0x35 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.18 Decompression Control Prearm, Address 0x38 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.19 Control, Address 0x3F - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

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5.0 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

5.1 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

5.2 Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5.3 Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5.4 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

6.0 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

7.0 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 7

7.1 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

7.2 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

8.0 AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 8

9.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

10.0 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

10.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

10.2 Part Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

11.0 Related Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Appendix A: Additional Timing Diagrams for DMA Mode Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Appendix B: Sequential Register Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

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Figures

Figure 1: Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 3: Microprocessor Port Read (PROCMODE[1:0]=“01”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 4: Microprocessor Port Write (PROCMODE[1:0]=“11”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 5: Microprocessor Port Read (PROCMODE[1:0]=“11”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100 . . . . . . . . . . . . . . . . . . . . . . .6

Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100 . . . . . . . . . . . . . . . . . . . . . . .6

Figure 8: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition ofDSC=100. . . . . . . .6

Figure 9: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=100 . . . . . . .7

Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition ofDSC=100. . . . . . .7

Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=100. . . . . . .7

Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 14: Timing Diagram, Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 15: Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 16: Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 17: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=0. . . . . . . . . . . . . . . . . . . . . . .28

Figure 18: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=1. . . . . . . . . . . . . . . . . . . . . . .29

Figure 19: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0 . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 20: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1 . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 21: Output Enable Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 22: Video Output Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 23: Microprocessor Interface Timing (PROCMODE[1]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 24: Microprocessor Interface Timing (PROCMODE[1]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 25: Interrupt Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 26: Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 27: Power On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure A1: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000 . . . . . . . . . . . . . . . . . . . . . .37

Figure A2: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000 . . . . . . . . . . . . . . . . . . . . . .37

Figure A3: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition ofDSC=000. . . . . . .37

Figure A4: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=000 . . . . . .38

Figure A5: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition ofDSC=000. . . . . .38

Figure A6: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=000. . . . . .38

Figure A7: DMA Mode Timing for Single Word Writes, Strobe Condition ofDSC=010 . . . . . . . . . . . . . . . . . . . . . .39

Figure A8: DMA Mode Timing for Single Word Reads, Strobe Condition ofDSC=010 . . . . . . . . . . . . . . . . . . . . . .39

Figure A9: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition ofDSC=010. . . . . . .39

Figure A10: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=010 . . . . . .40

Figure A11: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition ofDSC=010. . . . . .40

Figure A12: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=010. . . . . .40

Figure A13: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=011 . . . . . . . . . . . . . . . . . . . . . .41

Figure A14: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011 . . . . . . . . . . . . . . . . . . . . . .41

Figure A15: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=011. . . . . . .4 1

Figure A16: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition ofDSC=011 . . . . . .42

Figure A17: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition ofDSC=011. . . . . .42

Figure A18: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=011. . . . . .42

Figure A19: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=111 . . . . . . . . . . . . . . . . . . . . . .43

Figure A20: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=111 . . . . . . . . . . . . . . . . . . . . . .43

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Tables

Table 1: Data Bus and FIFO Sizes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 2: Connection to Host Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3: Microprocessor Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Table 4: Internal Strobe Conditions for DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 5: Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 6: Data Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 7: Request vs. EOR Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 8: Output Enable Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 0

Table 9: Video Output Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 10: Microprocessor Interface Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 11: Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 12: Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 13: Power On Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

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1.0 INTRODUCTION

AHA3422 is a lossless decompression
coprocessor IC for hardcopy systems on many
standard platforms. The device is targeted for high
throughput and high resolution hardcopy systems.

Multiple record counters, higher clock
frequency, advanced banding and duplex printing
features enhance this product from the first
StarLite introduction, AHA3410. Identical
decompression algorithm and similar firmware
considerations ease migration to this second
generation device.

Blank band generation in real time and
prearming registers between records enable
advanced banding techniqu es. Bands may be in raw
uncompressed, compressed or blank format in the
frame buffer. The device processes all three formats
and outputs the raster data to the printer engine.
Appropriate register s are prearmed when switch ing
from one type to t he next. Byt e order ing allows full
reversal of the image data for duplex printing
support. A system may use mult iple record counters
and End-of-Transfer interrupts to easily handle
pages partitioned into smaller records or bands.

This document contains f unctional des cription,
system configurations, register descriptions,
electrical characteristics and ordering information.
It is intended for system de signers considering a
decompression coprocessor in their embedded
applications. Software simulation and an analysis of
the algorithm for printer and copier images of
various com plexity are also available for
evaluation. A comprehensive Designer’s Guide
complements this document to assist with the
system design. Section 1 1.0 contains a list of related
technical publications.

1.1 CONVENTIONS, NOTATIONS AND

DEFINITIONS

– Active low signals h ave an “N” appended to the

end of the signal name. For example, CSN and
RDYN.

– A “bar” over a signal name indicates an i nverse of

the signal. For example, SD
of SD. This terminology is used only in logic
equations.

–“Signal assertion” means the output signal is

logically true.

– Hex values are represented with a prefix of “0x”,

such as Register “0x00”. Binary values do not
contain a prefix, for example, DSC=000.

indicates an inverse

– A rang e of signal names or re gister bits is denoted

by a set of colons between the numbers. Most
significant bit i s always shown first, followed by
least significant bit. For example, VOD[7:0]
indicates signal names VOD7 through VOD0.

– A logical “AND” function of two signals is

expressed with an “&” between variables.

– Mega Bytes per second is referred to as MBytes/

sec or MB/sec.

– In re ferencing micropr ocessors, an x, xx or xxx is

used as suffix to indicate more than one
processor. For example, Motorola 68xxx
processor family includes various 68000
processors from Motorola.

– Reserved bits in registers are referred as “
– REQN or ACKN refer to either DI, or DO

Request or Acknowledge signals, as applicable.

– NC in pinout description means “no connect”.

res”.

1.2 FEATURES

PERFORMANCE:

• 16 MBytes/sec maximum sustained data
throughput

• 132 MBytes/sec burst data rate over a 32-bit data bus

• 33 MBytes/sec synchronous 8-bit video out port

• Maximum clock speeds up to 33 MHz

• Average 15 to 1 compression ratio for 1200 dpi

bitmap image data

• Advanced banding support: blank ba nds,
prearming

FLEXIBILITY:

• Big Endian or Little Endian; 32 or 16-bit bus
width and data byte reord ering for duplex printing
support

• Prearmab le registers

• Scan line length up to 2K bytes

• Interfaces directly with various MIPS, Motorola

68xxx and Cold FIRE, Intel i960 embedded
processors

• Pass-through mode passes raw data through the
decompression engine

• Counter checks errors in decompression

SYSTEM INTERFACE:

• Single chip decompression sol ution – no exte rnal
SRAM required

• Two 16 × 32-bit FIFOs with programmable
threshold counters facilitate burst mode transfers

OTHERS:

• Low power modes

• Software emulation program available

• 128 pin quad flat package

• Test pin tristates outpu ts

PS3422-0600 Page 1 of 44

Advanced Hardwar e Architectures, Inc.

Figure 1: Functional Block Diagram

32

D[31:0]

DRIVEN

DATA

PORT

32 32

DI

FIFO

16x32

DIREQN

SD

DOACKN

DIACKN

DATA PORT CONTROL

DECOMPRESSOR

DOREQN

(To Printer)

VOEOTN

DO

FIFO

16x32

888

VOD

PORT

VOEORN
VOREQN
VOD[7:0]
VOACKN

CLOCK

MICROPROCESSOR INTERFACE

AHA3422
StarLiteTM

8

6

TEST

CLK

RSTN

1.3 FUNCTIONAL OVERVIEW

PROCMODE[1:0]

PD[7:0]

CSN

DIR

RDYN

PA[5:0]

INTRN

is made available on the 32-bit data port via the
Decompression Output FIFO (DO FIFO) or the 8-

The coprocessor device has two external high
speed synchronous data ports capable of transferring
once every clock cycle. These are a 32-bit
bidirectional data port and a V ideo Output Data
(VOD) port. The 32-bit port is capable of
transferring up to 4 bytes per clock. The VOD is
capable of up to one byte per clock.

Decompression data is acc epted through the 32­bit data port, buffered in the Decompression Input

bit Video Output port. The decompression engine
runs on the 33 MHz clock and is capable of
processing an uncompresse d byte every other cloc k.

The two FIFOs are organized as 16×32 each.
For data transfers through the two ports, the
“effective” FI FO sizes dif fer according to their data
bus widths. The table below shows the size of the
data port and the “effective” FIFO size for the
various configurations supported by the device.

FIFO (DI FIFO) and decompre ssed. The output data

Table 1: Data Bus and FIFO Sizes Supported

OPERATION DATA BUS WIDTH PORT EFFECTIVE FIFO SIZE

Decompression Data In/Out 32 Data Port 16 x 32
Decompression Data In/Out 16 Data Port 16 x 16
Decompressed Data Out 8 Video Out 16 x 8

Table 2: Connection to Host Microprocessors

PIN NAME i960Cx i960Kx IDT3081

PA A LAD Latched Address Latched Address

CSN

DIR

CS

W/R

CS

W/R WR R/W

PD D LAD A/D A/D[7:0]
SD

RDYN No Connect

DRIVEN

WAIT

DEN

READY
READY

System Dependent

CLOCK PCLK No Connect

Page 2 of 44 PS3422-0600

System Dependent

System Dependent

ACK TA

System Dependent System Dependent

SYSCLK

Motorola

MCFS102(ColdFIRE)

Decoded Chip Select

System Dependent

BCLOCK

Advanced Hardware Architectures, Inc.

Movement of data for decompression is
performed using sync hronous DMA over the 32- bit
data port. The Video port also supports synchronous
DMA mode transfers. The DMA strobe conditions
are configurable for the 32-bit data port depending
upon the system processor and the available DMA
controller.

Data transfer for dec ompression is synchronous
over the two data ports functioning as DMA
masters. To initiate a transfer out of the Video port,
the device asserts VORE QN, the external device
responds with VOACKN and begins to transfer data
over the VOD bus on each succeedi ng rising edge of
the clock until VOREQN is deasserted. The 32-bit
port relies on the FIFO Threshold settings to
determine the transfer.

The sections below describe the various
configurations, programming and other special
considerations in developing a decompression
system using AHA3422.

2.0 SYSTEM CONFIGURATION

This section provides information on
connecting the device to various microprocessors.

Data throughput is internally controlled by
writing a control code to the Control register . If this
feature is not used, the system must control data
throughput to remain within the specified limit of 16
MBytes/sec. The control code for this device is 0x0E.

2.1 MICROPROCESSOR INTERFACE

The device is capable of interfacing directly to
various processors for embedde d application. T able 2
and Table 3 show how to connect t o var iou s host
microprocessors.

All register accesse s are performed on the 8-bit
PD bus. The PD bus is the lowest byte of the 32-bit
microprocessor bus. During reads of th e internal
registers, the upper 24 bits are not driven. System
designers should terminate these lines with Pullup
resistors.

The part provides four modes of operation for
the microprocesso r port. Both active high and a ctive
low write enable si gnals are al lowed a s well as two
modes for chip select. T he mode of oper atio n is set
by the PROCMODE[1:0] pins. The
PROCMODE[1] signal selects when CSN must be
active and also how long an access lasts.

When PROCMODE[1] is high, CSN
determines the le ngth of the acces s. CSN must be at
least 5 clocks in length. On a read, valid data is
driven onto PD[7:0] during th e 5th clock. If CSN is
longer than 5 clocks, t hen valid data c ontinues to be
driven out onto PD[7:0]. When CSN goes inactive
(high), PD[7:0] goes tristate (asynchronously) and
RDYN is driven high as ynchronously . CSN must be
high for at least t wo clocks. RDYN is always drive n
(it is not tristated when P RO CM OD E [1 ] is high). The
mode is typical of processors such as the Motorola
68xxx.

When PROCMODE[1] is low, accesses are
fixed at 5 clocks, PD[7:0] is onl y driven dur ing the
fifth clock, and RDYN is driven high for the first 4
clocks and low during the fifth clock. RDYN is
tristated at all other times. Write data must be driven
the clock after CSN is sampled low. Accesses may
be back to back with no delays in between. This
mode is typical of RISC p rocessors such as the i960.

PROCMODE[0] determines the polarity of the
DIR pin. If PROCMODE[0] is high, then the DIR
pin is an active low write enable. If PROCMODE[0]
is low, then the DIR pin is an active high write
enable. Figure 2 through Figure 5 illustrate the
detailed timing diagrams for the microprocessor
interface.

For additional notes on interfacing to various
micropro cessors, refer to AHA Application Note
(ANDC16), Designer’ s Guid e for StarLite
Products. AHA Applications Engineering is
available to supp ort with other pr ocessors not i n the
Designer’s Guide.

TM

Family

Table 3: Microprocessor Port Configuration

PROCMODE[1:0] DIR CYCLE LENGTH EXAMPLE PROCESSOR

00 Active high write fixed i960
01 Active low write fixed
10 Active high write variable
11 Active low write variable 68xxx, MIPS R3000

PS3422-0600 Page 3 of 44

Advanced Hardwar e Architectures, Inc.

Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”)

CLOCK

PA[5:0]

CSN

DIR

PD[7:0]

RDYN

A0

D0 D1

Figure 3: Microprocessor Port Read (PROCMODE[1:0]=“01”)

CLOCK

PA[5:0]

CSN

DIR

A0

A1

A1

A2

PD[7:0]

RDYN

D0

Figure 4: Microprocessor Port Write (PROCMODE[1:0]=“11”)

CLOCK

PA[5:0]

CSN

DIR

PD[7:0]

RDYN

A0

D0

D1

A1

Page 4 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

ACKN()& SD()

ACKN()& SD()

ACKN

delayed

()& SD

delayed

()

ACKN

delayed

()& SD

delayed

()

ACKN()& ACKN

delayed

()

ACKN()& ACKN

delayed

()

Figure 5: Microprocessor Port Read (PROCMODE[1:0]=“11”)

CLOCK

PA[5:0]

CSN

DIR

PD[7:0]

RDYN

A0

3.0 FUNCTIONAL DESCRIPTION

This section describes the var ious data ports,

special handling, data formats and cl ocking structure.

3.1 DATA PORTS

The device contains one data input port, DI, and
one data output port, DO, on the same 32-bit data bus,
D[31:0]. Data transfers are controlled by external
DMA control. The logical conditions under which data
is written to the input FIFO or read from the output
FIFO are set by the DSC (Data Strobe Condition) field
of the

System Configuration 1 register.

A strobe condition defines under what logical
conditions the input FIFO is written or the output
FIFO read. DIACKN, DOACKN, and SD pins
combine to strobe data in a manner similar to DMA
controllers. The DMA Mode
the various data strobe options.

sub-section describes

A1

D0

3.2 DMA MODE

On the rising edge of CLOCK when the strobe
condition is met, the port with the active
acknowledge either strobes data into or out of the
chip. No more than one port may assert acknowledge
at any one time. T able 4 shows the various conditions
that may be programmed into register DSC.

Figure 6 through Figure 11 illustrate the DMA
mode timings for single, four word and eight word
burst transfers for DSC=100 selection. For other
DSC settings, please refer to Appe ndix A. Note that
the only differe nce between odd and eve n values of
DSC is the polarity of SD. Waveforms are only
shown for polari ties of SD correspondi ng to specific
systems.

Table 4: Internal Strobe Conditions for DMA Mode

PS3422-0600 Page 5 of 44

DSC[2:0] LOGIC EQUATION SYSTEM CONFIGURATION

000
001 No specifi c system

ACKN()& ACKN
ACKN()& ACKN

()& SD()
()& SD()

delayed

delayed

010 General purpose DMA controller

011

100 No specifi c system
101 No specifi c system

110 No specific sy stem
111 No specific syst em

CKN

SD

i960Cx with internal DMA contro ller. SD is connected to
WAITN.

i960Kx with external, bus master type DMA controller.
SD is connected to RDYN.

delayed
delayed

ACKN delayed 1 clock=
SD delayed 1 clock=

Advanced Hardwar e Architectures, Inc.

Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D0 D1

Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D1D0

Figure 8: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition

of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3

Page 6 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

Figure 9: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition

of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D1D0 D2 D3

Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition

of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wa it State, Strobe Condition

of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

PS3422-0600 Page 7 of 44

Advanced Hardwar e Architectures, Inc.

3.3 PAD WORD HANDLING IN
BURST MODE

A method is available to delete pad words during
decompression. Pad words may be deleted by using
the Decompression Pause on Record Boundaries bit
(DPOR), in the Decompression Control register.
After the part is paused, the DI FIFO must be reset by
asserting the DIRST bit in the Port Control register.
Decompressor must also be reset by asserting DDR
bit in Decompression Control register.

3.4 DMA REQUEST SIGNALS

AND STATUS

The part requests data using request pins
(DIREQN, DOREQN) . The req ues ts a re co nt rol le d
by programmable FIFO thresholds. Both input and
output FIFOs have programmable empty and full
thresholds set in the Input FIFO Threshol d
Output FIFO Threshold registers. By requesting
only when a FIFO can sustain a certain burst size, the
bus is used more efficiently.

Operation of these request signals should not be
confused with the request signals on the video port.
DIREQN active indicates space available in the input
FIFO and DOREQN active indicates data is available
in the output FIFO. These request signals being
inactive do not prevent data transfers. The data
transfers are controlled solely with the particular
acknowledge signal being active.

The input request, DIREQN, ope rates under the
following prioritized rules, listed in order of highest
to lowest:

1) If the FIFO re set in the
register is active, the requ est is inactive.

2) If a FIFO overflow interrupt is active, the
request is inactive.

3) If the FIFO is at or below the empty
threshold, the request remains active.

4) If the FIFO is a t or above the fu ll threshold,
the request stays inactive.

Port Control

and

The output request, DOREQN, operates under
the following prioritized rules, listed in order of
highest to lowest:

1) If the FIFO reset in the
register is active, the request is inactive.

2) If the output FIFO underflow interrupt is
active, the request is inactive.

3) If an EOR is pres ent in the output FIFO, th e
request goes active.

4) If the output FIFO is at or above the full
threshold, the request goes acti ve.

5) If an EOR is read (strobed) out of the FI FO,
the request goes inactive during the same
clock as the strobe (if ERC=0), otherwi se it
goes inactive on the next clock.

6) If the output FIFO i s at or below the empt y
threshold, the request goes inact ive.

Port Control

3.4.1 FIFO THRESHOLD

For maximum efficiency, the FIFO t hreshold
should be set in such a way that the decompressor
seldom runs out of data from the DI FIFO or
completely fills the output FIFO. The FIFO is 16
words deep.

For example, in a system with fixed 8-word
bursts, good values for the thresholds are:

IET=3, IFT=4, OFT=D, OET=C

Setting the input full threshold to one higher
than the input empty threshold simply guarantees
that the request deasserts as soon as possible. The
latency between a word being strobed in and the
request changing due to a FIFO threshold condition
is 3 clocks. This should be ke p t in mi nd wh e n
programming threshold values. Refer to Section 4.0
of AHA Applicat i o n Not e ( AND C1 6) , Designer’s

Guide for StarLite

thorough discussion of FIFO thresholds. The
following figure shows an example of an input FIFO
crossing its full threshold.

TM

Family Products for a more

Page 8 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO)

CLOCK

3

234

45

6

5

7

6

8

78

CIACKN

CIREQN

Threshold

Counter

D

1

1

2

Note: DIREQN deasserted when threshold counter exceeded IFT=4, but additional words are read as long as

ACKN is asserted.

Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010

CLOCK

CIACKN

D

EOR-2

EOR-1

EOR

9

REQN

(ERC=0)

REQN

(ERC=1)

EORN

3.4.2 REQUEST DURING AN END-OF-RECORD

The request deasserts at an EOR in one of two
ways. If ERC bit in System Conf igurati on 1 is zero,
the request deasserts as ynchronously during the
clock where the EOR is strobed out of the FIFO.
This leads to a lo ng output delay for REQN, but may
be necessary in some systems. For DSC values of 4
or 5, the request deasserts the first clock after the
acknowledge pulse for the EOR. If ERC is set to
one, then the request deasserts synchronously the
clock after the EOR is strobed out. The minimum
low time on the request in this case is one clock.

The request delay varies between the different
strobe conditions. See Section 8.0 AC Electrical
Specifications for further details.

3.4.3 REQUEST STATUS BITS

An externa l microproc essor can also read the
value of each requ est using the DIREQ and DOREQ
bits in the Decompression Port Status register.
Please note the request status bits are active high
while the pins are active low.

3.5 DATA FORMAT

The width of the D bus is selected with the
WIDE bit in System Configuration 0. If WIDE=1,
then D is a 32-bit bus. If WIDE=0, D is a 16-bit bus.
If the bus is configured to be 16-bits wide
(WIDE=0), all data transfers occur on D[15:0] and
the upper 16 bits of the bus, D[31:16], should be
terminated with Pullup res istors. If WIDE=0, the
FIFO is sixteen words deep.

PS3422-0600 Page 9 of 44

Advanced Hardwar e Architectures, Inc.

Since the compression algorithm is byte
oriented, it is necessary for AHA3422 to know the
ordering of the bytes within the word. The
DECOMP BIG bit in System Co nfiguration 0 selects
between big endian and little endian b yte or der in g.
Little endian stores the first byte in the lower eight
bits of a word (D[7:0]). Big endian stores the first
byte in the uppe rmost eight bi ts of a word ( D[3 1: 24 ]
for WIDE=1, D[15:8] for WIDE=0).

3.6 ODD BYTE HANDLING

All data transfers to or from the device are
performed on the D bus on wo rd bounda ries . Since
no provision is made for single byte transfers,
occasionally words will contain pad bytes.
Following is a descriptio n of when t hese pad bytes
are necessary for each of the data interfaces.

3.6.1 INPUT, PAD BYTES AND ERROR

CHECKING

The device reco gnizes the end of a record by the
appearance of a special End-of- Record sequence in
the data stream. Once this is seen, the remaining
bytes in the current word are treated as pad bytes
and discarded. The word following the end of the
record is the beginning of the next record.

The Decompression Record Length (DRLEN)
register can be used to provide er ror c hecking. The
expected length of the decompressed record is
programmed into the DRLEN register. The
decompressor then counts down from the value in
DRLEN to zero.

A DERR interrupt is issued if an EOR is not
read out of the decompressor when the counter
expires or if an EOR occurs before the counter
expires (i.e., when th e record lengths do not match).
If the DERR interrupt is masked, us e of the DRLEN
register is optional.

When operating in pass-thr ough mode, there is
no End-of-Record codeword for the decompressor
to see. In pass-through mode, the user must set the
record length in the DRLEN register.

Figure 14: Timing Diagram, Video Output

3.6.2 OUTPUT AND PAD BYTES

When the decompressor detects an End-of­Record codeword, it will add enough pad bytes of
value 0x00 to complete the current word as defined
by the WIDE bit in the System Configuration 0
register. For example, if a record ends on a byte
other than the last byte in a word, the final word
contains 1, 2 or 3 pad bytes. This applies to the 32­bit data port only, not the VOD port. The VOD port
never outputs pad bytes since it is 8-bits wide.

3.7 VIDEO INTERFACE

3.7.1 VIDEO OUTPUT

The video output por t i s enabled by the VDOE
bit in the System Configurat ion 1 regi st er. The port
uses VORE QN to indicate that the byte on
VOD[7:0] is valid. An 8-bit word is re ad each clock
when both VOREQN and VOACKN are sampled
low on a rising edge of CLOCK. Pad bytes at an end
of record are discarde d by the video outp ut port and
do not appear on VOD[7:0]. When the byte on
VOD[7:0] is the last by te in a record, the VOEORN
signal goes low . Unlike a DMA transfer , there are no
pad bytes after an End-of-Record.

VOEOTN operates similar to VOEORN. It flags
the end of an output transfer of one or more
decompressed records. VOEOTN is asserted when the
End-of-Record is at the output of the DO FIFO and the
decompression record count has decremented to zero.

The port requests whenever a valid byte is
present on the output. The values in OET and OFT
are all ignored. The decompression output FIFO is
16 bytes
can output up to one byte per clock. The DMA
interface cannot access the decompression output
FIFO when VDOE is set.

deep in this mode. The video output port

CLOCK

VOREQN

VOACKN

VOD[7:0]

VOEORN/

VOEOTN

Page 10 of 44 PS3422-0600

0 31 2 4 5

Advanced Hardware Architectures, Inc.

3.8 ALGORITHM

AHA3422 efficiently imple me nts an al gori th m
optimized for bitonal im ages . For so me compar ison
data refer to the AHA Application Note (ANDC1 3),

Compression Performance: StarLiteTM:
ENCODEB2 on Bitonal Images. A software

emulation of the algori thm is avai lable for
evaluation.

3.9 DECOMPRESSION ENGINE

The decompression engine is enabled with the
DCOMP bit in the Deco mpr ession Contr ol register .
When the engine is enabled, it takes data from the
DI FIFO as it becomes available. This dat a is either
decompressed by the engine or passed through
unaltered. Pass-through mode is selected with the
DPASS bit. DPASS may only be changed when
DCOMP is set to zero and DEMP is set to one. The
contents of the dictionary are preserved when
DCOMP is changed. However, when DPASS is
changed, the contents are lost. Consequently,
AHA3422 cannot be changed from pass-through
mode to decompression mode or vice versa without
losing the contents of the dictionary.

The decompressor can be i nstructed to halt at the
end of a record or an end of multiple- record tr ansfer.
If the DPOR bit is set, the decompressor stops taking
data out of the DI FIFO immediat ely aft er t he l ast
byte of a record, and the DCOMP bit is c leared. I f
DPOT bit is set the decompressor halts at the end of
the multiple-record trans fer . The DEMP bit indicates
the decompressor has emptied of a ll data . Decom­pression is restarted by set ti ng the DCOMP bit. If
DPOR or DPOT is set and data from a second r ecord
enters the FIFO immediately after the first record,
bytes from the second reco rd will have entered the
decompressor prior to decodin g the EOR. An impli­cation of this is that bytes from the second record will
remain in the decompressor and pr event DEMP from
setting after all of t he data from the first re cord has
left the decompressor. This differs from operati on of
the compression engine. In eit her mode , a DEOR
interrupt is generated when the last byte of a de com­pressed record is read out o f t he chi p, and DEOT
when the last byte of a transfer is read out of the chip.

The decompressor takes data from the
decompression input FIFO at a maximum rate of
16 MBytes/sec. AHA3422 can maintain this data
rate as long as t he deco mpression input FIFO is not
empty or the decompression output FIFO is not full.

Caveat: Changing the mode for the

decompressor between r ecords or multiple-record
transfers must be done with the data of t he following
record or transfer held off until the DEOR status bit
is true for the current record and the Decompression
Control registers have been reprogrammed. This
reprogramming can occur automatically with
prearming.

3.10 PREARMING

Prearming is the ability to write certain
registers that apply to the next record w hile the
device is processing the current record. These
registers may be prearmed for record bounda ri es.
Prearming is automatic, meani ng there is no way to
disable it. If a prearmable register is written while
the part is bus y processing a re cord, at the end o f the
record the part takes its program from the register
value last written. Decompression Control register
has a corresponding prearm register.

The lower 3 bytes of Decompression Length
register are prearmable. If the most significant byte
of this register is written to, the counter is
immediately loaded with the current 4 byte value. if
the most significant byte is not written to the counter,
the counter gets reloaded at the end of the current
record.

3.11 INTERRUPTS

Five conditions are reported in the Interrupt
Status/ Cont rol 0 and Status/Control 1 registers as

individual bits. All interrupts are maskable by
setting the corr esponding bit s in the Int errupt Mas k
register . A one in the Interrupt Mask register means
the corresponding bit in the Interrupt Status/Cont rol
register is masked and does not affect the interrupt
pin (INTRN). The INTRN pin is active whenever
any unmasked interrupt bit is set to a one.

An End-of-R ecord interrupt is posted w hen a
word containing an end-of-record is strobed out of
the decompression output FI FO (DEOR). A DEOR
interrupt is als o reported if an end-of -record i s read
from the video output port. A de compression end of
transfer interrupt will be posted if this is the last
record of a transfer. End-of-Transfer interrupt
(DEOT) is posted when an EOR occurs that causes
the counter to decrement to zero.

Two FIFO error conditions are also reported.
Overflowing the input FIFO generates a DIOF
interrupt. An overflow can only be cleared by
resetting the FIFO via the Port Control register.

Underflowing the outp ut FIFO (reading when it
is not ready) generates a DOUF. The underflow
interrupt is cleared by writi ng a one to DOUF . In the
event of an underflow, the FIFO must be reset.

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3.12 DUPLEX PRINTING

Duplex Printing is the ability to print on both
sides of the page. AHA3422 supports this with
endian control.

During decompression o f this reversed page the
BIG bit in this register must be programmed to the
same value used when this page of data was
compressed. Use of this feature has virtually no
effect on the decompress ion ratio when compared to
decompressing in forward order.

3.13 BLANK BANDS

Setting DBLANK in the Decompression
Control r egist er ca uses t he ne xt recor d outp ut from

the Decompressor to be co mprised of a r epeating 8­bit pattern defined by the Pattern register.
DBLANK automatically clears at the end of the
next record. This co mmand bit may be prearmed by
writing to the Decompression Control Prearm
register . When pr ogramming the device to generate
blank records the system must not send data to be
decompressed until the device has reached the end
of record for the blank record.

3.14 LOW PO WER MODE

The device is a data-driv en system. W hen no
data transfers are taking place, only the clock and
on-chip RAMs including the FIFOs require power.
To reduce power consumption to its absolute
minimum, the user can stop the clock when it is
high. With the system clock stopped and at a high
level, the current consumption is due to leakage.
Control and Status registers are preserved in this
mode. Reinitialization of Control registers are not
necessary when switching from Low Power to
Normal operating mode.

3.15 TEST MODE

In order to facilitate board level testing, the
device provides the ability to tristate all outputs.
When the TEST0 pin is high, all outputs of the chip
are tristated. When TEST0 is low, the chip returns to
normal operation.

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4.0 REGISTER DESCRIPTIONS

The microprocessor configures, controls and monitors IC operation through the use of the registers
defined in this sect ion. The bits la beled “
unless otherwise noted.

Always program the control r egi st er (address 0x3F) with a value of 0x0E f ol lowi ng powe r on and any
hard reset. This should be done prior to accessing any other registers.

A summary of registers is listed below.

Table 5: Internal Registers

ADDRESS R/W DESCRIPTION FUNCTION

res” are reserved and must b e set to zer o when writ ing t o re gis ters

DEFAULT

AFTER

RSTN

PREARM

0x00 R/W System Configuration 0

0x01 R/W System Configuration 1

0x02 R/W Input FIFO Thresholds

0x03 R/W Output FIFO Thresholds
0x04 R Reserved Reserved Undefined
0x05 R Decompression Ports Status
0x06 R/W Port Control 1 Reset Individual FIFOs 0x0F No

0x07 R/W Interrupt Status/Control 0 EOR, Overflow, Underflow 0x00 No
0x09 R/W Interrupt Mask 0 Interrupt Mask bits 0xFF No
0x0A R Version Die Version Number 0x21 No

0x0C R/W

0x0D R/W

0x0E R/W

0x0F R/W
0x10 R Reserved

0x11 R Reserved Reserved Undefined
0x12 R Reserved Reserved Undefined
0x13 R Reserved Reserved Undefined
0x14 R Reserved

0x15 R Reserved Reserved 0x00
0x16 R Reserved Reserved Undefined
0x17 R Reserved Reserved Undefined

0x18 R/W Decompression Control

Decompression Record
Length 0
Decompression Record
Length 1
Decompression Record
Length 2

Decompression Record
Length 3

Big Endian vs. Little Endian,
32-bit vs. 16-bit
Data Strobe Condition, EOR
Request Control, VDO Port
Enable

Input FIFO Empty Threshold,
Full Threshold
Output FIFO Empty
Threshold, Full Threshold

FIFO Status, Request St at us,
EOR Status

Bytes Remaining, Byte 0
Bytes Remaining, Byte 1 0xFF Yes

Bytes Remaining, Byte 2 0xFF Yes

Bytes Remaining, Byte 3 0xFF No
Reserved

Reserved

Pause on Record Boundaries,
Enable Decompression
Engine, Decompression
Engine Empty Status,
Dictionary Reset, Enable
Pass-Through Mode, Pause
End-of-Transfer, Generate
Blank Record, Enable Prearm

Undefined No

0x00 No

Undefined No

Undefined No

Undefined No

0xFF Yes

Undefined

0x04

0x04 Yes

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DEFAULT

ADDRESS R/W DESCRIPTION FUNCTION

0x1A R/W Decompression Reserved 1 Reserved 0x00 No
0x1C R/W Decompression Line Length 0

0x1D R/W Decompression Line Length 1
0x20 R Reserved Reserved FF

0x21 R Reserved Reserved FF
0x27 R/W Interrupt Status/Cont rol 1 Decompression EOT Inte rrupt 0x00 No
0x29 R/W Interrupt Mask 1 Interrupt Mask bit for DEOT 0xFF No

0x2C R/W Decompression Record Count 0

0x2D R/W Decompression Record Count 1
0x30 R Reserved Reserved 0x00

0x31 R Reserved Reserved 0x00
0x32 R Reserved Reserved 0x00
0x33 R Reserved Reserved 0x00
0x34 R Reserved Reserved 0x00

0x35 R/W Pattern

0x38 R/W Decompression Control Prearm
0x3A R/W Decompression Reserved 2 Reserved 0x00 No

0x3F R/W Cont ro l Pro gra m to 0x0E 0x0F No

Line Length Register Lower
8bits
Line Length Register Upper
3bits

Decompressor number of
records in a transfer
Decompressor number of
records in a transfer

8-bit pattern for blank record
generation
Prearm Register for
Decompression Control

AFTER

RSTN

Undefined No

Undefined No

0xFF No

0xFF No

Undefined No

0x00 No

PREARM

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4.1 SYSTEM CONFIGURATION 0, ADDRESS 0x00 - READ/WRITE

Address

0x00

After reset, its c ontents are undefined . It must be written be fore any input or out put data movement may
be performed. After changing this register, reset FIFOs via the Port Control register.

BIG- Selects between little or big endian byte order for the decompressor. See table.
res - Bits must always be written with zeros.
WIDE - Selects between 32 and 16-bit D buses.

COMP BIG or
DECOMP BIG

0 0 Little Endian data order 16-bit words

0 1 Little Endian data order 32-bit words

1 0 Big Endian data order 16-bit words

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

res

WIDE

res

BIG res

WIDE DESCRIPTION

D[15:8] D[7:0]

Byte 1 Byte 0

D[31:24] D[23:16] D[15:8] D[7:0]

Byte 3 Byte 2 Byte 1 Byte 0

D[15:8] D[7:0]

Byte 0 Byte 1

1 1 Big Endian data order 32-bit words

D[31:24] D[23:16] D[15:8] D[7:0]

Byte 0 Byte 1 Byte 2 Byte 3

4.2 SYSTEM CONFIGURATION 1, ADDRESS 0x01 - READ/WRITE

Address

0x01

This register is cleared by reset.
DSC[2:0] - Data Strobe Condit ion. Control the conditio n used to str obe da ta into and out of the data ports

res - Bits must always be written with zeros.
ERC - EOR Request Control. Determine s when DOREQN deass erts at an End-of- Record . If ERC=0,

VDOE - VDO Port Enable. When this bit is set, the data from the decompression output FIFO goes to

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

res

on the D bus. T a ble 4 shows the p rogramming for t he strobe cond ition for va rious DMA modes.

then the request deasserts asynchronously during the clock when an EOR is strobed out. If
ERC=1, then the request deasserts synchronously the clock after an EOR is strobed out. See
Figure 17 through Figure 20.

the VDO port. When the bit is clear, the decompressed data is read by DMA on the D bus.

VDOE ERC

res

DSC[2:0]

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4.3 INPUT FIFO THRESHOLDS, ADDRESS 0x02 - READ/WRITE

Address

0x02 IFT[3:0] IET[3:0]

After reset, its c ontents are undefined . It must be written be fore any input or out put data movement may
be performed.

IET[3:0] - Empty threshold for the i nput FIF O. If the n umber of wor ds in t he input FIFO (D I) is les s than

IFT[3:0] - Full threshold for t he input FIFO. If t he number of wo rds in the i nput FIFO (DI ) is greater than

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

or equal to this number, the request for that channel is asserted.

or equal to this number, the request for the channel is deasserted.

4.4 OUTPUT FIFO THRESHOLDS, ADDRESS 0x03 - READ/WRITE

Address

0x03 OFT[3:0] OET[3:0]

After reset, its c ontents are undefined . It must be written be fore any input or out put data movement may
be performed.

OET[3:0] - Empty threshold for the output FIFO. If the number of words in the output FIFO (DO) is less

OFT[3:0] - Full threshold for the output FIFO. If the number of words in the output FIFO (DO) is greater

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

than or equal to this number, the request for the channel is deasserted (except in the case of an
End-of-Record).

than or equal to this numb er, the request for that channel is asserted.

4.5 DECOMPRESSION PORTS STATUS, ADDRESS 0x05 - READ ONLY

Address

0x05 DOEMP DIEMP res DEOR DOREQ DOET DIREQ DIFT

This is a read only register. Writing to this register has no eff ect. Afte r reset , its cont ents are undefine d.
DIFT - Decompression input FI FO full th reshold. This s ignal is active when the DI FIFO is at or above

DIREQ - Decompression input request signal st ate. Reports the current stat e for the DIREQN pin. Notice

DOET - Decompression output FIFO empty threshold. This bit is active when the DO FIFO is at or

DOREQ - Decompression output request signal state. Reports the current state for the DOREQN pin.

DEOR - Decompression output end of record. This bit is active when th e output FIFO contai ns the End-

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

the progra mmed FIFO full threshold. After reset and the Input FIFO Threshold register h as
been written, this bit contains a zero.

that this bit is active high while the pin is active low. Therefore, the value of this bit is always
the inverse of the value of the signal. After reset this bit contains a zero.

below the programmed FIFO empty threshold. After reset and the Output FIFO Threshold
register has been written, this bit contains a one.

Notice that this bit is active high while the pin is active low. Therefore, the value of this bit is
always the inverse of the value of the signal. After reset this bit contains a zero.

of-Record code. After reset this bit contains a zero.

res - Bits must always be written with zeros.

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DIEMP - Decompression input empty. This bit is active when the DI FIFO is empty. After reset this bit

contains a one.

DOEMP - Decompression output empty. This bit is active when the DO FIFO is empty. After reset this bit

contains a one.

4.6 PORT CONTROL, ADDRESS 0x06 - READ/WRITE

Address

0x06 res DORST DIRST res

This register is initialized to 0x0F after reset.
DIRST - Decompression input reset. Setting this bit to a one resets the DI FIFO and clears the state

DORST - Decompression output reset. Setting this bit to a one resets the DO FIFO and clears the state

res - Bits must always be written with zeros.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

machines in the decompression input port. The reset condition remains active until the
microprocessor writes a zero to this bit.

machines in the decompression output port. The reset condition remains active until the
microprocessor writes a zero to this bit.

4.7 INTERRUPT STATUS/CONTROL 0, ADDRESS 0x07 - READ/WRITE

Address

0x07 DOUF res DIOF res DERR DEOR res

This register is initialized to 0x00 after reset.
DEOR - Decompression End-of-Recor d interrupt. This bit is set when the last byte of a recor d is strobed

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

out of the decompression DMA or video output port. The microprocessor must write a one to
this bit to clear this interrupt.

DERR - Decompression Error. This bit is set if an EOR leaves the decompressor before DRLEN has

counted down to zero or if DRLEN counts to zero and the last byte is not an EOR. DERR is
only active in decompression mode (DPASS=0). The microprocessor must write a one to this

bit to clear this interrupt.
res - Bits must always be written with zeros.
DIOF - Decompression Input FIFO Overflow. This interrupt is generated when a write to an already

full DI FIFO is performed . Data written in this condition is lost. The only means of recovery

from this error is to reset the FIFO with the DIRST bit. Resetting the FIFO causes this interrupt

to clear. DIREQN is inactive while the interrupt is set.
DOUF - Decompression Output FIFO underflow . Th is interrupt is generated when a read from an empt y

DO FIFO is performed. Once this interrupt is set, the DO FIFO must be reset with the DORST

bit. The micropro cessor mus t write a one to this bi t to c lear thi s inte rrupt. DOREQN i s inactive

while the interrupt is set.

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4.8 INTERRUPT MASK 0, ADDRESS 0x09 - READ/WRITE

Address

0x09 DOUFM res DIOFM res DERRM DEORM res

This register is initiali zed to 0xFF after reset.

DEORM - Decompression End-of-Record Interrupt Mask. When set to a one, prevents Decompression

DERRM - Decompression Error Mask. When set to a one, prevents a decompressi on er ro r (DERR) fro m

res - Bits must always be written with zeros.
DIOFM - Decompression Input FIFO Overflow Mask. When set to a one, prevents a decompression

DOUFM - Decompression Output FIFO Underflow Mask. When set to a one, prevents a decompression

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

End-of-Record from causing INTRN to go active.

causing INTRN to go active.

input FIFO overflow (DIOF) from causing INTRN to go active.

output FIFO underflow (DOUF) from causing INTRN to go active.

4.9 V ERSION, ADDRESS 0x0A - READ ONLY

Address

0x0A VERSION[7:0]

VERSION[7:0] - Contains version number of the die.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

4.10 DECOMPRESSION RECORD LENGTH, ADDRESS 0x0C, 0x0D, 0x0E, 0x0F -

READ/WRITE

Address

0x0C DRLEN[7:0]
0x0D DRLEN[15:8]
0x0E DRLEN[23:16]
0x0F DRLEN[31:24]

These registers are initialized to 0xFF after reset.

DRLEN[31:0]-Decompression Record Length. Contains the number of bytes in a decompressed record.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

These registers provide different functions depending on whether the decompressor is in pass-

through or decompression mode. In decompression mode, the data itself contains EOR

information and DRLEN is only used for error checking. DRLEN is decremented each time a

byte leaves the decompressor.

In decompression mode, a DERR interrupt is issued if an EOR is not read out of the

decompressor when the counter expires or if an EOR occurs before the counter expires (i.e.,

when the record lengths do not match). If the DERR interrupt is masked, use of the DRLEN

register is optional in decompression mode.

In pass-through mode, DRLEN determines the size of records read out of the decompressor.

The counter is decremented for each byte read into the decompressor.

In either mode, the counter reloads when it reaches zero or when DRLEN[31:24] is written.

Reading DRLEN returns the number of bytes left in the count. The lower three bytes of this

register may be prearmed since the counter is automatically reloaded at the end of a record

when the part is not progra mmed to pause on End-of-Re cord. The upper byte i s not prearmable

since writing to this byte triggers an immediate reload to the counter.

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4.11 DECOMPRESSION CONTROL, ADDRESS 0x18 - READ/WRITE

Address

0x18 DPREARM DBLANK DPOT DPASS DDR DEMP DCOMP DPOR

This register is initialized to 0x04 after reset. This register can be prearmed.

DPOR - Decompression Pause on record boundaries. When th is bit is set to on e, the decompressor sto ps

DCOMP - Decompression. Setting this bit to a one enables the decompression engine (or pass-through

DEMP - Decompression engine empty. This bit is set when the decompression e ngine is clear ed of data.

DDR - Decompression Dictionary Reset. Setting this bit immediately resets the decompressor

DPASS - Decompression pass-through mode. While this bit is set, data is passed directly through the

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

taking data from the input FIFO once a record boundary is found. Upon finding the record

boundary , DCOMP is cleared . This bit may only be changed wh en DCOMP is set to zero. After

system reset or DDR, this bit is cleared.

mode if DPASS is set) to take data from the decompression input FIFO. If this bit is cleared,

decompression stops. The bit is automatically cleared at the end of a record if DPOR is set.

Decompression can be r est ar te d wit hout loss of data by set ti ng DCOMP. After system r ese t o r

DDR, this bit is cleared.

Writing to this bit h as no effect. After system reset, this bit is set.

including the decompression dictionary. The reset condition remains active until the

microprocessor writes a zero to this bit.

decompression engine without any effect on the data. This bit may only be changed when

decompression is disabled (DCOMP=0) and the decompression engine is empty of data

(DEMP=1). The pass-th rough operat ion is sta rted by sett ing DCOMP. T o stop the pass-thr ough

operation, DCOMP should be cleared (to pause operation) and then DPASS may be cleared.
DPOT - Decompression Pause on Transfer Boundaries. When this bit is set the decompressor stops

taking data from the input FIFO once a decompression end of transfer boundary is found

indicated by the Decompression Record Counter decrementing to zero.
DBLANK -Decompression Blank record. The data in the next record output from the decompressor is a

repeating byte pattern using the 8-bit data defined in the PATTERN register. DBLANK

automatically clears at the end of the record when the Decompression Record Count

decrements to zero. When using DBLANK to generate a blank record the device must not

contain data to be decompressed an d the syste m must not send data to be dec ompressed for a ny

future records u ntil the pa rt has r eached the End- of-Rec ord fo r t he bla nk rec ord. Also, t he user

must not set the DCOMP bit when the DBLANK bit is set.
DPREARM -Prearm Enable. When this bit i s set, Decompre ssion Control Prearm regi ster is lo aded into the

Decompression Control register when the next end of record leaves the decompressor.

4.12 DECOMPRESSION RESERVED, ADDRESS 0x1A, 0X3A - READ/WRITE

Address

0x1A res
0x3A res

This regist er is used for production testing only. Initialized to 0x00 after reset.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

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4.13 DECOMPRESSION LINE LENGTH, ADDRESS 0x1C, 0x1D - READ/WRITE

Address

0x1C LINE[7:0]
0x1D res LINE[10:8]

This register conta ins information necessary for the decompression opera tion. It must be set prior to any
decompression operati on. It sho uld only be ch anged bet ween rec ords when DCOMP is clear ed and DEMP
is set. These registers are undefined af ter reset.

res - Bits must always be written with zeros.
LINE[10:0 ]-Line length. The numbe r of byt es i n the scan line. Minimum value is 16 . For s can l ine lengths

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

larger than the maximum allowed, set to 16.

4.14 INTERRUPT STATUS/CONTROL 1, ADDRESS 0x27 - READ/WRITE

Address

0x27 res DEOT res

This register is initialized to 0x00 after reset.
DEOT - Decompression End-of-Trans fer Interr upt. This bit is s et when a deco mpression end of transfer

res - Bits must always be written with zeros.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

condition is reached indicated by the Decompression Record Counter counting down to zero.
The microprocessor must w rite a one to this bit to clear this interrupt.

4.15 INTERRUPT MASK 1, ADDRESS 0x29 - READ/WRITE

Address

0x29 res DEOTM res

This register is initiali zed to 0xFF after reset.
DEOTM - Decompression End-of-Transfer Interrupt Mask. When set to a one, prevents Decompression

res - Bits must always be written with zeros.
res - Bits must always be written with zeros.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

End-of-Transfer from causing INTRN to go active.

4.16 DECOMPRESSION RECORD COUNT, ADDRESS 0x2C, 0x2D - READ/WRITE

Address

0x2C DRC[7:0]
0x2D DRC[15:8]

These registers are initialized to 0xFFFF after reset.
DRC[15:0] -Decompression Record Count is the number of records in the current transfer. The internal record

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

counter latches the value in this register when DRC[15:8] is written. The internal counter is
decremented as the last byte of the record is decompressed. At the End-of-Transfer, the value in
this register is reloaded into the internal record counter. Reading this register address returns the
internal record counter value. Expiration of this counter causes the DEOT interrupt to be posted.

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4.17 PATTERN, ADDRESS 0x35 - READ/WRITE

Address

0x35 PATTERN[7:0]

This register is undefined after reset.
P ATTERN[7:0]-Pattern i s the 8-bit data used to generate blank bands or rec ords. If DBLANK is set, the p art

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

outputs this register value repeatedly for the entire record (or band).

4.18 DECOMPRESSION CONTROL PREARM, ADDRESS 0x38 - READ/WRITE

Address

0x38 NDPREARM NDBLANK NDPOT NDPASS NDDR res NDCOMP NDPOR

This register initializes to 0x00 after reset. This register is cleared when the prearm loads into the
Decompression Control register, thus providing a method for the user to verify that the prearm loaded.

Note, the user must not change modes of operation between decompression, pass-through and blank
when there is data in the decompressor. See Decompression Control register for bit descriptions. This
register is the prearm register for the Decompression Control register.

res - Bits must always be written with zeros.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

4.19 CONTROL, ADDRESS 0x3F - READ/WRITE

Address

0x3F CONTROL CODE

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

This register must be written with 0x0E before a decompression or pass-through operation begins.
Default aft er reset is 0x0F.

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5.0 SIGNAL DESCRIPTIONS

This section contains descriptions for all the pins. Each signal has a type code associated with it. The
type codes are described in the following table.

TYPE CODE DESCRIPTION

I Input only pin

O Output only pin

I/O Input/Output pin

S Synchronous signal

A Asynchronous signal

5.1 MICROPROCESSOR INTERFACE

MICROPROCESSOR INTERFACE

SIGNAL TYPE DESCRIPTION

PD[7:0] I/O

S

PA[5:0] I

S

CSN I

S

DIR I

S

RDYN O

A,S

INTRN O

S

PROCMODE[1:0] I

S

Processor Data. Data for all microprocessor reads and writes of
registers within AHA3422 ar e per for med on this bus. This bu s may
be tied to the Data bus, D[31:0], provided microprocessor accesses
do not occur at the same time as DMA accesses.

Processor Address Bus. Used to address internal registers within
AHA3422.

Chip Select. Selects AHA3422 as the source or destination of the
current microprocesso r bus c ycle. CSN needs only be ac tive for one
clock cycle to start a microprocessor access.

Direction. This signal indicates whether the access to the register
specified by the P A bus is a read or a write. The polarity of this signal
is programmed with the PROCMODE0 pin.
Ready. Indicates valid data is on the data bus during read operation
and completion of write operation. Its operation depends on
PROCMODE[1:0] settings.
Interrupt. The compression and decompression processes generate
interrupts that are reported with this signal. INTRN is low whenever
any non-masked bits are set in the Interrupt Status/Control

Microprocessor Port Confi guration Mode. Selects the polarity of the
DIR pin and operation of the CSN pin. Refer to Section 2.1

Microprocessor Interface for details. (Figure 2 through Figure 5)

register.

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5.2 DATA INTERFACE

DATA INTERFACE

SIGNAL TYPE DESCRIPTION

D[31:0] I/O

S

DRIVEN I

A

SD I

S

DIREQN O

S

DIACKN I

S

DOREQN O

A, S

DOACKN I

S

Data for all channels is transmitted on this bus. The ACKN is used to
distinguish betwee n the four channels . Data being writte n to AHA3422 is
latched on the rising edge of CLOCK when the strobe condition is met.
Data setup and hold times a re relative to CLOCK. If the bus is configured
to 16-bit transfers (WIDE=0), data is carried on D[15:0]. In this case,
D[31:16] should be terminated with pullup resistors.
Drive Enable. Active low output dri ver enable. Thi s input must be low in
order to drive data onto D[31:0] in accordance with the current strobe
condition.

Strobe Delay . Active high. Allows insertion of wait states for DMA
access to the FIFOs. The strobe condition, as programmed in the DSC
field of System Configuration 1, enables this signal and selects its
polarity.

Decompression Input Data Request, active low. When this signal is
active, it indicates the ability of the DI port to accept data.

Decompression Input Data Acknowledge. Active low decompression
data input. When t his signa l is acti ve, it ind icate s the dat a on D is for the
decompression input port. Data on D is latched on the rising edge of
CLOCK when the strobe condition is met.

Decompression Output Data Request, active low. When this signal is
active, it indicates the ability of the DO port to transmit data.

Decompression Output Data Acknowledge . The definition of DOACKN
varies with the data strobe condition in System Configuratio n 1. See
Table 4.

5.3 VIDEO INTERFACE

VIDEO INTERFACE

SIGNAL TYPE DESCRIPTION

VOREQN O

S

VOACKN I

S

VOD[7:0] O

S

VOEORN O

S

VOEOTN O

S

Video Output Request. Active low output indicating that the byte on
VOD[7:0] is valid.

V ideo Output Acknowledge. Active l ow input indicating that the external
system is ready to read VOD[7:0].

Video Output Data. The value on this output bus is read when both
VOREQN and VOACKN are low.

Video Output End of Record is active low indicating the byte on
VOD[7:0] contains the last byte in a record.

Video Output End of Transfer is active low indicating the byte on
VOD[7:0] contains the last byte in a multi-record transfer.

PS3422-0600 Page 23 of 44

Advanced Hardwar e Architectures, Inc.

5.4 SYSTEM CONTROL

SYSTEM CONTROL

SIGNAL TYPE DESCRIPTION

CLOCK I System Clock. This signal is connected to the clock of the

microprocessor. The Intel i960Cx calls this pin PCLK.

RSTN I

A

TEST0 I

A

TEST1 I

A

Power on Reset. Active low reset signal . The devic e must be rese t before
any DMA or microprocessor activity is attempted. RSTN should be a
minimum of 10 CLOCK periods.

Board Test mode. When TEST is high, all outputs are tristated. When
TEST is low, the chip performs normally.

Used for production tests. This input should always be tied low.

Page 24 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

6.0 PINOUT

PIN SIGNAL PIN SIGNAL PIN SIGNAL

1 VDD or VSS* 44 VSS 87 VOD[7]
2 VDD or VSS* 45 VSS 88 NC
3 VDD or VSS* 46 VDD 89 VDD
4 VDD or VSS* 47 CLOCK 90 VSS
5 VDD or VSS* 48 VSS 91 VOACKN
6 INTRN 49 VDD 92 TEST0
7 VSS 50 VDD 93 PA[0]
8 VDD 51 VSS 94 PA[1]

9 DRIVEN 52 VDD 95 PA[2]
10 SD 53 D[15] 96 PA[3]
11 DOACKN 54 D[16] 97 VDD
12 VDD 55 D[17] 98 PA[5]
13 DIACKN 56 D[18] 99 VSS
14 VDD 57 D[19] 100 PA[4]
15 VSS 58 D[20] 101 NC
16 VDD 59 D[21] 102 VOEOTN
17 DOREQN 60 D[22] 103 PROCMODE[1]
18 NC 61 D[23] 104 PROCMODE[0]
19 DIREQN 62 D[24] 105 CSN
20 NC 63 VSS 106 VDD
21 NC 64 VDD 107 VSS
22 D[0] 65 D[25] 108 DIR
23 VSS 66 D[26] 109 RSTN
24 VSS 67 D[27] 110 PD[7]
25 VDD 68 D[28] 111 PD[6]
26 VDD 69 D[29] 112 PD[5]
27 D[1] 70 D[30] 113 VDD
28 D[2] 71 VDD 114 VSS
29 D[3] 72 VDD 115 PD[4]
30 D[4] 73 VSS 116 PD[3]
31 D[5] 74 VSS 117 PD[2]
32 D[6] 75 D[31] 118 PD[1]
33 D[7] 76 VOREQN 119 PD[0]
34 D[8] 77 VOEORN 120 VDD
35 D[9] 78 VOD[0] 121 VSS
36 D[10] 79 VOD[1] 122 RDYN
37 D[11] 80 VOD[2] 123 VDD
38 VSS 81 VDD 124 VDD or VSS*
39 VDD 82 VSS 125 VDD or VSS*
40 D[12] 83 VOD[3] 126 VDD or VSS*
41 D[13] 84 VOD[4] 127 VDD
42 D[14] 85 VOD[5] 128 VSS
43 TEST1 86 VOD[6]

*Note: the pins marked VDD or VSS can be connected to either VDD or VSS but should not be left unconnected.

PS3422-0600 Page 25 of 44

Figure 15: Pinout

Advanced Hardwar e Architectures, Inc.

TEST0

VOACKN

VSS

VDDNCVOD[7]

VOD[6]

VOD[5]

VOD[4]

VOD[3]

VSS

VDD

VOD[2]

VOD[1]

VOD[0]

VOEORN

VOREQN

D[31]

VSS

VSS

VDD

VDD

D[30]

D[29]

D[28]

D[27]

D[26]

PA[3]

PA[2]

PA[1]

PA[0]

D[25]

VDD

PA[5]

VSS

PA[4]

NC

VOEOTN
PROCMODE[1]
PROCMODE[0]

CSN
VDD

VSS

DIR
RSTN
PD[7]
PD[6]
PD[5]

VDD

VSS
PD[4]
PD[3]
PD[2]
PD[1]
PD[0]

VDD

VSS

RDYN

VDD

VDD

VSS

96959493929190898887868584838281807978777675747372717069686766

97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122

123
*I
*I
*I

124

125

126

127

128

AHA3422A-033 PQC

65

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

VDD
VSS
D[24]
D[23]
D[22]
D[21]
D[20]
D[19]
D[18]
D[17]
D[16]
D[15]
VDD
VSS
VDD
VDD
VSS
CLOCK
VDD
VSS
VSS
TEST1
D[14]
D[13]
D[12]
VDD
VSS
D[11]
D[10]
D[9]
D[8]
D[7]

123456789

*I*I*I*I*I

VSS

VDD

INTRN

*I = Connect to VDD or VSS

1011121314151617181920212223242526272829303132

SD

VDD

VDD

DRIVEN

DOACKN

DIACKN

NC

NC

NC

VSS

VDD

DOREQN

D[0]

VSS

DIREQN

D[1]

D[2]

VSS

VDD

D[3]

VDD

NC = No Connect

D[4]

D[5]

D[6]

Page 26 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

7.0 DC ELECTRICAL SPECIFICATIONS

7.1 OPERATING CONDITIONS

OPERATING CONDITIONS

SYMBOL PARAMETER MIN MAX UNITS NOTES

Vdd Supply voltage 4.75 5.25 V

Idd Supply current (active) 300 mA 4
Idd Supply current (standby) 80 mA 1, 4
Idd Supply current (low power) 1 mA 2, 4

Ta Ambient temperatur e 0 70 °

Input low voltage:

Vil

Vih

Iil Input leakage current -10 10 µA

Vol Output low voltage (Iol=-4mA) 0.4 V

Voh Output high voltage (Ioh=4mA) 2.4 V
Voh Output high voltage (Ioh=100µA) Vdd-0.8 V

Iol Output low current 4 mA

Ioh Output high current -4 mA
Ioz Output leakage current -10 10 µA
Ioz High impedance leakage current -10 10 µA

Cin Input capacitance 5 pF

Cout Output capacitance 7 pF

Cio Input/Output capacitance 7 pF

Comax

PROCMODE[1:0], TEST0, TEST1
Other signals

Input high voltage:

PROCMODE[1:0], TEST0, TEST1
Other signals

Maximum capacitance load for all
signals (including self loading)

Vss-0.5
Vss-0.5

0.7×Vdd

2.0

0.3×Vdd

0.8

Vdd+0.5
Vdd+0.5

50 pF 3

C

V

V

Notes:

1) Dynamic current; no data transfers

2) Static current (clo ck high)

3) Timings referenced to this load

4) ILOAD = 0 mA

7.2 ABSOLUTE MAXIMUM STRESS RATINGS

ABSOLUTE MAXIMUM STRESS RATINGS

SYMBOL PARAMETER MIN MAX UNITS NOTES

Tstg Storage temperature -50 150 °C
Vdd Supply voltage -0.5 7 V

Vin Input voltage Vss-0.5 Vdd+0.5 V

PS3422-0600 Page 27 of 44

Advanced Hardwar e Architectures, Inc.

8.0 AC ELECTRICAL SPECIFICATIONS

Notes:

1) Production test condition is 50 pF. Output delay is decreased 2 ns with 25 pF load guaranteed by design or
characterization.

2) All timings are referenced to 1.4 volts.

Figure 16: Data Interface Timing

CLOCK

1 2

ACKN/

SD

3 4

Valid

6

Valid 1

REQN

COEORN

D

5

7

D/

8

Valid 0

Table 6: Data Port Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 DIACKN, DOACKN and SD setup time 8 ns
2 DIACKN, DOACKN and SD hold time 2 ns
3 D-bus input setup time 8 ns
4 D-bus input hold time 2 ns
5 REQN delay (non-EOR case) 18 ns
6 REQN hold (non-EOR case) 2 ns

Figure 17: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=0

CLOCK

SD

ACKN

1

2

REQN

D

EOR-1 EOR

Page 28 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

Figure 18: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=1

CLOCK

SD

ACKN

3

REQN

D

EOR-1 EOR

Figure 19: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0

CLOCK

SD

ACKN

4

REQN

D

EOR-1 EOR

Figure 20: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1

CLOCK

SD

ACKN

5

REQN

D

EOR-1 EOR

Table 7: Request vs. EOR Timing

NUMBER PARAMETER MIN MAX UNITS

1 ACKN, SD to REQN ERC=0 16 ns
2 CLOCK to REQN ERC=0 16 ns
3 CLOCK to REQN DSC=0-3, 6, 7; ERC=1 16 ns
4 CLOCK to REQN DSC=4, 5; ERC=0 16 ns
5 CLOCK to REQN DSC=4, 5; ERC=1 16 ns

PS3422-0600 Page 29 of 44

Advanced Hardwar e Architectures, Inc.

Figure 21: Output Enable Timing

CLOCK

ACKN

DRIVEN

D

1 3 4 5

2

Table 8: Output Enable Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 DRIVEN to D valid 15 ns
2 DRIVEN to D tristate 10 ns
3 Signal to D valid 15 ns
4 Signal to D trista te 10 ns
5 CLOCK to D tristate (DSC=100, 101) 15 ns

Figure 22: Video Output Port Timing

CLOCK

VOREQN

1 2

VOACKN

43

VOD[7:0]

5

VOEORN

7 8

6

T a ble 9: Video Output Port Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 VOREQN delay 16 ns
2 VOREQN hold 2 ns
3 VOACKN setup 8 ns
4 VOACKN hold 2 ns
5 VOD delay 16 ns
6 VOD hold 2 ns
7 VOEORN hold 2 ns
8 VOEORN delay 16 ns

Page 30 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

Figure 23: Microprocessor Interface Timing (PROCMODE[1]=0)

234512

CLOCK

11212

PA

Valid

3 4

CSN

6

7

8

RDYN

READ

9

10

DIR

12 13

Valid

WRITE

PD

910

DIR

15

PD

14

Valid

Figure 24: Microprocessor Interface Timing (PROCMODE[1]=1)

123 5N4

CLOCK

3

9 10

910

4

tristate

tristate

READ

WRITE

PA

CSN

RDYN

DIR

PD

PD

DIR

1

A0

3

7

12

14

15

Valid

9

Valid

2

4

16

17

13

tristate

10

PS3422-0600 Page 31 of 44

Advanced Hardwar e Architectures, Inc.

Table 10: Microprocessor Interface Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 PA setup time 8 ns
2 PA hold time 2 ns
3 CSN setup time 8 ns
4 CSN hold time 2 ns
6 CSN to valid RDYN 15 ns
7 RDYN valid delay 16 ns
8 RDYN drive disable 10 ns

9 DIR setup time 8 ns
10 DIR hold time 2 ns
12 P D valid delay 16 ns
13 P D drive disable 12 ns
14 PD setup time 8 ns
15 PD hold time 2 ns
16 CSN high to PD tristate 10 ns
17 CSN high to RDYN high 15 ns

Figure 25: Interrupt Timing

CLOCK

INTRN

1 2

Table 11: Interrupt Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 INTRN delay time 15 ns

2 INTRN hold time 2 ns

Figure 26: Clock Timing

1

CLK

34

2

2.0V

1.4V

0.8V

5

Table 12: Clock Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 CLOCK rise time 2 ns

2 CLOCK fall time 2 ns

3 CLOCK high time 12 ns

4 CLOCK low time 12 ns

5 CLOCK period 30 ns

Page 32 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

Figure 27: Power On Reset Timing

CLOCK

2

RSTN

1

3

Table 13: Power On Reset Timing Requirements

NUMBER PARAMETER MIN MAX UNITS

1 RSTN low pulsewidth 10 clocks

2 RSTN setup to CLOCK rise 15 ns

3 RSTN hold time 2 ns

Notes:

1) RSTN signal can be asynchronous to the CLOCK signal. It is internally synchronized to the rising edge of
CLOCK.

PS3422-0600 Page 33 of 44

Advanced Hardwar e Architectures, Inc.

9.0 PACKAGE SPECIFICATIONS

P

B

DETAIL A

D

D1

A

A2

A

L

A1

(LCA)

100

125
126
127
128

97
98
99

AHA3422A-033 PQC

E1

E

P

(LCB)

3231302928

JEDEC outline is MO-108

Page 34 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

PLASTIC QUAD FLAT PACK PACKAGE DIMENSIONS

NUMBER OF PIN AND SPECIFICATION DIMENSION

SYMBOL

MIN NOM MAX

(LCA) 32

(LCB) 32

A 3.7 4.07
A1 0.25 0.33
A2 3.2 3.37 3.6

D 30.95 31.2 31.45
D1 27.99 28 28.12

E 30.95 31.2 31.45

E1 27.99 28 28.12

L 0.73 0.88 1.03
P0.8
B 0.3 0.35 0.4

128

SB

10.0 ORDERING INFORMATION

10.1 AVAILABLE PARTS

PART NUMBER DESCRIPTION

AHA3422A-033 PQC 16 MBytes/sec Lossless Decompressor IC

10.2 PART NUMBERING

AHA 3422 A- 033 P Q C

Manufacturer

Device Number:

3422

Revision Letter:

A

Device

Number

Revision

Level

Speed

Designation

Package
Material

Package

Type

Test

Specification

Package Material Codes:

P Plastic

Package Type Codes:

Q Quad Flat Pack

Test Specifications:

C Commercial 0°C to +70°C

PS3422-0600 Page 35 of 44

Advanced Hardwar e Architectures, Inc.

11.0 RELATED TECHNICAL PUBLICATIONS

DOCUMENT # DESCRIPTION

TM

PS3410C

PS3411

PS3431

PB3410C

PB3411
PB3422 AHA Product Brief – AHA3422 StarLite
PB3431

AHA Product Specification – AHA3410C St a r L i t e
Lossless Data Compression/Decompression Coprocessor IC
AHA Product Specification – AHA341 1 StarLite
Compressor/Decompressor IC
AHA Product Specification – AHA3431 St a r Lit e
Compressor/Decompressor IC, 3.3V
AHA Product Brief – AHA3410C StarLite

TM

25 MBytes/sec Simultaneous Lossless Data
Compression/Decompression Coprocessor IC
AHA Product Brief – AHA3411 StarLite

TM

33 MBytes/sec Simultaneous Compressor/

Decompressor IC

TM

16 MBytes/sec Lossless Decompressor IC

AHA Product Brief – AHA3431 StarLite

TM

40 MBytes/sec Simultaneous Co mpressor/

Decompressor IC, 3.3V

ABDC18 AHA Application Brief – AHA3410C, AHA3411 and AHA3431 Device Differences
ANDC12 AHA Application Note – AHA3410C StarLite
ANDC13 AHA Application Note – Compression Performance on Bitonal Images
ANDC14 AHA Application Note – StarLite

TM

Evaluation Software

ANDC15 AHA Application Note – ENCODEB2 Compression Algorithm Description
ANDC16
ANDC17 AHA Application Note – StarLite

AHA Application Note – Designer’s Guide for StarLite
AHA3422 and AHA3431

TM

Compression on Continuous Tone Images
GLGEN1 General Glossary of Terms
STARSW StarLite

TM

Evaluation Software (WindowsTM)

25 MBytes/sec Simultaneous

TM

33 MBytes/sec Simultaneous

TM

40 MBytes/sec Simultaneous

TM

Designer’s Guide

TM

Family Products: AHA3411,

Page 36 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

APPENDIX A: ADDITIONAL TIMING DIAGRAMS FOR DMA MODE TRANSFERS

Figure A1: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000

CLOCK

ACKN

SD

DRIVEN

D

D0 D1

Figure A2: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000

CLOCK

ACKN

SD

DRIVEN

D

D1D0

Figure A3: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition

of DSC=000

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3

PS3422-0600 Page 37 of 44

Advanced Hardwar e Architectures, Inc.

Figure A4: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition

of DSC=000

CLOCK

ACKN

SD

DRIVEN

D

D1D0 D2 D3

Figure A5: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition

of DSC=000

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

Figure A6: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition

of DSC=000

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

Page 38 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

Figure A7: DMA Mode Timing for Single Word Writes, Strobe Condition ofDSC=010

CLOCK

ACKN

SD

DRIVEN

D

D0 D1

Figure A8: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=010

CLOCK

ACKN

SD

DRIVEN

D

D1D0

Figure A9: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition

of DSC=010

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3

PS3422-0600 Page 39 of 44

Advanced Hardwar e Architectures, Inc.

Figure A10: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition

of DSC=010

CLOCK

ACKN

SD

DRIVEN

D

D1D0 D2 D3

Figure A11: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition

of DSC=010

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

Figure A12: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition

of DSC=010

CLOCK

ACKN

SD

DRIVEN

D

D2D1 D3 D4 D5 D6 D7D0

Page 40 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

Figure A13: DMA Mode Timing for Single Word Writes, Strobe Condition ofDSC=011

CLOCK

ACKN

SD

DRIVEN

D

D0 D1

Figure A14: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011

CLOCK

ACKN

SD

DRIVEN

D

D1D0

Figure A15: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition

of DSC=011

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3

PS3422-0600 Page 41 of 44

Advanced Hardwar e Architectures, Inc.

Figure A16: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition

of DSC=011

CLOCK

ACKN

SD

DRIVEN

D

D1D0 D2 D3

Figure A17: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition

of DSC=011

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

Figure A18: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition

of DSC=011

CLOCK

ACKN

SD

DRIVEN

D

D2D1 D3 D4 D5 D6 D7D0

Page 42 of 44 PS3422-0600

Advanced Hardware Architectures, Inc.

Figure A19: DMA Mode Timing for Single Word Writes, Strobe Condition ofDSC=111

CLOCK

ACKN

SD

DRIVEN

D

D0 D1 D2

Figure A20: DMA Mode Timing for Single Word Reads, Strobe Condition ofDSC=111

CLOCK

ACKN

SD

DRIVEN

D

D1D0 D2

PS3422-0600 Page 43 of 44

Advanced Hardwar e Architectures, Inc.

APPENDIX B: SEQUENTIAL REGISTER TABLE

ADDRESS DESCRIPTION

00 System Configuration 0
01 System Configuration 1
02 Input FIFO Thresholds
03 Output FIFO Thresholds
04 Reserved
05 Decompression Ports Status
06 Port Control
07 Interrupt Status/Control 0

09 Interrupt Mask 0
0A Version
0C Decompression Record Length 0
0D Decompression Record Length 1

0E Decompression Record Length 2

0F Decompression Record Length 3

10 Reserved

11 Reserved
12 Reserved
13 Reserved
14 Reserved
15 Reserved
16 Reserved
17 Reserved
18 Decompression Control

1A Decompression Reserved 1
1C Decompression Line Length 0
1D Decompression Line Leng th 1

20
21 Reserved
27 Interrupt Status/Control 1
29 Interrupt Mask 1

2C Decompression Record Count 0
2D Decompression Record Count 1

30 Reserved
31 Reserved
32 Reserved
33 Reserved
34 Reserved
35 Pattern
38 Decompression Control Prearm
3F Control

Reserved

Page 44 of 44 PS3422-0600