Advanced Hardware Architectures AHA3410C-025PQC Datasheet

PS3410C-0600

2365 NE Hopkins Court

Pullman, WA 99163-5601

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fax: [phone]

e-mail: [e-mail]

www.aha.com

advancedhardwarearchitectures

Product Specification

AHA3410C StarLite

TM

25 MBytes/sec Simultaneous Lossless Data

Compression/Decompression Coprocessor IC

PS3410C-0600

Notes to Customers

Am29K and Fusion29K are Trademarks of Advanced Micro Devices; i960 and
Solutions 960 are T radema rks of Intel Corpo ration; ColdFIRE is a T radema rk of Motorola
Corporation.

Advanced Hardware Architectures, Inc.

PS3410C-0600 i

Table of Contents

1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2.0 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.1 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3.1 Data Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3.2 DMA Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3.3 Pad Word Handling in BurstMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.4 DMA Request Signals andStatus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.4.1 FIFO Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.4.2 Request During an End-of-Record. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.4.3 Request Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.5 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.6 Odd Byte Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.6.1 Compression Input and Pad Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.6.2 Compression Output and PadBytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.6.3 Decompression Input, Pad Bytes and Error Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.6.4 Decompression Output and PadBytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.7 Video Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.7.1 Video Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.7.2 Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.8 Compression Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.9 Decompression Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.11 Low Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.12 Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4.0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.1 System Configuration 0, Address 0x00 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6

4.2 System Configuration 1, Address 0x01 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 7

4.3 Input FIFO Thresholds, Address 0x02 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.4 Output FIFO Thresholds, Address 0x03 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.5 Compression Ports Status, Address 0x04 - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.6 Decompression Ports Status, Address 0x05 - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.7 Port Control, Address 0x06 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.8 Interrupt Status/Control, Address 0x07 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.9 Interrupt Mask, Address 0x09 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.10 Version, Address 0x0A - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.11 Decompression Record Length, Address 0x0C, 0x0D, 0x0E, 0x0F - Read/Write. . . . . . . . . . . . . . . . . . . .21

4.12 Record Length, Address 0x10, 0x11, 0x12, 0x13 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.13 Compression Control, Address 0x14 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.14 Compression Reserved, Address 0x15 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.15 Compression Configuration, Address 0x16, 0x17 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.16 Decompression Control, Address 0x18 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.17 Decompression Reserved, Address 0x1A - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.18 Decompression Configuration, Address 0x1C, 0x1D - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

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ii PS3410C-0600

5.0 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

5.1 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

5.2 Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

5.3 Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

5.4 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

6.0 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 7

7.0 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

7.1 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

7.2 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

8.0 AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

9.0 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

10.0 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

10.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 9

10.2 Part Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

11.0 Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

11.1 AHA Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

11.2 Other Technical Publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Appendix A:Additional Timing Diagrams for DMA Mode Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Advanced Hardware Architectures, Inc.

PS3410C-0600 iii

Figures

Figure 1: Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 3: Microprocessor Port Read (PROCMODE[1:0]=“01”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 4: Microprocessor Port Write (PROCMODE[1:0]=“11”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 5: Microprocessor Port Read (PROCMODE[1:0]=“11”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100 . . . . . . . . . . . . . . . . . . . . . . .7

Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100 . . . . . . . . . . . . . . . . . . . . . . .7

Figure 8: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=100. . . . . . . .7

Figure 9: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=100 . . . . . . .8

Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=100. . . . . . .8

Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition ofDSC=100. . . . . . .8

Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 14: Timing Diagram, Video Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 15: Timing Diagram, Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 16: Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 17: Power vs. Data Rate at 25 MHz Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 18: Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 19: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=0. . . . . . . . . . . . . . . . . . . . . . .31

Figure 20: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=1. . . . . . . . . . . . . . . . . . . . . . .32

Figure 21: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0 . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 22: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1 . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 23: Output Enable Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 24: Video Input Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 25: Video Output Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 26: Microprocessor Interface Timing (PROCMODE[1]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 27: Microprocessor Interface Timing (PROCMODE[1]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 28: Interrupt Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 29: Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 30: Power On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure A1: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000 . . . . . . . . . . . . . . . . . . . . . .41

Figure A2: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000 . . . . . . . . . . . . . . . . . . . . . .41

Figure A3: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=000. . . . . . .41

Figure A4: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=000 . . . . . .42

Figure A5: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=000. . . . . .42

Figure A6: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=000. . . . . .42

Figure A7: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=010 . . . . . . . . . . . . . . . . . . . . . .43

Figure A8: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=010 . . . . . . . . . . . . . . . . . . . . . .43

Figure A9: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=010. . . . . . .43

Figure A10: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=010 . . . . . .44

Figure A11: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=010. . . . . .44

Figure A12: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition ofDSC=010. . . . . .44

Figure A13: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=011 . . . . . . . . . . . . . . . . . . . . . .45

Figure A14: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011 . . . . . . . . . . . . . . . . . . . . . .45

Figure A15: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=011. . . . . . .45

Figure A16: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=011 . . . . . .46

Figure A17: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=011. . . . . .46

Figure A18: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition ofDSC=011. . . . . .46

Figure A19: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=111 . . . . . . . . . . . . . . . . . . . . . .47

Figure A20: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=111 . . . . . . . . . . . . . . . . . . . . . .47

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iv PS3410C-0600

Tables

Table 1: Data Bus and FIFO Sizes Supported by StarLiteTM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 2: StarLite

TM

Connection to Host Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Table 3: Microprocessor Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Table 4: Internal Strobe Conditions for DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 5: Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 6: Data Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 7: Request vs. EOR Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 8: Output Enable Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 9: Video Input Port Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 10: Video Output Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 11: Microprocessor Interface Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 12: Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 13: Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 14: Power On Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

PS3410C-0600 Page 1 of 47

Advanced Hardware Architectures, Inc.

1.0 INTRODUCTION

StarLite™ is a s ingle chip CMOS VLSI
coprocessor device that implements a lossless
compression and decompression algorithm. The
algorithm exhibits an average compression ratio
over 13 to 1 for bitmap image data. The device
supports simultaneous compression and decom­pression operations at 25 MBytes/sec each.

The device interfaces directly to various RISC
and CISC processors from AMD, Intel and
Motorola. Compression and decompression data
transfers normally occur over a high speed
bidirectional 32-bit data bus capable of up to 100
MBytes/sec synchronous data rates. Two 8-bit
synchronous video data ports provide ability to
optionally interface to scanner and print engine
respectively for applications such as multifunction
laser printers and copiers.

A low power mode is achieved by stopping all
data transfers and the clock signal. All outpu ts may
be tristated to facilitate board level testing.

This document contains functional description,
system configurations, register descriptions and
timing diagrams. It is intended for system designers
considering a compression coprocessor in their
embedded applications. Software simulation and an
analysis of the algorithm for printer and copier
images of various complexity are also available for
evaluation. A comprehensive Designer’s Guide
complementing this document is also available from
AHA to assist with the system design. Section 11.0
contains a list of related technical publications.

1.1 CONVENTIONS, NOTATIONS AND

DEFINITIONS

– Active low signals have an “N” appended to the

end of the signal name. For example, CSN and
RDYN.

– A “bar” over a signal name indicates an inverse of

the signal. For example, SD

indicates an inverse
of SD. This terminology is used only in logic
equations.

– “Signal assertion” means the output signal is

logically true.

– Hex va lues a re r eprese nted wi th a prefi x of “0x”,

such as Register “0x00”. Binary values do not
contain a prefix, for example, DSC=000.

– A rang e of signal names or register bits is denoted

by a set of colons between the numbers. Most
significant bit i s a lways shown first, foll owed by
least significant bit. For exampl e, VOD[7: 0]
indicates signal names VOD7 through VOD0.

– A logical “AND” function of two signals is

expressed with an “&” between variables.

– Mega Bytes per second is referred to as MBytes/

sec or MB/sec.

– In re ferencing microproce ssors, an x or xx is used

as suffix to indic ate more tha n one proc essor. For
example, Am290xx proces sor family includes the

Am29000, 29005, 29030 and 29035.
– Reserved bits in registers are referred as “res”.
– REQN or ACKN refer to either CI, DI, CO or DO

Request or Acknowledge signals, as applicable.

1.2 FEATURES

PERFORMANCE:

• 25 MB/sec compression and decompression rates

• 100 MB/sec burst data rate over a 32-bit data bus

• 25 MB/sec synchronous 8-bit video in and video

out ports

• Simultaneous compression and decompression

operation at full bandwidth

• Average 13 to 1 compression performance for

bitmap image data

FLEXIBILITY:

• Configura ble I/O interface for DMA mod e; Big

Endian or Little Endian; and 32-bit or 16-bit bus
widths

• Interfaces directly with Am29K or i960 family of

RISC processors and Motorola 68xxx CISC
processors

• Optional 8-bit video input and output ports

• Pass-through mode passes raw data through

compression and decompression engines

• Optional counter enables error checking in

decompression operation

SYSTEM INTERFACE:

• Single chip compression and decompression

solution

• No external SRAM required

• Four 16 × 32-bit FIFOs

• Programmable interrupts

• 25 MHz maximum clock frequency

• Output signals may be tris tated to f acilit ate board

level testing

OTHERS:

• Low power modes

• Software emulation program available

• 120 pin quad flat package

Page 2 of 47 PS3410C-0600

Advanced Hardware Architectures, Inc.

Figure 1: Functional Block Diagram

1.3 FUNCTIONAL OVERVIEW

The coprocessor device has t hree exter nal h igh
speed synchronous data ports capable of
transferring once eve ry 25 MHz clock. These are a
32-bit bidirectional data port, an 8-bit Video Input
Data (VID) port and a Video Output Data (VOD)
port. The 32-bit port is capable of transferring up to
100 MBytes/sec. The VID and VOD are capable o f
up to 25 MBytes/sec each.

The device accepts uncompressed data through
the 8-bit VID port or the 32-bit data port in to its
Compression In FIFO (CI FIFO). The 32-bit data
port may be configured for 16-bit transfers.
Compressed data is available through the 32-bit
data port via the Compressed Output FIFO (CO

FIFO). The sustained data rate through the
compression engine is 25 MBytes/sec.

Decompression data may be simultaneously
processed by the device. Decompression data is
accepted through the 32-bit data port, buffered in
the Decompression Input FIFO (DI FIFO) and
decompressed. The output da ta is made available on
the 32-bit data port via th e Decompression Output
FIFO (DO FIFO) or the 8-bit Video Output port.
The decompression engine runs on the 25 MHz
clock and is capable of processing an unco mpressed
byte every clock, i.e., 25 MB/sec.

The four FIFOs are organized as 16 × 32 each.
For data transfers through the three ports, the
“effective” FI FO sizes differ according to the ir data
bus widths. The table below shows the size of the
data port and the “effective” FIFO size for the
various configurations supported by the device.

Table 1: Data Bus and FIFO Sizes Supported by StarLite

TM

(From Scanner)

VIREQN
VID[7:0]
VIACKN

D[31:0]

DRIVEN

TEST

CLK

RSTN

PROCMODE[1:0]

PD[7:0]

PA[4:0]

CSN

DIR

RDYN

INTRN

VOACKN

VOD[7:0]

VOREQN

VOEORN

(To Printe r )

COEORN

DOREQN

COREQN

DIREQN

CIREQN

SD

DOACKN

COACKN

DIACKN

CIACKN

VID

PORT

DATA
PORT

CI

FIFO

16x32

DI

FIFO

16x32

CLOCK

DATA PORT CONTROL

COMPRESSOR

DECOMPRESSOR

MICROPROCESSOR INTERFACE

CO

FIFO

16x32

DO

FIFO

16x32

VOD

PORT

AHA3410C

StarLiteTM

8

8 8

888

32

32 32

5

8

OPERATION DATA BUS WIDTH PORT EFFECTIVE FIFO SIZE

Compression Data In 8 Video In 16 × 8
Compressi on Data In/Out 32 Data Port 16 × 32
Compressi on Data In/Out 16 Data Port 16 × 16
Decompression Data In/Out 32 Data Port 16 × 32
Decompression Data In/Out 16 Data Port 16 × 16
Decompressed Data Out 8 Video Out 16 × 8

PS3410C-0600 Page 3 of 47

Advanced Hardware Architectures, Inc.

Table 2: StarLiteTM Connection to Host Microprocessors

Movement of data for compression or
decompression is performed using synchronous
DMA over the 32-bit data port. The Video ports
support synchronous DMA mode transfers. The
DMA strobe conditions are co nfigurabl e for the 32 ­bit data port dependi ng upon the RISC proc essor of
the system and the DMA controller available.

Data transfer for compression or decompression
is synchronous over the three data ports functioning
as DMA masters. To initiate a transfer into or out of
the Video ports, the device asserts VxREQN, the
external device responds with VxACKN and begins
to transfer data over the VID or VOD busses on each
succeeding rising edge of the clock until VxREQN
is deasserted. The 32-bit port relies on the FIFO
Threshold settings to determine the transfer.

The sections below describe the various
configurations, programming and other special
considerations in developing a compressi on system
using StarLite

TM

.

2.0 SYSTEM CONFIGURATION

This section provides information on
connecting StarLi te

TM

to various microproce ssors in

DMA mode.

2.1 MICROPROCESSOR INTERFACE

The device is capable of in te rf acing directly to
various processors for embedded application. The
table below shows how StarLite

TM

should be

connected to various host microprocessors.

All register accesses to StarLite

TM

are
performed on the 8-bit PD bus. The PD bus is the
lowest byte of the 32-bit microprocessor bus.
During reads of the internal registers, the upper 24
bits are not driven. System designers should
terminate these lines with Pullup resistors.

StarLite

TM

provides four modes of ope rat ion for
the microprocessor port. Both active high and acti ve
low write enable signals are all owed a s well as two
modes for chip select . The mode of operation is set by

the PROCMODE[1:0] pins. The PROCMODE[1]
signal selects when CSN must be active and also how
long an access lasts.

When PROCMODE[1] is high, CSN determines
the length of the access. CSN must be at least 5
clocks in length. On a read, valid data is driven onto
PD[7:0] during the 5th clock. If CSN is longer than 5
clocks, then valid data continues to be driven out
onto PD[7:0]. When CSN goes inactive (high),
PD[7:0] goes tristate (asynchronously) and RDYN is
driven high asynchronously. CSN must be high for at
least two clocks. RDYN is always driven (it is not
tristated when P R OCMO D E [1] is high). The mode is
typical of processors such as the Motorola 68xxx.

When PROCMODE[1] is low, accesses are
fixed at 5 clocks, PD[7:0] is onl y driven dur ing the
fifth clock, and RDYN is driven high for the f irst 4
clocks and low during the fifth clock. RDYN is
tristated at all other times. Write data must be driven
the clock af ter CSN is sam pled low. Accesses may
be back to back with no delays in between. This
mode is typical of RISC processors s uch as the i960
and Am29K.

PROCMODE[0] determines the polarity of the
DIR pin. If PROCMODE[0] is high, then the DIR
pin is an active low write enable. If PROCMODE[0]
is low, then the DIR pin is an active high write
enable. Figure 2 through Figure 5 illustrate the
detailed timing diagrams for the microprocessor
interface.

For additional notes on interfacing to various
microprocessors, refer to AHA Application Note
(ANDC12), StarLite

TM

Designer’s Guide.

PIN NAME Am290xx Am292xx i960Cx i960Kx

PA A A A LAD

CSN

CS

PIACS CS CS

DIR

R/W

R/W W/R W/R
PD D ID D LAD
SD VDD VDD

WAIT

READY

RDYN

DRDY

No Connect No Connect

READY

DRIVEN System Dependent

PIAOE

DEN

System Dependent

CLOCK SYSCLK MEMCLK PCLK No Connect

Page 4 of 47 PS3410C-0600

Advanced Hardware Architectures, Inc.

Table 3: Microprocessor Port Configuration

Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”)

Figure 3: Microprocessor Port Read (PROCMODE[1:0]=“01”)

PROCMODE[1:0] DIR CYCLE LENGTH EXAMPLE PROCESSOR

00 Active high write fixed i960
01 Active low write fixed Am29K
10 Active high write variable
11 Active low write variable 68xxx

CLOCK

PA[4:0]

CSN

DIR

PD[7:0]

A0

RDYN

A1

D0 D1

CLOCK

PA[4:0]

CSN

DIR

PD[7:0]

A0

RDYN

A1

D0

A2

D1

PS3410C-0600 Page 5 of 47

Advanced Hardware Architectures, Inc.

Figure 4: Microprocessor Port Write (PROCM ODE[1:0]=“11”)

Figure 5: Microprocessor Port Read (PROCMODE[1:0]=“11”)

CLOCK

PA[4:0]

CSN

DIR

PD[7:0]

A0

RDYN

A1

D0

CLOCK

PA[4:0]

CSN

DIR

PD[7:0]

A0

RDYN

A1

D0

Page 6 of 47 PS3410C-0600

Advanced Hardware Architectures, Inc.

3.0 FUNCTIONAL DESCRIPTION

This section describes the various data ports,
special handling, data formats and clocking
structure.

3.1 DATA PORTS

StarLiteTM contains two data input ports , CI and
DI, and two data output ports, CO and DO on the
same 32-bit data bus, D[31:0]. Data transfer s can be
controlled by an exte rnal DMA control. The logical
conditions under which data is written to the input
FIFOs or read from the output FIFOs are set by t he
DSC (Data Strobe Condition) field of the System
Configuration 1 register.

A strobe condition defines under what logical
conditions the input FIFOs ar e written or the output
FIFOs read. CIACKN, COACKN, DIACKN,
DOACKN, and SD pins combine to strobe data in a
manner similar to DMA controllers. The DMA
Mode sub-section descr ibes t he variou s data strob e
options.

3.2 DMA MODE

DMA data strobes are indicated by setting the
most significant bit of the data strobe condition to
zero (DSC[3]=0).

On the rising edge of CLOCK when the strobe
condition is met, the port with the active
acknowledge either strobes data into or out of the
chip. No more than one port may assert acknowledge
at any one time. Table 4 shows the various
conditions that may be programmed into register
DSC.

Figure 6 through Figure 11 illustrate the DMA
mode timings for single, four word and eight word
burst transfers for DSC=100 selection. For other
DSC settings, please refer to Appe ndix A. Note that
the only differe nce between odd and eve n values of
DSC is the polarity of SD. Waveforms are only
shown for polari ties of SD correspondi ng to specific
systems.

Table 4: Internal Strobe Conditions for DMA Mode

DSC[3:0] LOGIC EQUATION SYSTEM CONFIGURATION

0000

i960Cx with internal DMA contro ller. SD is connected to

WAITN.
0001 No specifi c system
0010 General purpose DMA controller

0011

i960Kx or Am290xx with extern al, bus master t ype DMA

controller. SD is connected to RDYN.
0100 Am2924x with internal DMA controller
0101 No specifi c system
0110 Am2920x with internal DMA controller
0111 Am2920x with internal DMA controller

ACKN()& ACKN

delayed

()& SD()

ACKN()& ACKN

delayed

()& SD()

ACKN()& SD()

ACKN()& SD()

ACKN

delayed

()& SD

delayed

()

ACKN

delayed

()& SD

delayed

()

ACKN()& ACKN

delayed

()

ACKN()& ACKN

delayed

()

ACKN

delayed

ACKN delayed 1 clock=

SD

delayed

SD delayed 1 clock=

PS3410C-0600 Page 7 of 47

Advanced Hardware Architectures, Inc.

Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100

Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100

Figure 8: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition

of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D0 D1

CLOCK

ACKN

SD

DRIVEN

D

D1D0

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3

Page 8 of 47 PS3410C-0600

Advanced Hardware Architectures, Inc.

Figure 9: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition

of DSC=100

Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition

of DSC=100

Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition

of DSC=100

CLOCK

ACKN

SD

DRIVEN

D

D1D0 D2 D3

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

CLOCK

ACKN

SD

DRIVEN

D

D0 D2D1 D3 D4 D5 D6 D7

PS3410C-0600 Page 9 of 47

Advanced Hardware Architectures, Inc.

3.3 PAD WORD HANDLING IN
BURST MODE

If a word containing an End-of-Record comes
out during a burst read, the words after the End-of­Record are invalid (pad) words. This prevents a
burst read from crossing record boundaries. The
first word of the next burst read is the first word of
the next record. The pad words must be deleted
during decompression by usi ng the Decompressi on
Pause on Record Boundaries bit (DPOR), in the
Decompression Control register. After the part is
paused, the DI FIFO must be reset by asserting the
DIRST bit in the Port Control register.
Decompressor must als o be reset by asserting DDR
bit in Decompression Control register.

The COEORN signal is asserted when an End­of-Record is present on the output of the CO FIFO.
COEORN is active while the EOR is strobed out. In
some systems COEORN can be used to generate a
DMA-done condition.

3.4 DMA REQUEST SIGNALS

AND STATUS

StarLiteTM requests data using request pins
(CIREQN, DIREQN, COREQN, DOREQN). The
requests are controlled by programmable FIFO
thresholds. Both input and output FIFOs have
programmable empty and full thresholds set in the
Input FIFO Thres hold and Output FIFO T hreshold
registers. By requesting only when a FIFO can
sustain a ce rtain burst size, the bus is used more
efficiently.

The input requests, CIREQN and DIREQN,
operate under the following prioritized rules:

1) If the FIFO rese t in the Port Control register
is active, the request is inactive.

2) If a FIFO overflow interrupt is active, the
request is ina ctive.

3) If the FIFO is at or below the empty
threshold , the request will go active.

4) If the FIFO is a t or above the fu ll threshold,
the request will go inactiv e.

The output requests, COREQN and DOREQN,

operate under the following prioritized rules:

1) If the FIFO rese t in the Port Control register
is active, the request is inactive.

2) If the output FIFO underflow interrupt is
active, the request is inactive.

3) If an EOR is present in the output FIFO, th e
request will go active.

4) If the output FIFO is at or above the full
threshold , the request will go active.

5) If an EOR is read (strobed) out of the FI FO,
the request will go inactive during the same
clock as the strobe (if ERC=0), otherwi se it
will go inactive on the next clock.

6) If the output FIFO is at or below the empt y
threshold, the request will go inactive.

3.4.1 FIFO THRESHOLDS

For maximum efficiency, the FIFO thresholds
should be set in such a way that the compressor
seldom runs out of data from the CI FIFO or
completely fills the output FIFO. The FIFOs are 16
words deep.

For example, in a system with fixed 8-word
bursts, good values for the thresholds are:

IET=3, IFT=4, OFT=D, OET=C

Setting the input full threshold to one higher
than the input empty threshold simply guarantees
that the request will deassert as soon as possible. The
latency between a word being strobed in and the
request changing due to a FIFO threshold condition
is 3 clocks. Th i s sh o ul d be kept in mind when
programming threshold values. Refer to AHA
Application Note (ANDC12), StarLite

TM

Designer’s

Guide for a more thorough discussion of FIFO

thresholds. The following figure shows an example
of an input FIFO crossing its full threshold.

Page 10 of 47 PS3410C-0600

Advanced Hardware Architectures, Inc.

Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO)

Note: CIREQN deasserted when threshold counter exceeded IFT=4.

Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010

3.4.2 REQUEST DURING AN END-OF-RECORD

The request deasserts at an EOR in one of two
ways. If ERC bit in System Configuration 1 is ‘0’,
the request will deasser t asynchronous ly during the
clock where the EOR is strobed out of the FIFO.
This leads to a lo ng output delay for REQN, but may
be necessary in some systems. For DSC values of 4
or 5, the request deasserts the first clock after the
acknowledge pulse for the EOR. If ERC is set to ‘1’,
then the request deasserts synchronously the clock
after the EOR is strobed out. The minimum low
time on the request in this case is one clock.

The request delay varies between the different
strobe conditi ons. See the timing se ction for further
details.

3.4.3 REQUEST STATUS BITS

An external microproc essor can also read the
value of each reque st using the CIREQ and COREQ
bits in the Compression Port Status register and the
DIREQ and DOREQ bits in the Decompression
Port Status register. Please note that the request
status bits are active high while the pins are active
low.

CLOCK

D

CIACKN

CIREQN

Threshold

1

2

3

45

6

7

8

1

234

5

6

78

9

Counter

EOR-2

CLOCK

D

ACKN

REQN

EOR-1

EOR

(ERC=0)

REQN

(ERC=1)