ADMTK ADM6996L Datasheet
ADM6996L
6 port 10/100 Mb/s
Single Chip Ethernet Switch Controller
Data Sheet
ADMtek.com.tw
Information in this document is provided in connection with ADMtek products. ADMtek may make
changes to specifications and product descriptions at an y time, without notice. Designers must not rely on
the absence or characteristics of any features or instructions marked “reserved” or “undefined”. ADMtek
reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them
The products may contain design defects or errors know as errata, which may cause the product to deviate
from published specifications. Current characterized errata are available on request. To obtain latest
documentation please contact you local ADMtek sales office or visit ADMtek’s website at
http://www.ADMtek.com.tw
*Third-party brands and names are the property of their respective owners.
Copyright 2003 by ADMtek Incorporated All Rights Reserved.
ADMtek Inc. V1.0
About this Manual
General Release
Intended Audience
ADMtek’s Customers
Structure
This Data sheet contains 6 chapters
Chapter 1 Product Overview
Chapter 2 Interface Description
Chapter 3 Function Description
Chapter 4. Register Description
Chapter 5. Electrical Specification
Chapter 6. Packaging
Revision History
Date Version Change
02 Sep 2003
1.0 1. First release of ADM6996L
Customer Support
ADMtek Incorporated,
2F, No.2, Li-Hsin Rd.,
Science-based Industrial Park,
Hsinchu, 300, Taiwan, R.O.C.
Sales Information
Tel + 886-3-5788879
Fax + 886-3-5788871
ADMtek Inc. V1.0
Table of Contents
Chapter 1 Product Overview........................................................................................1-1
1.1 Overview..........................................................................................................1-1
1.2 Features............................................................................................................1-2
1.3 Applications.....................................................................................................1-2
1.4 Block Diagram.................................................................................................1-3
1.5 Abbreviations...................................................................................................1-3
1.6 Conventions .....................................................................................................1-5
1.6.1 Data Lengths............................................................................................1-5
1.6.2 Pin Types..................................................................................................1-5
1.6.2 Register Types..........................................................................................1-5
Chapter 2 Interface Description...................................................................................2-1
2.1 Pin Diagram.....................................................................................................2-1
2.2 Pin Description by Function ............................................................................2-2
2.2.1 Twisted Pair Interface..............................................................................2-2
2.2.2 6th Port (MII) Interfaces..........................................................................2-2
2.2.3 LED Interface...........................................................................................2-4
2.2.4 EEPROM/Management Interface............................................................2-5
2.2.5 Power/Ground, 48 pins............................................................................2-5
2.2.6 MISC ........................................................................................................2-6
Chapter 3 Function Description...................................................................................3-1
3.1 Functional Descriptions...................................................................................3-1
3.2 10/100M PHY Block .......................................................................................3-1
3.3 100Base-X Module..........................................................................................3-1
3.4 100Base-X Receiver ........................................................................................3-2
3.4.1 A/D Converter..........................................................................................3-3
3.4.2 Adaptive Equalizer and timing Recovery Module ...................................3-3
3.4.3 NRZI/NRZ and Serial/Parallel Decoder..................................................3-3
3.4.4 Data De-scrambling.................................................................................3-3
3.4.5 Symbol Alignment....................................................................................3-3
3.4.6 Symbol Decoding.....................................................................................3-4
3.4.7 Valid Data Signal.....................................................................................3-4
3.4.8 Receive Errors .........................................................................................3-4
3.4.9 100Base-X Link Monitor..........................................................................3-4
3.4.10 Carrier Sense...........................................................................................3-5
3.4.11 Bad SSD Detection...................................................................................3-5
3.4.12 Far-End Fault..........................................................................................3-5
3.5 100Base-TX Transceiver.................................................................................3-5
3.5.1 Transmit Drivers......................................................................................3-6
3.5.2 Twisted-Pair Receiver..............................................................................3-6
3.6 10Base-T Module.............................................................................................3-6
3.6.1 Operation Modes .....................................................................................3-6
3.6.2 Manchester Encoder/Decoder.................................................................3-7
3.6.3 Transmit Driver and Receiver .................................................................3-7
3.6.4 Smart Squelch..........................................................................................3-7
3.7 Carrier Sense....................................................................................................3-8
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ADMtek Inc. V1.0
3.8 Jabber Function................................................................................................3-8
3.9 Link Test Function...........................................................................................3-8
3.10 Automatic Link Polarity Detection..............................................................3-8
3.11 Clock Synthesizer ........................................................................................3-8
3.12 Auto Negotiation..........................................................................................3-8
3.13 Memory Block .............................................................................................3-9
3.14 Switch Functional Description.....................................................................3-9
3.15 Basic Operation............................................................................................3-9
3.15.1 Address Learning...................................................................................3-10
3.15.2 Address Recognition and Packet Forwarding.......................................3-10
3.15.3 Address Aging........................................................................................3-11
3.15.4 Back off Algorithm.................................................................................3-11
3.15.5 Inter-Packet Gap (IPG) .........................................................................3-11
3.15.6 Illegal Frames........................................................................................3-11
3.15.7 Half Duplex Flow Control.....................................................................3-11
3.15.8 Full Duplex Flow Control......................................................................3-12
3.15.9 Broadcast Storm filter............................................................................3-12
3.16 Auto TP MDIX function................................................................................3-12
3.17 Port Locking...............................................................................................3-12
3.18 VLAN setting & Tag/Untag & port-base VLAN ......................................3-13
3.19 Priority Setting...........................................................................................3-14
3.20 LED Display ..............................................................................................3-14
Chapter 4 Register Description ....................................................................................4-1
4.1 EEPROM Content............................................................................................4-1
4.2 EEPROM Register Map...................................................................................4-1
4.3 EEPROM Register...........................................................................................4-2
4.3.1 Signature Register, offset: 0x00h..............................................................4-2
4.3.2 Configuration Registers, offset: 0x01h ~ 0x09h......................................4-3
4.3.3 Reserved Register, offset: 0x0ah..............................................................4-3
2.3.4 Configuration Register, offset: 0x0bh......................................................4-4
4.3.5 Reserved Register, offset: 0x0ch~0x0dh..................................................4-4
4.3.6 VLAN priority Map Register, offset: 0x0eh.............................................4-4
4.3.7 TOS priority Map Register, offset: 0x0fh.................................................4-4
4.3.8 Packet with Priority: Normal packet content ..........................................4-5
4.3.9 VLAN Packet............................................................................................4-5
4.3.10 TOS IP Packet..........................................................................................4-1
4.3.11 Miscellaneous Configuration Register, offset: 0x10h..............................4-1
4.3.12 VLAN mode select Register, offset: 0x11h...............................................4-2
4.3.13 Miscellaneous Configuration register, offset: 0x12h ..............................4-5
4.3.14 VLAN mapping table registers, offset: 0x22h ~ 0x13h............................4-5
4.3.15 Reserved Register, offset: 0x27h ~ 0x23h................................................4-5
4.3.16 Port0, 1 PVID bit 11 ~ 4 Configuration Register, offset: 0x28h.............4-1
4.3.17 Port2, 3 PVID bit 11 ~ 4 Configuration Register, offset: 0x29h.............4-1
4.3.18 Port4, 5 PVID bit 11~4 Configuration Register, offset: 0x2ah...............4-1
4.3.19 Port6, 7 PVID bit 11~4 Configuration Register, offset: 0x2bh...............4-1
4.3.20 Port8 PVID bit 11~4 & VLAN group shift bits Configuration Register..4-1
ADM6996L ii
ADMtek Inc. V1.0
4.3.21 Reserved Register, offset: 0x2dh..............................................................4-2
4.3.22 Reserved Register, offset: 0x2eh..............................................................4-2
4.3.23 PHY Restart, offset: 0x2fh........................................................................4-2
4.3.24 Miscellaneous Configuration Register, offset: 0x30h..............................4-2
4.3.25 Bandwidth Control Register0~3, offset: 0x31h........................................4-3
4.3.26 Bandwidth Control Register 4~5, offset: 0x32h.......................................4-3
4.3.27 Bandwidth Control Enable Register, offset: 0x33h..................................4-4
4.4 EEPROM Access.............................................................................................4-4
4.5 Serial Register Map..........................................................................................4-6
4.6 Serial Register Description..............................................................................4-7
4.6.1 Chip Identifier Register, offset: 0x00h.....................................................4-7
4.6.2 Port Status 0 Register, offset: 0x01h .......................................................4-7
4.6.3 Port Status 1 Register, offset: 0x02h .......................................................4-9
4.6.4 Cable Broken Status Register, offset: 0x03h............................................4-9
4.6.5 Over Flow Flag 0 Register, offset: 0x3ah..............................................4-10
4.6.6 Over Flow Flag 0: Register 0x3bh ........................................................4-10
4.6.7 Over Flow Flag 2 Register, offset: 0x3ch..............................................4-11
4.7 Serial Interface Timing....................................................................................4-1
Chapter 5 Electrical Specification................................................................................5-1
5.1 TX/FX Interface...............................................................................................5-1
5.1.1 TP Interface .............................................................................................5-1
5.1.2 FX Interface.............................................................................................5-1
5.2 DC Characteristics...........................................................................................5-2
5.2.1 Absolute Maximum Rating.......................................................................5-2
5.2.2 Recommended Operating Conditions......................................................5-2
5.2.3 DC Electrical Characteristics for 3.3V Operation..................................5-2
5.3 AC Characteristics...........................................................................................5-3
5.3.1 Power On Reset........................................................................................5-3
5.3.2 EEPROM Interface Timing......................................................................5-3
5.3.3 10Base-TX MII Input Timing...................................................................5-4
5.3.4 10Base-TX MII Output Timing................................................................5-4
5.3.5 100Base-TX MII Input Timing.................................................................5-5
5.3.6 100Base-TX MII Output Timing..............................................................5-5
5.3.7 GPSI(7-wire) Input Timing......................................................................5-6
5.3.8 GPSI(7-wire) Output Timing ...................................................................5-7
Chapter 6 Packaging......................................................................................................6-1
6.1 128 Pin PQFP Outside Dimension...................................................................6-1
ADM6996L iii
ADMtek Inc. V1.0
List of Figures
Figure 1-1 ADM6996L Block Diagram ..........................................................................1-3
Figure 2-1 5 TP/FX PORT + 1 MII PORT 128 Pin Diagram..........................................2-1
ADM6996L iv
ADM6996L Product Review
Chapter 1 Product Overview
1.1 Overview
The ADM6996L is a high performance, low cost, highly integration (Controller, PHY
and Memory) five-port 10/100 Mbps TX/FX plus one 10/100 MAC port Ethernet switch
controller with all ports supporting 10/100 Mbps Full/Half duplex. The ADM6996L is
intended for applications to stand alone bridge for low cost SOHO market such as 5Port,
Router application.
ADM6996L provides most advance function such as: 802.1p(Q.O.S.), 802.1q(VLAN),
Port MAC address Locking, Management, Port Status, TP Auto-MDIX, 25M
Crystal & Extra MII port function to meet customer request on Switch demand.
The ADM6996L also supports Back Pressure in Half-Duplex mode and 802.3x Flow
Control Pause packet in Full-Duplex mode to prevent packet lost when buffer full. When
Back Pressure is enabled, and there is no receive buffer available for the incoming
packet, the ADM6996L will issue a JAM pattern on the receiving port in Half Duplex
mode and transmit the 802.3x Pause packet back to receiving end in Full Duplex mode.
The built-in SRAM used for packet buffer and address learning table is divided into 256
bytes/block to achieve the optimized memory utilization through complicated link list on
packets with various lengths.
ADM6996L also supports priority features by Port-Base, VLAN and IP TOS field
checking. User can be easy to set as different priority mode in individual port, through a
small low-cost micro controller to initialize or on-the-fly to configure. Each output port
supports two queues in the way of fixed N: 1 fairness queuing to fit the bandwidth
demand on various types of packet such as Voice, Video and data. 802.1Q, Tag/Untag,
and up to 32 groups of VLAN also is supported. ADM6996L learns user define 4 or 5
bits of VLAN ID.
An intelligent address recognition algorithm makes ADM6996L to recognize up to 2048
different MAC addresses and enables filtering and forwarding at full wire speed.
Port MAC address Locking function is also supported by ADM6996L to use on Building
Internet access to prevent multiple users sharing one port traffic.
ADMtek Inc. 1-1
ADM6996L Product Review
1.2 Features
• Supports five 10M/100M auto-detect Half/Full duplex switch ports with TX/FX
interfaces and one MII/GPSI port.
• Supports 2048 MAC addresses table.
• Supports four queue for QoS
• Supports priority features by Port-Based, 802.1p VLAN & IP TOS of packets.
• Supports Store & Forward architecture and performs forwarding and filtering at non-
blocking full wire speed.
• Supports buffer allocation with 256 bytes per block
• Supports Aging function Enable/Disable.
• Supports per port Single/Dual color mode with Power On auto diagnostic.
• Supports 802.3x Flow Control pause packet for Full Duplex in case buffer is full.
• Supports Back Pressure function for Half Duplex operation in case buffer is full.
• Supports packet length up to 1522 bytes.
• Broadcast Storming Filter function.
• Supports 802.1Q VLAN. Up to 16 VLAN groups is implemented by the last four bits
of VLAN ID.
• 2bit MAC clone to support multiple WAN application
• Supports TP interface Auto MDIX function for auto TX/RX swap by strapping-pin.
• Easy Management 32bits smart counter for per port RX/TX byte/packet count, error
count and collision count.
• Support PHY status output for management system.
• 25M Crystal only for the whole system.
• 128 QFP package with 0.18um technology. 1.8V/3.3V power supply.
1.3 Applications
ADM6996L in 128-pin PQFP: SOHO 5-port switch
5-port switch + Router with MII CPU interface.
ADMtek Inc. 1-2
ADM6996L Product Review
1.4 Block Diagram
Twisted
Pai r
Interface
10/100M
MAC
RXP4
RXN 4
TXP4
TXN4
A/D
CONV ERTER
DRIVER
Embedded Memory
Switching Fabric
10/100M
MAC
PORT 0
PORT 1
PORT2
...
PORT N
DIGITAL
EQUALIZER
MLT3 Converter
...
10/100M
MAC
PARTITION HANDLER
SCRAMBLER
LED
DISPLAY
CONTROL
Memory
BIST
10/100M
MAC
Data Handler
TRANSMIT
STATE
MACHINE
LED
Interface
MII
Interface
1.5 Abbreviations
BER Bit Error Rate
CFI Canonical Format Indicator
COL Collision
CRC Cyclic Redundancy Check
CRS Carrier Sense
CS Chip Select
DA Destination Address
DI Data Input
DO Data Output
EDI EEPROM Data Input
EDO EEPROM Data Output
EECS EEPROM Chip Select
CLOCK GENERATORBIAS
Figure 1-1 ADM6996L Block Diagram
ADMtek Inc. 1-3
ADM6996L Product Review
EESK EEPROM Clock
ESD End of Stream Delimiter
FEFI Far End Fault Indication
FET Field Effect Transistor
FLP Fast Link Pulse
GND Ground
GPSI General Purpose Serial Interface
IPG Inter-Packet Gap
LFSR Linear Feedback Shift Register
MAC Media Access Controller
MDIX MDI Crossover
MII Media Independent Interface
NRZI Non Return to Zero Inverter
NRZ Non Return to Zero
PCS Physical Coding Sub-layer
PHY Physical Layer
PLL Phase Lock Loop
PMA Physical Medium Attachment
PMD Physical Medium Dependent
QoS Quality of Service
QFP Quad Flat Package
RST Reset
RXCLK Receive Clock
RXD Receive Data
RXDV Receive Data Valid
RXER Receive Data Errors
RXN Receive Negative (Analog receive differential signal)
RXP Receive Positive (Analog receive differential signal)
SA Source Address
SOHO Small Office Home Office
SSD Start of Stream Delimiter
SQE Signal Quality Error
TOS Type of Service
TP Twisted Pair
TTL Transistor Transistor Logic
TXCLK Transmission Clock
TXD Transmission Data
TXEN Transmission Enable
TXN Transmission Negative
TXP Transmission Positive
ADMtek Inc. 1-4
ADM6996L Product Review
1.6 Conventions
1.6.1 Data Lengths
qword 64-bits
dword 32-bits
word 16-bits
byte 8 bits
nibble 4 bits
1.6.2 Pin Types
Pin Type Description
I Input
O Output
I/O Bi-directional
OD Open drain
SCHE Schmitt Trigger
PD internal pull-down
PU internal pull-up
1.6.2 Register Types
Register Type Description
RO Read-only
WO Write-only
RW Read/Write
ADMtek Inc. 1-5
ADM6996L Interface Description
Chapter 2 Interface Description
2.1 Pin Diagram
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
RXER
GND
GNDO
VCC3O
RXCLK
RXDV
RXD0
VCCIK
GNDIK
CRS
COL
EDI (LEDMODE)
EECS
EESK (XOVEN)
VCCIK
GNDIK
EDO
CKO25M
CFG0
GNDO
VCC3O
SPDTNP5
LNKFP5
DPHALFP5
LNKACT4
GNDIK
VCCIK
LNKACT3
LNKACT2
LNKACT1
LNKACT0
GNDO
RXD1
RXD2
RXD3
65
66
67
68
VCCIK
TXEN (PHYAS0)
TXCLK
103
DUPCOL4
104
GNDO
105
VCC3O
106
DUPCOL3
107
DUPCOL2 (BPEN)
108
DUPCOL1 (PHYAS1)
109
DUPCOL0 (RECANEN)
110
VCCIK
111
GNDIK
112
RC
113
XI
114
XO
115
VCCPLL
116
GNDPLL
117
CONTROL
118
VREF
119
GNDBIAS
120
RTX
121
VCCBIAS
122
VCCA2
123
TXP0
124
TXN0
125
GNDA
126
RXP0
127
RXN0
128
VCCAD
NC
P4FX
TXP4
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
GNDIK
(GFCEN) TXD0
TXD1
TXD2
TXD3
LDSPD4
GNDO
VCC3O
LDSPD3
LDSPD2
VCCIK
ADM6996L
GNDA
VCCAD
RXN1
RXP1
12
11
10
GNDA
NC
NC
16
15
14
13
NC
VCCA2
VCCA2
TXN2
TXP2
NC
22
21
20
19
18
17
GNDA
NC
NC
NC
1
5
4
3
2
TXN1
TXP1
9
8
7
6
VCCA2
VCCA2
GNDA
VCCAD
RXN2
RXP2
25
24
23
GNDA
NC
NC
29
28
27
26
NC
VCCA2
VCCA2
NC
32
31
30
GNDA
TXN3
TXP3
36
35
34
33
GNDIK
LDSPD1
LDSPD0
TEST
VCCIK
GNDIK
GNDO
VCCA2
TXN4
GNDA
RXP4
RXN4
VCCAD
RXN3
RXP3
38
37
Figure 2-1 5 TP/FX PORT + 1 MII PORT 128 Pin Diagram
ADMtek Inc. 2-1
ADM6996L Interface Description
2.2 Pin Description by Function
ADM6996L pins are categorized into one of the following groups:
Section 2.2.1 Twisted Pair Interface
Section 2.2.2 6th Port (MII) Interfaces
Section 2.2.3 LED Interface
Section 2.2.4 EEPROM/Management Interface
Section 2.2.5 Power/Ground, 48 pins
Section 2.2.6 MISC
Note:
“Section 1.6.2 Pin Types” can be used for reference.
2.2.1 Twisted Pair Interface
Pin Name Pin# Type Descriptions
RXP[0:4] 126, 11, 24, 37, 41 I/O,
Analog
RXN[0:4] 127, 12, 25, 38, 40 I/O,
Analog
TXP[0:4] 123, 8, 21, 34, 44 I/O,
Analog
TXN[0:4] 124, 9, 22, 35, 43 I/O,
Analog
Twisted Pair Receive Input Positive.
Twisted Pair Receive Input Negative.
Twisted Pair Transmit Output Positive.
Twisted Pair Transmit Output Negative.
2.2.2 6th Port (MII) Interfaces
Pin Name Pin# Type Descriptions
TXD[0]
Setting
GFCEN
TXD[1]
Setting
P5GPSI
TXD[3:2] 59, 60 I/O, MII Transmit Data bit 3~2
63 I/O,
8mA
PU
61 I/O,
8mA
PD
MII transmit data 0 /GPSI TXD
Acts as MII transmit data TXD[0]. Synchronous to the rising
edge of TXCLK.
Setting
GFCEN: Global Flow Control Enable.
At power-on-reset, latched as Full Duplex Flow control
setting
“1” to enable flow-control (default ), “0” to disable flowcontrol.
MII Transmit Data bit 1
Synchronous to the rising edge of TXCLK. These pins act
as MII TXD[1].
Setting
P5GPSI: Port 5 GPSI Enable.
At power-on-reset, latched as P5 GPSI Enable.
“0” to disable port 5 GPSI (default ), “1” to enable port 5
GPSI.
ADMtek Inc. 2-2
ADM6996L Interface Description
Pin Name Pin# Type Descriptions
8mA
PD
P4FX 62 I
PD
XEN
Setting
PHYAS0
RXD[0] 74 I
RXD[3:1] 102, 101,
RXDV 73 I
RXER 68 I
COL 78 I
CRS 77 I
RXCLK 72 I MII Port Receive Clock Input /GPSI RXCLK
TXCLK 67 I MII Port Transmit clock Input /GPSI TXCLK
DHALFP5 91 I
LNKFP5 90 I
SPDTNP5 89 I
66 I/O
8mA
PD
PD
100
PD
PD
PD
PD
PD
PD
PD
PD
Synchronous to the rising edge of TXCLK. These pins act
as MII TXD[3:2].
Port4 FX/TX mode select. Internal pull down.
1: Port4 as FX port.
0: Port4 as TX port.
MII Transmit Enable/GPSI TXEN. Internal pull down.
Setting
PHYAS0: Chip physical address for multiple chip application
on read EEPROM data. Internal pull down.
Power on reset value PHYAS0 combines with PHYAS1
PHYAS1 PHYAS0
0 0 Master(93C46)
If there is no EEPROM then user must use 93C66 timing to
write chip’s register.
If user put 93C46 with correct Signature then user writes
chip register by 93C46 timing.
If user put 93C66 then data put in Bank0. User can write
chip register by 93C66 timing.
User must assert one SK cycle when CS at idle stage when
write chip internal register.
MII port receive data 0 /GPSI RXD
These pins act as MII RXD[0]. Synchronous to the rising
edge of RXCLK. Internal pull down.
I
MII port receive data 3~1
These pins act as MII RXD[3:1]. Synchronous to the rising
edge of RXCLK. Internal pull down.
MII receive data valid.
Internal pull down.
MII Port Receive Error.
Internal pull down.
MII Port Collision input /GPSI Collision Input
Internal pull down.
MII Port Carrier Sense /GPSI Carrier Sense
Internal pull down.
MII Port Hardware Duplex input pin.
Low: Full Duplex. High: Half Duplex.
Internal pull down.
MII Port Hardware Link input pin.
Low: Link OK. High: Link Off.
Internal pull down.
MII Port Hardware Speed input pin.
Low: 100M. High: 10M.
Internal pull down.
ADMtek Inc. 2-3
ADM6996L Interface Description
2.2.3 LED Interface
Pin Name Pin# Type Descriptions
LNKACT[4:0] 92, 95, 96, 97, 98 O,
8mA
DUPCOL[4:3] 103, 106 O,
8mA
DUPCOL2
Setting
BPEN
DUPCOL1
Setting
PHYAS1
DUPCOL0
Setting
ANEN
LDSPD[4:0] 58, 55, 54, 51, 50 O,
107 O,
8mA,
PU
108 O,
8mA,
PD
109 O,
8mA,
PU
8mA
LINK/Activity LED[4:0]. Active low
“1” indicates no link activity on cable
“0” indicates link okay on cable, but no activity and signals
on idle stage.
“Blinking” indicates link activity on cable.
Duplex/Collision LED[4:3]. Active low
“1” for half-duplex and “blinking” for collision indication
“0” for full-duplex indication
Duplex/Collision LED2. Active low
“1” for half-duplex and “blinking” for collision indication
“0” for full-duplex indication
Setting
BPEN: At power-on-reset, latched as Back Pressure setting
“1” to enable Back-Pressure (defaulted), “0” to disable Back
Pressure.
At power-on-reset, latched as Back Pressure setting “1” to
enable Back-Pressure (defaulted), “0” to disable Back
Pressure.
Duplex/Collision LED1. Active low
“1” for half-duplex and “blinking” for collision indication
“0” for full-duplex indication
Setting
PHYAS1: Power on Reset latch value combine with TXEN.
Internal pull down. Check pin 66.
Duplex/Collision LED0. Active low
“1” for half-duplex and “blinking” for collision indication
“0” for full-duplex indication
Setting
ANEN: On power-on-reset, latched as Auto Negotiation
capability for all ports.
“1” to enable Auto Negotiation ( defaulted by pulled up
internally ),
“0” to disable Auto Negotiation.
Speed LED[4:0]. Used to indicate corresponding port’s
speed status. “0” for 100Mb/s, “1” for 10Mb/s
ADMtek Inc. 2-4
ADM6996L Interface Description
2.2.4 EEPROM/Management Interface
Pin Name Pin# Type Descriptions
EDO 84 I,
TTL,PU
EECS 80 O,
4mA,PD
EECK
Setting
XOVEN
EDI
Setting
LEDMODE
81 I/O,
4mA
PD
79 I/O,
4mA
PD
EEPROM Data Output. Serial data input from EEPROM.
This pin is internally pull-up.
EEPROM Chip Select. This pin is active high chip enable
for EEPROM. When RESETL is low, it will be Tri-state.
Internally Pull-down
Serial Clock. This pin is clock source for EEPROM. When
RESETL is low, it will be tri-state.
Setting
XOVEN: This pin is internal pull-down. On power-on-reset,
latched as P4~0 Auto MDIX enable or not.
“0” to disable MDIX ( defaulted ), “1” to enable MDIX.
Suggest externally pull up to enable MDIX for all ports.
EEPROM Serial Data Input. This pin is output for serial
data transfer. When RESETL is low, it will be tri-state.
Setting
LEDMODE: This pin is internal pull-down. On power-onreset, latched as Dual Color mode or not.
“0” to set Single color mode for LED.
“1” to set Dual Color mode for LED.
2.2.5 Power/Ground, 48 pins
Pin Name Pin# Type Descriptions
GNDA 3, 10, 16,
23, 29, 36,
42, 125
VCCA2 6, 7, 19,
20, 32, 33,
45, 122
VCCAD 13, 26,
39, 128
GNDBIAS 119 I Ground Used by Bias Block
VCCBIAS 121 I 3.3V, Power Used by Bias Block.
GNDPLL 116 I Ground used by PLL
VCCPLL 115 I 1.8V, Power used by PLL
GNDIK 47, 52, 64,
76, 93, 83,
111
VCCIK 48, 53, 65,
75, 82, 94,
110
GNDO 46, 57, 70, 87, 99,
104
VCC3O 56, 71,
88, 105
GND 69 I Ground Used by Digital Pad.
I Ground Used by AD Block.
I 1.8V, Power Used by TX Line Driver.
I 3.3V, Power Used by AD Block.
I Ground Used by Digital Core
I 1.8V, Power Used by Digital Core
I Ground Used by Digital Pad
I 3.3V, Power Used by Digital Pad.
ADMtek Inc. 2-5
ADM6996L Interface Description
2.2.6 MISC
Pin Name Pin# Type Descriptions
CKO25M 85 O,
8mA
Control 117 O
RTX 120 Analog TX Resistor. Add 1.1K %1 resister to GND.
VREF 118 Analog
RC 112 I,
SCHE
XI 113 I,
Analog
XO 114 O,
Analog
CFG0 86 I,
TTL
TEST 49 I,
TTL
NC 1, 2, 4,5, 14, 15,17,
18, 27,28,
25M Clock Output.
FET Control Signal.
The pin is used to control FET for 3.3V to 1.8V regulator.
Analog Reference Voltage.
RC Input for Power On reset. Reset input pin.
25M Crystal Input. 25M Crystal Input. Variation is limited
to +/- 50ppm.
25M Crystal Output. When connected to oscillator, this pin
should left unconnected.
Must Connected to GND.
TEST Value.
At normal application connect to GND.
NC
ADMtek Inc. 2-6
ADM6996L Function Description
Chapter 3 Function Description
3.1 Functional Descriptions
The ADM6996L integrates five 100Base-X physical sub-layer (PHY), 100Base-TX
physical medium dependent (PMD) transceivers, five complete 10Base-T modules, 6 port
10/100 switch controller and one 10/100 MII/GPSI MAC and memory into a single chip
for both 10Mbits/s, 100Mbits/s Ethernet switch operation. It also supports 100Base-FX
operation through external fiber-optic transceivers. The device is capable of operating in
either Full Duplex mode or Half-Duplex mode in 10Mbits/s and 100Mbits/s. Operational
modes can be selected by hardware configuration pins, software settings of management
registers, or determined by the on-chip auto negotiation logic.
The ADM6996L consists of three major blocks:
• 10/100M PHY Block
• Switch Controller Block
• Built-in SSRAM
The interfaces used for communication between PHY block and switch core is MII
interface.
Auto MDIX function is supported in this block. This function can be Enable/Disable by
hardware pin.
3.2 10/100M PHY Block
The 100Base-X section of the device implements the following functional blocks:
• 100Base-X physical coding sub-layer (PCS)
• 100Base-X physical medium attachment (PMA)
• Twisted-pair transceiver (PMD)
• The 100Base-X and 10Base-T sections share the following functional blocks.
• Clock synthesizer module
• MII Registers
• IEEE 802.3u auto negotiation
3.3 100Base-X Module
The ADM6996L implements 100Base-X compliant PCS and PMA and 100Base-TX
compliant TP-PMD as illustrated in Figure 2. Bypass options for each of the major
functional blocks within the 100Base-X PCS provides flexibility for various applications.
100Mbits/s PHY loop back is included for diagnostic purpose.
ADMtek Inc. 3-1
ADM6996L Function Description
3.4 100Base-X Receiver
The 100Base-X receiver consists of functional blocks required to recover and condition
the 125Mbits/s receive data stream. The ADM6996L implements the 100Base-X
receiving state machine diagram as given in ANSI/IEEE Standard 802.3u, Clause 24. The
125Mbits/s receive data stream may originate from the on-chip twisted-pair transceiver in
a 100Base-TX application. Alternatively, the receive data stream may be generated by an
external optical receiver as in a 100Base-FX application.
The receiver block consists of the following functional sub-blocks :
• A/D Converter
• Adaptive Equalizer and timing recovery module
• NRZI/NRZ and serial/parallel decoder
• De-scrambler
• Symbol alignment block
• Symbol Decoder
• Collision Detect Block
• Carrier sense Block
• Stream decoder block
CLOCK/DATA RECOVERY
SDP
10/100
TX
DRIVER
FIBER
OPTIC
DRIVER
RXP
RXN
ADAPTIVE EQUALIZER
TXP
TXN
FOTX+
FOTX-
RXD[1:0]
CRSDV
TXEN
TXD[1:0]
MII TO RMII CONVERTER
RMII TO MII CONVERTER
RXD[3:0]
BP_ALIGN
CRS
RXDV
RXER
COL
TXCLK
TXEN
TXER
TXD[3:0]
BP_4B5B
4B/5B DECODER
BP_4B5B
4B/5B
DECODER
RX STATE
MACHINE
TX STATE
MACHINE
BP_SCR
SCRAMBLER
BP_ALIGN
BP_DSCR
100BASE-X RECEIVER
DESCRAMBLER
SERIAL-TO-PARALLEL
MLT-3
STATE
MACHINE
PARALLAL-TO-SERIAL
100BASE-X TRANSMITTER
ADMtek Inc. 3-2
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