ADLINK Express-LPC User Manual

Express-LPC

User’s Manual

Manual Revision: 2.01
Revision Date: January 4, 2012
Part Number: 50-1J034-1010

Revision History

Release Date Change

2.00 April 15, 2011 Initial release

2.01 January 4, 2012 Remove Atom Processor N570 support; update N455 memory support;
add SMBus address info to System Resources

Express-LPC User’s ManualPage 2

Table of Contents

Preface ............................................................................................................................5

1 Introduction...............................................................................................................7

1.1 Description ...........................................................................................................................7

2 Specifications............................................................................................................8

2.1 General................................................................................................................................. 8

2.2 Integrated Video ................................................................................................................... 8

2.3 Audio .................................................................................................................................... 9

2.4 LAN ....................................................................................................................................... 9

2.5 Multi I/O ................................................................................................................................9

2.6 TPM (Trusted Platform Module) .......................................................................................... 9

2.7 Super I/O .............................................................................................................................. 9

2.8 Power Specifications .........................................................................................................10

3 Functional Diagram................................................................................................. 11

4 Mechanical Dimensions..........................................................................................12

5 Pinout and Signal Descriptions..............................................................................13

5.1 COM Express™ Type 2 compatible pinout ....................................................................... 13

5.2 Carrier Board Design Guide ..............................................................................................13

5.3 Pin Definitions .................................................................................................................... 14

5.4 Signal Descriptions ............................................................................................................ 16

6 Embedded Functions..............................................................................................25

6.1 Watchdog Timer ................................................................................................................. 25

6.2 GPIO ................................................................................................................................... 26

6.3 Hardware Monitoring ......................................................................................................... 27

7 System Resources..................................................................................................28

7.1 System Memory Map .........................................................................................................28

7.2 Direct Memory Access Channels ......................................................................................28

7.3 Legacy I/O Map.................................................................................................................. 29

Page 3Express-IA533 User’s Manual Page 3Express-IA533 User’s ManualExpress-LPC User’s Manual Page 3

7.4 Interrupt Request (IRQ) Lines ........................................................................................... 30

7.5 PCI Configuration Space Map ...........................................................................................32

7.6 PCI Interrupt Routing Map ................................................................................................32

7.7 SMBus Slave Device Address ...........................................................................................32

8 BIOS Setup Utility....................................................................................................33

8.1 Starting the BIOS................................................................................................................33

8.2 Main Setup .........................................................................................................................37

8.3 Advanced BIOS Setup .......................................................................................................38

8.4 Power Management ..........................................................................................................58

8.5 Boot Setup..........................................................................................................................64

8.6 Security Setup ....................................................................................................................68

8.7 Exit Menu ...........................................................................................................................71

9 BIOS Checkpoints, Beep Codes.............................................................................73

9.1 Bootblock Initialization Code Checkpoints........................................................................74

9.2 Bootblock Recovery Code Checkpoints ...........................................................................75

9.3 POST Code Checkpoints ................................................................................................... 76

9.4 OEM POST Error Checkpoints ..........................................................................................78

9.5 DIM Code Checkpoints ......................................................................................................78

9.6 ACPI Runtime Checkpoints................................................................................................79

9.7 Boot Block Beep Codes .....................................................................................................80

9.8 POST BIOS Beep Codes....................................................................................................80

9.9 Troubleshooting POST BIOS Beep Codes........................................................................81

Important Safety Instructions......................................................................................82

Getting Service .............................................................................................................84

Express-LPC User’s ManualPage 4

Preface

Copyright 2011 ADLINK Technology, Inc.

This document contains proprietary information protected by copyright. All rights are
reserved. No part of this manual may be reproduced by any mechanical, electronic, or other
means in any form without prior written permission of the manufacturer.

Disclaimer

The information in this document is subject to change without prior notice in order to improve
reliability, design, and function and does not represent a commitment on the part of the
manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential
damages arising out of the use or inability to use the product or documentation, even if advised
of the possibility of such damages.

Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation
through compliance with the European Union's Restriction of Hazardous Substances (RoHS)
directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental
protection is a top priority for ADLINK. We have enforced measures to ensure that our products,
manufacturing processes, components, and raw materials have as little impact on the
environment as possible. When products are at their end of life, our customers are encouraged to
dispose of them in accordance with the product disposal and/or recovery programs prescribed by
their nation or company.

Trademarks

AMIBIOS®8 is a registered trademark of American Megatrends, Inc. COM Express™, and
PICMG® are registered trademarks of the PCI Industrial Computer Manufacturers Group.

Product names mentioned herein are used for identification purposes only and may be
trademarks and/or registered trademarks of their respective companies.

Page 5Express-IA533 User’s Manual Page 5Express-IA533 User’s ManualExpress-LPC User’s Manual Page 5

Conventions

Take note of the following conventions used throughout this manual to make sure that users
perform certain tasks and instructions properly.

Additional information, aids, and tips that help users perform tasks.

Information to prevent minor physical injury, component damage, data loss,

and/or program corruption when trying to complete a task.

Information to prevent serious physical injury, component damage, data

loss, and/or program corruption when trying to complete a specific task.

Express-LPC User’s ManualPage 6

1 Introduction

1.1 Description

The Express-LPC is a low power, low cost, COM Express Type 2, COM.0 R2.0 module in
Compact form factor that is specially designed to facilitate speedy development of semi
custom designs.

The COM Express standard embodies the convergence of the latest technology standards
based on serial differential signaling such as PCI Express, USB 2.0, SATA and LVDS
implemented on a compact size Computer on Module. Signals are brought out through two
220-pin board-to-board connectors that permit data transmission rates of up to 5GHz.
Mounting holes connect the module with a custom-made, application specific carrier boards
which provide protection from shock and vibration.

The Express-LPC is a COM Express COM.0 R2.0 Type 2 compatible module in
Compact form factor (95 mm x 95 mm). The module supports a 45nm process
Intel® Atom™ processor N455 and D425 with 512 KB L2 cache, and D525 with
1MB L2 cache. The Intel® Atom™ processor integrates a graphics processing
unit (GPU) that provides CRT and single channel LVDS. The Intel® Atom™ processor N455/
D425/D525 also supports Hyper-Threading Technology with 2-threads per core allowing the
Express-LPC to provide excellent performance for multi-tasking applications.

The Express-LPC is positioned as an entry level COM Express module for systems that
require a small footprint with dual core computing power and DDR3 memory. It is ideal for
applications that require Floating Point CPU performance with average graphics support and
moderate power consumption levels, such as Robotics, Industrial control and Data
Communications.

The Intel® I/O Controller Hub 8-M (ICH8-M) allows connection of up to five additional PCI
Express x1 ports, four of which can be grouped to a PCIe x4, while supporting the LAN
controller on the 5th port. The module comes with a single onboard Gigabit Ethernet port and
three SATA ports. It has legacy support for a single parallel IDE channel, 32-bit PCI and LPC.
The Express-LPC comes equipped with AMIBIOS®8 supporting embedded features such as:
Remote Console, CMOS backup in 16Mbit SPI BIOS, CPU and System Monitoring and a Dual
Watchdog Timer for NMI or RESET.

The Express-LPC is a RoHS compliant and leadfree product.

Page 7Express-IA533 User’s Manual Page 7Express-IA533 User’s ManualExpress-LPC User’s Manual Page 7

2 Specifications

2.1 General

f CPU: Atom™ N455: single core 1.66 GHz with 512 kB L2 cache, 6.5 W

Atom™ D425: single core 1.80 GHz with 512 kB L2 cache, 10 W
Atom™ D525: dual core 1.80 GHz with 1 MB L2 cache, 13 W

On-die primary 32-kB instructions cache and 24-kB write-back data cache

- Intel® Hyper-Threading Technology 2-threads per core

- Support for IA 32-bit

- Intel® Streaming SIMD Extensions 2 and 3 (SSE2 and SSE3) and
Supplemental Streaming SIMD Extensions 3 (SSSE3) support

- Intel® 64 architecture

- Micro-FCBGA8 packaging technologies

- Thermal management support via Intel® Thermal Monitor (TM1)

- Supports C0 and C1 states only

- Execute Disable Bit support for enhanced security

f Memory: Dual SODIMM socket for max. 4 GB of non-ECC, 677/800 MHz DDR3

(Atom™ N455 max. 2 GB)

f Chipset: Intel® I/O Controller Hub 8 Mobile (ICH8-M)
f BIOS: AMIBIOS®8 with CMOS backup in 16 Mbit SPI BIOS
f Hardware Monitor: Supply Voltages and CPU temperature
f Watchdog Timer: Programmable timer ranges to generate RESET
f Expansion Busses:

- 5x free PCI Express x1 (6th occupied by GbE LAN)

- PCIe x1 ports 0~3 can be optionally configured as 1 x4

- 32-bit PCI 2.3 at 33MHz, supporting 4 bus masters

- LPC

- SMBus, I2C

2.2 Integrated Video

f GPU: Integrated in CPU with Gen3.5+ GFX Core, core frequency at 200 MHz (N455) and

400 MHz (D425/D525)

f CRT Interface: Analog CRT support up to 2048 x1536 resolution @ 60Hz (QXGA)
f LVDS Interface: Single channel 18-bit TFT with resolution up to 1366x768, 18bpp

Express-LPC User’s ManualPage 8

2.3 Audio

f Chipset: Integrated in Intel® I/O Controller Hub 8 Mobile (ICH8M)
f Audio Codec: HDA type on carrier

2.4 LAN

f Chipset: Intel® 82583V Gigabit Ethernet Controller
f Interface: 10/100/1000 Mbps

2.5 Multi I/O

f IDE (PATA): Single channel IDE with UDMA 100 support
f SATA: Three ports SATA 1.5 Gb/s
f USB: Supports up to eight ports USB 2.0

2.6 TPM (Trusted Platform Module)

f Chipset: Infineon SLB9635TT1.2
f Type: TPM 1.2

2.7 Super I/O

f Connected to LPC bus on carrier if needed.

Page 9Express-IA533 User’s Manual Page 9Express-IA533 User’s ManualExpress-LPC User’s Manual Page 9

2.8 Power Specifications

f Input Power: AT mode (12 V) and ATX mode (12 V and 5 V

)

SB

f Power Management: ACPI 3.0 compliant with battery support.

All power testing was done on power supply wiring leading to the Express carrier
board. Although all voltages were measured, only 12 V and 5 VSB are relevant

because they are the only ones used by the Express module. The Idle power level was
measured under Windows XP with no applications running (logon screen). CPU Stress
was measured using Kpower, and Total System Stress was measured under burn-in

conditions.

Intel® Atom™ N455, 1.66 GHz

Power State +12V +5V

DOS (idle) 0.55 A N.S. 6.60 W
Windows XP logon screen (idle) 0.55 A N.S. 6.60 W
Windows XP CPU Stress (Kpower) 0.99 A N.S. 11.9 W
Windows XP Total System Stress (BurnIn) 1.02 A N.S. 12.2 W
S4 Mode (hibernate) - 0.14 A 0.70 W
S3 Mode (suspend to RAM) - 0.20 A 1.00 W

SB

Power Consumption

Intel® Atom™ D425, 1.80 GHz

Power State +12V +5V

DOS (idle) 1.08 A N.S. 13.0 W
Windows XP logon screen (idle) 1.08 A N.S. 13.0 W
Windows XP CPU Stress (Kpower) 1.17 A N.S. 14.0 W
Windows XP Total System Stress (BurnIn) 1.19 A N.S. 14.3 W
S4 Mode (hibernate) - 0.15 A 0.75 W
S3 Mode (suspend to RAM) - 0.20 A 1.00 W

SB

Power Consumption

Intel® Atom™ D525, 1.80 GHz

Power State +12V +5V

DOS (idle) 0.95 A N.S. 11.4 W
Windows XP logon screen (idle) 0.95 A N.S. 11.4 W
Windows XP CPU Stress (Kpower) 1.17 A N.S. 14.0 W
Windows XP Total System Stress (BurnIn) 1.24 A N.S. 14.9 W
S4 Mode (hibernate) - 0.16 A 0.80 W
S3 Mode (suspend to RAM) - 0.19 A 0.95 W

SB

Power Consumption

CMOS Battery Power Consumption

Current (+3V) Power

4.1 μA 0.000014 W

Express-LPC User’s ManualPage 10

3 Functional Diagram

AB

CRT

18-bit LVD S

5x PCIe x1

(port 0~4)

GbE LAN

82583V

HDA Audio

3x SATA (port 0~2)

PCIe x1

(port 5)

Atom

N455
N570
D425
D525

ICH8M

SODIMM 1

512MB ~ 2GB DDR3

SODIMM 2

512MB ~ 2GB DDR3

XDP

SFF-26

PCI Bus

PATA IDE

CD

4x GPI

4x GP0

8x USB

LPC bus

SMBus

GPIO

PCA9535

I2C

SPI

BC

SPI

SPI BIOS

Page 11Express-IA533 User’s Manual Page 11Express-IA533 User’s ManualExpress-LPC User’s Manual Page 11

4 Mechanical Dimensions

Express-LPC User’s ManualPage 12

5 Pinout and Signal Descriptions

5.1 COM Express™ Type 2 compatible pinout

All pinouts on AB and CD connector of the Express-LPC
comply with pin-out and signal descriptions used in the

®

“PICMG
Specification”.

COM.0 R2.0: COM Express™ Module Base

Parallel ATA, IDE port

alternate definition assigns this to

2 additional Gigabit Ethernet ports

32-bit PCI v2.3 bus

alternate definition assigns this to

10 additional PCI Express x1 lanes

PCI Express x16 for Graphics

these pins can also be assigned to

two SDVO extensions (multiplexed)

SMB and I2C bus

Power / Thermal control

+12V primary power input

95mm.

125mm.

95mm.

CD Connector

The above function mappings are a generic description of COM Express pinouts, and not
necessarily supported on the module described in this manual.

5.2 Carrier Board Design Guide

- Gigabit Ethernet port

- LPC interface

- 4 Serial ATA channels

- High Definition Audio

- 8 USB 2.0 ports

- 6 PCI Express Lanes x1

- Dual 24-bit LVDS channels

- Analog VGA

- 8 GPIO pins

- Keyboard

- primary power input +12V

+5V standby and 3.3V RTC

AB Connector

CD

AB

The PICMG COM Express Carrier Design Guide is a
150-page document that provides information for
designing a custom carrier board for COM Express
modules. The design guide includes reference
schematics for the external circuitry required to
implement the various COM Express peripheral
functions, explains how to extend the supported buses,
and how to add additional peripherals and expansion
slots to a COM Express-based system

Page 13Express-IA533 User’s Manual Page 13Express-IA533 User’s ManualExpress-LPC User’s Manual Page 13

5.3 Pin Definitions

D1

Pinouts for
COM.0 R2.0 Type 2

Pin No. Pin Name Pin N o. Pin Name Pin No. Pin Name Pin No . Pin Name
A1 GND (FIXED) B1 GND (FIXED) C1 GND FIXED) D1 GND FIXED)

A2 GBE0_MDI3- B2 GBE0_ACT# C2 IDE_D7 D2 IDE_D5
A3 GBE0_MDI3+ B3 LPC_FRAME# C3 IDE_D6 D3 IDE_D10
A4 GBE0_LINK100# B4 LPC_AD0 C4 IDE_D3 D4 IDE_D11
A5 GBE0_LINK1000# B5 LPC_AD1 C5 IDE_D15 D5 IDE_D12
A6 GBE0_MDI2- B6 LPC_AD2 C6 IDE_D8 D6 IDE_D4
A7 GBE0_MDI2+ B7 LPC_AD3 C7 IDE_D9 D7 IDE_D0
A8 GBE0_LINK# B8 LPC_DRQ 0# C8 IDE_D2 D8 IDE_REQ
A9 GBE0_MDI1- B9 LPC_DRQ1# C9 IDE_D13 D9 IDE_IOW#
A10 GBE0_MDI1+ B10 LPC_CLK C10 IDE_D1 D10 IDE_ACK#
A11 GND (FIXED) B11 GND (FIXED) C11 GND (FIXED) D11 GND (FIXED)
A12 GBE0_MDI0- B12 PWRBTN# C12 IDE_D14 D12 IDE_IRQ
A13 GBE0_MDI0+ B13 SMB_CK C13 IDE_IORDY D13 IDE_A0
A14 GBE0_CTREF
A15 SUS_S3# B15 SMB_ALERT# C15 PCI_PME# D15 IDE_A2
A16 SATA0_TX+ B16 SATA1_TX+ C16 PCI_GNT2# D16 IDE_CS1#
A17 SATA0_TX- B17 SATA1_TX- C17 PCI_REQ2# D17 IDE_CS3#
A18 SUS_S4# B18 SUS_STAT# C18 PCI_GNT1# D18 IDE_RESET#
A19 SATA0_RX+ B19 SATA1_RX+ C19 PCI_REQ1# D19 PCI_GNT3#
A20 SATA0_RX- B20 SATA1_RX- C20 PCI_GNT0# D20 PCI_REQ3#
A21 GND (FIXED) B21 GND (FIXED) C21 GND (FIXED) D21 GND (FIXED)
A22 SATA2_TX+ B22 SATA3_TX+
A23 SATA2_TX- B23 SATA3_TX­A24 SUS_S5# B24 PWR_OK C24 PCI_AD0 D24 PCI_AD5
A25 SATA2_RX+ B25 SATA3_RX+
A26 SATA2_RX- B26 SATA3_RX­A27 BATLOW# B27 WDT C27 PCI_AD6 D27 PCI_AD9
A28 ATA_ACT# B28 AC_SDIN2 C28 PCI_AD8 D28 PCI_AD11
A29 AC_SYNC B29 AC_SDIN1 C29 PCI_AD10 D29 PCI_AD13
A30 AC_RS T# B30 AC_SDIN0 C30 PCI_AD12 D30 PCI_AD15
A31 GND (FIXED) B31 GND (FIXED) C31 GND (FIXED) D31 GND (FIXED)
A32 AC_BITCLK B32 SPKR C32 PCI_AD14 D32 PCI_PAR
A33 AC_SDOUT B33 I2C_CK C33 PCI_C/BE1# D33 PCI_SERR#
A34 BIOS_DISABLE# B34 I2C_DAT C34 PCI_PERR# D34 PCI_STOP#
A35 THRMTRIP#
A36 USB6- B36 USB7- C36 PCI_DEVSEL# D36 PCI_FRAME#
A37 USB6+ B37 USB7+ C37 PCI_IRDY# D37 PCI_AD16
A38 USB_6_7_OC# B38 USB_4_5_OC# C38 PCI_C/BE2# D38 PCI_AD18
A39 USB4- B39 USB5- C39 PCI_AD17 D39 PCI_AD20
A40 USB4+ B40 USB5+ C40 PCI_AD19 D40 PCI_AD22
A41 GND (FIXED) B41 GND (FIXED) C41 GND (FIXED) D41 GND (FIXED)
A42 USB2- B42 USB3- C42 PCI_AD21 D42 PCI_AD24
A43 USB2+ B43 USB3+ C43 PCI_AD23 D43 PCI_AD26
A44 USB_2_3_OC# B44 USB_0_1_OC# C44 PCI_C/BE3# D44 PCI_AD28
A45 USB0- B45 USB1- C45 PCI_AD25 D45 PCI_AD30
A46 USB0+ B46 USB1+ C46 PCI_AD27 D46 PCI_IRQC#
A47 VCC_RTC B47 EXCD1_PERSET C47 PCI_AD29 D47 PCI_IRQ D#
A48 EXCD0_PERST# B48 EXCD1_CPPE C48 PCI_AD31 D48 PCI_CLKRUN#
A49 EXCD0_CPPE# B49 SYS_RESET# C49 PCI_IRQA# D49 PCI_M66EN
A50 LPC_SERIRQ B50 CB_RESET# C50 PCI_IRQB# D50 PCI_CLK

B14 SMB_DAT C14 IDE_IOR# D14 IDE_A1

B35 THRM# C35 PCI_LOCK# D35 PCI_TRDY#

C1

B1

A1

C22 PCI_REQ0# D22 PCI_AD1
C23 PCI_RESET# D23 PCI_AD3

C25 PCI_AD2 D25 PCI_AD7
C26 PCI_AD4 D26 PCI_C/BE0#

D110

C110

B110

A110

C D

A B

Express-LPC User’s ManualPage 14

Pin Definitions (cont’d)

Pin No. Pin Name Pin N o. Pin Name Pin No. Pin Name Pin No . Pin Name
A50 LPC_SERIRQ B50 CB_RESET# C50 PCI_IRQB# D50 PCI_CLK

A51 GND (FIXED) B51 GND (FIXED) C51 GND (F IXED) D51 GND (FIXED)
A52 PCIE_TX5+
A53 PCIE_TX5-
A54 GPI0 B54 GPO1 C54 TYPE0# D54 PEG_LANE_RV#
A55 PCI E_TX4+ B55 PCIE_RX4+ C55 PEG_RX1+ D55 SDVO B [GRN]+
A56 PCI E_TX4- B56 PCIE_RX4- C56 PEG_RX1- D56 SDVO B [GRN]-
A57 GND B57 GPO2 C57 TYPE1# D57 TYPE2#
A58 PCI E_TX3+ B58 PCIE_RX3+ C58 PEG_RX2+ D58 SDVO B [BLU]+
A59 PCI E_TX3- B59 PCIE_RX3 - C59 PEG_RX2- D59 SDVO B [BLU]-
A60 GND (FIXED) B60 GND (FIXED) C60 GND (F IXED) D60 GND (FIXED)
A61 PCIE_TX2+ B61 PCIE_RX2+ C61 PEG_RX3+
A62 PCIE_TX2- B62 PCIE_RX2- C62 PEG_RX3- D62 SDVO B Clock-
A63 GPI1 B63 GPO3 C63 RSVD D63 RSVD
A64 PCIE_TX1+ B64 PCIE_RX1+ C64 RSVD D64 RSVD
A65 PCIE_TX1- B65 PCIE_RX1- C65 PEG_RX4+
A66 GND B66 WAKE0# C66 PEG_RX4- D66 SDVO C [RED]-
A67 GPI2 B67 WAKE1# C67 RS VD (1 ) D 67 GND
A68 PCIE_TX0+ B68 PCIE_RX0+ C68 PEG_RX5+
A69 PCIE_TX0- B69 PCIE_RX0- C69 PEG_RX5- D69 SDVO C [GRN]-
A70 GND (FIXED) B70 GND (FIXED) C70 GND (F IXED) D70 GND (FIXED)
A71 LVDS_A0+ B71 LVDS_B0+
A72 LVDS_A0- B72 LVDS_B0- C72 PEG_RX6- D72 SDVO C [BLU]-
A73 LVDS_A1+ B73 LVDS_B1+ C73 SDVO_DATA D73 SDVO_CLK
A74 LVDS_A1- B74 LVDS_B1- C74 PEG_RX7+ D74 SDVO C Clock+
A75 LVDS_A2+ B75 LVDS_B2+ C75 PEG_RX7- D75 SDVO C Clock-
A76 LVDS_A2- B76 LVDS_B2- C76 GND D76 GND
A77 LVDS_VDD_EN B77 LVDS_B3+
A78 LVDS_A3+ B78 LVDS_B3- C78 PEG_RX8+ D78 PEG_TX8+
A79 LVDS_A3- B79 LVDS_BKLT_EN C79 PEG_RX8- D79 PEG_TX8-
A80 GND (FIXED) B80 GND (FIXED) C80 GND (F IXED) D80 GND (FIXED)
A81 LVDS_A_CK+ B81 LVDS_B_CK+
A82 LVDS_A_CK- B82 LVDS_B_CK- C82 PEG_RX9- D82 PEG_TX9-
A83 LVDS_I2C_CK B83 LVDS_BKLT_CT RL C83 RSVD D83 RSVD
A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84 GND D84 GND
A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10+
A86 KBD_RST# B86 VCC_5V_SBY C86 PEG_RX10- D86 PEG_TX10-
A87 KBD_A20GATE B87 VCC_5V_SBY C87 GND D87 GND
A88 PCIE0_CK_REF+ B88 BIOS_DIS1# C88 PEG_RX11+
A89 PCIE0_CK_REF- B89 VGA_RED C89 PEG_RX11- D89 PEG_TX11-
A90 GND (FIXED) B90 GND (FIXED) C90 GND (F IXED) D90 GND (FIXED)
A91 SPI_POWER B91 VGA_GRN C91 PEG_RX12+
A92 SPI_MISO B92 VGA_BLU C92 PEG_RX12- D92 PEG_TX12-
A93 GPO0 B93 VGA_HSYNC C93 GND D93 GND
A94 SPI_CLK B94 VGA_VSYNC C94 PEG_RX13+
A95 SPI_MISO B95 VGA_I2C_CK C95 PEG_RX13- D95 PEG_TX13-
A96 GND B96 VGA_I2C_DAT C96 GND D96 GND
A97 TYPE10#
A98 RSVD B98 RSVD C98 PEG_RX14+ D98 PEG_TX14+
A99 RSVD B99 RSVD C99 PEG_RX14- D99 PEG_TX14-
A100 GN D (FIXE D) B100 GND (FIXED) C100 GND (FIXED) D100 GND (FIXED)
A101 RSVD B101 RSVD C101 PEG_RX15+
A102

RSVD
A103 RSVD B103 RSVD C103 GND D103 GND
A104 VCC_12V B104 VCC_12V C104 VCC _12V D104 VCC_12V
A105 VCC_12V B105 VCC_12V C105 VCC _12V D105 VCC_12V
A106 VCC_12V B106 VCC_12V C106 VCC _12V D106 VCC_12V
A107 VCC_12V B107 VCC_12V C107 VCC _12V D107 VCC_12V
A108 VCC_12V B108 VCC_12V C108 VCC _12V D108 VCC_12V
A109 VCC_12V B109 VCC_12V C109 VCC _12V D109 VCC_12V
A110 GN D (FIXE D) B110 GND (FIXED) C110 GND (FIXED) D110 GND (FIXED)

(1)

(1)

B52 PCIE_RX5+
B53 PCIE_RX5-

B97 SPI_CS# C97 RSVD D97 PEG_ENABLE#

B102 RSVD C102 PEG_RX15- D102 PEG_TX15-

(1)

(1)

C52 PEG_RX0+ D52 SDVO B [RED]+
C53 PEG_RX0- D53 SDVO B [RED]-

D61 SDVO B Clock+

D65 SDVO C [RED]+

D68 SDVO C [GRN]+

C71 PEG_RX6+ D71 SDVO C [BLU]+

C77 RSVD D77 IDE_CBLID#

C81 PEG_RX9+ D81 PEG_TX9+

D85 PEG_TX10+

D88 PEG_TX11+

D91 PEG_TX12+

D94 PEG_TX13+

D101 PEG_TX15+

XXX Strikethrough pins are not supported on this module.
(1) The 6th PCI Express x1 port (PCIE5) is occupied by the onboard LAN controller. .

Page 15Express-IA533 User’s Manual Page 15Express-IA533 User’s ManualExpress-LPC User’s Manual Page 15

5.4 Signal Descriptions

_

_

_

AC_

C

_

_6_7_

_

Pin Signal Description Type PU/PD Comment

A1 GND Ground PWR - ­A2 GBE0_MDI3- Ethernet Media Dependent Interfac e - I/O - DP - ­A3 GBE0_MDI3+ Ethernet Me dia Dependent Interface + I/O - DP - ­A4 GBE0_LINK100# Ethernet Sp ee d LED (100Mb) O-3.3 - On at 100Mb/s
A5 GBE0_LINK1000# Ethernet Speed LED (1000Mb) O-3.3 - On at 1000Mb/s
A6 GBE0_MDI2- Ethernet Media Dependent Interfac e - I/O - DP - ­A7 GBE0_MDI2+ Ethernet Me dia Dependent Interface + I/O - DP - ­A8 GBE0 _LIN K # LAN Link LED O-3 .3 - -

A9 GBE0_MDI1- Ethernet Media Dependent Interfac e - I/O - DP - ­A10 GBE0_MDI1+ Ethernet Me dia Dependent Interface + I/O - DP - ­A11 GND Ground PWR - ­A12 GBE0_MDI0- Ethernet Media Dependent Interface - I/O - DP - ­A13 GBE0_MDI0+ Ethernet Me dia Dependent Interface + I/O - DP - ­A14 GBE0_C TREF ETHCTREF O-1,8 - not supported
A15 SUS_S3# PM_SLP_S#3 O-3.3 - ­A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55

SATA0

SATA0_TX-

SUS_S4#
SATA0_RX+
SATA0

GND

SATA2_TX+

SATA2_TX-

SUS_S5#
SATA2
SATA2_RX-

BATLOW#

ATA_ACT#

SYN

AC_RST#

GND
AC_BITCLK
AC_SDOUT

BIOS

DISABLE#

THRMTRIP#

USB6-

USB6+

USB

USB4-

USB4+

GND

USB2-

USB2+

USB_2_3_OC#

USB0-

USB0+

VCC

RTC

EXCD0_PERST#

EXCD0_CPPE#

LPC_SERIRQ

GND

PCIE5_TX+

PCIE5_TX-

GPI0

PCIE4_TX+

SATA0_TX+ | SATA 0 Transmit Data + O - DP - -

TX+

SATA0_TX- | SA TA 0 Transmit Data - O - DP - ­PM_SLP_S#4 O-3.3 - ­SA TA0_RX+ | SA TA 0 Recei ve Data + I - DP - ­SATA 0_RX - | SATA 0 Receive Data - I - DP - -

RX-

Ground PWR - ­SATA2_TX+ | SATA 2 Transmit Data + O - DP - ­SATA2_TX- | SA TA 2 Transmit Data - O - DP - ­PM_SLP_S#5 O-3.3 - -
SA TA2_RX+ | SA TA 2 Recei ve Data + I - DP - -

RX+

SATA2_R X- | SATA 2 Receive Data - I - DP - -
PM_BATLOW# | Battery Low I-3.3 PU 8k2 3.3Vsb ­ATA_LED# | SATA L ED O-3.3 PU 10k 3.3V
AC_SYNC | AC'97 Sync O-3.3 - int. PD 20k in ICH8
AC_RST# | AC'9 7 Reset O-3.3 - int. PD 20k i n ICH8
Ground PWR ­AC_BITCLK | AC'97 Clock O-3.3 - int. PD 20k in ICH8
AC_SDATAOUT | AC'97 Data O-3.3 - int. PD 20k in ICH8
BIOS_D I SA BLE # I-3.3 PU 10k 3.3Vsb ­PM_THRMTRIP#_CON O-3.3 PU 330 3.3V ­USB_PN6 | USB Data – Port6 I/O - DP - int. PD 15k in ICH8
USB_PP6 | USB Data + Port6 I/O - DP - int. PD 15k in ICH8
USB_OC #_6_7 | USB OverCurrent Port 6/7 I-3.3 PU 10k 3.3Vsb -

OC#

USB_PN4 | USB Data - Port4 I/O - DP - int. PD 15k in ICH8
USB_PP4 | USB Data + Port4 I/O - DP - int. PD 15k in ICH8
Ground PWR - ­USB_PN2 | USB Data - Port2 I/O - DP - int. PD 15k in ICH8
USB_PP2 | USB Data + Port2 I/O - DP - int. PD 15k in ICH8
USB_OC #_2_3 | USB OverCurrent Port 2/3 I-3.3 PU 10k 3.3Vsb
USB_PN0 | USB Data - Port0 I/O - DP - int. PD 15k in ICH8
USB_PP0 | USB Data + Port0 I/O - DP - int. PD 15k in ICH8
V_BAT PWR - ­Express Card Support [0]|card reset O-3.3 PU 10k 3.3Vsb -

Express Card Support [0]| capable c. request

INT_SERIRQ | Serial Interrupt Request IO-3.3 PU 8k 2 3.3V ­Ground PWR - ­PCI Express 5 Transmit + I - DP - ­PCI Express 5 Transmit - I - DP - ­General Purpose Input 0 I-3.3 PU 10k 3.3Vsb ­PCI Express 4 Transmit + (extended only) O - DP - -

Row A

I- 3.3 PU 10k 3.3 V -

Express-LPC User’s ManualPage 16

Signal Descriptions (cont’d)

_A0+

_A2+

_CK_

Row A

Pin Signal Description Type PU/PD Comment

A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A95
A96
A97
A98

A99
A100
A101
A102
A103
A104
A105
A106
A107
A108
A109
A110

PCIE4_TX-

GND

PCIE3_TX+

PCIE3_TX-

GND

PCIE2_TX+

PCIE2_TX-

GPI1

PCIE1_TX+

PCIE1_TX-

GND
GPI2

PCIE0_TX+

PCIE0_TX-

GND

LVDS

LVDS_A0-

LVDS_A1+

LVDS_A1-

LVDS

LVDS_A2-

LVDS_VDD_EN

LVDS_A3+

LVDS_A3-

GND

LVDS_A_CK+

LVDS_A_CK-

LVDS_I2C_CK

LVDS_I2C_DAT

GPI3

KBD_RST#
KBD_A20GATE
PCIE_CK_REF+
PCIE

GND

SPI_POWER

SPI_MISO

GPO0

SPI_CLK

SPI_MOSI

GND

TYPE10#

RSVD
RSVD

GND
RSVD
RSVD
RSVD

VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V

GND

PCI Express 4 Transmit - (extended only) O - DP - ­Ground PWR - ­PCI Express 3 Transmit (extended only) O - DP - ­PCI Express 3 Transmit (extended only) O - DP - ­Ground PWR - ­PCI Express 2 Transmit + O - DP - ­PCI Express 2 Transmit - O - DP - ­General Purpose Input 1 I-3.3 PU 10k 3.3Vsb ­PCI Express 1 Transmit + O - DP - ­PCI Express 1 Transmit - O - DP - ­Ground PWR - ­General Purpose Input 2 I-3.3 PU 10k 3.3Vsb ­PCI Express 0 + O - DP - ­PCI Express 0 - O - DP - ­Ground PWR - ­LVDS_AP0 | LVDS Channel A O - DP - 18-bit only
LVDS_AN0 | LVDS Channel A O - DP - 18-bit only
LVDS_AP1 | LVDS Channel A O - DP - 18-bit only
LVDS_AN1 | LVDS Channel A O - DP - 18-bit only
LVDS_AP2 | LVDS Channel A O - DP - 18-bit only
LVDS_AN2 | LVDS Channel A O - DP - 18-bit only
LVDS_V DDEN | LV DS Panel Power O-2,5 PD 100k ­LVDS_AP3 | LVDS Channel A O - DP ­LVDS_AN3 | LVDS Channel A O - DP ­Ground PWR - ­LVDS_CLK AP | LVDS Channel A O - DP - ­LVDS_CLKAN | LVDS Channel A O - DP - ­LVDS_DDCPCLK | JI LI I2C Clock IO-3.3 PU 10k 3.3V ­LVDS_DDCPDATA | JILI I2C Data IO-3.3 PU 10k 3.3V ­General Purpose Input 3 I-3.3 PU 10k 3.3Vsb ­H_RCIN# | Ke yboard Reset I-3.3 PU 10k 3.3V ­H_A20GATE I-3.3 PU 10k 3.3V ­CLK _PC IE_REF P O - DP - ­CLK _PC IE_REF N O - DP - -

REF-

Ground PWR - ­Power supply for Carrier Board SPI O-3.3 - -

IO - ­General Purpose Output 0 O-3.3 PU 10k 3.3Vsb ­Clock from Module to Carrier SPI IO - ­Data out from Module to Carrier SPI IO - ­Ground PWR - ­Module type ID p in 10 NC - -

NC - ­NC - -

Ground PWR - -

NC - ­NC - -

NC - ­Power 12V PWR - ­Power 12V PWR - ­Power 12V PWR - ­Power 12V PWR - ­Power 12V PWR - ­Power 12V PWR - ­Ground PWR - -

not supported
not supported

Page 17Express-IA533 User’s Manual Page 17Express-IA533 User’s ManualExpress-LPC User’s Manual Page 17

Signal Descriptions (cont’d)

_

_

_

Row B

Pin Signal Description Type PU/PD Comment

B1 GND Ground PWR - ­B2 GBE0_ACT# LAN_ACTLED# | Ethernet Activity LED O-3.3 - ­B3 LPC_FRAME# LPC_FRAME# | LPC Frame Indicator O-3.3 - ­B4 LPC_AD0 LPC_AD0 | LPC Adress & DATA Bus IO-3.3 - int. PU 20k in ICH8
B5 LPC_AD1 LPC_AD1 | LPC Adress & DATA Bus IO-3.3 - int. PU 20k in ICH8
B6 LPC_AD2 LPC_AD2 | LPC Adress & DATA Bus IO-3.3 - int. PU 20k in ICH8
B7 LPC_AD3 LPC_AD3 | LPC Adress & DATA Bus IO-3.3 - int. PU 20k in ICH8
B8 LPC_DRQ0# SIO_DRQ#0 | LPC Serial DMA Request 0 I-3.3 - int. PU 20k in ICH8

B9 LPC_DRQ1# SIO_DRQ#1 | LPC Serial DMA Request 1 I-3.3 - int. PU 20k in ICH8
B10 LPC_CLK CLK_SIOEXTPCI O-3.3 - ­B11 GND Ground I-3.3 - ­B12 PWRBTN# Power Button I-3.3 PU 10K 3.3Vsb ­B13 SMB_CK SMBUS Clock O-3.3 PU 2k2 3.3 V ­B14 SMB_DAT SMBUS Data IO-3 .3 PU 2k2 3.3V ­B15 SMB_ALERT# SMB_ALERT# I-3.3 PU 10k 3.3Vsb ­B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55

SATA1_TX+

SATA1_TX-

STAT#

SUS
SATA1_RX+
SATA1_RX-

GND

SATA3_TX+

SATA3

PWR_OK
SATA3_RX+
SATA3_RX-

WDT
AC_SDIN2
AC_SDIN1
AC_SDIN0

GND

SPKR

I2C_CK

I2C_DAT

THRM#

USB7­USB7+

USB_4_5_OC#

USB5­USB5+

GND

USB3­USB3+

USB_0_1_OC#

USB1­USB1+

EXCD1_PERST#

EXCD1_CPPE#

RESET#

SYS

CB_RESET#

GND

PCIE5_RX+

PCIE5_RX-

GPO1

PCIE4_RX+

SATA1_TX+ | SATA 1 Transmit Data + O - DP - ­SATA1_TX- | SATA 1 Transmit Data - O - DP - ­PM_SUS _ STAT# O-3.3 - ­SATA1_RX+ | SATA 1 Receive Data + I - DP - ­SATA1_RX - | SATA 1 Receive Data - I - DP - ­Ground PWR - ­SATA3_TX+ | SATA 3 Transmit Data +
SATA3_TX- | SATA 3 Transmit Data -

TX-

Power OK I-3.3 - ­SATA3_RX+ | SATA 3 Receive Data +
SATA3_RX - | SATA 3 Receive Data ­Watch Dog Timer O-3.3 - ­AC_SDATAIN2 I-3.3 - int. PD 20k in ICH8
AC_SDATAIN1 I-3.3 - int. PD 20k in ICH8
AC_SDATAIN0 I-3.3 - int. PD 20k in ICH8
Ground PWR ­AC_SPKR O-3.3 - int. PD 20k in ICH8
I2CLK O-3.3 PU 10k 3.3Vsb ­I2DAT IO-3.3 PU 10k 3.3Vs b ­PM THRM# CON | Over Temperature I-3.3 - ­USB_PN7 | USB Data – Port7 I/O - DP - int. PD 15k in ICH8
USB_PP7 | USB Data + Port7 I/O - DP - int. PD 15k in ICH8
USB_OC#_4_5 | USB OverCurrent Port I-3.3 PU 10k 3.3Vsb
USB_PN5 | USB Data- Port5 I/O - DP - int. PD 15k in ICH8
USB_PP5 | USB Data+ Port5 I/O - DP - int. PD 15k in ICH8
Ground PWR - ­USB_PN3 | USB Data- Port3 I/O - DP - int. PD 15k in ICH8
USB_PP3 | USB Data+ Port3 I/O - DP - int. PD 15k in ICH8
USB_OC#_0_1 | USB OverCurrent Port I-3.3 PU 10k 3.3Vsb ­USB_PN1 | USB Data- Port1 I/O - DP - int. PD 15k in ICH8
USB_PP1 | USB Data+ Port1 I/O - DP - int. PD 15k in ICH8
Express Card Support [1]|card reset O-3.3 PU 10k 3.3Vsb ­Express Card Support [1]| capable c. I-3.3 PU 10k 3.3V ­ETX_SYS_RESET# | Reset Input I-3.3 PU 10k 3.3V ­PCI_RST# | PCI Bus Reset O-3.3 - ­Ground PWR - ­PCI Express 5 Recieve + I - DP - ­PCI Express 5 Receive - I - DP - ­General Purpose Output 1 O-3.3 PU 10k 3.3V sb ­PCI Express 4 Recieve + (ex tended only) I - DP - -

NC
NC

NC
NC

- not supported

- not supported

- not supported

- not supported

Express-LPC User’s ManualPage 18

Signal Descriptions (cont’d)

_

_

_5V_SBY

v

_

Row B

Pin Signal Description Type PU/PD Comment

B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83

LVDS_BKLT_CTRL

B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
B95
B96
B97
B98

B99
B100
B101
B102
B103
B104
B105
B106
B107
B108
B109
B110

PCIE4_RX-

GPO2

PCIE3_RX+

PCIE3_RX-

GND

PCIE2_RX+

PCIE2_RX-

GPO3

PCIE1_RX+

PCIE1_RX-

WAKE0#
WAKE1#

PCIE0_RX+

PCIE0

GND

LVDS_B0+

LVDS_B0-

LVDS

LVDS_B1-

LVDS_B2+

LVDS_B2-

LVDS_B3+

LVDS_B3-

LVDS_BKLT_EN

GND
LVDS_B_CK+
LVDS_B_CK-

VCC_5V_SBY
VCC_5V_SBY
VCC_5V_SBY
VCC

BIOS_DIS1#

VGA_RED

GND

GRN

VGA

VGA_BLU
VGA_HSYNC
VGA_VSYNC
VGA_I2C_CK

VGA_I2C_DAT

SPI_CS#

RSVD
RSVD

GND
RSVD
RSVD
RSVD

VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V

GND

PCI Express 4 Receive - (extended only) I - DP - ­General Purpose Output 2 O-3.3 PU 10k 3.3V sb ­PCI Express 3 Receive + (ex tended only) I - DP - ­PCI Express 3 Receive - (extended only) I - DP - ­Ground PWR - ­PCI Express 2 Receive + I - DP - ­PCI Express 2 Receive - I - DP - ­General Purpose Output 3 O-3.3 PU 10k 3.3V sb ­PCI Express 1 Receive + I - DP - ­PCI Express 1 Receive - I - DP - ­PCIE_WAK EI # I-3. 3 PU 1k 3.3 V sb ­WAKE1# I-3.3 PU 10k 3.3Vsb ­PCI Express 0 Receive + I - DP - ­PCI Express 0 Receive - I - DP - -

RX-

Ground PWR - ­LVDS_BP0 | LVDS Channel B Data0+ O - DP - not supported
LVDS_BN0 | LVDS Channel B Data0- O - DP - not supported
LVDS_BP1 | LVDS Channel B Data1+ O - DP - not supported

B1+

LVDS_BN1 | LVDS Channel B Data1- O - DP - not supported
LVDS_BP2 | LVDS Channel B Data2+ O - DP - not supported
LVDS_BN2 | LVDS Channel B Data2- O - DP - not supported
LVDS_BP3 | LVDS Channel B Data3+ O - DP - not supported
LVDS_BN3 | LVDS Channel B Data3- O - DP - not supported
LVDS Panel Backlight Enable O-3.3 PD 100k 3.3V ­Ground PWR - ­LVDS_CLKBP | LVDS Ch annel B O - DP - ­LVDS_CLKBM | LVDS Channel B O - DP - ­Backlight Brightness O-3.3 - ­5V Standby PWR - ­5V Standby PWR - ­5V Standby PWR - ­5V Standby PWR - ­Selection straps to determine the BIOS boot de
Analog Video RGB-RED OA PD 150R ­Ground PWR - ­Analog Video RGB-GREEN OA PD 150R ­Analog Video RGB-BLUE OA PD 150R ­Analog Video H-Sync O-3.3 - ­Analog Video V-Sync O-3.3 - ­Display Data Channel - Cl ock O-3.3 PU 2k2 3.3V ­Display Data Channel - Data IO-3.3 PU 2k2 3.3V ­Chip select for Carrier Board SPI O-3.3 - -

Ground PWR - -

Power 12V PWR - ­Power 12V PWR - ­Power 12V PWR - ­Power 12V PWR - ­Power 12V PWR - ­Power 12V PWR - ­Ground PWR - -

I-3.3 - -

NC - ­NC - -

NC - ­NC - ­NC - -

Page 19Express-IA533 User’s Manual Page 19Express-IA533 User’s ManualExpress-LPC User’s Manual Page 19

Signal Descriptions (cont’d)

p

yp

Pin Signal Description Type PU/PD Comment

C1 GND Ground PWR - ­C2
C3
C4
C5 IDE_D15
C6
C7
C8

C9
C10 IDE_D1
C11
C12
C13
C14 IDE_IOR#
C15
C16
C17
C18 PCI_GNT1#
C19
C20
C21
C22
C23 PCI_RESET#
C24
C25
C26
C27 PCI_AD6
C28
C29
C30
C31
C32 PCI_AD14
C33
C34
C35
C36 PCI_DEVSEL#
C37
C38
C39
C40
C41 GND
C42
C43
C44
C45 PCI_AD25
C46
C47
C48
C49 PCI_IRQA#
C50
C51
C52
C53
C54 TYPE0 #
C55

IDE_D7 IDE Data Bus
IDE_D6 IDE Data Bus
IDE_D3 IDE Data Bus

IDE_D8 IDE Data Bus
IDE_D9 IDE Data Bus
IDE_D2 IDE Data Bus

IDE_D13 ID E Data Bus

GND Ground

IDE_D14 ID E Data Bus

ID E_IORDY IDE I/ O Ready

PCI _P ME# PCI Power Management Event
PCI_GNT2# PC I Bus Grant 2
PCI_REQ2# PCI Bus Re quest 2

PCI_REQ1# PCI Bus Re quest 1
PCI_GNT0# PC I Bus Grant 0

GND Ground

PCI_REQ0# PCI Bus Reqest 0

PCI_AD0 PCI Adre ss & Da t a Bus line
PCI_AD2 PCI Adre ss & Da t a Bus line
PCI_AD4 PCI Adre ss & Da t a Bus line

PCI_AD8 PCI Adre ss & Da t a Bus line
PCI_AD10 PCI Adress & Data Bus line
PCI_AD12 PCI Adress & Data Bus line

GND Ground

PCI_C/BE1# PCI Bus Command a nd Byte enables
PCI_PERR# PCI Bus Grant Erro r
P CI_LOCK# PCI Bus Lo ck

PCI_IRDY# PCI Bu s Bus Initiator Ready

PCI_C/BE2# PCI Bus Command a nd Byte enables

PCI_AD17 PCI Adress & Data Bus line
PCI_AD19 PCI Adress & Data Bus line

PCI_AD21 PCI Adress & Data Bus line
PCI_AD23 PCI Adress & Data Bus line

PCI_C/BE3# PCI Bus Command a nd Byte enables

PCI_AD27 PCI Adress & Data Bus line
PCI_AD29 PCI Adress & Data Bus line
PCI_AD31 PCI Adress & Data Bus line

PCI_IRQB# PCI Bus In terrupt Request B

GND Ground

PEG_RX0+ PCIe 0 Recieve + / SDVO TV clock +

PEG_RX0- PCIe 0 Recieve - / SDVO TV clock -

PEG_RX1+ PCIe 1 Recieve + / SDVO B Interrup t +

IDE Data Bus

IDE Data Bus

I/O read lin e to IDE device

PCI Bus Grant 1

PCI Bus Reset

PCI Adress & Data Bus line

PCI Adress & Data Bus line

PCI Bus De vice S elect

Ground

PCI Adress & Data Bus line

PCI Bus Interru

Module t

t Request A

e ID pin 0

IO ­IO ­IO ­IO ­IO ­IO ­IO ­IO ­IO -

PWR - -

IO -

I-3.3

O-3.3 -

IO-3.3 int. PU 20k in ICH8

O-3.3 int. PU 20k in ICH8

I-3.3

O-3.3 int. PU 20k in ICH8

I-3.3
O-3.3 int. PU 20k in ICH8
PWR -

I-3.3
O-3.3 - -

IO-3.3 ­IO-3.3 ­IO-3.3 ­IO-3.3 ­IO-3.3 ­IO-3.3 ­IO-3.3 -

PWR - -

IO-3.3 ­IO-3.3 - ­IO-3.3
IO-3.3
IO-3.3
IO-3.3
IO-3.3 ­IO-3.3 ­IO-3.3 -

PWR - -

IO-3.3 ­IO-3.3 ­IO-3.3 - ­IO-3.3 ­IO-3.3 ­IO-3.3 ­IO-3.3

I-3.3

I-3.3
PWR -

I - DP not supported
I - DP - not supported

I - DP - not supported

PU 4K7 3.3V

PU 8K2 3.3V

PU 8K2 3.3V

PU 8K2 3.3V

PU 8K2 3.3V
PU 8K2 3.3V
PU 8K2 3.3V
PU 8K2 3.3V

PU 8K2 3.3V
PU 8K2 3.3V

NC - -

Row C

-

-

-

-

-

-

-

-

-

-

Express-LPC User’s ManualPage 20

Signal Descriptions (cont’d)

p

p

_

Row C

Pin Signal Description Type PU/PD Comment

C56 PEG_RX1­C57
C58
C59
C60 GND
C61
C62
C63
C64
C65 PEG_RX4+
C66
C67
C68
C69 PEG_RX5­C70
C71
C72
C73 SDVO_D ATA
C74
C75
C76
C77
C78 PEG_RX8+
C79
C80
C81
C82 PEG_RX9­C83
C84
C85
C86
C87 GND
C88
C89
C90
C91 PEG_RX12+
C92
C93
C94
C95
C96 GND
C97
C98

C99
C100 GND
C101
C102
C103
C104 VCC_12V Power 12V PWR - ­C105
C106
C107
C108
C109 VCC_12V Power 12V PWR - ­C110

TYPE1# Module typ e ID pin 1

PEG_RX2+ PCIe 2 Recieve + / SDVO Field stall +

PEG_RX2- PCIe 2 Recieve - / SDVO Field stall -

PEG_RX3+ PCIe 3 Recieve +

PEG_RX3- PCIe 3 Recieve -

RSVD Rx from Board Controller
RSVD Tx from Board Control ler

PEG_RX4- PCIe 4 Recieve -

RSVD FAN_PWM_CTRL

PEG_RX5+ PCIe 5 Recieve + / SDVO C Interrupt +

GND Ground

PEG_RX6+ PCIe 6 Recieve +

PEG_RX6- PCIe 6 Recieve -

PEG_RX7+ PCIe 7 Recieve +

PEG_RX7- PCIe 7 Recieve -

GND Ground

RSVD FAN_TACH

PEG_RX8- PCIe 8 Recieve -

GND Ground

PEG_RX9+ PCIe 9 Recieve +

RSVD Physical Presence

GND Ground

PEG_RX10+ PCIe 10 Recieve +

PEG_RX10- PCIe 10 R ecieve -

PEG_RX11+ PCIe 11 Recieve +

PEG_RX11- PCIe 11 R ecieve –

GND Ground

PEG_RX12- PCIe 12 R ecieve -

GND Ground

PEG_RX13+ PCIe 13 Recieve +

PEG_RX13- PCIe 13 R ecieve -

RSVD NC NC

PEG_RX14+ PCIe 14 Recieve +

PEG_RX14- PCIe 14 R ecieve -

PEG_RX15+ PCIe 15 Recieve +

PEG_RX15- PCIe 15 R ecieve -

GND Ground

VCC_12V
VCC_12V
VCC_12V
VCC_12V

GND Ground

PCIe 1 Recieve - / SDVO B interru

Ground

PCIe 4 Recieve +

PCIe 5 Recieve - / SDVO C i nterru

CTRLDATA

SDVO

PCIe 8 Recieve +

PCIe 9 Recieve -

Ground

PCIe 12 Recieve +

Ground

Ground

Power 12V PWR - ­Power 12V PWR - ­Power 12V PWR - ­Power 12V PWR - -

t -

t -

I - DP - not supported

NC - ­I - DP - not supported
I - DP - not supported

PWR - ­I - DP - not supported
I - DP - not supported

I-3.3 - ­O-3.3 - ­I - DP - not supported
I - DP - not supported

0-5 - ­I - DP - not supported
I - DP - not supported

PWR - ­I - DP - not supported
I - DP - not supported
IO-2,5 - not supported
I - DP - not supported
I - DP - not supported

PWR - -

I-5 - ­I - DP - not supported
I - DP - not supported

PWR - ­I - DP - not supported
I - DP - not supported

I-3.3 - -

PWR - ­I - DP - not supported
I - DP - not supported

PWR - ­I - DP - not supported
I - DP - not supported

PWR - ­I - DP - not supported
I - DP - not supported

PWR - ­I - DP - not supported
I - DP - not supported

PWR - -

-­I - DP - not supported
I - DP - not supported

PWR - ­I - DP - not supported
I - DP - not supported

PWR - -

PWR - -

Page 21Express-IA533 User’s Manual Page 21Express-IA533 User’s ManualExpress-LPC User’s Manual Page 21

Signal Descriptions (cont’d)

Row D

Pin Signal Description Type PU/PD Comment

D1
D2
D3
D4
D5
D6
D7
D8

D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55

GND

IDE_D5
IDE_D10
IDE_D11
IDE_D12

IDE_D4

IDE_D0

IDE_REQ#
IDE_IOW#
IDE_ACK#

GND

IDE_IRQ

IDE_A0

IDE_A1

IDE_A2

IDE_CS1#
IDE_CS3#

IDE_RESET#

PCI_GNT3#
PCI_REQ3#

GND
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7

PCI_C/BE0#

PCI_AD9

PCI_AD11
PCI_AD13
PCI_AD15

GND
PCI_PAR

PCI_SERR#
PCI_STOP#
PCI_TRDY#

PCI_FRAME#

PCI_AD16
PCI_AD18
PCI_AD20
PCI_AD22

GND

PCI_AD24
PCI_AD26
PCI_AD28

PCI_AD30
PCI_IRQC#
PCI_IRQD#

PCI_CLKRUN#

PCI_M66EN#

PCI_CLK

GND

PEG_TX0+

PEG_TX0-

PEG_LANE_RV#

PEG_TX1+

Ground PWR - ­IDE Data Bus IO - ­IDE Data Bus IO - -
IDE Data Bus IO - ­IDE Data Bus
IDE Data Bus IO - ­IDE Data Bus IO - ­IDE Device DMA Request. IO - int. PD 11.5k in ICH8
IDE IO Write O-3.3 - ­IDE DMA Acknowledge O-3.3 - ­Ground PWR - ­IDE Interrupt Request I-3.3 PU 8K2 3.3V ­IDE Adress Bu s O-3.3 - ­IDE Adress Bu s
IDE Adress Bu s O-3.3 - ­IDE Chip Select for 1F0h to 1FFh range O-3.3 - ­IDE Chip Select for 3F0h to 3FFh range O-3.3 - ­IDE Reset O u tput to Device
PCI Bus Grant 3 O-3.3 - int. PU 20k in ICH8
PCI Bus Reqe st 3 I-3.3 PU 8K2 3.3V ­Ground PWR - ­PCI Adress & Data Bus line IO-3.3 ­PCI Adress & Data Bus line IO-3.3 ­PCI Adress & Data Bus line IO-3.3 ­PCI Adress & Data Bus line IO-3.3 ­PCI Bus Command and Byte enables 0 IO-3.3 - ­PCI Adress & Data Bus line
PCI Adress & Data Bus line IO-3.3 ­PCI Adress & Data Bus line IO-3.3 ­PCI Adress & Data Bus line IO-3.3 ­Ground PWR - ­PCI Bus Parity IO-3.3 - ­PCI Bus System Error IO-3.3 PU 8K2 3.3V ­PCI Bus Stop IO-3.3 PU 8K2 3.3V ­PCI Bus Ta rget Ready IO-3.3 PU 8K2 3.3V ­PCI Bus Cyc le Frame
PCI Adress & Data Bus line IO-3.3 ­PCI Adress & Data Bus line IO-3.3 ­PCI Adress & Data Bus line IO-3.3 ­PCI Adress & Data Bus line IO-3.3 ­Ground PWR - ­PCI Adress & Data Bus line IO-3.3 ­PCI Adress & Data Bus line IO-3.3 ­PCI Adress & Data Bus line IO-3.3 ­PCI Adress & Data Bus line
PCI Bus Interrupt Request C I-3.3 PU 8K2 3.3V ­PCI Bus Interrupt Request D I-3.3 PU 8K2 3.3V ­PCI Clock Run I-3.3 PU 8K2 3.3V ­Control PCI Speed 33/66 Mhz
PCI Clock O-3.3 - ­Ground PWR - ­PCIe 0 Trans mit + / SDVO B [RED] + O - DP - not supported
PCIe 0 Trans mit - / SDVO B [RED] - O - DP - not supported
PCIe Lane Re v ersal I-3.3 - ­PCIe 1 Trans mit + / SDVO B [G RN] + O - DP - not supported

IO - -

O-3.3 - -

O-3.3 - -

IO-3.3 -

IO-3.3

IO-3.3 -

I-3.3 - Fixed to 33 Mhz

PU 8K2 3.3V

-

Express-LPC User’s ManualPage 22

Signal Descriptions (cont’d)

Row D

Pin Signal Description Type PU/PD Comment

D56
D57
D58
D59
D60
D61
D62
D63
D64
D65
D66
D67
D68
D69
D70
D71
D72
D73
D74
D75
D76
D77
D78
D79
D80
D81
D82
D83
D84
D85
D86
D87
D88
D89
D90
D91
D92
D93
D94
D95
D96
D97
D98

D99
D100
D101
D102
D103
D104
D105
D106
D107
D108
D109
D110

PEG_TX1-

TYPE2#

PEG_TX2+

PEG_TX2-

GND

PEG_TX3+

PEG_TX3-

RSVD
RSVD

PEG_TX4+

PEG_TX4-

GND

PEG_TX5+

PEG_TX5-

GND

PEG_TX6+

PEG_TX6­SDVO_CLK
PEG_TX7+

PEG_TX7-

GND

IDE_CBLID#

PEG_TX8+

PEG_TX8-

GND

PEG_TX9+

PEG_TX9-

RSVD

GND

PEG_TX10+

PEG_TX10-

GND

PEG_TX11+

PEG_TX11-

GND

PEG_TX12+

PEG_TX12-

GND

PEG_TX13+

PEG_TX13-

GND

PEG_ENABLE#

PEG_TX14+

PEG_TX14-

GND

PEG_TX15+

PEG_TX15-

GND
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V

GND

PCIe 1 Trans mit - / SDVO B [GRN] - O - DP - not s u pported
Module type ID pin 2 STO - not conn ected
PCIe 2 Trans mit + / SDVO B [BLU ] + O - DP - not supported
PCIe 2 Trans mit - / SDVO B [BLU] - O - DP - not supp orted
Ground PWR - ­PCIe 3 Trans mit + / SDVO B Cloc k + O - DP - not supported
PCIe 3 Trans mit - / SDVO B Clock - O - DP - not supported

NC - -

NC - ­PCIe 4 Trans mit + / SDVO C [RED] + O - DP - not supported
PCIe 4 Trans mit - / SDVO C [R ED] - O - DP - not supported
Ground PWR - ­PCIe 5 Trans mit + / SDVO C [GRN] + O - DP - not supported
PCIe 5 Transmit - / SDVO C [GRN] ­Ground PWR - ­PCIe 6 Trans mit + / SDVO C [BLU] + O - DP - not supp orted
PCIe 6 Trans mit - / SDVO C [BLU] - O - DP - not supported
SDVO_CTRLCLK
PCIe 7 Trans mit + / SDVO C Clock + O - DP - not supported
PCIe 7 Trans mit - / SDVO C C lock - O - DP - not supp orted
Ground PWR - ­IDE Cable Indicator Signal I-3.3 PD 10k ­PCIe 8 Transmit + O - DP - not supported
PCIe 8 Transmit - O - DP - not supported
Ground PWR - ­PCIe 9 Transmit + O - DP - not supported
PCIe 9 Transmit -

Ground PWR - ­PCIe 10 Tran smit + O - DP - not supp orted
PCIe 10 Tran smit - O - DP - not supported
Ground PWR - ­PCIe 11 Tran smit + O - DP - not supp orted
PCIe 11 Tran smit - O - DP - not supported
Ground PWR - ­PCIe 12 Tran smit +
PCIe 12 Tran smit - O - DP - not supported
Ground PWR - ­PCIe 13 Tran smit + O - DP - not supported
PCIe 13 Tran smit - O - DP - not supported
Ground PWR - ­PCIe Enable I-3.3 NC
PCIe 14 Tran smit + O - DP - not supported
PCIe 14 Tran smit - O - DP - not supported
Ground PWR - ­PCIe 15 Tran smit + O - DP - not supported
PCIe 15 Tran smit - O - DP - not supported
Ground PWR - ­Power 12V PWR - ­Power 12V PWR - ­Power 12V PWR - ­Power 12V PWR - ­Power 12V PWR - ­Power 12V PWR - ­Ground PWR - -

O - DP - not supp orted

IO-2,5 - -

O - DP - not supp orted

NC - -

O - DP - not supp orted

Page 23Express-IA533 User’s Manual Page 23Express-IA533 User’s ManualExpress-LPC User’s Manual Page 23

Signal Descriptions (cont’d)

Signal Type Legend

IO-2,5 Bi-directional 2,5 V Input/Output
IO-3,3 Bi-directional 3,3 V Input/Output

IO-5 Bi-directional 5 V Input/Output
I-3,3 3,3 V Input

I-5 5 V Input
O-2,5 2,5 V Output
O-3,3 3,3 V Output

O-5 5 V Output

IO Input/Output

OA Analog Output

OD Open Drain
IO-DP Differential Pai r Inp ut/Output
O -DP Differential Pair Output

I -D P Differential Pair Input
PWR Power or Ground

STO Strapping Output

PU Pull Up Resist or
PD Pull Down Resistor

NC Not Connected / Reserved

Express-LPC User’s ManualPage 24

6 Embedded Functions

All embedded board functions on ADLINK’s Computer on Modules are supported at the
operating system level using the ADLINK Intelligent Device Interface (AIDI) library. The AIDI API
programming interface is compatible and identical across all ADLINK Computer on Modules and
all supported operating systems. The AIDI library includes a demo program to demonstrate the
library’s functionallity.

6.1 Watchdog Timer

The Express-LPC implements a Watchdog timer that can be used to
automatically detect software execution problems or system hangs and
reset the board if necessary. The Watchdog timer consists of a counter
that counts down from an initial value to zero. When the system is
operating normally, the software that sets the intial value periodically
resets the counter so that the it never reaches zero. If the counter
reaches zero before the software resets it, the system is presumed to be
malfunctioning and a reset signal is asserted.

The AIDI Library Watchdog functions support Watchdog control of the board. If the Watchdog
begins countdown and reaches zero, it will access the CPU's RESET signal to reset the system.
This application must call another function named AidiWDogTrigger that triggers the Watchdog to
restart to prevent system reset.

AIDI Demo Program

- Watchdog Tab

The AIDI Demo Program allows
retrieval of the current Watchdog
status and updating of the
Watchdog settings

If the Watchdog is enabled, the

user can click the WDT Trigger

button to manually reset the
counter and prevent the system
from resetting

Page 25Express-IA533 User’s Manual Page 25Express-IA533 User’s ManualExpress-LPC User’s Manual Page 25

6.2 GPIO

GPIO library support is limited to GPIO signals that originate from the Computer on Module
and extended to the carrier board. COM Express modules support 4 GPO and 4 GPI signals.
Some of ADLINK’s COM Express boards can configure all 8 ports for GPI or GPO use.

GPIO signals can be monitored and controlled by using the ADLINK Intelligent Device
Interface (AIDI) library that is compatible and identical across all ADLINK COM Express
modules and all supported operating systems.

The COM Express type II standard assigns the following pins for either GPI or GPO

Pin Signal Type # AIDI ID (bit) Remark

A54 GPI0 0 Express-LPC can configure this pin for GPI and GPO
A63 GPI1 1 Express-LPC can configure this pin for GPI and GPO
A67 GPI2 2 Express-LPC can configure this pin for GPI andGPO
A85 GPI3 3 Express-LPC can configure this pin for GPI andGPO
A93 GPO0 4 Express-LPC can configure this pin for GPI and GPO
B54 GPO1 5 Express-LPC can configure this pin for GPI and GPO
B57 GPO2 6 Express-LPC can configure this pin for GPI and GPO
B63 GPO3 7 Express-LPC can configure this pin for GPI and GPO

AIDI Demo Program

- GPIO Tab

The AIDI Demo Program displays
current GPI or GPO status and
allows reading of GPI and writing
to GPO.

The table above links logical port
numbers in AIDI to physical port
numbers on the COM Express
board-to-board connector.

For boards that support multi-
direction the “SetDirection” button

can configure the port for either
GPI or GPO

Express-LPC User’s ManualPage 26