Express-LPC
User’s Manual
Manual Revision: 2.01
Revision Date: January 4, 2012
Part Number: 50-1J034-1010
Revision History
Release Date Change
2.00 April 15, 2011 Initial release
2.01 January 4, 2012 Remove Atom Processor N570 support; update N455 memory support;
add SMBus address info to System Resources
Express-LPC User’s ManualPage 2
Table of Contents
Preface ............................................................................................................................5
1 Introduction...............................................................................................................7
1.1 Description ...........................................................................................................................7
2 Specifications............................................................................................................8
2.1 General................................................................................................................................. 8
2.2 Integrated Video ................................................................................................................... 8
2.3 Audio .................................................................................................................................... 9
2.4 LAN ....................................................................................................................................... 9
2.5 Multi I/O ................................................................................................................................9
2.6 TPM (Trusted Platform Module) .......................................................................................... 9
2.7 Super I/O .............................................................................................................................. 9
2.8 Power Specifications .........................................................................................................10
3 Functional Diagram................................................................................................. 11
4 Mechanical Dimensions..........................................................................................12
5 Pinout and Signal Descriptions..............................................................................13
5.1 COM Express™ Type 2 compatible pinout ....................................................................... 13
5.2 Carrier Board Design Guide ..............................................................................................13
5.3 Pin Definitions .................................................................................................................... 14
5.4 Signal Descriptions ............................................................................................................ 16
6 Embedded Functions..............................................................................................25
6.1 Watchdog Timer ................................................................................................................. 25
6.2 GPIO ................................................................................................................................... 26
6.3 Hardware Monitoring ......................................................................................................... 27
7 System Resources..................................................................................................28
7.1 System Memory Map .........................................................................................................28
7.2 Direct Memory Access Channels ......................................................................................28
7.3 Legacy I/O Map.................................................................................................................. 29
Page 3Express-IA533 User’s Manual Page 3Express-IA533 User’s ManualExpress-LPC User’s Manual Page 3
7.4 Interrupt Request (IRQ) Lines ........................................................................................... 30
7.5 PCI Configuration Space Map ...........................................................................................32
7.6 PCI Interrupt Routing Map ................................................................................................32
7.7 SMBus Slave Device Address ...........................................................................................32
8 BIOS Setup Utility....................................................................................................33
8.1 Starting the BIOS................................................................................................................33
8.2 Main Setup .........................................................................................................................37
8.3 Advanced BIOS Setup .......................................................................................................38
8.4 Power Management ..........................................................................................................58
8.5 Boot Setup..........................................................................................................................64
8.6 Security Setup ....................................................................................................................68
8.7 Exit Menu ...........................................................................................................................71
9 BIOS Checkpoints, Beep Codes.............................................................................73
9.1 Bootblock Initialization Code Checkpoints........................................................................74
9.2 Bootblock Recovery Code Checkpoints ...........................................................................75
9.3 POST Code Checkpoints ................................................................................................... 76
9.4 OEM POST Error Checkpoints ..........................................................................................78
9.5 DIM Code Checkpoints ......................................................................................................78
9.6 ACPI Runtime Checkpoints................................................................................................79
9.7 Boot Block Beep Codes .....................................................................................................80
9.8 POST BIOS Beep Codes....................................................................................................80
9.9 Troubleshooting POST BIOS Beep Codes........................................................................81
Important Safety Instructions......................................................................................82
Getting Service .............................................................................................................84
Express-LPC User’s ManualPage 4
Preface
Copyright 2011 ADLINK Technology, Inc.
This document contains proprietary information protected by copyright. All rights are
reserved. No part of this manual may be reproduced by any mechanical, electronic, or other
means in any form without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior notice in order to improve
reliability, design, and function and does not represent a commitment on the part of the
manufacturer.
In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential
damages arising out of the use or inability to use the product or documentation, even if advised
of the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global environmental preservation
through compliance with the European Union's Restriction of Hazardous Substances (RoHS)
directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental
protection is a top priority for ADLINK. We have enforced measures to ensure that our products,
manufacturing processes, components, and raw materials have as little impact on the
environment as possible. When products are at their end of life, our customers are encouraged to
dispose of them in accordance with the product disposal and/or recovery programs prescribed by
their nation or company.
Trademarks
AMIBIOS®8 is a registered trademark of American Megatrends, Inc. COM Express™, and
PICMG® are registered trademarks of the PCI Industrial Computer Manufacturers Group.
Product names mentioned herein are used for identification purposes only and may be
trademarks and/or registered trademarks of their respective companies.
Page 5Express-IA533 User’s Manual Page 5Express-IA533 User’s ManualExpress-LPC User’s Manual Page 5
Conventions
Take note of the following conventions used throughout this manual to make sure that users
perform certain tasks and instructions properly.
Additional information, aids, and tips that help users perform tasks.
Information to prevent minor physical injury, component damage, data loss,
and/or program corruption when trying to complete a task.
Information to prevent serious physical injury, component damage, data
loss, and/or program corruption when trying to complete a specific task.
Express-LPC User’s ManualPage 6
1 Introduction
1.1 Description
The Express-LPC is a low power, low cost, COM Express Type 2, COM.0 R2.0 module in
Compact form factor that is specially designed to facilitate speedy development of semi
custom designs.
The COM Express standard embodies the convergence of the latest technology standards
based on serial differential signaling such as PCI Express, USB 2.0, SATA and LVDS
implemented on a compact size Computer on Module. Signals are brought out through two
220-pin board-to-board connectors that permit data transmission rates of up to 5GHz.
Mounting holes connect the module with a custom-made, application specific carrier boards
which provide protection from shock and vibration.
The Express-LPC is a COM Express COM.0 R2.0 Type 2 compatible module in
Compact form factor (95 mm x 95 mm). The module supports a 45nm process
Intel® Atom™ processor N455 and D425 with 512 KB L2 cache, and D525 with
1MB L2 cache. The Intel® Atom™ processor integrates a graphics processing
unit (GPU) that provides CRT and single channel LVDS. The Intel® Atom™ processor N455/
D425/D525 also supports Hyper-Threading Technology with 2-threads per core allowing the
Express-LPC to provide excellent performance for multi-tasking applications.
The Express-LPC is positioned as an entry level COM Express module for systems that
require a small footprint with dual core computing power and DDR3 memory. It is ideal for
applications that require Floating Point CPU performance with average graphics support and
moderate power consumption levels, such as Robotics, Industrial control and Data
Communications.
The Intel® I/O Controller Hub 8-M (ICH8-M) allows connection of up to five additional PCI
Express x1 ports, four of which can be grouped to a PCIe x4, while supporting the LAN
controller on the 5th port. The module comes with a single onboard Gigabit Ethernet port and
three SATA ports. It has legacy support for a single parallel IDE channel, 32-bit PCI and LPC.
The Express-LPC comes equipped with AMIBIOS®8 supporting embedded features such as:
Remote Console, CMOS backup in 16Mbit SPI BIOS, CPU and System Monitoring and a Dual
Watchdog Timer for NMI or RESET.
The Express-LPC is a RoHS compliant and leadfree product.
Page 7Express-IA533 User’s Manual Page 7Express-IA533 User’s ManualExpress-LPC User’s Manual Page 7
2 Specifications
2.1 General
f CPU: Atom™ N455: single core 1.66 GHz with 512 kB L2 cache, 6.5 W
Atom™ D425: single core 1.80 GHz with 512 kB L2 cache, 10 W
Atom™ D525: dual core 1.80 GHz with 1 MB L2 cache, 13 W
On-die primary 32-kB instructions cache and 24-kB write-back data cache
- Intel® Hyper-Threading Technology 2-threads per core
- Support for IA 32-bit
- Intel® Streaming SIMD Extensions 2 and 3 (SSE2 and SSE3) and
Supplemental Streaming SIMD Extensions 3 (SSSE3) support
- Intel® 64 architecture
- Micro-FCBGA8 packaging technologies
- Thermal management support via Intel® Thermal Monitor (TM1)
- Supports C0 and C1 states only
- Execute Disable Bit support for enhanced security
f Memory: Dual SODIMM socket for max. 4 GB of non-ECC, 677/800 MHz DDR3
(Atom™ N455 max. 2 GB)
f Chipset: Intel® I/O Controller Hub 8 Mobile (ICH8-M)
f BIOS: AMIBIOS®8 with CMOS backup in 16 Mbit SPI BIOS
f Hardware Monitor: Supply Voltages and CPU temperature
f Watchdog Timer: Programmable timer ranges to generate RESET
f Expansion Busses:
- 5x free PCI Express x1 (6th occupied by GbE LAN)
- PCIe x1 ports 0~3 can be optionally configured as 1 x4
- 32-bit PCI 2.3 at 33MHz, supporting 4 bus masters
- LPC
- SMBus, I2C
2.2 Integrated Video
f GPU: Integrated in CPU with Gen3.5+ GFX Core, core frequency at 200 MHz (N455) and
400 MHz (D425/D525)
f CRT Interface: Analog CRT support up to 2048 x1536 resolution @ 60Hz (QXGA)
f LVDS Interface: Single channel 18-bit TFT with resolution up to 1366x768, 18bpp
Express-LPC User’s ManualPage 8
2.3 Audio
f Chipset: Integrated in Intel® I/O Controller Hub 8 Mobile (ICH8M)
f Audio Codec: HDA type on carrier
2.4 LAN
f Chipset: Intel® 82583V Gigabit Ethernet Controller
f Interface: 10/100/1000 Mbps
2.5 Multi I/O
f IDE (PATA): Single channel IDE with UDMA 100 support
f SATA: Three ports SATA 1.5 Gb/s
f USB: Supports up to eight ports USB 2.0
2.6 TPM (Trusted Platform Module)
f Chipset: Infineon SLB9635TT1.2
f Type: TPM 1.2
2.7 Super I/O
f Connected to LPC bus on carrier if needed.
Page 9Express-IA533 User’s Manual Page 9Express-IA533 User’s ManualExpress-LPC User’s Manual Page 9
2.8 Power Specifications
f Input Power: AT mode (12 V) and ATX mode (12 V and 5 V
)
SB
f Power Management: ACPI 3.0 compliant with battery support.
All power testing was done on power supply wiring leading to the Express carrier
board. Although all voltages were measured, only 12 V and 5 VSB are relevant
because they are the only ones used by the Express module. The Idle power level was
measured under Windows XP with no applications running (logon screen). CPU Stress
was measured using Kpower, and Total System Stress was measured under burn-in
conditions.
Intel® Atom™ N455, 1.66 GHz
Power State +12V +5V
DOS (idle) 0.55 A N.S. 6.60 W
Windows XP logon screen (idle) 0.55 A N.S. 6.60 W
Windows XP CPU Stress (Kpower) 0.99 A N.S. 11.9 W
Windows XP Total System Stress (BurnIn) 1.02 A N.S. 12.2 W
S4 Mode (hibernate) - 0.14 A 0.70 W
S3 Mode (suspend to RAM) - 0.20 A 1.00 W
SB
Power Consumption
Intel® Atom™ D425, 1.80 GHz
Power State +12V +5V
DOS (idle) 1.08 A N.S. 13.0 W
Windows XP logon screen (idle) 1.08 A N.S. 13.0 W
Windows XP CPU Stress (Kpower) 1.17 A N.S. 14.0 W
Windows XP Total System Stress (BurnIn) 1.19 A N.S. 14.3 W
S4 Mode (hibernate) - 0.15 A 0.75 W
S3 Mode (suspend to RAM) - 0.20 A 1.00 W
SB
Power Consumption
Intel® Atom™ D525, 1.80 GHz
Power State +12V +5V
DOS (idle) 0.95 A N.S. 11.4 W
Windows XP logon screen (idle) 0.95 A N.S. 11.4 W
Windows XP CPU Stress (Kpower) 1.17 A N.S. 14.0 W
Windows XP Total System Stress (BurnIn) 1.24 A N.S. 14.9 W
S4 Mode (hibernate) - 0.16 A 0.80 W
S3 Mode (suspend to RAM) - 0.19 A 0.95 W
SB
Power Consumption
CMOS Battery Power Consumption
Current (+3V) Power
4.1 μA 0.000014 W
Express-LPC User’s ManualPage 10
3 Functional Diagram
AB
CRT
18-bit LVD S
5x PCIe x1
(port 0~4)
GbE LAN
82583V
HDA Audio
3x SATA (port 0~2)
PCIe x1
(port 5)
Atom
N455
N570
D425
D525
ICH8M
SODIMM 1
512MB ~ 2GB DDR3
SODIMM 2
512MB ~ 2GB DDR3
XDP
SFF-26
PCI Bus
PATA IDE
CD
4x GPI
4x GP0
8x USB
LPC bus
SMBus
GPIO
PCA9535
I2C
SPI
BC
SPI
SPI BIOS
Page 11Express-IA533 User’s Manual Page 11Express-IA533 User’s ManualExpress-LPC User’s Manual Page 11
4 Mechanical Dimensions
Express-LPC User’s ManualPage 12
5 Pinout and Signal Descriptions
5.1 COM Express™ Type 2 compatible pinout
All pinouts on AB and CD connector of the Express-LPC
comply with pin-out and signal descriptions used in the
®
“PICMG
Specification”.
COM.0 R2.0: COM Express™ Module Base
Parallel ATA, IDE port
alternate definition assigns this to
2 additional Gigabit Ethernet ports
32-bit PCI v2.3 bus
alternate definition assigns this to
10 additional PCI Express x1 lanes
PCI Express x16 for Graphics
these pins can also be assigned to
two SDVO extensions (multiplexed)
SMB and I2C bus
Power / Thermal control
+12V primary power input
95mm.
125mm.
95mm.
CD Connector
The above function mappings are a generic description of COM Express pinouts, and not
necessarily supported on the module described in this manual.
5.2 Carrier Board Design Guide
- Gigabit Ethernet port
- LPC interface
- 4 Serial ATA channels
- High Definition Audio
- 8 USB 2.0 ports
- 6 PCI Express Lanes x1
- Dual 24-bit LVDS channels
- Analog VGA
- 8 GPIO pins
- Keyboard
- primary power input +12V
+5V standby and 3.3V RTC
AB Connector
CD
AB
The PICMG COM Express Carrier Design Guide is a
150-page document that provides information for
designing a custom carrier board for COM Express
modules. The design guide includes reference
schematics for the external circuitry required to
implement the various COM Express peripheral
functions, explains how to extend the supported buses,
and how to add additional peripherals and expansion
slots to a COM Express-based system
Page 13Express-IA533 User’s Manual Page 13Express-IA533 User’s ManualExpress-LPC User’s Manual Page 13
5.3 Pin Definitions
D1
Pinouts for
COM.0 R2.0 Type 2
Pin No. Pin Name Pin N o. Pin Name Pin No. Pin Name Pin No . Pin Name
A1 GND (FIXED) B1 GND (FIXED) C1 GND FIXED) D1 GND FIXED)
A2 GBE0_MDI3- B2 GBE0_ACT# C2 IDE_D7 D2 IDE_D5
A3 GBE0_MDI3+ B3 LPC_FRAME# C3 IDE_D6 D3 IDE_D10
A4 GBE0_LINK100# B4 LPC_AD0 C4 IDE_D3 D4 IDE_D11
A5 GBE0_LINK1000# B5 LPC_AD1 C5 IDE_D15 D5 IDE_D12
A6 GBE0_MDI2- B6 LPC_AD2 C6 IDE_D8 D6 IDE_D4
A7 GBE0_MDI2+ B7 LPC_AD3 C7 IDE_D9 D7 IDE_D0
A8 GBE0_LINK# B8 LPC_DRQ 0# C8 IDE_D2 D8 IDE_REQ
A9 GBE0_MDI1- B9 LPC_DRQ1# C9 IDE_D13 D9 IDE_IOW#
A10 GBE0_MDI1+ B10 LPC_CLK C10 IDE_D1 D10 IDE_ACK#
A11 GND (FIXED) B11 GND (FIXED) C11 GND (FIXED) D11 GND (FIXED)
A12 GBE0_MDI0- B12 PWRBTN# C12 IDE_D14 D12 IDE_IRQ
A13 GBE0_MDI0+ B13 SMB_CK C13 IDE_IORDY D13 IDE_A0
A14 GBE0_CTREF
A15 SUS_S3# B15 SMB_ALERT# C15 PCI_PME# D15 IDE_A2
A16 SATA0_TX+ B16 SATA1_TX+ C16 PCI_GNT2# D16 IDE_CS1#
A17 SATA0_TX- B17 SATA1_TX- C17 PCI_REQ2# D17 IDE_CS3#
A18 SUS_S4# B18 SUS_STAT# C18 PCI_GNT1# D18 IDE_RESET#
A19 SATA0_RX+ B19 SATA1_RX+ C19 PCI_REQ1# D19 PCI_GNT3#
A20 SATA0_RX- B20 SATA1_RX- C20 PCI_GNT0# D20 PCI_REQ3#
A21 GND (FIXED) B21 GND (FIXED) C21 GND (FIXED) D21 GND (FIXED)
A22 SATA2_TX+ B22 SATA3_TX+
A23 SATA2_TX- B23 SATA3_TXA24 SUS_S5# B24 PWR_OK C24 PCI_AD0 D24 PCI_AD5
A25 SATA2_RX+ B25 SATA3_RX+
A26 SATA2_RX- B26 SATA3_RXA27 BATLOW# B27 WDT C27 PCI_AD6 D27 PCI_AD9
A28 ATA_ACT# B28 AC_SDIN2 C28 PCI_AD8 D28 PCI_AD11
A29 AC_SYNC B29 AC_SDIN1 C29 PCI_AD10 D29 PCI_AD13
A30 AC_RS T# B30 AC_SDIN0 C30 PCI_AD12 D30 PCI_AD15
A31 GND (FIXED) B31 GND (FIXED) C31 GND (FIXED) D31 GND (FIXED)
A32 AC_BITCLK B32 SPKR C32 PCI_AD14 D32 PCI_PAR
A33 AC_SDOUT B33 I2C_CK C33 PCI_C/BE1# D33 PCI_SERR#
A34 BIOS_DISABLE# B34 I2C_DAT C34 PCI_PERR# D34 PCI_STOP#
A35 THRMTRIP#
A36 USB6- B36 USB7- C36 PCI_DEVSEL# D36 PCI_FRAME#
A37 USB6+ B37 USB7+ C37 PCI_IRDY# D37 PCI_AD16
A38 USB_6_7_OC# B38 USB_4_5_OC# C38 PCI_C/BE2# D38 PCI_AD18
A39 USB4- B39 USB5- C39 PCI_AD17 D39 PCI_AD20
A40 USB4+ B40 USB5+ C40 PCI_AD19 D40 PCI_AD22
A41 GND (FIXED) B41 GND (FIXED) C41 GND (FIXED) D41 GND (FIXED)
A42 USB2- B42 USB3- C42 PCI_AD21 D42 PCI_AD24
A43 USB2+ B43 USB3+ C43 PCI_AD23 D43 PCI_AD26
A44 USB_2_3_OC# B44 USB_0_1_OC# C44 PCI_C/BE3# D44 PCI_AD28
A45 USB0- B45 USB1- C45 PCI_AD25 D45 PCI_AD30
A46 USB0+ B46 USB1+ C46 PCI_AD27 D46 PCI_IRQC#
A47 VCC_RTC B47 EXCD1_PERSET C47 PCI_AD29 D47 PCI_IRQ D#
A48 EXCD0_PERST# B48 EXCD1_CPPE C48 PCI_AD31 D48 PCI_CLKRUN#
A49 EXCD0_CPPE# B49 SYS_RESET# C49 PCI_IRQA# D49 PCI_M66EN
A50 LPC_SERIRQ B50 CB_RESET# C50 PCI_IRQB# D50 PCI_CLK
B14 SMB_DAT C14 IDE_IOR# D14 IDE_A1
B35 THRM# C35 PCI_LOCK# D35 PCI_TRDY#
C1
B1
A1
C22 PCI_REQ0# D22 PCI_AD1
C23 PCI_RESET# D23 PCI_AD3
C25 PCI_AD2 D25 PCI_AD7
C26 PCI_AD4 D26 PCI_C/BE0#
D110
C110
B110
A110
C D
A B
Express-LPC User’s ManualPage 14
Pin Definitions (cont’d)
Pin No. Pin Name Pin N o. Pin Name Pin No. Pin Name Pin No . Pin Name
A50 LPC_SERIRQ B50 CB_RESET# C50 PCI_IRQB# D50 PCI_CLK
A51 GND (FIXED) B51 GND (FIXED) C51 GND (F IXED) D51 GND (FIXED)
A52 PCIE_TX5+
A53 PCIE_TX5-
A54 GPI0 B54 GPO1 C54 TYPE0# D54 PEG_LANE_RV#
A55 PCI E_TX4+ B55 PCIE_RX4+ C55 PEG_RX1+ D55 SDVO B [GRN]+
A56 PCI E_TX4- B56 PCIE_RX4- C56 PEG_RX1- D56 SDVO B [GRN]-
A57 GND B57 GPO2 C57 TYPE1# D57 TYPE2#
A58 PCI E_TX3+ B58 PCIE_RX3+ C58 PEG_RX2+ D58 SDVO B [BLU]+
A59 PCI E_TX3- B59 PCIE_RX3 - C59 PEG_RX2- D59 SDVO B [BLU]-
A60 GND (FIXED) B60 GND (FIXED) C60 GND (F IXED) D60 GND (FIXED)
A61 PCIE_TX2+ B61 PCIE_RX2+ C61 PEG_RX3+
A62 PCIE_TX2- B62 PCIE_RX2- C62 PEG_RX3- D62 SDVO B Clock-
A63 GPI1 B63 GPO3 C63 RSVD D63 RSVD
A64 PCIE_TX1+ B64 PCIE_RX1+ C64 RSVD D64 RSVD
A65 PCIE_TX1- B65 PCIE_RX1- C65 PEG_RX4+
A66 GND B66 WAKE0# C66 PEG_RX4- D66 SDVO C [RED]-
A67 GPI2 B67 WAKE1# C67 RS VD (1 ) D 67 GND
A68 PCIE_TX0+ B68 PCIE_RX0+ C68 PEG_RX5+
A69 PCIE_TX0- B69 PCIE_RX0- C69 PEG_RX5- D69 SDVO C [GRN]-
A70 GND (FIXED) B70 GND (FIXED) C70 GND (F IXED) D70 GND (FIXED)
A71 LVDS_A0+ B71 LVDS_B0+
A72 LVDS_A0- B72 LVDS_B0- C72 PEG_RX6- D72 SDVO C [BLU]-
A73 LVDS_A1+ B73 LVDS_B1+ C73 SDVO_DATA D73 SDVO_CLK
A74 LVDS_A1- B74 LVDS_B1- C74 PEG_RX7+ D74 SDVO C Clock+
A75 LVDS_A2+ B75 LVDS_B2+ C75 PEG_RX7- D75 SDVO C Clock-
A76 LVDS_A2- B76 LVDS_B2- C76 GND D76 GND
A77 LVDS_VDD_EN B77 LVDS_B3+
A78 LVDS_A3+ B78 LVDS_B3- C78 PEG_RX8+ D78 PEG_TX8+
A79 LVDS_A3- B79 LVDS_BKLT_EN C79 PEG_RX8- D79 PEG_TX8-
A80 GND (FIXED) B80 GND (FIXED) C80 GND (F IXED) D80 GND (FIXED)
A81 LVDS_A_CK+ B81 LVDS_B_CK+
A82 LVDS_A_CK- B82 LVDS_B_CK- C82 PEG_RX9- D82 PEG_TX9-
A83 LVDS_I2C_CK B83 LVDS_BKLT_CT RL C83 RSVD D83 RSVD
A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84 GND D84 GND
A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10+
A86 KBD_RST# B86 VCC_5V_SBY C86 PEG_RX10- D86 PEG_TX10-
A87 KBD_A20GATE B87 VCC_5V_SBY C87 GND D87 GND
A88 PCIE0_CK_REF+ B88 BIOS_DIS1# C88 PEG_RX11+
A89 PCIE0_CK_REF- B89 VGA_RED C89 PEG_RX11- D89 PEG_TX11-
A90 GND (FIXED) B90 GND (FIXED) C90 GND (F IXED) D90 GND (FIXED)
A91 SPI_POWER B91 VGA_GRN C91 PEG_RX12+
A92 SPI_MISO B92 VGA_BLU C92 PEG_RX12- D92 PEG_TX12-
A93 GPO0 B93 VGA_HSYNC C93 GND D93 GND
A94 SPI_CLK B94 VGA_VSYNC C94 PEG_RX13+
A95 SPI_MISO B95 VGA_I2C_CK C95 PEG_RX13- D95 PEG_TX13-
A96 GND B96 VGA_I2C_DAT C96 GND D96 GND
A97 TYPE10#
A98 RSVD B98 RSVD C98 PEG_RX14+ D98 PEG_TX14+
A99 RSVD B99 RSVD C99 PEG_RX14- D99 PEG_TX14-
A100 GN D (FIXE D) B100 GND (FIXED) C100 GND (FIXED) D100 GND (FIXED)
A101 RSVD B101 RSVD C101 PEG_RX15+
A102
RSVD
A103 RSVD B103 RSVD C103 GND D103 GND
A104 VCC_12V B104 VCC_12V C104 VCC _12V D104 VCC_12V
A105 VCC_12V B105 VCC_12V C105 VCC _12V D105 VCC_12V
A106 VCC_12V B106 VCC_12V C106 VCC _12V D106 VCC_12V
A107 VCC_12V B107 VCC_12V C107 VCC _12V D107 VCC_12V
A108 VCC_12V B108 VCC_12V C108 VCC _12V D108 VCC_12V
A109 VCC_12V B109 VCC_12V C109 VCC _12V D109 VCC_12V
A110 GN D (FIXE D) B110 GND (FIXED) C110 GND (FIXED) D110 GND (FIXED)
(1)
(1)
B52 PCIE_RX5+
B53 PCIE_RX5-
B97 SPI_CS# C97 RSVD D97 PEG_ENABLE#
B102 RSVD C102 PEG_RX15- D102 PEG_TX15-
(1)
(1)
C52 PEG_RX0+ D52 SDVO B [RED]+
C53 PEG_RX0- D53 SDVO B [RED]-
D61 SDVO B Clock+
D65 SDVO C [RED]+
D68 SDVO C [GRN]+
C71 PEG_RX6+ D71 SDVO C [BLU]+
C77 RSVD D77 IDE_CBLID#
C81 PEG_RX9+ D81 PEG_TX9+
D85 PEG_TX10+
D88 PEG_TX11+
D91 PEG_TX12+
D94 PEG_TX13+
D101 PEG_TX15+
XXX Strikethrough pins are not supported on this module.
(1) The 6th PCI Express x1 port (PCIE5) is occupied by the onboard LAN controller. .
Page 15Express-IA533 User’s Manual Page 15Express-IA533 User’s ManualExpress-LPC User’s Manual Page 15
5.4 Signal Descriptions
_
_
_
AC_
C
_
_6_7_
_
Pin Signal Description Type PU/PD Comment
A1 GND Ground PWR - A2 GBE0_MDI3- Ethernet Media Dependent Interfac e - I/O - DP - A3 GBE0_MDI3+ Ethernet Me dia Dependent Interface + I/O - DP - A4 GBE0_LINK100# Ethernet Sp ee d LED (100Mb) O-3.3 - On at 100Mb/s
A5 GBE0_LINK1000# Ethernet Speed LED (1000Mb) O-3.3 - On at 1000Mb/s
A6 GBE0_MDI2- Ethernet Media Dependent Interfac e - I/O - DP - A7 GBE0_MDI2+ Ethernet Me dia Dependent Interface + I/O - DP - A8 GBE0 _LIN K # LAN Link LED O-3 .3 - -
A9 GBE0_MDI1- Ethernet Media Dependent Interfac e - I/O - DP - A10 GBE0_MDI1+ Ethernet Me dia Dependent Interface + I/O - DP - A11 GND Ground PWR - A12 GBE0_MDI0- Ethernet Media Dependent Interface - I/O - DP - A13 GBE0_MDI0+ Ethernet Me dia Dependent Interface + I/O - DP - A14 GBE0_C TREF ETHCTREF O-1,8 - not supported
A15 SUS_S3# PM_SLP_S#3 O-3.3 - A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
SATA0
SATA0_TX-
SUS_S4#
SATA0_RX+
SATA0
GND
SATA2_TX+
SATA2_TX-
SUS_S5#
SATA2
SATA2_RX-
BATLOW#
ATA_ACT#
SYN
AC_RST#
GND
AC_BITCLK
AC_SDOUT
BIOS
DISABLE#
THRMTRIP#
USB6-
USB6+
USB
USB4-
USB4+
GND
USB2-
USB2+
USB_2_3_OC#
USB0-
USB0+
VCC
RTC
EXCD0_PERST#
EXCD0_CPPE#
LPC_SERIRQ
GND
PCIE5_TX+
PCIE5_TX-
GPI0
PCIE4_TX+
SATA0_TX+ | SATA 0 Transmit Data + O - DP - -
TX+
SATA0_TX- | SA TA 0 Transmit Data - O - DP - PM_SLP_S#4 O-3.3 - SA TA0_RX+ | SA TA 0 Recei ve Data + I - DP - SATA 0_RX - | SATA 0 Receive Data - I - DP - -
RX-
Ground PWR - SATA2_TX+ | SATA 2 Transmit Data + O - DP - SATA2_TX- | SA TA 2 Transmit Data - O - DP - PM_SLP_S#5 O-3.3 - -
SA TA2_RX+ | SA TA 2 Recei ve Data + I - DP - -
RX+
SATA2_R X- | SATA 2 Receive Data - I - DP - -
PM_BATLOW# | Battery Low I-3.3 PU 8k2 3.3Vsb ATA_LED# | SATA L ED O-3.3 PU 10k 3.3V
AC_SYNC | AC'97 Sync O-3.3 - int. PD 20k in ICH8
AC_RST# | AC'9 7 Reset O-3.3 - int. PD 20k i n ICH8
Ground PWR AC_BITCLK | AC'97 Clock O-3.3 - int. PD 20k in ICH8
AC_SDATAOUT | AC'97 Data O-3.3 - int. PD 20k in ICH8
BIOS_D I SA BLE # I-3.3 PU 10k 3.3Vsb PM_THRMTRIP#_CON O-3.3 PU 330 3.3V USB_PN6 | USB Data – Port6 I/O - DP - int. PD 15k in ICH8
USB_PP6 | USB Data + Port6 I/O - DP - int. PD 15k in ICH8
USB_OC #_6_7 | USB OverCurrent Port 6/7 I-3.3 PU 10k 3.3Vsb -
OC#
USB_PN4 | USB Data - Port4 I/O - DP - int. PD 15k in ICH8
USB_PP4 | USB Data + Port4 I/O - DP - int. PD 15k in ICH8
Ground PWR - USB_PN2 | USB Data - Port2 I/O - DP - int. PD 15k in ICH8
USB_PP2 | USB Data + Port2 I/O - DP - int. PD 15k in ICH8
USB_OC #_2_3 | USB OverCurrent Port 2/3 I-3.3 PU 10k 3.3Vsb
USB_PN0 | USB Data - Port0 I/O - DP - int. PD 15k in ICH8
USB_PP0 | USB Data + Port0 I/O - DP - int. PD 15k in ICH8
V_BAT PWR - Express Card Support [0]|card reset O-3.3 PU 10k 3.3Vsb -
Express Card Support [0]| capable c. request
INT_SERIRQ | Serial Interrupt Request IO-3.3 PU 8k 2 3.3V Ground PWR - PCI Express 5 Transmit + I - DP - PCI Express 5 Transmit - I - DP - General Purpose Input 0 I-3.3 PU 10k 3.3Vsb PCI Express 4 Transmit + (extended only) O - DP - -
Row A
I- 3.3 PU 10k 3.3 V -
Express-LPC User’s ManualPage 16
Signal Descriptions (cont’d)
_A0+
_A2+
_CK_
Row A
Pin Signal Description Type PU/PD Comment
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A95
A96
A97
A98
A99
A100
A101
A102
A103
A104
A105
A106
A107
A108
A109
A110
PCIE4_TX-
GND
PCIE3_TX+
PCIE3_TX-
GND
PCIE2_TX+
PCIE2_TX-
GPI1
PCIE1_TX+
PCIE1_TX-
GND
GPI2
PCIE0_TX+
PCIE0_TX-
GND
LVDS
LVDS_A0-
LVDS_A1+
LVDS_A1-
LVDS
LVDS_A2-
LVDS_VDD_EN
LVDS_A3+
LVDS_A3-
GND
LVDS_A_CK+
LVDS_A_CK-
LVDS_I2C_CK
LVDS_I2C_DAT
GPI3
KBD_RST#
KBD_A20GATE
PCIE_CK_REF+
PCIE
GND
SPI_POWER
SPI_MISO
GPO0
SPI_CLK
SPI_MOSI
GND
TYPE10#
RSVD
RSVD
GND
RSVD
RSVD
RSVD
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND
PCI Express 4 Transmit - (extended only) O - DP - Ground PWR - PCI Express 3 Transmit (extended only) O - DP - PCI Express 3 Transmit (extended only) O - DP - Ground PWR - PCI Express 2 Transmit + O - DP - PCI Express 2 Transmit - O - DP - General Purpose Input 1 I-3.3 PU 10k 3.3Vsb PCI Express 1 Transmit + O - DP - PCI Express 1 Transmit - O - DP - Ground PWR - General Purpose Input 2 I-3.3 PU 10k 3.3Vsb PCI Express 0 + O - DP - PCI Express 0 - O - DP - Ground PWR - LVDS_AP0 | LVDS Channel A O - DP - 18-bit only
LVDS_AN0 | LVDS Channel A O - DP - 18-bit only
LVDS_AP1 | LVDS Channel A O - DP - 18-bit only
LVDS_AN1 | LVDS Channel A O - DP - 18-bit only
LVDS_AP2 | LVDS Channel A O - DP - 18-bit only
LVDS_AN2 | LVDS Channel A O - DP - 18-bit only
LVDS_V DDEN | LV DS Panel Power O-2,5 PD 100k LVDS_AP3 | LVDS Channel A O - DP LVDS_AN3 | LVDS Channel A O - DP Ground PWR - LVDS_CLK AP | LVDS Channel A O - DP - LVDS_CLKAN | LVDS Channel A O - DP - LVDS_DDCPCLK | JI LI I2C Clock IO-3.3 PU 10k 3.3V LVDS_DDCPDATA | JILI I2C Data IO-3.3 PU 10k 3.3V General Purpose Input 3 I-3.3 PU 10k 3.3Vsb H_RCIN# | Ke yboard Reset I-3.3 PU 10k 3.3V H_A20GATE I-3.3 PU 10k 3.3V CLK _PC IE_REF P O - DP - CLK _PC IE_REF N O - DP - -
REF-
Ground PWR - Power supply for Carrier Board SPI O-3.3 - -
IO - General Purpose Output 0 O-3.3 PU 10k 3.3Vsb Clock from Module to Carrier SPI IO - Data out from Module to Carrier SPI IO - Ground PWR - Module type ID p in 10 NC - -
NC - NC - -
Ground PWR - -
NC - NC - -
NC - Power 12V PWR - Power 12V PWR - Power 12V PWR - Power 12V PWR - Power 12V PWR - Power 12V PWR - Ground PWR - -
not supported
not supported
Page 17Express-IA533 User’s Manual Page 17Express-IA533 User’s ManualExpress-LPC User’s Manual Page 17
Signal Descriptions (cont’d)
_
_
_
Row B
Pin Signal Description Type PU/PD Comment
B1 GND Ground PWR - B2 GBE0_ACT# LAN_ACTLED# | Ethernet Activity LED O-3.3 - B3 LPC_FRAME# LPC_FRAME# | LPC Frame Indicator O-3.3 - B4 LPC_AD0 LPC_AD0 | LPC Adress & DATA Bus IO-3.3 - int. PU 20k in ICH8
B5 LPC_AD1 LPC_AD1 | LPC Adress & DATA Bus IO-3.3 - int. PU 20k in ICH8
B6 LPC_AD2 LPC_AD2 | LPC Adress & DATA Bus IO-3.3 - int. PU 20k in ICH8
B7 LPC_AD3 LPC_AD3 | LPC Adress & DATA Bus IO-3.3 - int. PU 20k in ICH8
B8 LPC_DRQ0# SIO_DRQ#0 | LPC Serial DMA Request 0 I-3.3 - int. PU 20k in ICH8
B9 LPC_DRQ1# SIO_DRQ#1 | LPC Serial DMA Request 1 I-3.3 - int. PU 20k in ICH8
B10 LPC_CLK CLK_SIOEXTPCI O-3.3 - B11 GND Ground I-3.3 - B12 PWRBTN# Power Button I-3.3 PU 10K 3.3Vsb B13 SMB_CK SMBUS Clock O-3.3 PU 2k2 3.3 V B14 SMB_DAT SMBUS Data IO-3 .3 PU 2k2 3.3V B15 SMB_ALERT# SMB_ALERT# I-3.3 PU 10k 3.3Vsb B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
SATA1_TX+
SATA1_TX-
STAT#
SUS
SATA1_RX+
SATA1_RX-
GND
SATA3_TX+
SATA3
PWR_OK
SATA3_RX+
SATA3_RX-
WDT
AC_SDIN2
AC_SDIN1
AC_SDIN0
GND
SPKR
I2C_CK
I2C_DAT
THRM#
USB7USB7+
USB_4_5_OC#
USB5USB5+
GND
USB3USB3+
USB_0_1_OC#
USB1USB1+
EXCD1_PERST#
EXCD1_CPPE#
RESET#
SYS
CB_RESET#
GND
PCIE5_RX+
PCIE5_RX-
GPO1
PCIE4_RX+
SATA1_TX+ | SATA 1 Transmit Data + O - DP - SATA1_TX- | SATA 1 Transmit Data - O - DP - PM_SUS _ STAT# O-3.3 - SATA1_RX+ | SATA 1 Receive Data + I - DP - SATA1_RX - | SATA 1 Receive Data - I - DP - Ground PWR - SATA3_TX+ | SATA 3 Transmit Data +
SATA3_TX- | SATA 3 Transmit Data -
TX-
Power OK I-3.3 - SATA3_RX+ | SATA 3 Receive Data +
SATA3_RX - | SATA 3 Receive Data Watch Dog Timer O-3.3 - AC_SDATAIN2 I-3.3 - int. PD 20k in ICH8
AC_SDATAIN1 I-3.3 - int. PD 20k in ICH8
AC_SDATAIN0 I-3.3 - int. PD 20k in ICH8
Ground PWR AC_SPKR O-3.3 - int. PD 20k in ICH8
I2CLK O-3.3 PU 10k 3.3Vsb I2DAT IO-3.3 PU 10k 3.3Vs b PM THRM# CON | Over Temperature I-3.3 - USB_PN7 | USB Data – Port7 I/O - DP - int. PD 15k in ICH8
USB_PP7 | USB Data + Port7 I/O - DP - int. PD 15k in ICH8
USB_OC#_4_5 | USB OverCurrent Port I-3.3 PU 10k 3.3Vsb
USB_PN5 | USB Data- Port5 I/O - DP - int. PD 15k in ICH8
USB_PP5 | USB Data+ Port5 I/O - DP - int. PD 15k in ICH8
Ground PWR - USB_PN3 | USB Data- Port3 I/O - DP - int. PD 15k in ICH8
USB_PP3 | USB Data+ Port3 I/O - DP - int. PD 15k in ICH8
USB_OC#_0_1 | USB OverCurrent Port I-3.3 PU 10k 3.3Vsb USB_PN1 | USB Data- Port1 I/O - DP - int. PD 15k in ICH8
USB_PP1 | USB Data+ Port1 I/O - DP - int. PD 15k in ICH8
Express Card Support [1]|card reset O-3.3 PU 10k 3.3Vsb Express Card Support [1]| capable c. I-3.3 PU 10k 3.3V ETX_SYS_RESET# | Reset Input I-3.3 PU 10k 3.3V PCI_RST# | PCI Bus Reset O-3.3 - Ground PWR - PCI Express 5 Recieve + I - DP - PCI Express 5 Receive - I - DP - General Purpose Output 1 O-3.3 PU 10k 3.3V sb PCI Express 4 Recieve + (ex tended only) I - DP - -
NC
NC
NC
NC
- not supported
- not supported
- not supported
- not supported
Express-LPC User’s ManualPage 18
Signal Descriptions (cont’d)
_
_
_5V_SBY
v
_
Row B
Pin Signal Description Type PU/PD Comment
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
LVDS_BKLT_CTRL
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
B95
B96
B97
B98
B99
B100
B101
B102
B103
B104
B105
B106
B107
B108
B109
B110
PCIE4_RX-
GPO2
PCIE3_RX+
PCIE3_RX-
GND
PCIE2_RX+
PCIE2_RX-
GPO3
PCIE1_RX+
PCIE1_RX-
WAKE0#
WAKE1#
PCIE0_RX+
PCIE0
GND
LVDS_B0+
LVDS_B0-
LVDS
LVDS_B1-
LVDS_B2+
LVDS_B2-
LVDS_B3+
LVDS_B3-
LVDS_BKLT_EN
GND
LVDS_B_CK+
LVDS_B_CK-
VCC_5V_SBY
VCC_5V_SBY
VCC_5V_SBY
VCC
BIOS_DIS1#
VGA_RED
GND
GRN
VGA
VGA_BLU
VGA_HSYNC
VGA_VSYNC
VGA_I2C_CK
VGA_I2C_DAT
SPI_CS#
RSVD
RSVD
GND
RSVD
RSVD
RSVD
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND
PCI Express 4 Receive - (extended only) I - DP - General Purpose Output 2 O-3.3 PU 10k 3.3V sb PCI Express 3 Receive + (ex tended only) I - DP - PCI Express 3 Receive - (extended only) I - DP - Ground PWR - PCI Express 2 Receive + I - DP - PCI Express 2 Receive - I - DP - General Purpose Output 3 O-3.3 PU 10k 3.3V sb PCI Express 1 Receive + I - DP - PCI Express 1 Receive - I - DP - PCIE_WAK EI # I-3. 3 PU 1k 3.3 V sb WAKE1# I-3.3 PU 10k 3.3Vsb PCI Express 0 Receive + I - DP - PCI Express 0 Receive - I - DP - -
RX-
Ground PWR - LVDS_BP0 | LVDS Channel B Data0+ O - DP - not supported
LVDS_BN0 | LVDS Channel B Data0- O - DP - not supported
LVDS_BP1 | LVDS Channel B Data1+ O - DP - not supported
B1+
LVDS_BN1 | LVDS Channel B Data1- O - DP - not supported
LVDS_BP2 | LVDS Channel B Data2+ O - DP - not supported
LVDS_BN2 | LVDS Channel B Data2- O - DP - not supported
LVDS_BP3 | LVDS Channel B Data3+ O - DP - not supported
LVDS_BN3 | LVDS Channel B Data3- O - DP - not supported
LVDS Panel Backlight Enable O-3.3 PD 100k 3.3V Ground PWR - LVDS_CLKBP | LVDS Ch annel B O - DP - LVDS_CLKBM | LVDS Channel B O - DP - Backlight Brightness O-3.3 - 5V Standby PWR - 5V Standby PWR - 5V Standby PWR - 5V Standby PWR - Selection straps to determine the BIOS boot de
Analog Video RGB-RED OA PD 150R Ground PWR - Analog Video RGB-GREEN OA PD 150R Analog Video RGB-BLUE OA PD 150R Analog Video H-Sync O-3.3 - Analog Video V-Sync O-3.3 - Display Data Channel - Cl ock O-3.3 PU 2k2 3.3V Display Data Channel - Data IO-3.3 PU 2k2 3.3V Chip select for Carrier Board SPI O-3.3 - -
Ground PWR - -
Power 12V PWR - Power 12V PWR - Power 12V PWR - Power 12V PWR - Power 12V PWR - Power 12V PWR - Ground PWR - -
I-3.3 - -
NC - NC - -
NC - NC - NC - -
Page 19Express-IA533 User’s Manual Page 19Express-IA533 User’s ManualExpress-LPC User’s Manual Page 19
Signal Descriptions (cont’d)
p
yp
Pin Signal Description Type PU/PD Comment
C1 GND Ground PWR - C2
C3
C4
C5 IDE_D15
C6
C7
C8
C9
C10 IDE_D1
C11
C12
C13
C14 IDE_IOR#
C15
C16
C17
C18 PCI_GNT1#
C19
C20
C21
C22
C23 PCI_RESET#
C24
C25
C26
C27 PCI_AD6
C28
C29
C30
C31
C32 PCI_AD14
C33
C34
C35
C36 PCI_DEVSEL#
C37
C38
C39
C40
C41 GND
C42
C43
C44
C45 PCI_AD25
C46
C47
C48
C49 PCI_IRQA#
C50
C51
C52
C53
C54 TYPE0 #
C55
IDE_D7 IDE Data Bus
IDE_D6 IDE Data Bus
IDE_D3 IDE Data Bus
IDE_D8 IDE Data Bus
IDE_D9 IDE Data Bus
IDE_D2 IDE Data Bus
IDE_D13 ID E Data Bus
GND Ground
IDE_D14 ID E Data Bus
ID E_IORDY IDE I/ O Ready
PCI _P ME# PCI Power Management Event
PCI_GNT2# PC I Bus Grant 2
PCI_REQ2# PCI Bus Re quest 2
PCI_REQ1# PCI Bus Re quest 1
PCI_GNT0# PC I Bus Grant 0
GND Ground
PCI_REQ0# PCI Bus Reqest 0
PCI_AD0 PCI Adre ss & Da t a Bus line
PCI_AD2 PCI Adre ss & Da t a Bus line
PCI_AD4 PCI Adre ss & Da t a Bus line
PCI_AD8 PCI Adre ss & Da t a Bus line
PCI_AD10 PCI Adress & Data Bus line
PCI_AD12 PCI Adress & Data Bus line
GND Ground
PCI_C/BE1# PCI Bus Command a nd Byte enables
PCI_PERR# PCI Bus Grant Erro r
P CI_LOCK# PCI Bus Lo ck
PCI_IRDY# PCI Bu s Bus Initiator Ready
PCI_C/BE2# PCI Bus Command a nd Byte enables
PCI_AD17 PCI Adress & Data Bus line
PCI_AD19 PCI Adress & Data Bus line
PCI_AD21 PCI Adress & Data Bus line
PCI_AD23 PCI Adress & Data Bus line
PCI_C/BE3# PCI Bus Command a nd Byte enables
PCI_AD27 PCI Adress & Data Bus line
PCI_AD29 PCI Adress & Data Bus line
PCI_AD31 PCI Adress & Data Bus line
PCI_IRQB# PCI Bus In terrupt Request B
GND Ground
PEG_RX0+ PCIe 0 Recieve + / SDVO TV clock +
PEG_RX0- PCIe 0 Recieve - / SDVO TV clock -
PEG_RX1+ PCIe 1 Recieve + / SDVO B Interrup t +
IDE Data Bus
IDE Data Bus
I/O read lin e to IDE device
PCI Bus Grant 1
PCI Bus Reset
PCI Adress & Data Bus line
PCI Adress & Data Bus line
PCI Bus De vice S elect
Ground
PCI Adress & Data Bus line
PCI Bus Interru
Module t
t Request A
e ID pin 0
IO IO IO IO IO IO IO IO IO -
PWR - -
IO -
I-3.3
O-3.3 -
IO-3.3 int. PU 20k in ICH8
O-3.3 int. PU 20k in ICH8
I-3.3
O-3.3 int. PU 20k in ICH8
I-3.3
O-3.3 int. PU 20k in ICH8
PWR -
I-3.3
O-3.3 - -
IO-3.3 IO-3.3 IO-3.3 IO-3.3 IO-3.3 IO-3.3 IO-3.3 -
PWR - -
IO-3.3 IO-3.3 - IO-3.3
IO-3.3
IO-3.3
IO-3.3
IO-3.3 IO-3.3 IO-3.3 -
PWR - -
IO-3.3 IO-3.3 IO-3.3 - IO-3.3 IO-3.3 IO-3.3 IO-3.3
I-3.3
I-3.3
PWR -
I - DP not supported
I - DP - not supported
I - DP - not supported
PU 4K7 3.3V
PU 8K2 3.3V
PU 8K2 3.3V
PU 8K2 3.3V
PU 8K2 3.3V
PU 8K2 3.3V
PU 8K2 3.3V
PU 8K2 3.3V
PU 8K2 3.3V
PU 8K2 3.3V
NC - -
Row C
-
-
-
-
-
-
-
-
-
-
Express-LPC User’s ManualPage 20
Signal Descriptions (cont’d)
p
p
_
Row C
Pin Signal Description Type PU/PD Comment
C56 PEG_RX1C57
C58
C59
C60 GND
C61
C62
C63
C64
C65 PEG_RX4+
C66
C67
C68
C69 PEG_RX5C70
C71
C72
C73 SDVO_D ATA
C74
C75
C76
C77
C78 PEG_RX8+
C79
C80
C81
C82 PEG_RX9C83
C84
C85
C86
C87 GND
C88
C89
C90
C91 PEG_RX12+
C92
C93
C94
C95
C96 GND
C97
C98
C99
C100 GND
C101
C102
C103
C104 VCC_12V Power 12V PWR - C105
C106
C107
C108
C109 VCC_12V Power 12V PWR - C110
TYPE1# Module typ e ID pin 1
PEG_RX2+ PCIe 2 Recieve + / SDVO Field stall +
PEG_RX2- PCIe 2 Recieve - / SDVO Field stall -
PEG_RX3+ PCIe 3 Recieve +
PEG_RX3- PCIe 3 Recieve -
RSVD Rx from Board Controller
RSVD Tx from Board Control ler
PEG_RX4- PCIe 4 Recieve -
RSVD FAN_PWM_CTRL
PEG_RX5+ PCIe 5 Recieve + / SDVO C Interrupt +
GND Ground
PEG_RX6+ PCIe 6 Recieve +
PEG_RX6- PCIe 6 Recieve -
PEG_RX7+ PCIe 7 Recieve +
PEG_RX7- PCIe 7 Recieve -
GND Ground
RSVD FAN_TACH
PEG_RX8- PCIe 8 Recieve -
GND Ground
PEG_RX9+ PCIe 9 Recieve +
RSVD Physical Presence
GND Ground
PEG_RX10+ PCIe 10 Recieve +
PEG_RX10- PCIe 10 R ecieve -
PEG_RX11+ PCIe 11 Recieve +
PEG_RX11- PCIe 11 R ecieve –
GND Ground
PEG_RX12- PCIe 12 R ecieve -
GND Ground
PEG_RX13+ PCIe 13 Recieve +
PEG_RX13- PCIe 13 R ecieve -
RSVD NC NC
PEG_RX14+ PCIe 14 Recieve +
PEG_RX14- PCIe 14 R ecieve -
PEG_RX15+ PCIe 15 Recieve +
PEG_RX15- PCIe 15 R ecieve -
GND Ground
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND Ground
PCIe 1 Recieve - / SDVO B interru
Ground
PCIe 4 Recieve +
PCIe 5 Recieve - / SDVO C i nterru
CTRLDATA
SDVO
PCIe 8 Recieve +
PCIe 9 Recieve -
Ground
PCIe 12 Recieve +
Ground
Ground
Power 12V PWR - Power 12V PWR - Power 12V PWR - Power 12V PWR - -
t -
t -
I - DP - not supported
NC - I - DP - not supported
I - DP - not supported
PWR - I - DP - not supported
I - DP - not supported
I-3.3 - O-3.3 - I - DP - not supported
I - DP - not supported
0-5 - I - DP - not supported
I - DP - not supported
PWR - I - DP - not supported
I - DP - not supported
IO-2,5 - not supported
I - DP - not supported
I - DP - not supported
PWR - -
I-5 - I - DP - not supported
I - DP - not supported
PWR - I - DP - not supported
I - DP - not supported
I-3.3 - -
PWR - I - DP - not supported
I - DP - not supported
PWR - I - DP - not supported
I - DP - not supported
PWR - I - DP - not supported
I - DP - not supported
PWR - I - DP - not supported
I - DP - not supported
PWR - -
-I - DP - not supported
I - DP - not supported
PWR - I - DP - not supported
I - DP - not supported
PWR - -
PWR - -
Page 21Express-IA533 User’s Manual Page 21Express-IA533 User’s ManualExpress-LPC User’s Manual Page 21
Signal Descriptions (cont’d)
Row D
Pin Signal Description Type PU/PD Comment
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
GND
IDE_D5
IDE_D10
IDE_D11
IDE_D12
IDE_D4
IDE_D0
IDE_REQ#
IDE_IOW#
IDE_ACK#
GND
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_CS1#
IDE_CS3#
IDE_RESET#
PCI_GNT3#
PCI_REQ3#
GND
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7
PCI_C/BE0#
PCI_AD9
PCI_AD11
PCI_AD13
PCI_AD15
GND
PCI_PAR
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_AD16
PCI_AD18
PCI_AD20
PCI_AD22
GND
PCI_AD24
PCI_AD26
PCI_AD28
PCI_AD30
PCI_IRQC#
PCI_IRQD#
PCI_CLKRUN#
PCI_M66EN#
PCI_CLK
GND
PEG_TX0+
PEG_TX0-
PEG_LANE_RV#
PEG_TX1+
Ground PWR - IDE Data Bus IO - IDE Data Bus IO - -
IDE Data Bus IO - IDE Data Bus
IDE Data Bus IO - IDE Data Bus IO - IDE Device DMA Request. IO - int. PD 11.5k in ICH8
IDE IO Write O-3.3 - IDE DMA Acknowledge O-3.3 - Ground PWR - IDE Interrupt Request I-3.3 PU 8K2 3.3V IDE Adress Bu s O-3.3 - IDE Adress Bu s
IDE Adress Bu s O-3.3 - IDE Chip Select for 1F0h to 1FFh range O-3.3 - IDE Chip Select for 3F0h to 3FFh range O-3.3 - IDE Reset O u tput to Device
PCI Bus Grant 3 O-3.3 - int. PU 20k in ICH8
PCI Bus Reqe st 3 I-3.3 PU 8K2 3.3V Ground PWR - PCI Adress & Data Bus line IO-3.3 PCI Adress & Data Bus line IO-3.3 PCI Adress & Data Bus line IO-3.3 PCI Adress & Data Bus line IO-3.3 PCI Bus Command and Byte enables 0 IO-3.3 - PCI Adress & Data Bus line
PCI Adress & Data Bus line IO-3.3 PCI Adress & Data Bus line IO-3.3 PCI Adress & Data Bus line IO-3.3 Ground PWR - PCI Bus Parity IO-3.3 - PCI Bus System Error IO-3.3 PU 8K2 3.3V PCI Bus Stop IO-3.3 PU 8K2 3.3V PCI Bus Ta rget Ready IO-3.3 PU 8K2 3.3V PCI Bus Cyc le Frame
PCI Adress & Data Bus line IO-3.3 PCI Adress & Data Bus line IO-3.3 PCI Adress & Data Bus line IO-3.3 PCI Adress & Data Bus line IO-3.3 Ground PWR - PCI Adress & Data Bus line IO-3.3 PCI Adress & Data Bus line IO-3.3 PCI Adress & Data Bus line IO-3.3 PCI Adress & Data Bus line
PCI Bus Interrupt Request C I-3.3 PU 8K2 3.3V PCI Bus Interrupt Request D I-3.3 PU 8K2 3.3V PCI Clock Run I-3.3 PU 8K2 3.3V Control PCI Speed 33/66 Mhz
PCI Clock O-3.3 - Ground PWR - PCIe 0 Trans mit + / SDVO B [RED] + O - DP - not supported
PCIe 0 Trans mit - / SDVO B [RED] - O - DP - not supported
PCIe Lane Re v ersal I-3.3 - PCIe 1 Trans mit + / SDVO B [G RN] + O - DP - not supported
IO - -
O-3.3 - -
O-3.3 - -
IO-3.3 -
IO-3.3
IO-3.3 -
I-3.3 - Fixed to 33 Mhz
PU 8K2 3.3V
-
Express-LPC User’s ManualPage 22
Signal Descriptions (cont’d)
Row D
Pin Signal Description Type PU/PD Comment
D56
D57
D58
D59
D60
D61
D62
D63
D64
D65
D66
D67
D68
D69
D70
D71
D72
D73
D74
D75
D76
D77
D78
D79
D80
D81
D82
D83
D84
D85
D86
D87
D88
D89
D90
D91
D92
D93
D94
D95
D96
D97
D98
D99
D100
D101
D102
D103
D104
D105
D106
D107
D108
D109
D110
PEG_TX1-
TYPE2#
PEG_TX2+
PEG_TX2-
GND
PEG_TX3+
PEG_TX3-
RSVD
RSVD
PEG_TX4+
PEG_TX4-
GND
PEG_TX5+
PEG_TX5-
GND
PEG_TX6+
PEG_TX6SDVO_CLK
PEG_TX7+
PEG_TX7-
GND
IDE_CBLID#
PEG_TX8+
PEG_TX8-
GND
PEG_TX9+
PEG_TX9-
RSVD
GND
PEG_TX10+
PEG_TX10-
GND
PEG_TX11+
PEG_TX11-
GND
PEG_TX12+
PEG_TX12-
GND
PEG_TX13+
PEG_TX13-
GND
PEG_ENABLE#
PEG_TX14+
PEG_TX14-
GND
PEG_TX15+
PEG_TX15-
GND
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND
PCIe 1 Trans mit - / SDVO B [GRN] - O - DP - not s u pported
Module type ID pin 2 STO - not conn ected
PCIe 2 Trans mit + / SDVO B [BLU ] + O - DP - not supported
PCIe 2 Trans mit - / SDVO B [BLU] - O - DP - not supp orted
Ground PWR - PCIe 3 Trans mit + / SDVO B Cloc k + O - DP - not supported
PCIe 3 Trans mit - / SDVO B Clock - O - DP - not supported
NC - -
NC - PCIe 4 Trans mit + / SDVO C [RED] + O - DP - not supported
PCIe 4 Trans mit - / SDVO C [R ED] - O - DP - not supported
Ground PWR - PCIe 5 Trans mit + / SDVO C [GRN] + O - DP - not supported
PCIe 5 Transmit - / SDVO C [GRN] Ground PWR - PCIe 6 Trans mit + / SDVO C [BLU] + O - DP - not supp orted
PCIe 6 Trans mit - / SDVO C [BLU] - O - DP - not supported
SDVO_CTRLCLK
PCIe 7 Trans mit + / SDVO C Clock + O - DP - not supported
PCIe 7 Trans mit - / SDVO C C lock - O - DP - not supp orted
Ground PWR - IDE Cable Indicator Signal I-3.3 PD 10k PCIe 8 Transmit + O - DP - not supported
PCIe 8 Transmit - O - DP - not supported
Ground PWR - PCIe 9 Transmit + O - DP - not supported
PCIe 9 Transmit -
Ground PWR - PCIe 10 Tran smit + O - DP - not supp orted
PCIe 10 Tran smit - O - DP - not supported
Ground PWR - PCIe 11 Tran smit + O - DP - not supp orted
PCIe 11 Tran smit - O - DP - not supported
Ground PWR - PCIe 12 Tran smit +
PCIe 12 Tran smit - O - DP - not supported
Ground PWR - PCIe 13 Tran smit + O - DP - not supported
PCIe 13 Tran smit - O - DP - not supported
Ground PWR - PCIe Enable I-3.3 NC
PCIe 14 Tran smit + O - DP - not supported
PCIe 14 Tran smit - O - DP - not supported
Ground PWR - PCIe 15 Tran smit + O - DP - not supported
PCIe 15 Tran smit - O - DP - not supported
Ground PWR - Power 12V PWR - Power 12V PWR - Power 12V PWR - Power 12V PWR - Power 12V PWR - Power 12V PWR - Ground PWR - -
O - DP - not supp orted
IO-2,5 - -
O - DP - not supp orted
NC - -
O - DP - not supp orted
Page 23Express-IA533 User’s Manual Page 23Express-IA533 User’s ManualExpress-LPC User’s Manual Page 23
Signal Descriptions (cont’d)
Signal Type Legend
IO-2,5 Bi-directional 2,5 V Input/Output
IO-3,3 Bi-directional 3,3 V Input/Output
IO-5 Bi-directional 5 V Input/Output
I-3,3 3,3 V Input
I-5 5 V Input
O-2,5 2,5 V Output
O-3,3 3,3 V Output
O-5 5 V Output
IO Input/Output
OA Analog Output
OD Open Drain
IO-DP Differential Pai r Inp ut/Output
O -DP Differential Pair Output
I -D P Differential Pair Input
PWR Power or Ground
STO Strapping Output
PU Pull Up Resist or
PD Pull Down Resistor
NC Not Connected / Reserved
Express-LPC User’s ManualPage 24
6 Embedded Functions
All embedded board functions on ADLINK’s Computer on Modules are supported at the
operating system level using the ADLINK Intelligent Device Interface (AIDI) library. The AIDI API
programming interface is compatible and identical across all ADLINK Computer on Modules and
all supported operating systems. The AIDI library includes a demo program to demonstrate the
library’s functionallity.
6.1 Watchdog Timer
The Express-LPC implements a Watchdog timer that can be used to
automatically detect software execution problems or system hangs and
reset the board if necessary. The Watchdog timer consists of a counter
that counts down from an initial value to zero. When the system is
operating normally, the software that sets the intial value periodically
resets the counter so that the it never reaches zero. If the counter
reaches zero before the software resets it, the system is presumed to be
malfunctioning and a reset signal is asserted.
The AIDI Library Watchdog functions support Watchdog control of the board. If the Watchdog
begins countdown and reaches zero, it will access the CPU's RESET signal to reset the system.
This application must call another function named AidiWDogTrigger that triggers the Watchdog to
restart to prevent system reset.
AIDI Demo Program
- Watchdog Tab
The AIDI Demo Program allows
retrieval of the current Watchdog
status and updating of the
Watchdog settings
If the Watchdog is enabled, the
user can click the WDT Trigger
button to manually reset the
counter and prevent the system
from resetting
Page 25Express-IA533 User’s Manual Page 25Express-IA533 User’s ManualExpress-LPC User’s Manual Page 25
6.2 GPIO
GPIO library support is limited to GPIO signals that originate from the Computer on Module
and extended to the carrier board. COM Express modules support 4 GPO and 4 GPI signals.
Some of ADLINK’s COM Express boards can configure all 8 ports for GPI or GPO use.
GPIO signals can be monitored and controlled by using the ADLINK Intelligent Device
Interface (AIDI) library that is compatible and identical across all ADLINK COM Express
modules and all supported operating systems.
The COM Express type II standard assigns the following pins for either GPI or GPO
Pin Signal Type # AIDI ID (bit) Remark
A54 GPI0 0 Express-LPC can configure this pin for GPI and GPO
A63 GPI1 1 Express-LPC can configure this pin for GPI and GPO
A67 GPI2 2 Express-LPC can configure this pin for GPI andGPO
A85 GPI3 3 Express-LPC can configure this pin for GPI andGPO
A93 GPO0 4 Express-LPC can configure this pin for GPI and GPO
B54 GPO1 5 Express-LPC can configure this pin for GPI and GPO
B57 GPO2 6 Express-LPC can configure this pin for GPI and GPO
B63 GPO3 7 Express-LPC can configure this pin for GPI and GPO
AIDI Demo Program
- GPIO Tab
The AIDI Demo Program displays
current GPI or GPO status and
allows reading of GPI and writing
to GPO.
The table above links logical port
numbers in AIDI to physical port
numbers on the COM Express
board-to-board connector.
For boards that support multi-
direction the “SetDirection” button
can configure the port for either
GPI or GPO
Express-LPC User’s ManualPage 26
6.3 Hardware Monitoring
To ensure system health of your embedded system ADLINK’s COM Express modules come
with built in support for monitoring and control of CPU and system temperatures, fan speed
and critical module voltage levels.
The AIDI Library provides simple APIs at the application level to support these functions and
adds alarm functions when voltage or temperature levels exceeds the upper or lower limit set
by the user.
On the Express-LPC the following monitored values can be read from the module:
CPU temperature, system temperature, Vcore, 1.8V, 5V, 3.3V and 12V.
AIDI Demo Program
- HW Monitor Tab
Field 1 displays detected sensors
(number).
Field 2 allows setting of upper and
lower alarm limits.
Field 3 displays read out
information of sensors.
Page 27Express-IA533 User’s Manual Page 27Express-IA533 User’s ManualExpress-LPC User’s Manual Page 27
7 System Resources
7.1 System Memory Map
Address Range (decimal) Address Range (hex) Size Description
(4GB-2MB) FFE00000–FFFFFFFF 2 MB High BIOS Area
(4GB-18MB)–(4GB-17MB-1) FEE00000–FEEFFFFF 1 MB FSB Interrupt Memory Space
(4GB-19MB)–(4GB-18MB-1) FED00000–FEDFFFFF 1 MB Chipset configuration Space
(4GB-20MB)–(4GB-19MB-1) FEC00000–FECFFFFF 1 MB APIC Configuration Space
15MB – 16MB F00000–FFFFFF 1 MB ISA Hole
960 K – 1024 K F0000–FFFFF 64 KB System BIOS Area
896 K – 960 K E0000–EFFFF 64 KB Extended System BIOS Area
768 K – 896 K C0000–DFFFF 128 KB PCI expansion ROM area
640 K – 768 K A0000–BFFFF 128 KB Video Buffer & SMM space
0 K – 640 K 00000–9FFFF 640 KB DOS Area
C0000–CEFFF: Onboard VGA BIOS
CF000–D0FFF: PXE option ROM when
onboard LAN boot ROM is enabled
7.2 Direct Memory Access Channels
Channel Number Data Width System Resource Comment
0 8-bits Parallel port Note (1)
1 8-bits Parallel port Note (1)
2 8-bits Diskette drive Note (1)
3 8-bits Parallel port Note (1)
4 DMA controller
5 16-bits Open
6 16-bits Open
7 16-bits Open
(1) DMA channel 0/1/3 is selected when using parallel port. DMA2 is used by Floppy.
Express-LPC User’s ManualPage 28
7.3 Legacy I/O Map
Address (hex) Size Description Comment
0000 – 001F 32 bytes DMA controller
0020 – 0021 2 bytes Interrupt controller
0024 – 0025 2 bytes Interrupt controller
0028 – 0029 2 bytes Interrupt controller
002C – 002D 2 bytes Interrupt controller
002E – 002F 2 bytes Super IO
0040 – 0043 4 bytes System Timer
004E – 004F 2 bytes TPM configuration port
0060 1 byte Keyboard controller
0061 1 byte NMI, speaker control
0063 1 byte NMI controller
0064 1 byte Keyboard controller
0065 1 byte NMI controller
0067 1 byte NMI controller
0070 – 0077 8 bytes CMOS/Real time clock controller
0080 – 0091 18 bytes DMA controller
0092 1 bytes Reset Generator
0093 – 009F 13 bytes DMA controller
00A0 – 00A1 2 bytes Interrupt controller
00A4 – 00A5 2 bytes Interrupt controller
00A8 – 00A9 2 bytes Interrupt controller
00AC – 00AD 2 bytes Interrupt controller
00B0 – 00B1 2 bytes Interrupt controller
00B2 – 00B3 2 bytes Power Management
00B4 – 00B5 2 bytes Interrupt controller
00B8 – 00B9 2 bytes Interrupt controller
00BC – 00BD 2 bytes Interrupt controller
00C0 – 00DF 32 bytes DMA controller
00E0 – 00EF 16 bytes System reserved
00F0 – 00FF 16 bytes Numeric processor
0170 – 0177 8 bytes Secondary IDE controller
01F0 – 01F7 8 bytes Primary IDE controller
0274 – 0277 4 bytes ISA PnP read port
0278 – 027F 8 bytes LPT2
0290 – 029F 16 bytes Onboard Sensor index(0x295)/data port (0x296)
02E8 – 02EF 8 bytes COM4/Video
02F8 – 02FF 8 bytes COM2
0376 – 0377 2 bytes Secondary IDE controller
0378 – 037F 8 bytes LPT1
03B0 – 03BB 12 bytes Video (monochrome)
03BC – 03BF 4 bytes LPT3
03C0 – 03DF 32 bytes Video (VGA†)
03E8 – 03EF 8 bytes COM3
03F0 – 03F5, 03F7 7 bytes Diskette controller
Page 29Express-IA533 User’s Manual Page 29Express-IA533 User’s ManualExpress-LPC User’s Manual Page 29
Legacy I/O Map (cont’d)
Address (hex) Size Description Comment
03F6 – 03F7 2 bytes Primary IDE controller
03F8 – 03FF 8 bytes COM1
0400 – 041F 32 bytes Onboard SMBus control registers
0480 – 04BF 64 bytes GPIO control registers
04D0 – 04D1 2 bytes Edge/level triggered PIC
0800 – 087F 128 bytes ACPI control registers.
0A79 – 0A79 1 bytes ISA PnP read data Port
0CF8 – 0CFF* 8 bytes PCI configuration registers Note (*)
0CF9** 1 byte Reset control register Note (**)
04700 – 0470F 16 bytes TPM control registers
(*) DWORD access only
(**) Byte access only
7.4 Interrupt Request (IRQ) Lines
PIC Mode
IRQ# Typical Interrupt Resource Connected Available
0 Counter 0 N/A No
1 Keyboard controller N/A No
2 Cascade interrupt from slave PIC N/A No
3 Serial Port 2 (COM2) / PCI IRQ3 via SERIRQ Note (1)
4 Serial Port 1 (COM1) / PCI IRQ4 via SERIRQ Note (1)
5 Parallel Port 2 (LPT2) / PCI IRQ5 via SERIRQ Note (1)
6 Floppy Drive Controller IRQ6 via SERIRQ No
7 Parallel Port 1 (LPT1) / PCI IRQ7 via SERIRQ, Note (1)
8 Real-time clock N/A No
9 SCI / PCI IRQ9 via SERIRQ Note (1)
10 PCI IRQ10 via SERIRQ Note (1)
11 PCI IRQ11 via SERIRQ Note (1)
12 PS/2 Mouse / PCI IRQ12 via SERIRQ Note (1)
13 Math Processor N/A No
14 Primary IDE controller / PCI IRQ14 via SERIRQ Note (1)
15 Secondary IDE controller / PCI IRQ15 via SERIRQ Note (1)
(1) These IRQs can be used for PCI devices when onboard device is disabled.
Express-LPC User’s ManualPage 30
Interrupt Request (IRQ) Lines (cont’d)
APIC Mode
IRQ# Typical Interrupt Resource Connected Available
0 Counter 0 N/A No
1 Keyboard controller N/A No
2 Cascade interrupt from slave PIC N/A No
3 Serial Port 2 (COM2) / PC IRQ3 via SERIRQ Note (1)
4 Serial Port 1 (COM1) / PCI IRQ4 via SERIRQ Note (1)
5 Parallel Port 2 (LPT2) / PCI IRQ5 via SERIRQ Note (1)
6 Floppy Drive Controller IRQ6 via SERIRQ No
7 Parallel Port 1 (LPT1) / PCI IRQ7 via SERIRQ Note (1)
8 Real-time clock N/A No
9 ACPI N/A No
10 PCI IRQ10 via SERIRQ Note (1)
11 PCI IRQ11 via SERIRQ Note (1)
12 PS/2 Mouse / PCI IRQ12 via SERIRQ Note (1)
13 Math Processor N/A No
14 Primary IDE controller / PCI IRQ14 via SERIRQ Note (1)
15 Secondary IDE controller / PCI IRQ15 via SERIRQ Note (1)
16 N/A PCI Slot INT A, USB, VGA controller, Yes
High Definition Audio controller
17 N/A PCI Slot INT B, PCI-E Gigabit Ethernet NIC Yes
18 N/A PCI Slot INT C, USB Yes
19 N/A PCI Slot INT D, USB controller Yes
20 N/A No
21 N/A No
22 N/A No
23 N/A EHCI, USB No
(1) These IRQs can be used for PCI devices when onboard device is disabled.
7.5 PCI Configuration Space Map
Bus No. Device No. Function No. Routing Description
00h 00h 00h N/A Intel 945 GME GMCH Host-Hub Interface Bridge
00h 02h 00h Internal Intel Integrated Graphics Device
00h 02h 01h Internal Intel Integrated Graphics Device (Function 1)
00h 1Bh 00h Internal High Definition Audio controller
00h 1Ch 00h Internal Intel ICH Express Root port
00h 1Dh 00h Internal Intel USB UHCI Controller 1
00h 1Dh 01h Internal Intel USB UHCI Controller 2
Page 31Express-IA533 User’s Manual Page 31Express-IA533 User’s ManualExpress-LPC User’s Manual Page 31
PCI Configuration Space Map (cont’d)
Bus No. Device No. Function No. Routing Description
00h 1Dh 07h Internal Intel USB EHCI Controller
00 h 1Eh 00h N/A Intel Hub Interface to PCI Bridge
00 h 1Fh 00h N/A Intel LPC Interface Bridge
00h 1Fh 01h Internal Intel IDE Controller
00h 1Fh 02h Internal Intel SATA controller
00h 1Fh 03h Internal Intel SMBus Controller
02h 00h 00h onboard Onboard LAN 8111C - Note (*)
03h 04h 00h PIRQA-PIRQD External PCI Slot 1
03h 05h 00h PIRQA-PIRQD External PCI Slot 2
03h 06h 00h PIRQA-PIRQD External PCI Slot 3
03h 07h 00h PIRQA-PIRQD External PCI Slot 4
(*) The bus number may differ if there are PCIE devices installed on the carrier board.
7.6 PCI Interrupt Routing Map
PIRQ INT VGA UHCI 1 UHCI 2 EHCI SATA SMbus Audio PCI PCI PCI PCI LAN
A INTA X X INTA INTD INTC INTB
B INTB INTB INTA INTD INTC X
C INTC INTC INTB INTA INTD
D INTD X X X INTD INTC INTB INTA
E
F
G
HXX
Slot 1 Slot 2 Slot 3 Slot 4
7.7 SMBus Slave Device Address
Address (hex) Device Function
D2 CK505 Clock Generator
A0 SODIMM1 DDR3 socket
A4 SODIMM2 DDR3 socket
5C LM87 Hardware Monitor
40 PCA9535 GPIO
4C ADT7481 CPU Temperature Sensor
Express-LPC User’s ManualPage 32
8 BIOS Setup Utility
The following chapter describes basic navigation for the AMIBIOS8 BIOS setup utility.
8.1 Starting the BIOS
To enter the setup screen, follow these steps:
1. Power on the motherboard
2. Press the < Delete > key on your keyboard when you see the following text prompt:
< Press DEL or Delete to run Setup >
3. After you press the < Delete > key, the main BIOS setup menu displays. You can
access the other setup screens from the main BIOS setup menu, such as Chipset and
Power menus.
In most cases, the < Delete > key is used to invoke the setup screen. There are
several cases that use other keys, such as < F1 >, < F2 >, and so on.
Page 33Express-IA533 User’s Manual Page 33Express-IA533 User’s ManualExpress-LPC User’s Manual Page 33
8.1.1 Main Setup Menu
The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup
menu option is described in this user’s guide.
The Main BIOS setup menu screen has two main frames. The left frame displays all the options
that can be configured. “Grayed” options cannot be configured, “Blue” options can be.
The right frame displays the key legend. Above the key legend is an area reserved for a text
message. When an option is selected in the left frame, it is highlighted in white. Often a text
message will accompany it.
Express-LPC User’s ManualPage 34
8.1.2 Navigation
The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS
setup utility hot keys can be used at any time during the setup navigation process.
These keys include < F1 >, < F10 >, < Enter >, < ESC >, < Arrow > keys, and so on.
There is a hot key legend located in the right frame on most setup screens.
Hot Key Description
Left/Right The Left and Right < Arrow > keys allow you to select a setup screen.
For example: Main screen, Advanced screen, Chipset screen, and so on.
Up/Down The Up and Down < Arrow > keys allow you to select a setup item or sub-screen.
+- Plus/Minus The Plus and Minus < Arrow > keys allow you to change the field value of a particular
setup item.
For example: Date and Time.
Tab The < Tab > key allows you to select setup fields.
The < F8 > key on your keyboard is the Fail-Safe key. It is not displayed on the key
legend by default. To set the Fail-Safe settings of the BIOS, press the < F8 > key on your
keyboard. It is located on the upper row of a standard 101 keyboard. The Fail-Safe
settings allow the motherboard to boot up with the least amount of options set. This can
lessen the probability of conflicting settings.
Page 35Express-IA533 User’s Manual Page 35Express-IA533 User’s ManualExpress-LPC User’s Manual Page 35
Hot Key Description
F1 The < F1 > key allows you to display the General Help screen.
Press the < F1 > key to open the General Help screen.
F10 The < F10 > key allows you to save any changes you have made and exit Setup. Press the < F10 >
key to save your changes. The following screen will appear:
Press the < Enter > key to save the configuration and exit. You can also use the < Arrow > key
to select Cancel and then press the < Enter > key to abort this function and return to the previous screen.
ESC The < Esc > key allows you to discard any changes you have made and exit the Setup. Press the
< Esc > key to exit the setup without saving your changes. The following screen will appear:
Press the < Enter > key to discard changes and exit. You can also use the < Arrow > key to select
Cancel and then press the < Enter > key to abort this function and return to the previous screen.
Enter The < Enter > key allows you to display or change the setup option listed for a particular setup
item. The < Enter > key can also allow you to display the setup sub-screens.
Express-LPC User’s ManualPage 36
8.2 Main Setup
When you first enter the Setup Utility, you will enter the Main setup screen. You can always return
to the Main setup screen by selecting the Main tab. There are two Main Setup options. They are
described in this section. The Main BIOS Setup screen is shown below.
System Time/System Date
Use this option to change the system time and date. Highlight System Time or System Date
using the < Arrow > keys. Enter new values using the keyboard. Press the < Tab > key or
the < Arrow > keys to move between fields. The date must be entered in MM/DD/YY
format. The time is entered in HH:MM:SS format.
The time is in 24-hour format. For example, 5:30 A.M. appears as 05:30:00, and 5:30
P.M. as 17:30:00.
I2C Speed Control
Use this option to set I2C Speed Control. Options: 100k/200k/400k.
Page 37Express-IA533 User’s Manual Page 37Express-IA533 User’s ManualExpress-LPC User’s Manual Page 37
8.3 Advanced BIOS Setup
Select the Advanced tab from the setup screen to enter the Advanced BIOS Setup screen.
You can select any of the items in the left frame of the screen to go to the sub menu for that
item. You can display an Advanced BIOS Setup option by highlighting it using the
< Arrow > keys. The Advanced BIOS Setup screen is shown below.
The sub menus are described on the following pages.
Setting incorrect or conflicting values in Advanced BIOS Setup may cause system
malfunctions.
Express-LPC User’s ManualPage 38
8.3.1 CPU Configuration
CPU Configuration Settings
You can use this screen to select options for the CPU Configuration Settings. Use the up and
down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of
the selected option. A description of the selected item appears on the right side of the screen.
The settings are described on the following pages. An example of the CPU Configuration screen
is shown below.
Max CPUID Value Limit
When the computer is boots, the operating system executes its CPUID instruction to identify the
processor and its capabilities. Before it can do so, it must first query the processor to find out the
highest input value the CPUID recognizes. This determines the kind of basic information CPUID
can provide the operating system. This option allows you to circumvent problems with older
operating systems.
When Enabled, the processor will limit the maximum CPUID input value to 03h when queried,
even if the processor supports a higher CPUID input value. When Disabled, the processor will
return the actual maximum CPUID input value of the processor when queried.
Page 39Express-IA533 User’s Manual Page 39Express-IA533 User’s ManualExpress-LPC User’s Manual Page 39
Execute Disable Bit Capability
This is an Intel hardware-based security feature that can help reduce system exposure to
viruses and malicious code. It allows the processor to classify areas in memory where
application code can or cannot execute. When a malicious worm attempts to insert code in
the buffer, the processor disables its code execution, preventing damage and worm
propagation. To use Execute Disable Bit you must have a PC or server with a processor with
Execute Disable Bit capability and a supporting operating system.
Hyper Threading Technology
This item allows you to Enable/Disable Hyper-Threading Technology.
Intel® SpeedStep tech
This option enables or disables Intel SpeedStep technology.
Intel® C-STATE tech
This item allows you to Enable/Disable the C-STATE function. C-STATE make the power and
thermal control unit part of the core logic and not part of the chipset as before.
Enhanced C-STATE
This item allows you to Enable/Disable the Enhanced C-STATE function.
MPS Revision
This item allows you to select which MPS revision to use for the operating system.
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8.3.2 Chipset Configuration
Chipset Configuration Settings
Select the Chipset tab from the setup screen to enter the Chipset BIOS Setup screen. You can
select any of Chipset BIOS Setup options by highlighting it using the < Arrow > keys. The Chipset
BIOS Setup screen is shown below.
DRAM Frequency
Set DRAM frequency. You can let frequency be set by BIOS automatically or configure it
manually.
Configure DRAM Timing by SPD
Enable/Disable the timing set of DRAM is configured from SPD or set by manually.
APIC ACPI SCI IRQ
This item allows you to enable or disable the APIC ACPI SCI interrupt.
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8.3.3 Video Function Configuration
Video Function Configuration Settings
You can use this screen to select options for Video Function configuration settings. Use the up and
down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of the
selected option. A description of the selected item appears on the right side of the screen. The
video function BIOS Setup screen is shown below.
Boots Graphic Adapter Priority
Select which graphics controller to use as the primary boot display device. IGD=Integrated
Graphic device. PCI means external PCI graphics device.
Internal Graphics Mode Select
Select amount of system memory which is used by internal graphics device.
DVMT Mode Select
Unified Memory Architecture (UMA) is a concept whereby system memory is shared by both
CPU and graphics processor. While this reduces cost, it also reduces the system's
performance by taking up a large portion of memory for the graphics processor. Intel's
Dynamic Video Memory Technology (DVMT) takes that concept further by allowing the
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system to dynamically allocate memory resources according to the demands of the system at
any point in time. The key idea in DVMT is to improve the efficiency of the memory allocated
to either system or graphics processor.
When set to Fixed Mode, the graphics driver will reserve a fixed portion of the system
memory as graphics memory. When set to DVMT Mode, the graphics chip will dynamically
allocate system memory as graphics memory, according to system and graphics
requirements. When set to Combo Mode, the graphics driver will allocate a fixed amount of
memory as dedicated graphics memory, as well as allow more system memory to be
dynamically allocated between the graphics processor and the operating system.
DVMT/FIXED Memory
Set the amount of memory according to DVMT Mode Select.
Boot Display Device
Select which display interface you want to make it active.
Local Flat Panel Scaling
Allows you to determine how various resolutions appear on your LCD display.
Auto: The scaling unit on your graphics card will rescale the image before it reaches your
LCD display. This option results in the best image quality.
Forced Scaling: This option will maintain the original aspect ratio of the chosen resolution
and display it with black bars to the sides/above/below the on-screen image as required.
Disabled: The image isn't scaled at all, but instead your LCD display will run at its maximum
resolution and the image will display in the centre of your LCD display. This may result in a
black border around the sides of the image.
Flat Panel Type
Once LVDS is selected from Boot Display Device, this option opens some resolution settings
for correct timing out to LVDS interface you want to use.
LVDS Backlight Control
This field allows you to set the LVDS backlight level. Options: 0%, 25%, 50%, 75%, 100%,
Auto
Spread Spectrum Clock
This field allows you to enable/disable the Spread Spectrum Clock function.
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8.3.4 IDE Configuration
IDE Configuration Settings
You can use this screen to select options for the IDE Configuration Settings. Use the up and
down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of
the selected option. A description of the selected item appears on the right side of the screen.
The settings are described on the following pages. An example of the IDE Configuration screen
is shown below.
ATA/IDE Configuration
This item specifies whether the IDE channels should be initialized in Compatible or
Enhanced mode of operation. The settings are Disabled, Compatible and Enhanced.
Legacy IDE Channels
When running in compatible mode, the SATA channel can be configured as a legacy IDE
channel. The location of the IDE channel is selectable.
Primary IDE Master/Slave, Secondary IDE Master/Slave
Select one of the hard disk drives to configure it. Press < Enter > to access its sub menu.
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Hard Disk Write Protect
Set this value to Enabled to prevent the hard disk drive from being overwritten.
IDE Detect Time Out
This field allows you to set the time to stop searching for IDE devices within the specified
number of seconds.
ATA(PI)80Pin Cable Detection
Selects the method used to detect the type of IDE cable used.
8.3.5 AHCI Configuration
You can use this screen to select options for the AHCI Settings.
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AHCI Ports
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8.3.6 Onboard Device Configuration
Onboard Device Configuration Settings
You can use this screen to specify options for the onboard device configuration Settings.
Use the up and down < Arrow > keys to select an item. Use the < + > and < - > keys to
change the value of the selected option. The settings are described on the following pages.
The screen is shown below.
Onboard LAN Boot ROM
Set this value to enable/disable the onboard LAN’s PXE ROM to enable boot from LAN.
Setting to Disabled can shorten the POST time without initializing LAN PXE ROM if boot from
LAN is not needed.
HD Audio Controller
Set this value to Enable/Disable the Audio Controller.
SMBus Controller
Set this value to Enable/Disable the SMBus Controller.
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SuperIO Configuration Screen
SuperIO configuration screen is a sub-menu of Onboard Device Configuration. You can use
this screen to select options for the Super IO settings. Use the up and down < Arrow >
keys to select an item. Use the < + > and < - > keys to change the value of the selected
option. The settings are described on the following pages. The screen is shown below. The
visibility of this SuperIO configuration screen depends on the presence of an onboard
SuperIO (Winbond W83627HF). If the Express-LPC is used on carrier w/o a SIO chip, the
legacy-free mode will take effect.
Floppy A
Use this field to specify options for the Floppy Configuration Settings.
Options: Disabled, 360 KB 5 ¼”, 1.2 MB 5 ¼”, 720 KB 3 ½”, 1.44 MB 3 ½”, 2.88 MB 3 ½”.
OnBoard Floppy Controller
This option enables/disables the Super IO’s floppy controller.
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Serial Port1 Address
This option specifies the base I/O port address and Interrupt Request address of serial port 1.
Option Description
Disabled Set this value to prevent the serial port from accessing any system resources. When this option is
set to Disabled, the serial port physically becomes unavailable.
3F8/IRQ4 Set this value to allow the serial port to use 3F8 as its I/O port address and IRQ 4 for the interrupt
address.
3E8/IRQ4 Set this value to allow the serial port to use 3E8 as its I/O port address and IRQ 4 for the interrupt
address.
2F8/IRQ3 Set this value to allow the serial port to use 2F8 as its I/O port address and IRQ 3 for the interrupt
address.
2E8/IRQ3 Set this value to allow the serial port to use 2E8 as its I/O port address and IRQ 3 for the interrupt
address.
Serial Port2 Address
This option specifies the base I/O port address and Interrupt Request address of Serial
Port2. The settings of Serial Port2 are the same as Serial Port1. However, the setting used
by Serial Port1 will not be available for Serial Port2. For example, if Serial Port1 uses 3F8/
IRQ4, the option, the 3F8/IRQ4 will not appear in the options of Serial Port2.
Parallel Port Address
This option lets to configure the SuperIO’s parallel port address.
Parallel Port Mode
This option specifies the parallel port mode.
Option Description
Normal Set this value to allow the standard parallel port mode to be used.
EPP The parallel port can be used with devices that adhere to the Enhanced Parallel Port (EPP)
specification. EPP uses the existing parallel port signals to provide asymmetric bidirectional data
transfer driven by the host device.
ECP The parallel port can be used with devices that adhere to the Extended Capabilities Port (ECP)
specification. ECP uses the DMA protocol to achieve data transfer rates up to 2.5 Megabits per
second. ECP provides symmetric Bidirectional communication.
EPP+ECP Allows the parallel port to support both the ECP and EPP modes simultaneously.
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Parallel Port IRQ
This option specifies the IRQ used by the parallel port.
Option Description
IRQ5 Set this value to allow the serial port to use Interrupt 5.
IRQ7 Set this value to allow the serial port to use Interrupt 7. The majority of parallel ports on computer
systems use IRQ7 and I/O Port 378H as the standard setting.
8.3.7 USB Configuration
USB Configuration Settings
You can use this screen to specify options for the USB configuration Settings. Use the up and
down < Arrow > keys to select an item. Use the < + > and < - > keys to change the value of
the selected option. The settings are described on the following pages. The screen is shown below.
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USB Function
Set this value to allow the system to Disable, Enable, and select a set number of onboard USB ports.
USB 2.0 Controller
Depends on the setting of USB Function. If USB Function is set to Disabled, this option will have
no effect. Enabled will open USB 2.0 functionality to all USB ports.
USB 2.0 Controller Mode
The USB 2.0 Controller Mode configures the data rate of the USB port. The options are
FullSpeed (12 Mbps) and HiSpeed (480 Mbps).
Legacy USB Support
Legacy USB Support refers to USB mouse and keyboard support. Normally if this option is
not enabled, any attached USB mouse or keyboard will not become available until a USB
compatible operating system is fully booted with all USB drivers loaded. When this option is
enabled, any attached USB mouse or keyboard can control the system even when there are
no USB drivers loaded on the system. Set this value to enable or disable the Legacy USB
Support (see below).
Option Description
Disabled Set this value to prevent the use of any USB device in DOS or during system boot.
Enabled Set this value to allow the use of USB devices during boot and while using DOS.
Auto This option auto detects USB Keyboards or Mice and if found, allows them to be utilized during boot
and while using DOS.
USB Beep Message
Allows you to Enable/Disable the beep during USB device enumeration.
BIOS EHCI hand-off
This option provides a work around for OSes without ECHI hand-off support. The EHCI
ownership change should be claimed by the EHCI driver.
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USB Mass Storage Device Configuration
This is a submenu for configuring the USB Mass Storage Class Devices when BIOS finds
they are in use on the USB ports. Emulation Type can be set according to the type of
attached USB mass storage device(s). ). If set to Auto, USB devices less than 530MB will be
emulated as Floppy and those greater than 530MB will remain as hard drive. The Forced
FDD option can be used to force a hard disk type drive (such as a Zip drive) to boot as FDD.
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8.3.8 PCI Express Configuration
You can use this screen to specify options for the PCI Express Configuration Settings.
Active State Power-Management
This option allows you to enable/disable the Active State Power Management (ASPM)
function. ASPM is a PCIe power management specification.
PCIE Ports 0-3 Configuration
Allows you to configure the PCIE0~PCIE3 of the south bridge as one x4 slot or four x1 slots.
This function is only available on the Extended Version module supporting six PCIe x1.
PCIE Port (0-5) IOxAPIC Enable
This function is used to control the availability of the PCIE Port 0~5 IOxAPIC.
PCIE High Priority Port
This function is used to select a PCIE port as high priority port. Transactions on this port
have higher priority than other ports.
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8.3.9 PCIPnP Configuration
You can use this screen to specify options for Plug and Play BIOS Configuration.
Clear NVRAM
This option clears ESCD (Extended System Configuration Data) information in NVRAM.
Plug & Play O/S
When set to "Yes" and a Plug and Play operating system is installed, the operating system
configures the Plug and Play devices not required for boot.
PCI Latency Timer
Set this value to allow the PCI Latency Timer to be adjusted. This option sets the latency of
all PCI devices on the PCI bus.
Allocate IRQ to PCI VGA
When set to "Yes", the BIOS will assign an IRQ for a PCI VGA card.
IRQ
Set this value to allow the IRQ settings to be modified. Available - This setting allows the
specified IRQ to be used by a PCI/PnP device. Reserved - This setting allows the specified
IRQ to be used by a legacy ISA device.
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8.3.10 Remote Access Configuration
Remote Access Configuration
Remote access configuration provides the settings to allow remote access by another
computer to get POST messages and send commands through serial port access. This
screen will not be visible if the module is used on a carrier w/o a SuperIO chip, due to lack of
serial port support.
Remote Access
Select this option to Enable or Disable the BIOS remote access feature here.
Enabled Remote Access requires a dedicated serial port connection. Once both serial
ports are configured to disabled, you should set this value to Disabled or it may cause
abnormal boot.
Serial Port Number
Select the serial port you want to use for the remote access interface. You can set the value
for this option to either COM1 or COM2.
If you have changed the resource assignment of the serial ports in Advanced>Onboard
Device Configuration>SuperIO Configuration, you must Save Changes and Exit, reboot the
system, and enter the setup menu again in order to see those changes reflected in the
available Remote Access options.
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Serial Port Mode
Select the baud rate you want the serial port to use for console redirection. The options are
115200 8,n,1; 57600 8,n,1; 19200 8,n,1; and 09600 8,n,1.
Flow Control
Set this option to select Flow Control for console redirection. The settings for this value are None,
Hardware, or Software.
Redirection After BIOS POST
This option allows you to set Redirection configuration after BIOS POST. The settings for this
value are Disabled, Boot Loader, or Always.
Option Description
Disabled Set this value to turn off the redirection after POST
Boot Loader Set this value to allow the redirection to be active during POST and Boot Loader.
Always Set this value to allow the redirection to be always active.
Terminal Type
This option is used to select either VT100/VT-UTF8 or ANSI terminal type. The settings for this
value are ANSI, VT100, or VT-UTF8.
VT-UTF8 Combo Key Support
This option enables VT-UTF8 Combination Key Support for ANSI/VT100 terminals. The settings
for this value are Enabled or Disabled.
Sredir Memory Display Delay
This option gives the delay in seconds to display memory information. The options for this value
are No Delay, Delay 1 Sec, Delay 2 Sec, or Delay 4 Sec.
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8.3.11 Trusted Computing
Trusted computing is an industry standard to make personal computers more secure through a
dedicated hardware chip, called a Trusted Platform Module (TPM). This option allows you to
enable or disable the TPM support.
Execute TPM Command
This field is used to Enable(activate)/Disable(deactivate) the Execute TPM Command
function.
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8.4 Power Management
Select the Power tab from the setup screen to enter the power management BIOS Setup screen.
You can select any of the items in the left frame of the screen, such as ACPI Configuration, to go
to the sub menu for that item. The power management BIOS Setup screen is shown below.
8.4.1 ACPI Configuration
Advanced ACPI Configuration
You can use this screen to select options for the ACPI Advanced Configuration Settings. Use the
up and down < Arrow > keys to select an item. Use the < + > and < - > keys to change the
value of the selected option. A description of the selected item appears on the right side of the
screen. The settings are described on this page. The screen is shown below.
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ACPI Aware O/S
The item allows you to set the BIOS for an ACPI aware operation. Options: Yes/No.
ACPI Version Features
The item allows you to select the ACPI version.
ACPI APIC Support
Used to enable or disable the Advanced Programmable Interrupt Controller (APIC) for
PC2001 compliance. Enabling APIC mode will expand available IRQs resources for the
system
USB Device Wakeup from S3/S4
This option allows a USB device to wake up the system from S3/S4. Options: enabled/
diasbled.
AMI OEMB Table
Include OEMB table pointer to R(X)SDT pointer lists.
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Suspend mode
This setting selects either S1 (POS) or S3 (STR) system suspend mode. The Optimal and
Fail-Safe Default setting is S3 (STR).
Option Description
S1 (POS) Power On Suspend - Under this setting the
supply system level reference of S0 are off, system memory context is maintained, devices that
reference power resources that are on are on, and devices that can wake-up the system can cause
the cpu to continue to execute from where it left off.
S3 (STR) Suspend to RAM - Under this setting the system enters a low power state instead of being
completely shut off. This allows the computer system to boot up in a few seconds.
CPU
is not executing instructions, all power resources that
Headless mode
This is a server-specific feature. A headless server is one that operates without a keyboard,
monitor or mouse. To run in headless mode, both BIOS and operating system (e.g. Windows
Server 2003) must support headless operation
Restore on AC Power Loss
Determines what state the computer enters when AC power is restored after a power loss.
The options for this value are Last State, Power On and Power Off.
Option Description
Power Off Set this value to always power off the system while AC power is restored.
Power On Set this value to always power on the system while AC power is restored.
Last State
Set this value to power off/on the system depending on the last system power state while AC power is
restored.
ACPI OS Shutdown Mode
Option Description
AT System will display “It's Now Safe To Turn Off Your Computer” and wait for manual power off.
ATX System will automatically power down.
AT mode does not support S3 & S4.
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8.4.2 APM Configuration
Select the Advanced tab from the setup screen to enter the APM Configuration Setup screen.
You can display a Power Management/APM Setup option by highlighting it using the <
Arrow > keys.
Power Management/APM
Set this value to Enable or Disable Power Management/APM (Advanced Power
Management) features.
Power Button Mode
This option sets the function of the power button. Options: On/Off, Suspend.
Suspend Time Out
This option specifies the length of time the system waits before it enters suspend mode. The
options are Disabled, 1 Min, 2 Min, 4 Min, 8 Min, 10 Min, 20 Min, 30 Min, 40 Min, 50 Min,
and 60 Min.
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Video Power Down Mode
This option specifies the Power State that the video subsystem enters when the BIOS places
it in a power saving state after the specified period of display inactivity has expired. The
options are Disabled and Suspend.
Suspend Time Out
This option specifies the length of time the system waits before it enters suspend mode. The
options are Disabled, 1 Min, 2 Min, 4 Min, 8 Min, 10 Min, 20 Min, 30 Min, 40 Min, 50 Min, and
60 Min.
Hard Disk Drive Power Down Mode
This option specifies the power conserving state that the hard disk drive enters after the
specified period of hard drive inactivity has expired.
Advanced Resume Event Controls
These settings specify which events will generate a system wake event. The available events are
On LAN, PME# and RTC Alarm. The options are Enabled and Disabled.
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8.4.3 Hardware Health Configuration
Voltage and temperature monitoring is supported onboard. Fan speed monitoring is
supported by the Super IO on the carrier board.
Throttle Temperature
This setting determines the temperature of the thermal trip point at which PROCHOT#
becomes active. Above this temperature the CPU will be throttled according to the value set
for Throttle Duty. Options: Disabled, 65°C/149°F, 70°C/158°F, 75°C/167°F, 80°C/176°F,
85°C/185°F, 90°C/194°F, 95°C/203°F
Throttle Duty
This setting determines the throttle duty of the CPU when the its temperature exceeds the
thermal trip point set by the Throttle Temperature option. Options: 12.5%, 25%, 37.5%,
50%, 62.5%, 75%, 87.5%
Critical Temperature
This setting determines the temperature at which the THERMTRIP# signal becomes active,
causing the system to reboot. Options: Disabled, 80°C/176°F, 85°C/185°F, 90°C/194°F,
95°C/203°F.
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8.5 Boot Setup
Select the Boot tab from the setup screen to enter the Boot BIOS Setup screen. You can
select any of the items in the left frame of the screen, such as Boot Device Priority, to go to
the sub menu for that item. You can display an Boot BIOS Setup option by highlighting it
using the < Arrow > keys. The Boot Settings screen is shown below:
Boot Settings Configuration
Use this screen to select options for the Boot Settings Configuration. Use the up and down
<Arrow> keys to select an item. Use the <Plus> and <Minus> keys to change the value of the
selected option. The settings are described on the following pages. The screen is shown below.
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Quick Boot
Disabled - Set this value to allow the BIOS to perform all POST tests.
Enabled - Set this value to allow the BIOS to skip certain POST tests to boot faster.
Quiet Boot
Disabled - Set this value to allow the computer system to display the POST messages.
Enabled - Set this value to allow the computer system to display the OEM logo.
AddOn ROM Display Mode
This BIOS feature controls the display of ROM messages from the BIOS of add-on devices
like the graphics card or the SATA controller during the boot sequence. When set to Force
BIOS, AddOn ROM messages will be forced to display during the boot sequence. When set
to Keep Current, AddOn ROM messages will only be displayed if the third-party manufacturer
had set the add-on device to do so.
An AddOn ROM typically consists of firmware that is called by the system BIOS. For example,
an adapter card that controls a boot device might contain firmware that is used to connect
the device to the system once the AddOn ROM is loaded.
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Bootup Num-Lock
Set this value to allow the Number Lock setting to be modified during boot up.
Off - This option does not enable the keyboard Number Lock automatically. To use the 10-
keys on the keyboard, press the Number Lock key located on the upper left-hand corner of the
10-key pad. The Number Lock LED on the keyboard will light up when the Number Lock is
engaged.
On - Set this value to allow the Number Lock on the keyboard to be enabled automatically
when the computer system is boot up. This allows the immediate use of 10-keys numeric
keypad located on the right side of the keyboard. To confirm this, the Number Lock LED light on
the keyboard will be lit.
PS/2 Mouse Support
Allows you to Enable/Disable PS/2 mouse support.
Wait for ‘F1’ If Error
If this option is set to Disabled, AMIBIOS does not wait for you to press the <F1> key after an error
message.
Hit ‘DEL’ Message Display
When set to Enabled, the system displays the message "Press DEL to run Setup during POST".
Interrupt 19 Capture
Interrupt 19 is the software interrupt that handles the boot disk function. When enabled, this BIOS
feature allows the AddOn ROM of these host adaptors to “capture” Interrupt 19 during the boot
process so that drives attached to these adaptors can function as bootable disks. In addition, it
allows you to gain access to the host adaptor’s AddOn ROM setup utility, if one is available.
When disabled, the AddOn ROM of these host adaptors will not be able to “capture” interrupt 19.
Therefore, you will not be able to boot operating systems from any bootable disks attached to
these host adaptors. Nor will you be able to gain access to their AddOn ROM utilities.
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Boot Device Priority
Set the boot device options to determine the sequence in which the computer checks which
device to boot from.
Boot Device Groups
The Boot devices are listed in groups by device type. First press <Enter> to enter the submenu. Then you may use the arrow keys to select the desired device, then press <+>, <-> or
<PageUp>, <PageDown> key to move it up/down in the priority list. For example, USB storage
disks will be listed as “USB Drives” in the sub-menu as below. Only the first device in each device
group will be available for selection in the Boot Device Priority option.
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8.6 Security Setup
8.6.1 Password Support
Two Levels of Password Protection
Provides both a Supervisor and a User password. If you use both passwords, the Supervisor
password must be set first.
The system can be configured so that all users must enter a password every time the system
boots or when Setup is executed, using either or either the Supervisor password or User
password.
The Supervisor and User passwords activate two different levels of password security. If you
select password support, you are prompted for a one to six character password. Type the
password on the keyboard. The password does not appear on the screen when typed. Make
sure you write it down. If you forget it, you must drain NVRAM and re-configure.
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Remember the Password
Keep a record of the new password when the password is changed. If you forget the
password, you must erase the system configuration information in NVRAM.
Select Security Setup from the Setup main BIOS setup menu. Security Setup options, such as
password protection and virus protection, are described in this section. To access the sub menu
for the following items, select the item and press < Enter >:
- Change Supervisor Password
- Change User Password
- Clear User Password
Supervisor Password
Indicates whether a supervisor password has been set.
User Password
Indicates whether a user password has been set.
Change Supervisor Password
Select this option and press < Enter > to access the sub menu. You can use the sub menu to
change the supervisor password.
Change User Password
Select this option and press < Enter > to access the sub menu. You can use the sub menu to
change the user password.
Clear User Password
Select this option and press < Enter > to access the sub menu. You can use the sub menu to
clear the user password.
8.6.2 Change Supervisor Password
Select Change Supervisor Password from the Security Setup menu and press < Enter >.
Enter New Password:
Type the password and press < Enter >. The screen does not display the characters entered.
Retype the password as prompted and press < Enter >. If the password confirmation is incorrect,
an error message appears. The password is stored in NVRAM after setup completes.
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8.6.3 Change User Password
Select Change User Password from the Security Setup menu and press < Enter >.
Enter New Password:
Type the password and press < Enter >. The screen does not display the characters entered.
Retype the password as prompted and press < Enter >. If the password confirmation is incorrect,
an error message appears. The password is stored in NVRAM after setup completes.
8.6.4 Clear User Password
Select Clear User Password from the Security Setup menu and press < Enter >.
Clear New Password
[Ok] [Cancel]
Type the password and press < Enter >. The screen does not display the characters entered.
Retype the password as prompted and press < Enter >. If the password confirmation is incorrect,
an error message appears. The password is stored in NVRAM after setup completes.
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8.7 Exit Menu
Select the Exit tab from the setup screen to enter the Exit BIOS Setup screen. You can display an
Exit BIOS Setup option by highlighting it using the < Arrow > keys. The Exit BIOS Setup
screen is shown below.
Save Changes and Exit
When you have completed the system configuration changes, select this option to leave Setup
and reboot the computer so the new system configuration parameters can take effect. Select Exit
Saving Changes from the Exit menu and press < Enter >.
Save Configuration Changes and Exit Now?
[Ok] [Cancel]
appears in the window. Select Ok to save changes and exit.
Discard Changes and Exit
Select this option to quit Setup without making any permanent changes to the system
configuration. Select Exit Discarding Changes from the Exit menu and press <Enter>.
Discard Changes and Exit Setup Now?
[Ok] [Cancel]
appears in the window. Select Ok to discard changes and exit.
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Discard Changes
Select Discard Changes from the Exit menu and press < Enter >.
Select Ok to discard changes.
Load Optimal Defaults
Automatically sets all Setup options to a complete set of default settings when you Select this
option. The Optimal settings are designed for maximum system performance, but may not work
best for all computer applications. In particular, do not use the Optimal Setup options if your
computer is experiencing system configuration problems.
Select Load Optimal Defaults from the Exit menu and press < Enter >.
Select Ok to load optimal defaults.
Load Failsafe Defaults
Automatically sets all Setup options to a complete set of default settings when you Select this
option. The Failsafe settings are designed for maximum system stability, but not maximum
performance. Select the Fail-Safe Setup options if your computer is experiencing system
configuration problems.
Select Load Fail-Safe Defaults from the Exit menu and press < Enter >.
Load Fail-Safe Defaults?
[Ok] [Cancel]
appears in the window. Select Ok to load Fail-Safe defaults.
Express-LPC User’s ManualPage 72
9 BIOS Checkpoints, Beep Codes
This section of this document lists checkpoints and beep codes generated by AMIBIOS. The
checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not
include any chipset or board specific checkpoint definitions.
Checkpoints and Beep Codes Definition
A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints
throughout bootblock and Power-On Self Test (POST) to indicate the task the system is currently
executing. Checkpoints are very useful for debugging problems that occur during the preboot process.
Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error
occurs before the system video has been initialized, and generated by the system board speaker.
Viewing BIOS Checkpoints
Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a
“POST Card” or “POST Diagnostic Card”. These are ISA or PCI add-in cards that show the value
of I/O port 80h on a LED display.
Some computers display checkpoints in the bottom right corner of the screen during POST. This
display method is limited, since it only displays checkpoints that occur after the video card has
been activated.
Keep in mind that not all computers using AMIBIOS enable this feature. In most cases, a
checkpoint card is the best tool for viewing AMIBIOS checkpoints.
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9.1 Bootblock Initialization Code Checkpoints
The Bootblock initialization code sets up the chipset, memory and other components before
system memory is available. The following table describes the type of checkpoints that may occur
during the bootblock initialization portion of the BIOS:
Checkpoints may differ between different platforms based on system configuration.
Checkpoints may change due to vendor requirements, system chipset or option ROMs
from add-in PCI devices.
Checkpoint Description
Before D0 If boot block debugger is enabled, CPU cache-as-RAM functionality is enabled at this point.
Stack will be enabled from this point.
D0 Early Boot Strap Processor (BSP) initialization like microcode update, frequency and other CPU
critical initialization. Early chipset initialization is done.
D1 Early super I/O initialization is done including RTC and keyboard controller. Serial port is
enabled at this point if needed for debugging. NMI is disabled. Perform keyboard controller BAT
test. Save power-on CPUID value in scratch CMOS. Go to flat mode with 4GB limit and GA20
enabled.
D2 Verify the boot block checksum. System will hang here if checksum is bad.
D3 Disable CACHE before memory detection. Execute full memory sizing module. If memory sizing
module not executed, start memory refresh and do memory sizing in Boot block code. Do
additional chipset initialization. Re-enable CACHE. Verify that flat mode is enabled.
D4 Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.
D5 Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS
now executes out of RAM. Copies compressed boot block code to memory in right segments.
Copies BIOS from ROM to RAM for faster access. Performs main BIOS checksum and updates
recovery status accordingly.
D6 Both key sequence and OEM specific method is checked to determine if BIOS recovery is
forced. If BIOS recovery is necessary, control flows to checkpoint E0. See Bootblock Recovery
Code Checkpoints section of document for more information.
D7 Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to
system memory and control is given to it. Determine whether to execute serial flash.
D8 The Runtime module is uncompressed into memory. CPUID information is stored in memory.
D9 Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory.
Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but closing
SMRAM.
DA Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel). See
POST Code Checkpoints section of document for more information.
DC System is waking from ACPI S3 state
E1-E8, EC-EE OEM memory detection/configuration error. This range is reserved for chipset vendors & system
manufacturers. The error associated with this value may be different from one platform to the
next.
Express-LPC User’s ManualPage 74
9.2 Bootblock Recovery Code Checkpoints
The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery
needs to occur because the user has forced the update or the BIOS checksum is corrupt. The
following table describes the type of checkpoints that may occur during the Bootblock recovery
portion of the BIOS:
Checkpoints may differ between different platforms based on system configuration.
Checkpoints may change due to vendor requirements, system chipset or option ROMs
From add-in PCI devices.
Checkpoint Description
E0 Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA
controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled.
E9 Set up floppy controller and data. Attempt to read from floppy.
EA Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM.
EB Disable ATAPI hardware. Jump back to checkpoint E9.
EF Read error occurred on media. Jump back to checkpoint EB.
F0 Search for pre-defined recovery file name in root directory.
F1 Recovery file not found.
F2 Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file.
F3 Start reading the recovery file cluster by cluster.
F5 Disable L1 cache.
FA Check the validity of the recovery file configuration to the current configuration of the flash part.
FB Make flash write enabled through chipset and OEM specific method. Detect proper flash part.
Verify that the found flash part size equals the recovery file size.
F4 The recovery file size does not equal the found flash part size.
FC Erase the flash part.
FD Program the flash part.
FF The flash has been updated successfully. Make flash write disabled. Disable ATAPI hardware.
Restore CPUID value back into register. Give control to F000 ROM at F000:FFF0h.
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9.3 POST Code Checkpoints
The POST code checkpoints are the largest set of checkpoints during the BIOS preboot process. The
following table describes the type of checkpoints that may occur during the POST portion of the BIOS:
Checkpoints may differ between different platforms based on system configuration.
Checkpoints may change due to vendor requirements, system chipset or option ROMs
From add-in PCI devices.
Checkpoint Description
03 Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data
area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as
mentioned in the Kernel Variable "wCMOSFlags."
04 Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK.
Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad,
update CMOS with power-on default values and clear passwords. Initialize status register A.
Initializes data variables that are based on CMOS setup questions. Initializes both the 8259
compatible PICs in the system
05 Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
06 Do R/W test to CH-2 count reg. Initialize CH-0 as system timer.Install the POSTINT1Ch handler.
Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to
"POSTINT1ChHandlerBlock."
07 Fixes CPU POST interface calling pointer.
08 Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller
command byte is being done after Auto detection of KB/MS using AMI KB-5.
C0 Early CPU Init Start -- Disable Cache – Init Local APIC
C1 Set up boot strap processor Information
C2 Set up boot strap processor for POST
C5 Enumerate and set up application processors
C6 Re-enable cache for boot strap processor
C7 Early CPU Init Exit
0A Initializes the 8042 compatible Key Board Controller.
0B Detects the presence of PS/2 mouse.
0C Detects the presence of Keyboard in KBC port.
0E Testing and initialization of different Input Devices. Also, update the Kernel Variables.
Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress
all available language, BIOS logo, and Silent logo modules.
13 Early POST initialization of chipset registers.
20 Relocate System Management Interrupt vector for all CPU in the system.
24 Uncompress and initialize any platform specific BIOS modules. GPNV is initialized at this
checkpoint.
2A Initializes different devices through DIM. See DIM Code Checkpoints section of document for
more information.
2C Initializes different devices. Detects and initializes the video adapter installed in the system that
have optional ROMs.
2E Initializes all the output devices.
Express-LPC User’s ManualPage 76
POST Code Checkpoints cont’d:
Checkpoint Description
31 Allocate memory for ADM module and uncompress it. Give control to ADM module for
initialization. Initialize language and font modules for ADM. Activate ADM module.
33 Initializes the silent boot module. Set the window for displaying text information.
37 Displaying sign-on message, CPU information, setup key message, and any OEM specific
information.
38 Initializes different devices through DIM. See DIM Code Checkpoints section of document for
more information. USB controllers are initialized at this point.
39 Initializes DMAC-1 & DMAC-2.
3A Initialize RTC date/time.
3B Test for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory
test. Display total memory in the system.
3C Mid POST initialization of chipset registers.
40 Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, … etc.)
successfully installed in the system and update the BDA, EBDA…etc.
52 Updates CMOS memory size from memory found in memory test. Allocates memory for
Extended BIOS Data Area from base memory. Programming the memory hole or any kind of
implementation that needs an adjustment in system RAM size if needed.
60 Initializes NUM-LOCK status and programs the KBD typematic rate.
75 Initialize Int-13 and prepare for IPL detection.
78 Initializes IPL devices controlled by BIOS and option ROMs.
7C Generate and write contents of ESCD in NVRam.
84 Log errors encountered during POST.
85 Display errors to the user and gets the user response for error.
87 Execute BIOS setup if needed / requested. Check boot password if installed.
8C Late POST initialization of chipset registers.
8D Build ACPI tables (if ACPI is supported)
8E Program the peripheral parameters. Enable/Disable NMI as selected
90 Initialization of system management interrupt by invoking all handlers. Please note this
checkpoint comes right after checkpoint 20h
A1 Clean-up work needed before booting to OS.
A2 Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h
segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language
module. Disables the system configuration display if needed.
A4 Initialize runtime language module. Display boot option popup menu.
A7 Displays the system configuration screen if enabled. Initialize the CPU’s before boot, which
includes the programming of the MTRR’s.
A9 Wait for user input at config display if needed.
AA Uninstall POST INT1Ch vector and INT09h vector.
AB Prepare BBS for Int 19 boot. Init MP tables.
AC End of POST initialization of chipset registers. De-initializes the ADM module.
B1 Save system context for ACPI. Prepare CPU for OS boot including final MTRR values.
00 Passes control to OS Loader (typically INT19h).
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9.4 OEM POST Error Checkpoints
Checkpoints from the range 61h to 70h are reserved for chipset vendors & system
manufacturers. The error associated with this value may be different from one platform to the next.
9.5 DIM Code Checkpoints
The Device Initialization Manager (DIM) gets control at various times during BIOS POST to
initialize different system busses. The following table describes the main checkpoints where the
DIM module is accessed:
Checkpoints may differ between different platforms based on system configuration.
Checkpoints may change due to vendor requirements, system chipset or option ROMs
from add-in PCI devices.
Checkpoint Description
2A Initialize different buses and perform the following functions: Reset, Detect, and Disable
(function 0); Static Device Initialization (function 1); Boot Output Device Initialization (function 2).
Function 0 disables all device nodes, PCI devices, and PnP ISA cards. It also assigns PCI bus
numbers. Function 1 initializes all static devices that include manual configured onboard
peripherals, memory and I/O decode windows in PCI- PCI bridges, and noncompliant PCI
devices. Static resources are also reserved. Function 2 searches for and initializes any PnP,
PCI, or AGP video devices.
38 Initialize different buses and perform the following functions: Boot Input Device Initialization
(function 3); IPL Device Initialization (function 4); General Device Initialization (function 5).
Function 3 searches for and configures PCI input devices and detects if system has standard
keyboard controller. Function 4 searches for and configures all PnP and PCI boot devices.
Function 5 configures all onboard peripherals that are set to an automatic configuration and
configures all remaining PnP and PCI devices.
While control is in the different functions, additional checkpoints are output to port 80h as a
word value to identify the routines under execution. The low byte value indicates the main
POST Code Checkpoint. The high byte is divided into two nibbles and contains two fields. The
details of the high byte of these checkpoints are as follows:
Express-LPC User’s ManualPage 78
HIGH BYTE XY
The upper nibble ‘X’ indicates the function number that is being executed. ‘X’ can be from 0 to 7.
0 = func#0, disable all devices on the BUS concerned.
1 = func#1, static devices initialization on the BUS concerned.
2 = func#2, output device initialization on the BUS concerned.
3 = func#3, input device initialization on the BUS concerned.
4 = func#4, IPL device initialization on the BUS concerned.
5 = func#5, general device initialization on the BUS concerned.
6 = func#6, error reporting for the BUS concerned.
7 = func#7, add-on ROM initialization for all BUSes.
8 = func#8, BBS ROM initialization for all BUSes.
The lower nibble ‘Y’ indicates the BUS on which the different routines are being executed. ‘Y’ can
be from 0 to 5.
0 = Generic DIM (Device Initialization Manager).
1 = Onboard System devices.
2 = ISA devices.
3 = EISA devices.
4 = ISA PnP devices.
5 = PCI devices.
9.6 ACPI Runtime Checkpoints
ACPI checkpoints are displayed when an ACPI capable operating system either enters or
leaves a sleep state. The following table describes the type of checkpoints that may occur
during ACPI sleep or wake events:
Checkpoints may differ between different platforms based on system configuration.
Checkpoints may change due to vendor requirements, system chipset or option ROMs
from add-in PCI devices.
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9.7 Boot Block Beep Codes
No. of Beeps Description
1 Insert diskette in floppy drive A:
2 ‘AMIBOOT.ROM’ file not found in root directory of diskette in A:
3 Base Memory error
4 Flash Programming successful
5 Floppy read error
6 Keyboard controller BAT command failed
7 No Flash EPROM detected
8 Floppy controller failure
9 Boot Block BIOS checksum error
10 Flash Erase error
11 Flash Program error
12 ‘AMIBOOT.ROM’ file size error
13 BIOS ROM image mismatch (file layout does not match image present in flash device)
9.8 POST BIOS Beep Codes
No. of Beeps Description
1 Memory refresh timer error.
2 Parity error in base memory (first 64KB block)
3 Base memory read/write test error
4 Motherboard timer not operational
5 Processor error
6 8042 Gate A20 test error (cannot switch to protected mode)
7 General exception error (processor exception interrupt error)
8 Display memory error (system video adapter)
9 AMIBIOS ROM checksum error
10 CMOS shutdown register read/write error
11 Cache memory test failed
Express-LPC User’s ManualPage 80
9.9 Troubleshooting POST BIOS Beep Codes
No. of Beeps Description
1, 2 or 3 Reseat the memory, or replace with known good modules.
4-7, 9-11 Fatal error indicating a serious problem with the system. Consult your system manufacturer.
Before declaring the motherboard beyond all hope, eliminate the possibility of interference by a
malfunctioning add-in card. Remove all expansion cards except the video adapter.
- If beep codes are generated when all other expansion cards are absent, consult your system
manufacturer’s technical support.
- If beep codes are not generated when all other expansion cards are absent, one of the add-in
cards is causing the malfunction. Insert the cards back into the system one at a time until the
problem happens again. This will reveal the malfunctioning card.
8 If the system video adapter is an add-in card, replace or reseat the video adapter. If the video
adapter is an integrated part of the system board, the board may be faulty.
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Important Safety Instructions
For user safety, please read and follow all instructions, warnings, cautions, and notes
marked in this manual and on the associated equipment before handling/operating the
equipment.
f Read these safety instructions carefully.
f Keep this user’s manual for future reference.
f Read the specifications section of this manual for detailed information on the operating
environment of this equipment.
f When installing/mounting or uninstalling/removing equipment:
- Turn off power and unplug any power cords/cables.
f To avoid electrical shock and/or damage to equipment:
- Keep equipment away from water or liquid sources;
- Keep equipment away from high heat or high humidity;
- Keep equipment properly ventilated (do not block or cover ventilation openings);
- Make sure to use recommended voltage and power source settings;
- Always install and operate equipment near an easily accessible electrical socket-outlet;
- Secure the power cord (do not place any object on/over the power cord);
- Only install/attach and operate equipment on stable surfaces and/or recommended
mountings; and,
- If the equipment will not be used for long periods of time, turn off and unplug the
equipment from its power source.
f Never attempt to fix the equipment. Equipment should only be serviced by qualified
personnel.
f A Lithium-type battery may be provided for uninterrupted, backup or emergency power.
Risk of explosion if battery is replaced by an incorrect type. Dispose of used batteries
according to the instructions.
Express-LPC User’s ManualPage 82
f Equipment must be serviced by authorized technicians when:
- The power cord or plug is damaged;
- Liquid has penetrated the equipment;
- It has been exposed to high humidity/moisture;
- It is not functioning or does not function according to the user’s manual;
- It has been dropped and/or damaged; and/or,
- It has an obvious sign of breakage.
Page 83Express-IA533 User’s Manual Page 83Express-IA533 User’s ManualExpress-LPC User’s Manual Page 83
Getting Service
Contact us should you require any service or assistance.
ADLINK Technology, Inc.
Address: 9F, No.166 Jian Yi Road, Zhonghe District
New Taipei City 235, Taiwan
ᄅקؑխࡉ৬ԫሁ 166 ᇆ 9 ᑔ
Tel: +886-2-8226-5877
Fax: +886-2-8226-5717
Email: service@adlinktech.com
Ampro ADLINK Technology, Inc.
Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA
Tel: +1-408-360-0200
Toll Free: +1-800-966-5200 (USA only)
Fax: +1-408-360-0222
Email: info@adlinktech.com
ADLINK Technology (China) Co., Ltd.
Address: Ϟ⍋Ꮦ⌺ϰᮄᓴ∳催⾥ᡔು㢇䏃 300 ো(201203)
300 Fang Chun Rd., Zhangjiang Hi-Tech Park,
Pudong New Area, Shanghai, 201203 China
Tel: +86-21-5132-8988
Fax: +86-21-5132-3588
Email: market@adlinktech.com
ADLINK Technology Beijing
Address: ࣫ҀᏖ⍋⎔Ϟഄϰ䏃 1 োⲜ߯ࡼ E ᑻ 801 ᅸ(100085)
Rm. 801, Power Creative E, No. 1, B/D
Shang Di East Rd., Beijing, 100085 China
Tel: +86-10-5885-8666
Fax: +86-10-5885-8625
Email: market@adlinktech.com
ADLINK Technology Shenzhen
Address: ⏅ഇᏖቅ⾥ᡔು催ᮄϗ䘧᭄ᄫᡔᴃು
A1 2 ὐ C (518057)
2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7,
High-Tech Industrial Park S., Shenzhen, 518054 China
Tel: +86-755-2643-4858
Fax: +86-755-2664-6353
Email: market@adlinktech.com
ADLINK Technology (Europe) GmbH
Address: Nord Carree 3, 40477 Duesseldorf, Germany
Tel: +49-211-495-5552
Fax: +49-211-495-5557
Email: emea@adlinktech.com
Express-LPC User’s ManualPage 84
ADLINK Technology, Inc. (French Liaison Office)
Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France
Tel: +33 (0) 1 60 12 35 66
Fax: +33 (0) 1 60 12 35 66
Email: france@adlinktech.com
ADLINK Technology Japan Corporation
Address: ͱ101-0045 ᵅҀ䛑ҷ⬄⼲⬄䤯ފ⬎ 3-7-4
⼲⬄ 374 ɛɳ 4F
KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho,
Chiyoda-ku, Tokyo 101-0045, Japan
Tel: +81-3-4455-3722
Fax: +81-3-5209-6013
Email: japan@adlinktech.com
ADLINK Technology, Inc. (Korean Liaison Office)
Address: 昢殾柢 昢爎割 昢爎壟 1675-12 微汾瘶捒娯 8猻
8F Mointer B/D,1675-12, Seocho-Dong, Seocho-Gu,
Seoul 137-070, Korea
Tel: +82-2-2057-0565
Fax: +82-2-2057-0563
Email: korea@adlinktech.com
ADLINK Technology Singapore Pte. Ltd.
Address: 84 Genting Lane #07-02A, Cityneon Design Centre,
Singapore 349584
Tel: +65-6844-2261
Fax: +65-6844-2263
Email: singapore@adlinktech.com
ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)
Address: 1st Floor, #50-56 (Between 16th/17th Cross) Margosa Plaza,
Margosa Main Road, Malleswaram, Bangalore-560055, India
Tel: +91-80-65605817, +91-80-42246107
Fax: +91-80-23464606
Email: india@adlinktech.com
ADLINK Technology, Inc. (Israeli Liaison Office)
Address: 6 Hasadna St., Kfar Saba 44424, Israel
Tel: +972-9-7446541
Fax: +972-9-7446542
Email: israel@adlinktech.com
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