ADLINK Express-IBE2 User Manual
Express-IBE2
User’s Manual
Manual Revision: 2.02
Revision Date: December 3, 2014
Part Number: 50-1J045-1020
Revision History
Revision Description Date By
2.00 Initial release 2013-08-30 JC
2.01 Correct CPU models, GBE0_MDI0- pin description; remove "Type 6", "USB 3.0", "QNX"; update
Functional Diagram
2.02 Add BIOS beep codes; remove Industrial Temp. SKU 2014-12-03 JC
2014-02-10 JC
Page 2 Express-IBE2
Preface
Copyright 2013-14 ADLINK Technology, Inc.
This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by
any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not
represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or
consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such
damages.
Environmental Responsibility
ADLINK is committed to fulfilling its social responsibility to global environmental preservation through compliance with the European Union's
Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental
protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and
raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to
dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their
respective companies.
Express-IBE2 Page 3
Table of Contents
Revision History ............................................................................................................ 2
Preface............................................................................................................................ 3
1. Introduction......................................................................................................... 7
2. Specifications....................................................................................................... 8
2.1. Core System..............................................................................................................................8
2.2. Expansion Busses......................................................................................................................9
2.3. Video.........................................................................................................................................9
2.4. Audio.........................................................................................................................................9
2.5. LAN ...........................................................................................................................................9
2.6. Multi I/O and Storage ...............................................................................................................9
2.7. Super I/O (on carrier using LPC -bus) .................................................................................... 10
2.8. GPIO........................................................................................................................... ............ 10
2.9. Board Controller .................................................................................................................... 10
2.10. Fan Control ............................................................................................................................ 10
2.11. Debug..................................................................................................................................... 10
2.12. Power Specifications ............................................................................................................. 11
2.13. Mechanical and Environmental............................................................................................. 11
2.14. Specification Compliance ...................................................................................................... 11
2.15. Functional Diagram................................................................................................................ 12
2.16. Mechanical Drawing .............................................................................................................. 13
3. COM Express Pinouts and Signal Descriptions ..............................................
3.1. AB / CD Pin Definitions .......................................................................................................... 14
3.2. Signal Description Terminology............................................................................................. 17
3.3. AB Signal Descriptions ........................................................................................................... 18
14
3.3.1. Audio Signals....................................................................................................................................18
3.3.2. Analog VGA ......................................................................................................................................18
3.3.3. LVDS .................................................................................................................................................19
3.3.4. Gigabit Ethernet...............................................................................................................................19
3.3.5. Serial ATA.........................................................................................................................................20
3.3.6. PCI Express.......................................................................................................................................21
3.3.7. Express Card.....................................................................................................................................21
3.3.8. LPC bus.............................................................................................................................................22
3.3.9. USB...................................................................................................................................................22
3.3.10. SPI (BIOS only).............................................................................................................................23
Page 4 Express-IBE2
3.3.11. Miscellaneous..............................................................................................................................23
3.3.12. SMBus..........................................................................................................................................24
3.3.13. I2C Bus.........................................................................................................................................24
3.3.14. General Purpose I/O (GPIO) ........................................................................................................24
3.3.15. Power And System Management................................................................................................25
3.3.16. Power and Ground ......................................................................................................................26
3.4. CD Signal Descriptions ........................................................................................................... 27
3.4.1. PATA IDE ..........................................................................................................................................27
3.4.2. PCI ....................................................................................................................................................28
3.4.3. PCI Express Graphics x16 (PEG) or SDVO .........................................................................................30
3.4.4. Module Type Definition ...................................................................................................................32
3.4.5. Power and Ground...........................................................................................................................32
4. Module Configuration ......................................................................................
33
4.1. PCI Express Configuration Switch (SW1) ............................................................................... 33
4.2. PCIe x16-to-two-x8 Adapter Card.......................................................................................... 33
5. System Resources.............................................................................................. 34
5.1. System Memory Map ............................................................................................................ 34
5.2. Direct Memory Access Channels ........................................................................................... 34
5.3. Legacy I/O Map...................................................................................................................... 35
5.4. Interrupt Request (IRQ) Lines................................................................................................ 36
5.5. PCI Configuration Space Map ................................................................................................ 38
5.6. PCI Interrupt Routing Map .................................................................................................... 39
6. BIOS Setup .........................................................................................................40
6.1. Starting the BIOS ................................................................................................................... 40
6.1.1. Setup Menu......................................................................................................................................41
6.1.2. Navigation........................................................................................................................................42
6.2. Main Setup ............................................................................................................................ 45
6.2.1. System Management.......................................................................................................................46
6.3. Advanced Setup..................................................................................................................... 48
6.3.1. ACPI Settings....................................................................................................................................48
6.3.2. Trusted Computing ..........................................................................................................................49
6.3.3. CPU Configuration............................................................................................................................50
6.3.4. SATA Configuration..........................................................................................................................51
6.3.5. Thermal Configuration.....................................................................................................................51
6.3.6. Intel TXT(LT) Configuration ..............................................................................................................53
6.3.7. PCH-FW Configuration.....................................................................................................................53
6.3.8. Intel Anti-Theft Technology Configuration ......................................................................................54
Express-IBE2 Page 5
6.3.9. AMT Configuration...........................................................................................................................55
6.3.10. USB Configuration .......................................................................................................................56
6.3.11. W8362DHG Super IO Configuration............................................................................................57
6.3.12. Serial Port Console Redirection...................................................................................................58
6.3.13. CPU PPM Configuration ..............................................................................................................59
6.4. Chipset Setup......................................................................................................................... 60
6.4.1. PCH-IO Configuration.......................................................................................................................60
6.4.2. System Agent (SA) Configuration.....................................................................................................64
6.5. Boot Setup ............................................................................................................................. 70
6.6. Security Setup........................................................................................................................ 71
6.7. Save & Exit Menu................................................................................................................... 72
7. BIOS Checkpoints, Beep Codes........................................................................ 73
7.1. Status Code Ranges ............................................................................................................... 74
7.2. Standard Status Codes........................................................................................................... 74
7.2.1. SEC Status Codes..............................................................................................................................74
7.2.2. SEC Beep Codes................................................................................................................................75
7.2.3. PEI Status Codes...............................................................................................................................75
7.2.4. PEI Beep Codes.................................................................................................................................77
7.2.5. DXE Status Codes .............................................................................................................................77
7.2.6. DXE Beep Codes...............................................................................................................................79
7.2.7. ACPI/ASL Checkpoint .......................................................................................................................80
7.3. OEM-Reserved Checkpoint Ranges ....................................................................................... 80
Safety Instructions ...................................................................................................... 81
Getting Service ............................................................................................................ 82
Page 6 Express-IBE2
1. Introduction
The Module Computing Product Segment (MCPS) is pleased to introduce its latest COM Express® Type 2 Module with Intel® Core™ i7/i5/i3
Processor and QM77 Chipset, the Express-IBE2.
The Express-IBE2 is a COM Express® COM.0 R2.1 Type 2 module with a 3rd Generation Intel® Core™ i7/i5/3 processor and support
for error-correcting code (ECC) memory.
Based on the latest Mobile Intel® QM77 Express Chipset, the Express-IBE2 is specifically designed for customers who need a highly
reliable platform and/or continued support for PCI-bus and PATA IDE in a long product life solution.
The Express-IBE2 features the Intel® Core™ i7/i5/i3 processor supporting Intel® Hyper-Threading Technology (up to 4 cores, 8 threads)
and DDR3 dual-channel memory at 1066/1333/1600 MHz with error-correcting code (ECC). Integrated HD Graphics 4000 includes features
such as OpenGL 3.1, DirectX11, Intel® Clear Video HD Technology, Advanced Scheduler 2.0, 1.0, XPDM support, and DirectX Video
Acceleration (DXVA) support for full AVC/VC1/MPEG2 hardware decode. Graphics outputs include VGA, LVDS and SDVO. In addition to
the onboard integrated graphics, a multiplexed PCI Express® x16 Graphics bus is available for discrete graphics expansion or general
purpose x8 or x4 PCI Express® connectivity. The Express-IBE2 features a single onboard Gigabit Ethernet port, four USB eight USB 2.0
ports, two SATA 6 Gb/s ports, two SATA 3 Gb/s ports and one PATA IDE port. Support is provided for SMBus and I
The module is equipped with an SPI AMI EFI BIOS and supports SEMA (Smart Embedded Management Agent). SEMA functionality is
consistent over ADLINK's whole COM product line and provides the following embedded features: BIOS failsafe,
voltage/current/temperature monitoring, power sequence control and monitoring, watchdog control, board info and statistics. SEMA comes
with extensive software and library support for Windows, Linux, and VxWorks.
2
C.
Express-IBE2 Page 7
2. Specifications
2.1. Core System
• CPU: 3rd Generation Intel® Core™ Processor, 2-core and 4-core mobile processor with Integrated Graphics, BGA 1023 type
• Intel® Core™ i7-3615QE Quad-Core at 2.3 GHz (3.3/3.1 GHz Turbo), 6MB L3 cache, 45W
• Intel® Core™ i7-3612QE Quad-Core at 2.1 GHz (3.1/2.8 GHz Turbo), 6MB L3 cache, 35W
• Intel® Core™ i7-3555LE Dual-Core at 2.5 GHz (3.2/3.1 GHz Turbo), 4MB L3 cache, 25W
• Intel® Core™ i7-3517UE Dual-Core at 1.7 GHz (2.8/2.6 GHz Turbo), 4MB L3 cache, 17W
• Intel® Core™ i5-3610ME Dual-Core at 2.7 GHz (3.3/3.1 GHz Turbo), 3MB L3 cache, 35W
• Intel® Core™ i3-3120ME Dual-Core at 2.4 GHz, 3MB L3 cache, 35W
• Intel® Core™ i3-3127UE Dual-Core at 1.6 GHz, 3MB L3 cache, 17W
• Intel® Celeron® 1020E Dual-Core at 2.20 GHz, 2MB L3 Cache, 35W
• Intel® Celeron® 1047UE Dual-Core at 1.40 GHz, 2MB L3 Cache, 17W
• Intel® Celeron® 927UE Single-Core at 1.50 GHz, 1MB L3 Cache, 17W
• Cache: 2MB to 16MB LLC cache depending on CPU type
• Memory: dual stacked SO-DIMM socket memory on top
Dual channel DDR3 Memory DDR3 data transfer rates of 1066 MT/s, 1333 MT/s and 1600 MT/s
• Chipset: Mobile Intel® QM77 Express Chipset
• BIOS: AMI EFI with CMOS backup in 16 Mbit SPI BIOS
• Hardware Monitor: Supply voltages and CPU temperature
• Fan Control: on mini connector on module
• Debug Interface: XDP SFF-26 extension for ICE debug
• Management: Intel® AMT 8.0
Page 8 Express-IBE2
2.2. Expansion Busses
• PCI Express Gen 3.0 Graphics (PEG) Port x16 supporting up to 8GT/Sec transactions
Configurable as 1 x16 , 2 x8 or 1 x8-lane and 2 x4-lane
• AB Connenctor
PCI Express Gen 2.0 Ports 8 x1 from PCH, 5 x1 free for use
(lane 7 to GbE LAN, lane 6 to PCI bridge, lane 5 to PATA bridge)
Port 0/1/2/3/4 configurable as 5 x1 or 1 x4 and 1 x1
• LPC bus, SPI bus (BIOS only)
• SMBus (system) , I2C (user)
2.3. Video
• Integrated in Processor: Intel® HD Graphics 4000 at 650–1200 MHz (depending on processor)
• Integrated Video: DirectX 11, OpenGL *3.1, OpenCL* 1.1
• Feature Support:
Intel Clear Video HD Technology
Advanced Scheduler 2.0, 1.0, XPDM support
DirectX Video Acceleration (DXVA) support for full AVC/VC1/
MPEG2 hardware decode
Multi Display Support: 3 independent displays
• Display Types
VGA Interface support with 300 MHz DAC Analog monitor support up to QXGA (2048 x 1536)
LVDS Interface Dual channel 18/24-bit LVDS
SDVO (mulitplexed on PEG, selectable in BIOS)
2.4. Audio
• Integrated: Intel® HD Audio integrated in PCH QM77
• Audio Codec: Realtek ALC888/886 on Express-BASE
2.5. LAN
• Integrated: LAN MAC integrated in PCH QM77
• Intel PHY: 82579 Gigabit Ethernet
• Interface: 10/100/1000 GbE connection
2.6. Multi I/O and Storage
• Integrated in PCH QM77
• USB ports: 8 ports USB 2.0 (USB0~7)
• SATA ports: two ports SATA 6Gb/s (SATA0, SATA1), two ports SATA 3 Gb/s (SATA2, SATA3)
• PATA ports: through PCIe to PATA bridge Marvell 88SE6101
Express-IBE2 Page 9
2.7. Super I/O (on carrier using LPC -bus)
• Chipset: Winbond W83627HG-AW and W83627DHG-P, without keyboard A20 line
• Parallel Port: LPT1
• Serial Ports: COM1 / COM2 (with console redirection)
2.8. GPIO
• Chipset: NXP PCA9535
• Description: 16-bit I2C-bus and SMBus, low power I/O port with interrupt
• GPO: 4 ports
• GPI: 4 ports with interrupt
2.9. Board Controller
• Type: SEMA BMC
• Functions:
• Power Features
• AT mode control
• ECO mode support (cut 5Vsb during S5) but keep power on RTC clock
• Emergency Shutdown
• Power Status Mointoring and Signalling (LED)
• Current Monitor
• Flat Panel Control
• Support for PWM control on carrier
• Backlight Enable and Vdde inhibit
• General Purpose I2C
• Dual BIOS with Failsave mode
• Watchdog Timer
• Fan Control
• TPM (Trusted Platform Module)
• Chipset: Infineon SLB9635TT1.2
• Type: TPM 1.2
2.10. Fan Control
• Control Source: Temperature Sensor
• Location
• 4-pin Mini connector on module: PWM and TACH 5V based on module
2.11. Debug
• JTAG: SFF connector for XDP to CPU
• LPC header: for mounting POST CODE assembly
Page 10 Express-IBE2
2.12. Power Specifications
• Power Modes: AT and ATX mode (AT mode start controlled by ADMT)
• Standard Voltage Input: ATX = 12V±5% / 5Vsb or AT = 12V±5%
• Wide Voltage Input: ATX = 8.5~19V / 5Vsb or AT = 8.5 ~19V
• Power Management: ACPI 3.0 compliant, Smart battery support.
• Power States: supports C1-C6, S0, S1, S4, S3, S5 (Wake on USB S3/S4, WOL S3/S4/S5)
2.13. Mechanical and Environmental
• Standard Operating Temperature: 0 to 60°C
2.14. Specification Compliance
• PICMG COM.0: Rev 2.1 Type 2, basic size 125 x 95
Express-IBE2 Page 11
2.15. Functional Diagram
Page 12 Express-IBE2
2.16. Mechanical Drawing
Express-IBE2 Page 13
3. COM Express Pinouts and Signal Descriptions
The following information is a summary of the most important information regarding pinout and signal description in the official PICMG
COM.0 Rev 2.0 (soon 2.1)
The pinout is described here to emphazise issues that have not been followed in the past. The following description may still contain small
inacuaracies; in case of doubt, the offical design guide of PICMG should be consulted.
3.1. AB / CD Pin Definitions
All pins in the specification are described, including those not supported on the Express-IB. Those not supported on the Express-IBE2
module are crossed out
Row A Row B Row C Row D
Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
A1 GND (FIXED) B1 GND (FIXED) C1 GND FIXED) D1 GND FIXED)
A2 GBE0_MDI3- B2 GBE0_ACT# C2 IDE_D7 D2 IDE_D5
A3 GBE0_MDI3+ B3 LPC_FRAME# C3 IDE_D6 D3 IDE_D10
A4 GBE0_LINK100# B4 LPC_AD0 C4 IDE_D3 D4 IDE_D11
A5 GBE0_LINK1000# B5 LPC_AD1 C5 IDE_D15 D5 IDE_D12
A6 GBE0_MDI2- B6 LPC_AD2 C6 IDE_D8 D6 IDE_D4
A7 GBE0_MDI2+ B7 LPC_AD3 C7 IDE_D9 D7 IDE_D0
A8 GBE0_LINK# B8 LPC_DRQ0# C8 IDE_D2 D8 IDE_REQ
A9 GBE0_MDI1- B9 LPC_DRQ1# C9 IDE_D13 D9 IDE_IOW#
A10 GBE0_MDI1+ B10 LPC_CLK C10 IDE_D1 D10 IDE_ACK#
A11 GND (FIXED) B11 GND (FIXED) C11 GND (FIXED) D11 GND (FIXED)
A12 GBE0_MDI0- B12 PWRBTN# C12 IDE_D14 D12 IDE_IRQ
A13 GBE0_MDI0+ B13 SMB_CK C13 IDE_IORDY D13 IDE_A0
A14 GBE0_CTREF B14 SMB_DAT C14 IDE_IOR# D14 IDE_A1
A15 SUS_S3# B15 SMB_ALERT# C15 PCI_PME# D15 IDE_A2
A16 SATA0_TX+ B16 SATA1_TX+ C16 PCI_GNT2# D16 IDE_CS1#
A17 SATA0_TX- B17 SATA1_TX- C17 PCI_REQ2# D17 IDE_CS3#
A18 SUS_S4# B18 SUS_STAT# C18 PCI_GNT1# D18 IDE_RESET#
A19 SATA0_RX+ B19 SATA1_RX+ C19 PCI_REQ1# D19 PCI_GNT3#
A20 SATA0_RX- B20 SATA1_RX- C20 PCI_GNT0# D20 PCI_REQ3#
A21 GND (FIXED) B21 GND (FIXED) C21 GND (FIXED) D21 GND (FIXED)
A22 SATA2_TX+ B22 SATA3_TX+ C22 PCI_REQ0# D22 PCI_AD1
A23 SATA2_TX- B23 SATA3_TX- C23 PCI_RESET# D23 PCI_AD3
A24 SUS_S5# B24 PWR_OK C24 PCI_AD0 D24 PCI_AD5
A25 SATA2_RX+ B25 SATA3_RX+ C25 PCI_AD2 D25 PCI_AD7
A26 SATA2_RX- B26 SATA3_RX- C26 PCI_AD4 D26 PCI_C/BE0#
A27 BATLOW# B27 WDT C27 PCI_AD6 D27 PCI_AD9
A28 (S)ATA_ACT# B28 AC/HDA_SDIN2 C28 PCI_AD8 D28 PCI_AD11
A29 AC/HDA_SYNC B29 AC/HDA_SDIN1 C29 PCI_AD10 D29 PCI_AD13
A30 AC/HDA_RST# B30 AC/HDA_SDIN0 C30 PCI_AD12 D30 PCI_AD15
A31 GND (FIXED) B31 GND (FIXED) C31 GND (FIXED) D31 GND (FIXED)
A32 AC/HDA_BITCLK B32 SPKR C32 PCI_AD14 D32 PCI_PAR
A33 AC/HDA_SDOUT B33 I2C_CK C33 PCI_C/BE1# D33 PCI_SERR#
A34 BIOS_DIS0# B34 I2C_DAT C34 PCI_PERR# D34 PCI_STOP#
A35 THRMTRIP# B35 THRM# C35 PCI_LOCK# D35 PCI_TRDY#
A36 USB6- B36 USB7- C36 PCI_DEVSEL# D36 PCI_FRAME#
Page 14 Express-IBE2
A37 USB6+ B37 USB7+ C37 PCI_IRDY# D37 PCI_AD16
A38 USB_6_7_OC# B38 USB_4_5_OC# C38 PCI_C/BE2# D38 PCI_AD18
A39 USB4- B39 USB5- C39 PCI_AD17 D39 PCI_AD20
A40 USB4+ B40 USB5+ C40 PCI_AD19 D40 PCI_AD22
A41 GND (FIXED) B41 GND (FIXED) C41 GND (FIXED) D41 GND (FIXED)
A42 USB2- B42 USB3- C42 PCI_AD21 D42 PCI_AD24
A43 USB2+ B43 USB3+ C43 PCI_AD23 D43 PCI_AD26
A44 USB_2_3_OC# B44 USB_0_1_OC# C44 PCI_C/BE3# D44 PCI_AD28
A45 USB0- B45 USB1- C45 PCI_AD25 D45 PCI_AD30
A46 USB0+ B46 USB1+ C46 PCI_AD27 D46 PCI_IRQC#
A47 VCC_RTC B47 EXCD1_PERST# C47 PCI_AD29 D47 PCI_IRQD#
A48 EXCD0_PERST# B48 EXCD1_CPPE# C48 PCI_AD31 D48 PCI_CLKRUN#
A49 EXCD0_CPPE# B49 SYS_RESET# C49 PCI_IRQA# D49 PCI_M66EN (GND)
A50 LPC_SERIRQ B50 CB_RESET# C50 PCI_IRQB# D50 PCI_CLK
A51 GND (FIXED) B51 GND (FIXED) C51 GND (FIXED) D51 GND (FIXED)
A52 PCIE_TX5+ B52 PCIE_RX5+ C52 PEG_RX0+ D52 PEG_TX0+
A53 PCIE_TX5- B53 PCIE_RX5- C53 PEG_RX0- D53 PEG_TX0A54 GPI0 B54 GPO1 C54 TYPE0# D54 PEG_LANE_RV#
A55 PCIE_TX4+ B55 PCIE_RX4+ C55 PEG_RX1+ D55 PEG_TX1+
A56 PCIE_TX4- B56 PCIE_RX4- C56 PEG_RX1- D56 PEG_TX1A57 GND B57 GPO2 C57 TYPE1# D57 TYPE2#
A58 PCIE_TX3+ B58 PCIE_RX3+ C58 PEG_RX2+ D58 PEG_TX2+
A59 PCIE_TX3- B59 PCIE_RX3- C59 PEG_RX2- D59 PEG_TX2A60 GND (FIXED) B60 GND (FIXED) C60 GND (FIXED) D60 GND (FIXED)
A61 PCIE_TX2+ B61 PCIE_RX2+ C61 PEG_RX3+ D61 PEG_TX3+
A62 PCIE_TX2- B62 PCIE_RX2- C62 PEG_RX3- D62 PEG_TX3A63 GPI1 B63 GPO3 C63 RSVD D63 RSVD
A64 PCIE_TX1+ B64 PCIE_RX1+ C64 RSVD D64 RSVD
A65 PCIE_TX1- B65 PCIE_RX1- C65 PEG_RX4+ D65 PEG_TX4+
A66 GND B66 WAKE0# C66 PEG_RX4- D66 PEG_TX4-
A67 GPI2 B67 WAKE1# C67 RSVD D67 GND
A68 PCIE_TX0+ B68 PCIE_RX0+ C68 PEG_RX5+ D68 PEG_TX5+
A69 PCIE_TX0- B69 PCIE_RX0- C69 PEG_RX5- D69 PEG_TX5A70 GND (FIXED) B70 GND (FIXED) C70 GND (FIXED) D70 GND (FIXED)
A71 LVDS_A0+ B71 LVDS_B0+ C71 PEG_RX6+ D71 PEG_TX6+
A72 LVDS_A0- B72 LVDS_B0- C72 PEG_RX6- D72 PEG_TX6A73 LVDS_A1+ B73 LVDS_B1+ C73 SDVO_DATA D73 SDVO_CLK
A74 LVDS_A1- B74 LVDS_B1- C74 PEG_RX7+ D74 PEG_TX7+
A75 LVDS_A2+ B75 LVDS_B2+ C75 PEG_RX7- D75 PEG_TX7A76 LVDS_A2- B76 LVDS_B2- C76 GND D76 GND
A77 LVDS_VDD_EN B77 LVDS_B3+ C77 RSVD D77 IDE_CBLID#
A78 LVDS_A3+ B78 LVDS_B3- C78 PEG_RX8+ D78 PEG_TX8+
A79 LVDS_A3- B79 LVDS_BKLT_EN C79 PEG_RX8- D79 PEG_TX8A80 GND (FIXED) B80 GND (FIXED) C80 GND (FIXED) D80 GND (FIXED)
A81 LVDS_A_CK+ B81 LVDS_B_CK+ C81 PEG_RX9+ D81 PEG_TX9+
A82 LVDS_A_CK- B82 LVDS_B_CK- C82 PEG_RX9- D82 PEG_TX9A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C83 RSVD D83 RSVD
A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84 GND D84 GND
A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10+ D85 PEG_TX10+
A86 KBD_RST# B86 VCC_5V_SBY C86 PEG_RX10- D86 PEG_TX10A87 KBD_A20GATE B87 VCC_5V_SBY C87 GND D87 GND
Express-IBE2 Page 15
A88 PCIE0_CK_REF+ B88 BIOS_DIS1# C88 PEG_RX11+ D88 PEG_TX11+
A89 PCIE0_CK_REF- B89 VGA_RED C89 PEG_RX11- D89 PEG_TX11A90 GND (FIXED) B90 GND (FIXED) C90 GND (FIXED) D90 GND (FIXED)
A91 SPI_POWER B91 VGA_GRN C91 PEG_RX12+ D91 PEG_TX12+
A92 SPI_MISO B92 VGA_BLU C92 PEG_RX12- D92 PEG_TX12-
A93 GPO0 B93 VGA_HSYNC C93 GND D93 GND
A94 SPI_CLK B94 VGA_VSYNC C94 PEG_RX13+ D94 PEG_TX13+
A95 SPI_MOSI B95 VGA_I2C_CK C95 PEG_RX13- D95 PEG_TX13-
A96 GND B96 VGA_I2C_DAT C96 GND D96 GND
A97 TYPE10# B97 SPI_CS# C97 RSVD D97 PEG_ENABLE#
A98 RSVD B98 RSVD C98 PEG_RX14+ D98 PEG_TX14+
A99 RSVD B99 RSVD C99 PEG_RX14- D99 PEG_TX14A100 GND (FIXED) B100 GND (FIXED) C100 GND (FIXED) D100 GND (FIXED)
A101 RSVD B101 RSVD C101 PEG_RX15+ D101 PEG_TX15+
A102 RSVD B102 RSVD C102 PEG_RX15- D102 PEG_TX15A103 RSVD B103 RSVD C103 GND D103 GND
A104 VCC_12V B104 VCC_12V C104 VCC_12V D104 VCC_12V
A105 VCC_12V B105 VCC_12V C105 VCC_12V D105 VCC_12V
A106 VCC_12V B106 VCC_12V C106 VCC_12V D106 VCC_12V
A107 VCC_12V B107 VCC_12V C107 VCC_12V D107 VCC_12V
A108 VCC_12V B108 VCC_12V C108 VCC_12V D108 VCC_12V
A109 VCC_12V B109 VCC_12V C109 VCC_12V D109 VCC_12V
A110 GND (FIXED) B110 GND (FIXED) C110 GND (FIXED) D110 GND (FIXED)
Page 16 Express-IBE2
3.2. Signal Description Terminology
These terms are used in the COM Express AB/CD Signal Descriptions which follow.
I Input to the Module
O Output from the Module
I/O Bi-directional input/output signal
OD Open drain output
I 3.3V Input 3.3V tolerant
I 5V Input 5V tolerant
O 3.3V Output 3.3V signal level
O 5V Output 5V signal level
I/O 3.3V Bi-directional signal 3.3V tolerant
I/O 5V Bi-directional signal 5V tolerant
I/O 3.3Vsb Input 3.3V tolerant active in standby state
P Power Input/Output
REF Reference voltage output that may be sourced from a module power plane.
PDS Pull-down strap. This is an output pin on the module that is either tied to GND, or not connected.
The signal is used to indicate the PICMG module type to the Carrier Board.
PU ADLINK implemented pull-up resistor on module
PD ADLINK implemented pull-down resistor on module
Express-IBE2 Page 17
3.3. AB Signal Descriptions
3.3.1. Audio Signals
Signal Pin Description I/O PU/PD Comment
AC_RST# /
HDA_RST#
AC_SYNC /
HDA_SYNC
AC_BITCLK /
HDA_BITCLK
AC _SDOUT /
HDA_SDOUT
AC _SDIN[2:0]
HDA_SDIN[2:0]
A30 Reset output to CODEC, active low. O 3.3VSB
A29 Sample-synchronization signal to the CODEC(s). O 3.3V
A32 Serial data clock generated by the external
CODEC(s).
A33 Serial TDM data output to the CODEC. O 3.3V
B28
B30
Serial TDM data inputs from up to 3 CODECs. I/O 3.3VSB
I/O 3.3V
3.3.2. Analog VGA
Signal Pin Description I/O PU/PD Comment
VGA_RED B89 Red for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
VGA_GRN B91 Green for monitor
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
O Analog If VGA is used, signal should be
pulled to GND by 150Ω on the
carrier
O Analog If VGA is used, signal should be
pulled to GND by 150Ω on the
carrier
VGA_BLU B92 Blue for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
VGA_HSYNC B93 Horizontal sync output to VGA monitor O 3.3V
VGA_VSYNC B94 Vertical sync output to VGA monitor O 3.3V
VGA_I2C_CK B95 DDC clock line (I²C port dedicated to identify
VGA monitor capabilities)
VGA_I2C_DAT B96 DDC data line. I/O OD 3.3V PU 2k2 3.3V
O Analog If VGA is used, signal should be
I/O OD 3.3V PU 2k2 3.3V
pulled to GND by 150Ω on the
carrier
Page 18 Express-IBE2
3.3.3. LVDS
Signal Pin Description I/O PU/PD Comment
LVDS_A0+
LVDS_A0-
LVDS_A1+
LVDS_A1-
LVDS_A2+
LVDS_A2-
LVDS_A3+
LVDS_A3-
LVDS_A_CK+
LVDS_A_CK-
LVDS_B0+
LVDS_B0-
LVDS_B1+
LVDS_B1-
LVDS_B2+
LVDS_B2-
LVDS_B3+
LVDS_B3-
LVDS_B_CK+
LVDS_B_CK-
LVDS_VDD_EN A77 LVDS panel power enable O 3.3V
LVDS_BKLT_EN B79 LVDS panel backlight enable O 3.3V
LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3.3V
LVDS_I2C_CK A83 DDC lines used for flat panel detection and control. O 3.3V PU 2k2 3.3V
A71
A72
A73
A74
A75
A76
A78
A79
A81
A82
B71
B72
B73
B74
B75
B76
B77
B78
B81
B82
LVDS Channel A differential pairs O LVDS
LVDS Channel A differential clock O LVDS
LVDS Channel B differential pairs O LVDS
LVDS Channel B differential clock O LVDS
LVDS_I2C_DAT A84 DDC lines used for flat panel detection and control. I/O 3.3V PU 2k2 3.3V
3.3.4. Gigabit Ethernet
Gigabit Ethernet Pin Description I/O PU/PD Comment
GBE0_MDI0+
GBE0_MDI0-
GBE0_MDI1+
GBE0_MDI1-
GBE0_MDI2+
GBE0_MDI2-
GBE0_MDI3+
GBE0_MDI3-
GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. OD 3.3VSB PU 1k
GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. OD 3.3VSB
GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low. OD 3.3VSB
GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low. OD 3.3VSB
GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 1 and 2
A13
A12
A10
A9
A7
A6
A3
A2
Gigabit Ethernet Controller 0: Media Dependent Interface Differential
Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec
modes. Some pairs are unused in some modes, as described here:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/MDI[3]+/- B1_DD+/-
magnetics center tap. The reference voltage is determined by the
requirements of the Module PHY and may be as low as 0V and as high
as 3.3V. The reference voltage output shall be current limited on the
Module. Where the reference is shorted to ground, the current shall be
250 mA or less.
I/O Analog Twisted pair
signals for
external
transformer.
3.3V
GND min
3.3V max
Express-IBE2 Page 19
3.3.5. Serial ATA
Signal Pin Description I/O PU/PD Comment
SATA0_TX+
SATA0_TX-
SATA0_RX+
SATA0_RX-
SATA1_TX+
SATA1_TX-
SATA1_RX+
SATA1_RX-
SATA2_TX+
SATA2_TX-
SATA2_RX+
SATA2_RX-
SATA3_TX+
SATA3_TX-
SATA3_RX+
SATA3_RX-
(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity
A16
A17
A19
A20
B16
B17
B19
B20
A22
A23
A25
A26
B22
B23
B25
B26
Serial ATA channel 0, Transmit Output
differential pair.
Serial ATA channel 0, Receive Input
differential pair.
Serial ATA channel 1, Transmit Output
differential pair.
Serial ATA channel 1, Receive Input
differential pair.
Serial ATA channel 2, Transmit Output
differential pair.
Serial ATA channel 2, Receive Input
differential pair.
Serial ATA channel 3, Transmit Output
differential pair.
Serial ATA channel 3, Receive Input
differential pair.
indicator, active low.
O SATA AC coupled on Module
I SATA AC coupled on Module
O SATA AC coupled on Module
I SATA AC coupled on Module
O SATA AC coupled on Module
I SATA AC coupled on Module
O SATA AC coupled on Module
I SATA AC coupled on Module
O 3.3V
Page 20 Express-IBE2
3.3.6. PCI Express
Signal Pin Description I/O PU/PD Comment
PCIE_TX0+
PCIE_TX0-
PCIE_RX0+
PCIE_RX0-
PCIE_TX1+
PCIE_TX1-
PCIE_RX1+
PCIE_RX1-
PCIE_TX2+
PCIE_TX2-
PCIE_RX2+
PCIE_RX2-
PCIE_TX3+
PCIE_TX3-
PCIE_RX3+
PCIE_RX3-
PCIE_TX4+
PCIE_TX4-
PCIE_RX4+
PCIE_RX4-
A68
A69
B68
B69
A64
A65
B64
B65
A61
A62
B61
B62
A58
A59
B58
B59
A55
A56
B55
B56
PCI Express channel 0, Transmit Output differential pair. O PCIE AC coupled on Module
PCI Express channel 0, Receive Input differential pair. I PCIE AC coupled off Module
PCI Express channel 1, Transmit Output differential pair. O PCIE AC coupled on Module
PCI Express channel 1, Receive Input differential pair. I PCIE AC coupled off Module
PCI Express channel 2, Transmit Output differential pair. O PCIE AC coupled on Module
PCI Express channel 2, Receive Input differential pair. I PCIE AC coupled off Module
PCI Express channel 3, Transmit Output differential pair. O PCIE AC coupled on Module
PCI Express channel 3, Receive Input differential pair. I PCIE AC coupled off Module
PCI Express channel 4, Transmit Output differential pair. O PCIE AC coupled on Module
PCI Express channel 4, Receive Input differential pair. I PCIE AC coupled off Module
PCIE_TX5+
PCIE_TX5-
PCIE_RX5+
PCIE_RX5-
PCIE_CLK_REF+
PCIE_CLK_REF-
A52
A53
B52
B53
A88
A89
PCI Express channel 5, Transmit Output differential pair. O PCIE not supported on this module
PCI Express channel 5, Receive Input differential pair. I PCIE not supported on this module
PCI Express Reference Clock output for all PCI Express
and PCI Express Graphics Lanes.
O PCIE
3.3.7. Express Card
Signal Pin Description I/O PU/PD Comment
EXCD0_CPPE#
EXCD1_CPPE#
EXCD0_PERST#
EXCD1_PERST#
A49
B48
A48
B47
PCI ExpressCard: PCI Express capable card request I 3.3V PU 10k 3.3V
PCI ExpressCard: reset O 3.3V
Express-IBE2 Page 21
3.3.8. LPC bus
Signal Pin Description I/O PU/PD Comment
LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V
LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V
LPC_DRQ0#
LPC_DRQ1#
LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V PU 8k2 3.3V
LPC_CLK B10 LPC clock output - 33MHz nominal O 3.3V
B8
B9
LPC serial DMA request I 3.3V
3.3.9. USB
Signal Pin Description I/O PU/PD Comment
USB0+
USB0-
USB1+
USB1-
USB2+
USB2-
USB3+
USB3-
USB4+
USB4-
USB5+
USB5-
A46
USB differential data pairs for Port 0 I/O 3.3VSB USB 1.1/ 2.0 compliant
A45
B46
USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant
B45
A43
USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant
A42
B43
USB differential data pairs for Port 2 I/O 3.3VSB USB 1.1/ 2.0 compliant
B42
A40
USB differential data pairs for Port 3 I/O 3.3VSB USB 1.1/ 2.0 compliant
A39
B40
USB differential data pairs for Port 4 I/O 3.3VSB USB 1.1/ 2.0 compliant
B39
USB6+
USB6-
USB7+
USB7-
USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up
USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up
USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up
USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up
A37
USB differential data pairs for Port 5 I/O 3.3VSB USB 1.1/ 2.0 compliant
A36
B37
USB differential data pairs for Port 6 I/O 3.3VSB USB 1.1/ 2.0 compliant
B37
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
Page 22 Express-IBE2
3.3.10. SPI (BIOS only)
Signal Pin Description I/O PU/PD Comment
SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB
SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB
SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module
– nominally 3.3V. The Module shall provide a minimum of
100mA on SPI_POWER. Carriers shall use less than
100mA of SPI_POWER. SPI_POWER shall only be used
to power SPI devices on the Carrier
BIOS_DIS0# A34 Selection strap to determine the BIOS boot device. I PU 10K 3.3V Carrier shall pull to GND
BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. I PU 10K 3.3V Carrier shall pull to GND
O P 3.3VSB
or leave unconnected
or leave unconnected
3.3.11. Miscellaneous
Signal Pin Description I/O PU/PD Comment
SPKR B32 Output for audio enunciator, the “speaker” in PC-AT
systems.
WDT B27 Output indicating that a watchdog time-out event has
occurred.
KBD_RST# A86 Input to module from (optional) external keyboard
controller which can force a reset. Pulled high on the
module. This is a legacy artifact of the PC-AT.
KBD_A20GATE A87 Input to module from (optional) external keyboard
controller which can be used to control the CPU A20 gate
line. The A20GATE restricts the memory access to the
bottom megabyte and is a legacy artifact of the PC-AT.
Pulled low on the module.
THRM# B35 Input from off-module temp sensor indicating an over-temp
situation.
O 3.3V
O 3.3V
I 3.3V PU 10K 3.3V
I 3.3V PU 10K 3.3V
I 3.3V
THERMTRIP# A35 Active low output indicating the CPU has entered thermal
shutdown.
TPM_PP11 C83 Trusted Platform Module (TPM) Physical Presence pin.
Active high. TPM chip has an internal pull down. This
signal is used to indicate Physical Presence to the TPM.
O 3.3V
I 3.3V PD 3.3V If TPM not installed on
module, remove PD
3.3V
Express-IBE2 Page 23
3.3.12. SMBus
Signal Pin Description I/O PU/PD Comment
SMB_CK B13 System Management Bus bidirectional clock line. Power
sourced through 5V standby rail and main power rails.
SMB_DAT# B14 System Management Bus bidirectional data line. Power
sourced through 5V standby rail and main power rails.
SMB_ALERT# B15 System Management Bus Alert – active low input can
be used to generate an SMI# (System Management
Interrupt) or to wake the system. Power sourced
through 5V standby rail and main power rails.
I/O OD 3.3VSB PU 2k2 3.3VSB
I/O OD 3.3VSB PU 2k2 3.3VSB
I 3.3VSB PU 10k 3.3VSB
3.3.13. I2C Bus
Signal Pin Description I/O PU/PD Comment
I2C_CK B33 General purpose I²C port clock output/input I/O OD 3.3VSB PU 2k2 3.3VSB
I2C_DAT B34 General purpose I²C port data I/O line I/O OD 3.3VSB PU 2k2 3.3VSB
3.3.14. General Purpose I/O (GPIO)
Signal Pin Description I/O PU/PD Comment
GPO[0] A93 General purpose output pins. O 3.3V
GPO[1] B54 General purpose output pins. O 3.3V
GPO[2] B57 General purpose output pins. O 3.3V
GPO[3] B63 General purpose output pins. O 3.3V
GPI[0] A54 General purpose input pins. Pulled high internally on the module. I 3.3V PU 10K 3.3V
GPI[1] A63 General purpose input pins. Pulled high internally on the module. I 3.3V PU 10K 3.3V
GPI[2] A67 General purpose input pins. Pulled high internally on the module. I 3.3V PU 10K 3.3V
GPI[3] A85 General purpose input pins. Pulled high internally on the module. I 3.3V PU 10K 3.3V
Page 24 Express-IBE2
3.3.15. Power And System Management
Signal Pin Description I/O PU/PD Comment
PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge. I 3.3VSB PU 10k 3.3VSB
SYS_RESET# B49 Reset button input. Active low request for module to reset and reboot. May
be falling edge sensitive. For situations when SYS_RESET# is unable to
reestablish control of the system, PWR_OK or a power cycle may be used.
CB_RESET# B50 Reset output from module to Carrier Board. Active low. Issued by module
chipset and may result from a low SYS_RESET# input, a low PWR_OK
input, a VCC_12V power input that falls below the minimum specification, a
watchdog timeout, or may be initiated by the module software.
PWR_OK B24 Power OK from main power supply. A high value indicates that the power is
good. This signal can be used to hold off Module startup, to allow carrier
based FPGAs or other configurable devices time to be programmed.
SUS_STAT# B18 Indicates imminent suspend operation; used to notify LPC devices. O 3.3VSB
SUS_S3# A15 Indicates system is in Suspend to RAM state. Active-low output. An inverted
copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be
used to enable the non-standby power on a typical ATX power supply.
SUS_S4# A18 Indicates system is in Suspend to Disk state. Active low output. O 3.3VSB
SUS_S5# A24 Indicates system is in Soft Off state. O 3.3VSB
WAKE0# B66 PCI Express wake up signal. I 3.3VSB PU 10k 3.3VSB
WAKE1# B67 General purpose wake up signal. May be used to implement wake-up on
PS/2 keyboard or mouse activity.
BATLOW# A27 Battery low input. This signal may be driven low by external circuitry to signal
that the system battery is low, or may be used to signal some other e xternal
power-management event.
I 3.3VSB PU 10k 3.3VSB
O 3.3VSB
I 3.3V PU 10k 3.3V
O 3.3VSB
I 3.3VSB PU 10k 3.3VSB
I 3.3VSB PU 10k 3.3VSB
PU 10k 3.3VSB
Express-IBE2 Page 25
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