ADLINK Express-HL2 User Manual
Express-HL2
User’s Manual
Manual Revision: 1.01
Revision Date: October 22, 2014
Part Number: 50-1J058-1010
Revision History
Revision Description Date By
1.00 Initial release 2014-08-29 JC
1.01 Add BIOS beep codes; correct PCIe Configuration Switch settings 2014-10-22 JC
Page 2 Express-HL2
Preface
Copyright 2014 ADLINK Technology, Inc.
This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by
any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not
represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or
consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such
damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's
Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental
protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and
raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to
dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their
respective companies.
Express-HL2 Page 3
Table of Contents
Revision History ............................................................................................................ 2
Preface............................................................................................................................ 3
1 Introduction............................................................................................................ 6
2 Specifications.......................................................................................................... 7
2.1 Core System ..................................................................................................................................7
2.2 Expansion Busses ..........................................................................................................................7
2.3 Video .............................................................................................................................................7
2.4 Audio.............................................................................................................................................7
2.5 LAN................................................................................................................................................8
2.6 Multi I/O and Storage ...................................................................................................................8
2.7 TPM (Trusted Platform Module)...................................................................................................8
2.8 SEMA Board Controller .................................................................................................................8
2.9 Debug............................................................................................................................................8
2.10 Power Specifications .................................................................................................................9
2.11 Operating Temperatures...........................................................................................................9
2.12 Environmental .................................................................................................................. .........9
2.13 Specification Compliance ..........................................................................................................9
2.14 Operating Systems ....................................................................................................................9
2.15 Function Diagram ................................................................................................................... 10
2.16 Mechanical Drawing............................................................................................................... 11
3 Pinouts and Signal Descriptions......................................................................... 12
3.1 AB / CD Pin Definitions............................................................................................................... 12
3.2 Signal Description Terminology ................................................................................................. 15
3.3 AB Signal Descriptions ............................................................................................................... 16
3.4 CD Signal Descriptions ............................................................................................................... 25
4 Connector Pinouts on Module............................................................................ 28
4.1 40-pin Debug Connector............................................................................................................ 29
4.2 Status LEDs................................................................................................................................. 31
4.3 XDP Debug header ..................................................................................................................... 32
4.4 Fan Connector............................................................................................................................ 33
4.5 BIOS Setup Defaults Reset Button ............................................................................................. 33
4.6 Express-HL2 Switch Settings ...................................................................................................... 34
4.7 PCIe x16-to-two-x8 Adapter Card .............................................................................................. 36
Page 4 Express-HL2
5 Smart Embedded Management Agent (SEMA) ................................................ 37
5.1 Board Specific SEMA Functions ................................................................................................. 38
6 System Resources................................................................................................. 40
6.1 System Memory Map................................................................................................................. 40
6.2 Direct Memory Access Channels ............................................................................................... 40
6.3 I/O Map...................................................................................................................................... 41
6.4 Interrupt Request (IRQ) Lines .................................................................................................... 43
6.5 PCI Configuration Space Map .................................................................................................... 45
6.6 PCI Interrupt Routing Map......................................................................................................... 46
6.7 SMBus Slave Addresses.............................................................................................................. 46
7 BIOS Setup ............................................................................................................47
7.1 Menu Structure.......................................................................................................................... 47
7.2 Main ........................................................................................................................................... 48
7.3 Advanced ................................................................................................................................... 53
7.4 Boot............................................................................................................................................ 69
7.5 Security ...................................................................................................................................... 70
7.6 Save & Exit ................................................................................................................................. 70
8 BIOS Checkpoints, Beep Codes........................................................................... 71
8.1 Status Code Ranges.................................................................................................................... 72
8.2 Standard Status Codes ............................................................................................................... 72
8.3 OEM-Reserved Checkpoint Ranges............................................................................................ 78
9 Mechanical Information ...................................................................................... 79
9.1 Board-to-Board Connectors....................................................................................................... 79
9.2 Thermal Solution........................................................................................................................ 80
9.3 Mounting Methods .................................................................................................................... 82
9.4 Standoff Types ........................................................................................................................... 83
Safety Instructions ...................................................................................................... 84
Getting Service ............................................................................................................ 85
Express-HL2 Page 5
1 Introduction
The Express-HL2 is a COM Express® COM.0 R2.1 Type 2 module supporting the 64-bit 4th Generation Intel® Core™ i7/i5/3 processor with
mobile Intel® QM87 Chipset or 4th Generation Intel® Celeron® processor with mobile Intel® HM86 Chipset. The Express-HL2 is specifically
designed for customers who need high-level processing and graphics performance in a long product life solution.
The Express-HL2 features Intel® Hyper-Threading Technology (up to 4 cores, 8 threads) and non-ECC type DDR3L dual-channel memory
at 1333/1600 MHz in dual stacked SODIMM sockets up to 16 GB to provide excellent overall performance. Intel® Flexible Display Interface
and Direct Media Interface provide high speed connectivity to the mobile Intel® QM87/HM86 Chipset.
Integrated Intel® Generation 7.5 Graphics includes features such as OpenGL 3.1, DirectX 11, Intel® Clear Video HD Technology, Advanced
Scheduler 2.0, 1.0, XPDM support, and DirectX Video Acceleration (DXVA) support for full AVC/VC1/MPEG2 hardware decode. Graphics
outputs include VGA and LVDS. The Express-HL2 is specifically designed for customers with high-performance processing graphics
requirements who want to outsource the custom core logic of their systems for reduced development time.
The Express-HL2 features a single onboard Gigabit Ethernet port, USB 2.0 ports, PATA port, SATA 6 Gb/s ports, 32-bit PCI bus, rev 2.3,
and a multiplexed PCI Express® x16 graphics bus for discrete graphics expansion or general purpose PCI Express® x8 or x4 connectivity.
Support is also provided for SMBus and I
features such as remote console, CMOS backup, hardware monitor, and watchdog timer.
2
C and the module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded
Page 6 Express-HL2
2 Specifications
2.1 Core System
¾ CPU: 4th Generation Intel® Core™ and Intel® Celeron® Processors - 22nm (formerly “Haswell”)
• Intel® Core™ i7-4860EQ 1.8 GHz (3.2 GHz Turbo), 47W (4C/GT3)
• Intel® Core™ i7-4700EQ 2.4/1.7 GHz (3.4 GHz Turbo), 47/37W (4C/GT2)
• Intel® Core™ i5-4400E 2.7 GHz (3.3 GHz Turbo), 37W (2C/GT2)
• Intel® Core™ i5-4402E 1.6 GHz (2.7 GHz Turbo), 25W (2C/GT2)
• Intel® Core™ i3-4100E 2.4 GHz (no Turbo) 3MB, 37W (2C/GT2)
• Intel® Core™ i5-4102E 1.6 GHz (no Turbo) 3MB, 25W (2C/GT2)
• Intel® Celeron 2000E 2.2 GHz (no Turbo) 35W (2C/GT1)
• Intel® Celeron 2002E 1.5 GHz (no Turbo) 25W (2C/GT1)
¾ L3 Cache: 6MB for i7-4650U, 3MB for i5-4400E, i5-4402E, i3-4100E and i3-4102E, 2MB for 2000E and 2002E
¾ Memory: Dual channel non-ECC 1600/1333 MHz DDR3L memory up to 16GB in dual SODIMM socket
¾ Chipset: Mobile Intel®
Mobile Intel®
QM87 Chipset (Intel® Core™ i7/i5/i3)
QM87 Chipset (Intel® Celeron)
¾ BIOS: AMI EFI with CMOS backup in 8MB SPI BIOS with Intel® AMT 9.0 support (Intel® AMT not supported by HM86)
2.2 Expansion Busses
¾ PCI Express x16 (Gen3) or PCI Express (2 x8 or 1 x8 with 2 x4)
¾ 6 PCI Express x1 (AB): Lanes 0/1/2/3/4/5
¾ PCI: 32-bit PCI bus, rev 2.3
¾ LPC bus, SMBus (system) , I
2
C (user)
2.3 Video
¾ Integrated in Processor: Intel® Generation 7.5 graphics core architecture
¾ GPU Feature Support:
• 2 independent and simultaneous display combinations of VGA / LVDS monitors
• Encode/transcode HD content
• Playback of high definition content including Blu-ray Disc
• Superior image quality with sharper, more colorful images
• Playback of Blu-ray disc S3D content using HDMI (1.4a spec compliant with 3D)
• DirectX Video Acceleration (DXVA) support for accelerating video processing
• Full AVC/VC1/MPEG2 HW Decode
• Advanced Scheduler 2.0, 1.0, XPDM support
• Windows 8, Windows 7, OSX, Linux OS support
• DirectX 11, DirectX
¾ Multi Display Support: 2 independent displays
¾ Display Types
• VGA Interface support with 300 MHz DAC Analog monitor support up to QXGA (2048 x 1536)
• LVDS Interface single/dual channel 18/24-bit LVDS through eDP (two lane) to LVDS Realtek RTD2136R
2.4 Audio
¾ Integrated: Intel® HD Audio integrated in PCH QM87/HM86
¾ Audio Codec: Realtek ALC886 on Express-BASE
Express-HL2 Page 7
2.5 LAN
¾ Integrated: LAN MAC integrated in PCH QM87/HM86
¾ Intel PHY: Intel® Ethernet Controller i217LM
¾ Interface: 10/100/1000 GbE connection
2.6 Multi I/O and Storage
¾ Integrated in Intel® QM87/HM86 Express Chipset
¾ USB ports: 8 ports USB 2.0 (USB 0,1,2,3,4,5,6,7)
¾ SATA ports: four ports SATA 6Gb/s (SATA0, SATA1, SATA2, SATA3) – QM87
three ports SATA 6Gb/s (SATA0, SATA2, SATA3, no SATA1) – HM86
¾ PATA ports: one PATA IDE (through SATA to PATA bridge)
¾ GPIO: 4 GPO and 4 GPI with interrupt
2.7 TPM (Trusted Platform Module)
¾ Chipset: ATMELAT97SC3204
¾ Type: TPM 1.2
2.8 SEMA Board Controller
¾ Type: ADLINK Smart Embedded Management Agent (SEMA)
¾ Supports:
• Voltage/Current monitoring
• Power sequence debug support
• AT/ATX mode control
• Logistics and forensic information
• Flat panel control
• General purpose I2C
• Failsafe BIOS (dual BIOS )
• Watchdog timer and fan control
2.9 Debug
¾ 40-pin flat cable connector to be used with DB-40 debug module
• Supports: BIOS POST code LEDs, BMC access, SPI BIOS flashing, power testpoints, debug LEDs
¾ 60-pin XDP header for ICE debug of CPU/chipset
Page 8 Express-HL2
2.10 Power Specifications
¾ Power Modes: AT and ATX mode (AT mode start controlled by SEMA)
¾ Standard Voltage Input: ATX = 12V±5% / 5Vsb ±5% or AT = 12V ±5%
¾ Wide Voltage Input: ATX = 8.5~20 V / 5Vsb ±5% or AT = 8.5 ~20V
¾ Power Management: ACPI 4.0 compliant, Smart Battery support
¾ Power States: supports C1-C6, S0, S1, S4, S3, S5, S5 ECO mode (Wake on USB S3/S4, WOL S3/S4/S5)
2.11 Operating Temperatures
¾ Standard Operating Temperature: 0°C to 60°C (wide voltage input)
¾ Extreme Rugged Operating Temperature: -40°C to 85°C (standard voltage input)
2.12 Environmental
¾ Humidity: 5-90% RH operating, non-condensing
5-95% RH storage (and operating with conformal coating).
¾ Shock and Vibration: IEC 60068-2-64 and IEC-60068-2-27
MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D
¾ Halt: Thermal Stress, Vibration Stress, Thermal Shock and Combined Test
2.13 Specification Compliance
¾ PICMG COM.0: Rev 2.1 Type 2, basic size 125 x 95 mm
2.14 Operating Systems
¾ Standard Support: Windows 7/8 32/64-bit, Linux 32/64-bit
¾ Extended Support (BSP): Windows Embedded Standard 7/8, Linux , VxWorks, QNX
Express-HL2 Page 9
2.15 Function Diagram
Page 10 Express-HL2
2.16 Mechanical Drawing
connector onbottom side
All tolerances ± 0.05 mm
Othertolerances ± 0.2 mm
Express-HL2 Page 11
3 Pinouts and Signal Descriptions
3.1 AB / CD Pin Definitions
The Express-HL2 is a Type 2 module supporting PCI and PATA on the CD connector
All pins in the COM Express specification are described, including those not supported on the Express-HL2. Those not supported on the
Express-HL2 module are crossed out
Row A Row B Row C Row D
Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
A1 GND (FIXED) B1 GND (FIXED) C1 GND FIXED) D1 GND FIXED)
A2 GBE0_MDI3- B2 GBE0_ACT# C2 IDE_D7 D2 IDE_D5
A3 GBE0_MDI3+ B3 LPC_FRAME# C3 IDE_D6 D3 IDE_D10
A4 GBE0_LINK100# B4 LPC_AD0 C4 IDE_D3 D4 IDE_D11
A5 GBE0_LINK1000# B5 LPC_AD1 C5 IDE_D15 D5 IDE_D12
A6 GBE0_MDI2- B6 LPC_AD2 C6 IDE_D8 D6 IDE_D4
A7 GBE0_MDI2+ B7 LPC_AD3 C7 IDE_D9 D7 IDE_D0
A8 GBE0_LINK# B8 LPC_DRQ0# C8 IDE_D2 D8 IDE_REQ
A9 GBE0_MDI1- B9 LPC_DRQ1# C9 IDE_D13 D9 IDE_IOW#
A10 GBE0_MDI1+ B10 LPC_CLK C10 IDE_D1 D10 IDE_ACK#
A11 GND (FIXED) B11 GND (FIXED) C11 GND (FIXED) D11 GND (FIXED)
A12 GBE0_MDI0- B12 PWRBTN# C12 IDE_D14 D12 IDE_IRQ
A13 GBE0_MDI0+ B13 SMB_CK C13 IDE_IORDY D13 IDE_A0
A14 GBE0_CTREF B14 SMB_DAT C14 IDE_IOR# D14 IDE_A1
A15 SUS_S3# B15 SMB_ALERT# C15 PCI_PME# D15 IDE_A2
A16 SATA0_TX+ B16
A17 SATA0_TX- B17
A18 SUS_S4# B18 SUS_STAT# C18 PCI_GNT1# D18 IDE_RESET#
A19 SATA0_RX+ B19
A20 SATA0_RX- B20
A21 GND (FIXED) B21 GND (FIXED) C21 GND (FIXED) D21 GND (FIXED)
A22 SATA2_TX+ B22 SATA3_TX+ C22 PCI_REQ0# D22 PCI_AD1
A23 SATA2_TX- B23 SATA3_TX- C23 PCI_RESET# D23 PCI_AD3
A24 SUS_S5# B24 PWR_OK C24 PCI_AD0 D24 PCI_AD5
A25 SATA2_RX+ B25 SATA3_RX+ C25 PCI_AD2 D25 PCI_AD7
A26 SATA2_RX- B26 SATA3_RX- C26 PCI_AD4 D26 PCI_C/BE0#
A27 BATLOW# B27 WDT C27 PCI_AD6 D27 PCI_AD9
A28 (S)ATA_ACT# B28 AC/HDA_SDIN2 C28 PCI_AD8 D28 PCI_AD11
A29 AC/HDA_SYNC B29 AC/HDA_SDIN1 C29 PCI_AD10 D29 PCI_AD13
A30 AC/HDA_RST# B30 AC/HDA_SDIN0 C30 PCI_AD12 D30 PCI_AD15
A31 GND (FIXED) B31 GND (FIXED) C31 GND (FIXED) D31 GND (FIXED)
A32 AC/HDA_BITCLK B32 SPKR C32 PCI_AD14 D32 PCI_PAR
A33 AC/HDA_SDOUT B33 I2C_CK C33 PCI_C/BE1# D33 PCI_SERR#
A34 BIOS_DIS0# B34 I2C_DAT C34 PCI_PERR# D34 PCI_STOP#
A35 THRMTRIP# B35 THRM# C35 PCI_LOCK# D35 PCI_TRDY#
A36 USB6- B36 USB7- C36
A37 USB6+ B37 USB7+ C37 PCI_IRDY# D37 PCI_AD16
A38 USB_6_7_OC# B38 USB_4_5_OC# C38 PCI_C/BE2# D38 PCI_AD18
SATA1_TX+ *
SATA1_TX- *
SATA1_RX+ *
SATA1_RX- *
C16
C17
C19
C20
PCI_GNT2# D16 IDE_CS1#
PCI_REQ2# D17 IDE_CS3#
PCI_REQ1# D19 PCI_GNT3#
PCI_GNT0# D20 PCI_REQ3#
PCI_DEVSEL
#
D36
PCI_FRAME#
Page 12 Express-HL2
A39 USB4- B39 USB5- C39 PCI_AD17 D39 PCI_AD20
A40 USB4+ B40 USB5+ C40 PCI_AD19 D40 PCI_AD22
A41 GND (FIXED) B41 GND (FIXED) C41 GND (FIXED) D41 GND (FIXED)
A42 USB2- B42 USB3- C42 PCI_AD21 D42 PCI_AD24
A43 USB2+ B43 USB3+ C43 PCI_AD23 D43 PCI_AD26
A44 USB_2_3_OC# B44 USB_0_1_OC# C44 PCI_C/BE3# D44 PCI_AD28
A45 USB0- B45 USB1- C45 PCI_AD25 D45 PCI_AD30
A46 USB0+ B46 USB1+ C46 PCI_AD27 D46 PCI_IRQC#
A47 VCC_RTC B47 EXCD1_PERST# C47 PCI_AD29 D47 PCI_IRQD#
A48 EXCD0_PERST# B48 EXCD1_CPPE# C48 PCI_AD31 D48 PCI_CLKRUN#
A49 EXCD0_CPPE# B49 SYS_RESET# C49 PCI_IRQA# D49 PCI_M66EN GND)
A50 LPC_SERIRQ B50 CB_RESET# C50 PCI_IRQB# D50 PCI_CLK
A51 GND (FIXED) B51 GND (FIXED) C51 GND (FIXED) D51 GND (FIXED)
A52 PCIE_TX5+ B52 PCIE_RX5+ C52 PEG_RX0+ D52 PEG_TX0+
A53 PCIE_TX5- B53 PCIE_RX5- C53 PEG_RX0- D53 PEG_TX0A54 GPI0 B54 GPO1 C54 TYPE0# D54 PEG_LANE_RV#
A55 PCIE_TX4+ B55 PCIE_RX4+ C55 PEG_RX1+ D55 PEG_TX1+
A56 PCIE_TX4- B56 PCIE_RX4- C56 PEG_RX1- D56 PEG_TX1A57 GND B57 GPO2 C57 TYPE1# D57 TYPE2#
A58 PCIE_TX3+ B58 PCIE_RX3+ C58 PEG_RX2+ D58 PEG_TX2+
A59 PCIE_TX3- B59 PCIE_RX3- C59 PEG_RX2- D59 PEG_TX2A60 GND (FIXED) B60 GND (FIXED) C60 GND (FIXED) D60 GND (FIXED)
A61 PCIE_TX2+ B61 PCIE_RX2+ C61 PEG_RX3+ D61 PEG_TX3+
A62 PCIE_TX2- B62 PCIE_RX2- C62 PEG_RX3- D62 PEG_TX3A63 GPI1 B63 GPO3 C63 RSVD D63 RSVD
A64 PCIE_TX1+ B64 PCIE_RX1+ C64 RSVD D64 RSVD
A65 PCIE_TX1- B65 PCIE_RX1- C65 PEG_RX4+ D65 PEG_TX4+
A66 GND B66 WAKE0# C66 PEG_RX4- D66 PEG_TX4-
A67 GPI2 B67 WAKE1# C67 RSVD D67 GND
A68 PCIE_TX0+ B68 PCIE_RX0+ C68 PEG_RX5+ D68 PEG_TX5+
A69 PCIE_TX0- B69 PCIE_RX0- C69 PEG_RX5- D69 PEG_TX5A70 GND (FIXED) B70 GND (FIXED) C70 GND (FIXED) D70 GND (FIXED)
A71 LVDS_A0+ B71 LVDS_B0+ C71 PEG_RX6+ D71 PEG_TX6+
A72 LVDS_A0- B72 LVDS_B0- C72 PEG_RX6- D72 PEG_TX6A73 LVDS_A1+ B73 LVDS_B1+ C73 SDVO_DATA D73 SDVO_CLK
A74 LVDS_A1- B74 LVDS_B1- C74 PEG_RX7+ D74 PEG_TX7+
A75 LVDS_A2+ B75 LVDS_B2+ C75 PEG_RX7- D75 PEG_TX7A76 LVDS_A2- B76 LVDS_B2- C76 GND D76 GND
A77 LVDS_VDD_EN B77 LVDS_B3+ C77 RSVD D77 IDE_CBLID#
A78 LVDS_A3+ B78 LVDS_B3- C78 PEG_RX8+ D78 PEG_TX8+
A79 LVDS_A3- B79 LVDS_BKLT_EN C79 PEG_RX8- D79 PEG_TX8A80 GND (FIXED) B80 GND (FIXED) C80 GND (FIXED) D80 GND (FIXED)
A81 LVDS_A_CK+ B81 LVDS_B_CK+ C81 PEG_RX9+ D81 PEG_TX9+
A82 LVDS_A_CK- B82 LVDS_B_CK- C82 PEG_RX9- D82 PEG_TX9A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C83 RSVD D83 RSVD
A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84 GND D84 GND
A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10+ D85 PEG_TX10+
A86 KBD_RST# B86 VCC_5V_SBY C86 PEG_RX10- D86 PEG_TX10A87 KBD_A20GATE B87 VCC_5V_SBY C87 GND D87 GND
A88 PCIE0_CK_REF+ B88 BIOS_DIS1# C88 PEG_RX11+ D88 PEG_TX11+
Express-HL2 Page 13
A89 PCIE0_CK_REF- B89 VGA_RED C89 PEG_RX11- D89 PEG_TX11A90 GND (FIXED) B90 GND (FIXED) C90 GND (FIXED) D90 GND (FIXED)
A91 SPI_POWER B91 VGA_GRN C91 PEG_RX12+ D91 PEG_TX12+
A92 SPI_MISO B92 VGA_BLU C92 PEG_RX12- D92 PEG_TX12-
A93 GPO0 B93 VGA_HSYNC C93 GND D93 GND
A94 SPI_CLK B94 VGA_VSYNC C94 PEG_RX13+ D94 PEG_TX13+
A95 SPI_MOSI B95 VGA_I2C_CK C95 PEG_RX13- D95 PEG_TX13-
A96 GND B96 VGA_I2C_DAT C96 GND D96 GND
A97 TYPE10# B97 SPI_CS# C97 RSVD D97 PEG_ENABLE#
A98 RSVD B98 RSVD C98 PEG_RX14+ D98 PEG_TX14+
A99 RSVD B99 RSVD C99 PEG_RX14- D99 PEG_TX14A100 GND (FIXED) B100 GND (FIXED) C100 GND (FIXED) D100 GND (FIXED)
A101 RSVD B101 RSVD C101 PEG_RX15+ D101 PEG_TX15+
A102 RSVD B102 RSVD C102 PEG_RX15- D102 PEG_TX15A103 RSVD B103 RSVD C103 GND D103 GND
A104 VCC_12V B104 VCC_12V C104 VCC_12V D104 VCC_12V
A105 VCC_12V B105 VCC_12V C105 VCC_12V D105 VCC_12V
A106 VCC_12V B106 VCC_12V C106 VCC_12V D106 VCC_12V
A107 VCC_12V B107 VCC_12V C107 VCC_12V D107 VCC_12V
A108 VCC_12V B108 VCC_12V C108 VCC_12V D108 VCC_12V
A109 VCC_12V B109 VCC_12V C109 VCC_12V D109 VCC_12V
A110 GND (FIXED) B110 GND (FIXED) C110 GND (FIXED) D110 GND (FIXED)
*Note: SATA1 port not supported by HM86 chipset.
Page 14 Express-HL2
3.2 Signal Description Terminology
The following terms are used in the COM Express AB/CD Signal Descriptions below.
I Input to the Module
O Output from the Module
I/O Bi-directional input / output signal
OD Open drain output
I 3.3V Input 3.3V tolerant
I 5V Input 5V tolerant
O 3.3V Output 3.3V signal level
O 5V Output 5V signal level
I/O 3.3V Bi-directional signal 3.3V tolerant
I/O 5V Bi-directional signal 5V tolerant
I/O 3.3Vsb Input 3.3V tolerant active in standby state
P Power Input/Output
REF Reference voltage output that may be sourced from a module power plane.
PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected.
The signal is used to indicate the PICMG module type to the Carrier Board.
PU ADLINK implemented pull-up resistor on module
PD ADLINK implemented pull-down resistor on module
Express-HL2 Page 15
3.3 AB Signal Descriptions
3.3.1 Audio Signals
Signal Pin # Description I/O PU/PD Comment
AC_RST# /
HDA_RST#
AC_SYNC /
HDA_SYNC
AC_BITCLK /
HDA_BITCLK
AC _SDOUT /
HDA_SDOUT
AC _SDIN[2:0]
HDA_SDIN[2:0]
A30 Reset output to codec, active low. O 3.3VSB
A29 Sample-synchronization signal to the codec(s). O 3.3V
A32 Serial data clock generated by the external codec(s). I/O 3.3V
A33 Serial TDM data output to the codec. O 3.3V
B28
Serial TDM data inputs from up to 3 codecs. I/O 3.3V
B30
3.3.2 Analog VGA
Signal Pin # Description I/O PU/PD Comment
VGA_RED B89 Red for monitor.
Analog DAC output, designed to drive a 37.5-Ohm
equivalent load.
VGA_GRN B91 Green for monitor
Analog DAC output, designed to drive a 37.5-Ohm
equivalent load.
O Analog
O Analog
PD 150R
PD 150R
Shall also be terminated on the
carrier with 150Ω resistor to
ground close to VGA connector
Shall also be terminated on the
carrier with 150Ω resistor to
ground close to VGA connector
VGA_BLU B92 Blue for monitor.
Analog DAC output, designed to drive a 37.5-Ohm
equivalent load.
VGA_HSYNC B93 Horizontal sync output to VGA monitor O 3.3V
VGA_VSYNC B94 Vertical sync output to VGA monitor O 3.3V
VGA_I2C_CK B95 DDC clock line (I²C port dedicated to identify VGA
monitor capabilities)
VGA_I2C_DAT B96 DDC data line. I/O OD 3.3V PU 2k2
O Analog
I/O OD 3.3V PU 2k2
PD 150R
3.3V
3.3V
Shall also be terminated on the
carrier with 150Ω resistor to
ground close to VGA connector
Page 16 Express-HL2
3.3.3 LVDS
Signal Pin # Description I/O PU/PD Comment
LVDS_A0+
LVDS_A0-
LVDS_A1+
LVDS_A1-
LVDS_A2+
LVDS_A2-
LVDS_A3+
LVDS_A3-
LVDS_A_CK+
LVDS_A_CK-
LVDS_B0+
LVDS_B0-
LVDS_B1+
LVDS_B1-
LVDS_B2+
LVDS_B2-
LVDS_B3+
LVDS_B3-
LVDS_B_CK+
LVDS_B_CK-
LVDS_VDD_EN A77 LVDS panel power enable O 3.3V
LVDS_BKLT_EN B79 LVDS panel backlight enable O 3.3V
LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3.3V PD 100K
A71
A72
A73
A74
A75
A76
A78
A79
A81
A82
B71
B72
B73
B74
B75
B76
B77
B78
B81
B82
LVDS Channel A differential pairs O LVDS
LVDS Channel A differential clock O LVDS
LVDS Channel B differential pairs O LVDS
LVDS Channel B differential clock O LVDS
Realtek ePD to
LVDS requirement
LVDS_I2C_CK A83 DDC lines used for flat panel detection and control. O 3.3V PU 2k2 3.3V
LVDS_I2C_DAT A84 DDC lines used for flat panel detection and control. I/O 3.3V PU 2k2 3.3V
3.3.4 Gigabit Ethernet
Gigabit Ethernet Pin # Description I/O PU/PD Comment
GBE0_MDI0+
GBE0_MDI0-
GBE0_MDI1+
GBE0_MDI1-
GBE0_MDI2+
GBE0_MDI2-
GBE0_MDI3+
GBE0_MDI3-
GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. O 3.3VSB PU 10k
GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. O 3.3VSB
GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low. O 3.3VSB
GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low. O 3.3VSB
GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics
A13
A12
A10
A9
A7
A6
A3
A2
Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs
0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes.
Some pairs are unused in some modes according to the following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/MDI[3]+/- B1_DD+/-
center tap. The reference voltage is determined by the requirements of the
Module PHY and may be as low as 0V and as high as 3.3V. The
reference voltage output shall be current limited on the Module. In the
case in which the reference is shorted to ground, the current shall be 250
mA or less.
I/O Analog Twisted pair
signals for
external
transformer.
3.3VSB
GND min
3.3V max
Express-HL2 Page 17
3.3.5 Serial ATA
Signal Pin # Description I/O PU/PD Comment
SATA0_TX+
SATA0_TX-
SATA0_RX+
SATA0_RX-
SATA1_TX+*
SATA1_TX-*
SATA1_RX+*
SATA1_RX-*
SATA2_TX+
SATA2_TX-
SATA2_RX+
SATA2_RX-
SATA3_TX+
SATA3_TX-
SATA3_RX+
SATA3_RX-
(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity indicator, active low. O 3.3V
A16
Serial ATA channel 0, Transmit Output differential pair. O SATA AC coupled on Module
A17
A19
Serial ATA channel 0, Receive Input differential pair. I SATA AC coupled on Module
A20
B16
Serial ATA channel 1, Transmit Output differential pair. O SATA AC coupled on Module
B17
B19
Serial ATA channel 1, Receive Input differential pair. I SATA AC coupled on Module
B20
A22
Serial ATA channel 2, Transmit Output differential pair. O SATA AC coupled on Module
A23
A25
Serial ATA channel 2, Receive Input differential pair. I SATA AC coupled on Module
A26
B22
Serial ATA channel 3, Transmit Output differential pair. O SATA AC coupled on Module
B23
B25
Serial ATA channel 3, Receive Input differential pair. I SATA AC coupled on Module
B26
*Note: SATA1 port not supported by HM86 chipset.
Page 18 Express-HL2
3.3.6 PCI Express
Signal Pin # Description I/O PU/PD Comment
PCIE_TX0+
PCIE_TX0-
PCIE_RX0+
PCIE_RX0-
PCIE_TX1+
PCIE_TX1-
PCIE_RX1+
PCIE_RX1-
PCIE_TX2+
PCIE_TX2-
PCIE_RX2+
PCIE_RX2-
PCIE_TX3+
PCIE_TX3-
PCIE_RX3+
PCIE_RX3-
PCIE_TX4+
PCIE_TX4-
PCIE_RX4+
PCIE_RX4-
PCIE_TX5+
PCIE_TX5-
A68
A69
B68
B69
A64
A65
B64
B65
A61
A62
B61
B62
A58
A59
B58
B59
A55
A56
B55
B56
A52
A53
PCI Express channel 0, Transmit Output
differential pair.
PCI Express channel 0, Receive Input
differential pair.
PCI Express channel 1, Transmit Output
differential pair.
PCI Express channel 1, Receive Input
differential pair.
PCI Express channel 2, Transmit Output
differential pair.
PCI Express channel 2, Receive Input
differential pair.
PCI Express channel 3, Transmit Output
differential pair.
PCI Express channel 3, Receive Input
differential pair.
PCI Express channel 4, Transmit Output
differential pair.
PCI Express channel 4, Receive Input
differential pair.
PCI Express channel 5, Transmit Output
differential pair.
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
PCIE_RX5+
PCIE_RX5-
PCIE_CLK_REF+
PCIE_CLK_REF-
B52
B53
A88
A89
PCI Express channel 5, Receive Input
differential pair.
PCI Express Reference Clock output for all PCI
Express and PCI Express Graphics Lanes.
I PCIE AC coupled off Module
O PCIE
3.3.7 Express Card
Signal Pin # Description I/O PU/PD Comment
EXCD0_CPPE#
EXCD1_CPPE#
EXCD0_PERST#
EXCD1_PERST#
A49
B48
A48
B47
PCI ExpressCard: PCI Express capable card request I 3.3V PU 10k 3.3V
PCI ExpressCard: reset O 3.3V
3.3.8 LPC Bus
Signal Pin # Description I/O PU/PD Comment
LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V
LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V
LPC_DRQ0#
LPC_DRQ1#
B8
B9
LPC serial DMA request I 3.3V
LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V PU 8k2 3.3V
LPC_CLK B10 LPC clock output - 33MHz nominal O 3.3V
Express-HL2 Page 19
3.3.9 USB
Signal Pin # Description I/O PU/PD Comment
USB0+
USB0-
USB1+
USB1-
USB2+
USB2-
USB3+
USB3-
USB4+
USB4-
USB5+
USB5-
USB6+
USB6-
USB7+
USB7-
USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up
A46
USB differential data pairs for Port 0 I/O 3.3VSB USB 1.1/ 2.0 compliant
A45
B46
USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant
B45
A43
USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant
A42
B43
USB differential data pairs for Port 2 I/O 3.3VSB USB 1.1/ 2.0 compliant
B42
A40
USB differential data pairs for Port 3 I/O 3.3VSB USB 1.1/ 2.0 compliant
A39
B40
USB differential data pairs for Port 4 I/O 3.3VSB USB 1.1/ 2.0 compliant
B39
A37
USB differential data pairs for Port 5 I/O 3.3VSB USB 1.1/ 2.0 compliant
A36
B37
USB differential data pairs for Port 6 I/O 3.3VSB USB 1.1/ 2.0 compliant
B37
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low. .
USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
Page 20 Express-HL2
3.3.10 USB Root Segmentation
Express-HL2 Page 21
3.3.11 SPI (BIOS only)
Signal Pin # Description I/O PU/PD Comment
SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB
SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB
SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module –
nominally 3.3V.
The Module shall provide a minimum of 100mA on
SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER.
SPI_POWER shall only be used to power SPI devices on the
Carrier
BIOS_DIS0# A34 Selection strap to determine the BIOS boot device. I PU 10K 3.3V Carrier shall pull to GND or
BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. I PU 10K 3.3V Carrier shall pull to GND or
O P 3.3VSB
leave no- connect.
leave no- connect
3.3.12 Miscellaneous
Signal Pin # Description I/O PU/PD Comment
SPKR B32 Output for audio enunciator, the “speaker” in PC-AT
systems
WDT B27 Output indicating that a watchdog time-out event has
occurred.
THRM# B35 Input from off-module temp sensor indicating an over-
temp situation.
THERMTRIP# A35 Active low output indicating that the CPU has entered
thermal shutdown.
O 3.3V
O 3.3V
I 3.3V
O 3.3V PU 330 3.3V
FAN_PWMOUT B101 Fan speed control. Uses the Pulse Width Modulation
(PWM) technique to control the fan’s RPM.
FAN_TACHIN11 B102 Fan tachometer input for a fan with a two pulse output. I OD 3.3V PU 10k 3.3V
TPM_PP11 C83 Trusted Platform Module (TPM) Physical Presence pin.
Active high. TPM chip has an internal pull down. This
signal is used to indicate Physical Presence to the TPM.
O OD 3.3V
I 3.3V
PD 10k 3.3V
PD is only placed when
TPM is installed on module
3.3.13 SMBus
Signal Pin # Description I/O PU/PD Comment
SMB_CK B13 System Management Bus bidirectional clock line. Power
sourced through 5V standby rail and main power rails.
SMB_DAT# B14 System Management Bus bidirectional data line. Power
sourced through 5V standby rail and main power rails.
SMB_ALERT# B15 System Management Bus Alert – active low input can be
used to generate an SMI# (System Management Interrupt) or
to wake the system. Power sourced through 5V standby rail
and main power rails.
Page 22 Express-HL2
I/O OD
3.3VSB
I/O OD
3.3VSB
I 3.3VSB PU 10k
PU 2k2
3.3VSB
PU 2k2
3.3VSB
3.3VSB
3.3.14 I2C Bus
Signal Pin # Description I/O PU/PD Comment
I2C_CK B33 General purpose I²C port clock output/input I/O OD 3.3VSB PU 2k2 3.3VSB
I2C_DAT B34 General purpose I²C port data I/O line I/O OD 3.3VSB PU 2k2 3.3VSB
3.3.15 General Purpose I/O (GPIO)
Signal Pin # Description I/O PU/PD Comment
GPO[0] A93 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET
output low
GPO[1] B54 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET
output low
GPO[2] B57 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET
output low
GPO[3] B63 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET
GPI[0] A54 General purpose input pins.
Pulled high internally on the module.
GPI[1] A63 General purpose input pins.
Pulled high internally on the module.
GPI[2] A67 General purpose input pins.
Pulled high internally on the module.
GPI[3] A85 General purpose input pins.
Pulled high internally on the module.
output low
I 3.3V PU 10K 3.3V
I 3.3V PU 10K 3.3V
I 3.3V PU 10K 3.3V
I 3.3V PU 10K 3.3V
3.3.16 Serial Interface Signals
Signal Pin # Description I/O PU/PD Comment
SER0_TX A98 General purpose serial port transmitter (TTL level output) O CMOS Power rail tolerance 5V /
12V
SER0_RX A99 General purpose serial port receiver (TTL level input) I CMOS Power rail tolerance 5V /
12V
SER1_TX A101 General purpose serial port transmitter (TTL level output) O CMOS Power rail tolerance 5V /
12V
SER1_RX A102 General purpose serial port receiver (TTL level input) I CMOS Power rail tolerance 5V /
12V
Express-HL2 Page 23
3.3.17 Power and System Management
Signal Pin # Description I/O PU/PD Comment
PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge. I 3.3VSB PU 10k
3.3VSB
SYS_RESET# B49 Reset button input. Active low request for module to reset and reboot. May
be falling edge sensitive. For situations when SYS_RESET# is not able to
reestablish control of the system, PWR_OK or a power cycle may be used.
CB_RESET# B50 Reset output from module to Carrier Board. Active low. Issued by module
chipset and may result from a low SYS_RESET# input, a low PWR_OK
input, a VCC_12V power input that falls below the minimum specification, a
watchdog timeout, or may be initiated by the module software.
PWR_OK B24 Power OK from main power supply. A high value indicates that the power is
good. This signal can be used to hold off Module startup to allow carrier
based FPGAs or other configurable devices time to be programmed.
SUS_STAT# B18 Indicates imminent suspend operation; used to notify LPC devices. O 3.3VSB
SUS_S3# A15 Indicates system is in Suspend to RAM state. Active-low output. An inverted
copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be
used to enable the non-standby power on a typical ATX power supply.
SUS_S4# A18 Indicates system is in Suspend to Disk state. Active low output. O 3.3VSB
SUS_S5# A24 Indicates system is in Soft Off state. O 3.3VSB
WAKE0# B66 PCI Express wake up signal. I 3.3VSB PU 10k
WAKE1# B67 General purpose wake up signal. May be used to implement wake-up on
PS/2 keyboard or mouse activity.
I 3.3VSB PU 10k
3.3VSB
O 3.3VSB
I 3.3V PU 100k
3.3VSB
O 3.3VSB
3.3VSB
I 3.3VSB PU 10k
3.3VSB
BATLOW# A27 Battery low input. This signal may be driven low by external circuitry to
signal that the system battery is low, or may be used to signal some other
external power-management event.
LID# LID button. Low active signal used by the ACPI operating system for a LID
switch.
SLEEP# Sleep button. Low active signal used by the ACPI operating system to bring
the system to sleep state or to wake it up again.
I 3.3VSB PU 10k
3.3VSB
I OD
3.3VSB
I OD
3.3VSB
PU 10k
3.3VSB
PU 10K
3.3VSB
3.3.18 Power and Ground
Signal Pin # Description I/O PU/PD Comment
VCC_12V A104-A109
B104-B109
VCC_5V_SBY B84-B87 Standby power input: +5.0V nominal. If VCC5_SBY is used, all
VCC_RTC A47 Real-time clock circuit-power input. Nominally +3.0V. P
GND A1, A11, A21, A31,
A41, A51, A57, A66,
A80, A90, A96,
A100, A110, B1,
B11, B21 ,B31, B41,
B51, B60, B70, B80,
B90, B100, B110
Primary power input: +12V nominal (8.5 ~ 20V wide input).
All available VCC_12V pins on the connector(s) shall be used.
available VCC_5V_SBY pins on the connector(s) shall be used.
Only used for standby and suspend functions. May be left
unconnected if these functions are not used in the system design.
Ground - DC power and signal and AC signal return path. P
P 8.5V ~20V
P 5Vsb ±5%
Page 24 Express-HL2
3.4 CD Signal Descriptions
3.4.1 PATA IDE
Signal Pin # Description I/O PU/PD Comment
Bidirectional data to / from IDE device. I/O 3.3V
IDE_D0
IDE_D1
IDE_D2
IDE_D3
IDE_D4
IDE_D5
IDE_D6
IDE_D7
IDE_D8
IDE_D9
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
IDE_A0 D13 Address lines to IDE device. O 3.3V
IDE_A1 D14 Address lines to IDE device. O 3.3V
IDE_A2 D15 Address lines to IDE device. O 3.3V
IDE_IOW# D9 I/O write line to IDE device. Data latched on trailing (rising) edge. O 3.3V
IDE_IOR# C14 I/O read line to IDE device. O 3.3V
IDE_REQ D8 IDE Device DMA Request. It is asserted by the IDE device to request a
IDE_ACK# D10 IDE Device DMA Acknowledge. O 3.3V
IDE_CS1# D16 IDE Device Chip Select for 1F0h to 1FFh range. O 3.3V
IDE_CS3# D17 IDE Device Chip Select for 3F0h to 3FFh range. O 3.3V
IDE_IORDY C13 IDE device I/O ready input. Pulled low by the IDE device to extend the
IDE_RESET# D18 Reset output to IDE device, active low. O 3.3V
IDE_IRQ D12 Interrupt request from IDE device. I 3.3V PD 10k
IDE_CBLID# D77 Input from off-module hardware indicating the type of IDE cable being
D7
C10
C8
C4
D6
D2
C3
C2
C6
C7
D3
D4
D5
C9
C12
C5
I 3.3V
data transfer.
I 3.3V PU 4k7 3.3V
cycle.
shall
I 3.3V
used. High indicates a 40-pin cable used for legacy IDE modes. Low
indicates that an 80-pin cable with interleaved grounds is used. Such a
cable is required for Ultra-DMA 66, 100 and 133 modes.
3.4.2 PCI
Signal Pin # Description I/O PU/PD Comment
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
Express-HL2 Page 25
C24
D22
C25
D23
C26
D24
C27
D25
C28
D27
C29
D28
C30
PCI bus multiplexed address and data lines I/O 3.3V
Signal Pin # Description I/O PU/PD Comment
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
D29
C32
D30
D37
C39
D38
C40
D39
C42
D40
C43
D42
C45
D43
C46
D44
C47
D45
C48
PCI_C/BE0#
PCI_C/BE1#
PCI_C/BE2#
PCI_C/BE3#
PCI_DEVSEL# C36 PCI bus Device Select, active low. I/O 3.3V PU 8k2
PCI_FRAME# D36 PCI bus Frame control line, active low. I/O 3.3V PU 8k2
PCI_IRDY# C37 PCI bus Initiator Ready control line, active low. I/O 3.3V PU 8k2
PCI_TRDY# D35 PCI bus Target Ready control line, active low. I/O 3.3V PU 8k2
PCI_STOP# D34 PCI bus STOP control line, active low, driven by cycle initiator. I/O 3.3V PU 8k2
PCI_PAR D32 PCI bus parity I/O 3.3V
PCI_PERR# C34 Parity Error:
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
D26
C33
C38
C44
C22
C19
C17
D20
PCI bus byte enable lines, active low I/O 3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
I/O 3.3V PU 8k2
An external PCI device drives PERR# when it receives data that
has a parity error.
PCI bus master request input lines, active low. I 3.3V PU 8k2
3.3V
3.3V
PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#
PCI_RESET# C23 PCI Reset output, active low. O 3.3V
PCI_LOCK# C35 PCI Lock control line, active low. I/O 3.3V PU 8k2
PCI_SERR# D33 System Error: SERR# may be pulsed active by any PCI device
PCI_PME# C15 PCI Power Management Event: PCI peripherals drive PME# to
PCI_CLKRUN# D48 Bidirectional pin used to support PCI clock run protocol for mobile
PCI_IRQA# C49 PCI interrupt request lines I 3.3V PU 8k2
C20
C18
C16
D19
PCI bus master grant output lines, active low. O 3.3V PCI_GNT[0..3]# are boot
strap signals
3.3V
that detects a system error condition.
wake system from low-power states S1–S5.
systems.
I/O 3.3V PU 8k2
3.3V
I 3.3VSB
I/O 3.3V PU 10k
3.3V
Page 26 Express-HL2
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