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Express-HL2 Page 3
Table of Contents
Revision History ............................................................................................................ 2
2.3 Video .............................................................................................................................................7
7.1 Menu Structure.......................................................................................................................... 47
7.2 Main ........................................................................................................................................... 48
Getting Service ............................................................................................................ 85
Express-HL2 Page 5
1 Introduction
The Express-HL2 is a COM Express® COM.0 R2.1 Type 2 module supporting the 64-bit 4th Generation Intel® Core™ i7/i5/3 processor with
mobile Intel® QM87 Chipset or 4th Generation Intel® Celeron® processor with mobile Intel® HM86 Chipset. The Express-HL2 is specifically
designed for customers who need high-level processing and graphics performance in a long product life solution.
The Express-HL2 features Intel® Hyper-Threading Technology (up to 4 cores, 8 threads) and non-ECC type DDR3L dual-channel memory
at 1333/1600 MHz in dual stacked SODIMM sockets up to 16 GB to provide excellent overall performance. Intel® Flexible Display Interface
and Direct Media Interface provide high speed connectivity to the mobile Intel® QM87/HM86 Chipset.
Integrated Intel® Generation 7.5 Graphics includes features such as OpenGL 3.1, DirectX 11, Intel® Clear Video HD Technology, Advanced
Scheduler 2.0, 1.0, XPDM support, and DirectX Video Acceleration (DXVA) support for full AVC/VC1/MPEG2 hardware decode. Graphics
outputs include VGA and LVDS. The Express-HL2 is specifically designed for customers with high-performance processing graphics
requirements who want to outsource the custom core logic of their systems for reduced development time.
The Express-HL2 features a single onboard Gigabit Ethernet port, USB 2.0 ports, PATA port, SATA 6 Gb/s ports, 32-bit PCI bus, rev 2.3,
and a multiplexed PCI Express® x16 graphics bus for discrete graphics expansion or general purpose PCI Express® x8 or x4 connectivity.
Support is also provided for SMBus and I
features such as remote console, CMOS backup, hardware monitor, and watchdog timer.
2
C and the module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded
• 2 independent and simultaneous display combinations of VGA / LVDS monitors
• Encode/transcode HD content
• Playback of high definition content including Blu-ray Disc
• Superior image quality with sharper, more colorful images
• Playback of Blu-ray disc S3D content using HDMI (1.4a spec compliant with 3D)
• DirectX Video Acceleration (DXVA) support for accelerating video processing
• Full AVC/VC1/MPEG2 HW Decode
• Advanced Scheduler 2.0, 1.0, XPDM support
• Windows 8, Windows 7, OSX, Linux OS support
• DirectX 11, DirectX
¾ Multi Display Support: 2 independent displays
¾ Display Types
• VGA Interface support with 300 MHz DAC Analog monitor support up to QXGA (2048 x 1536)
• LVDS Interface single/dual channel 18/24-bit LVDS through eDP (two lane) to LVDS Realtek RTD2136R
2.4 Audio
¾ Integrated: Intel® HD Audio integrated in PCH QM87/HM86
¾ Audio Codec: Realtek ALC886 on Express-BASE
Express-HL2 Page 7
2.5 LAN
¾ Integrated: LAN MAC integrated in PCH QM87/HM86
¾ Intel PHY: Intel® Ethernet Controller i217LM
¾ Interface: 10/100/1000 GbE connection
2.6 Multi I/O and Storage
¾ Integrated in Intel® QM87/HM86 Express Chipset
¾ USB ports: 8 ports USB 2.0 (USB 0,1,2,3,4,5,6,7)
¾ SATA ports: four ports SATA 6Gb/s (SATA0, SATA1, SATA2, SATA3) – QM87
three ports SATA 6Gb/s (SATA0, SATA2, SATA3, no SATA1) – HM86
¾ PATA ports: one PATA IDE (through SATA to PATA bridge)
¾ GPIO: 4 GPO and 4 GPI with interrupt
¾ 40-pin flat cable connector to be used with DB-40 debug module
• Supports: BIOS POST code LEDs, BMC access, SPI BIOS flashing, power testpoints, debug LEDs
¾ 60-pin XDP header for ICE debug of CPU/chipset
Page 8 Express-HL2
2.10 Power Specifications
¾ Power Modes: AT and ATX mode (AT mode start controlled by SEMA)
¾ Standard Voltage Input: ATX = 12V±5% / 5Vsb ±5% or AT = 12V ±5%
¾ Wide Voltage Input: ATX = 8.5~20 V / 5Vsb ±5% or AT = 8.5 ~20V
¾ Power Management: ACPI 4.0 compliant, Smart Battery support
¾ Power States: supports C1-C6, S0, S1, S4, S3, S5, S5 ECO mode (Wake on USB S3/S4, WOL S3/S4/S5)
2.11 Operating Temperatures
¾ Standard Operating Temperature: 0°C to 60°C (wide voltage input)
¾ Extreme Rugged Operating Temperature: -40°C to 85°C (standard voltage input)
2.12 Environmental
¾ Humidity: 5-90% RH operating, non-condensing
5-95% RH storage (and operating with conformal coating).
¾ Shock and Vibration: IEC 60068-2-64 and IEC-60068-2-27
MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D
¾ Halt: Thermal Stress, Vibration Stress, Thermal Shock and Combined Test
2.13 Specification Compliance
¾ PICMG COM.0: Rev 2.1 Type 2, basic size 125 x 95 mm
2.14 Operating Systems
¾ Standard Support: Windows 7/8 32/64-bit, Linux 32/64-bit
¾ Extended Support (BSP): Windows Embedded Standard 7/8, Linux , VxWorks, QNX
Express-HL2 Page 9
2.15 Function Diagram
Page 10 Express-HL2
2.16Mechanical Drawing
connector onbottom side
Alltolerances ± 0.05 mm
Othertolerances ± 0.2 mm
Express-HL2Page 11
3Pinouts and Signal Descriptions
3.1 AB / CD Pin Definitions
The Express-HL2 is a Type 2 module supporting PCI and PATA on the CD connector
All pins in the COM Express specification are described, including those not supported on the Express-HL2. Those not supported on the
Express-HL2 module are crossed out
Row A Row B Row C Row D
Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. O 3.3VSB PU 10k
GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. O 3.3VSB
GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low. O 3.3VSB
GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low. O 3.3VSB
GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics
A13
A12
A10
A9
A7
A6
A3
A2
Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs
0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes.
Some pairs are unused in some modes according to the following:
center tap. The reference voltage is determined by the requirements of the
Module PHY and may be as low as 0V and as high as 3.3V. The
reference voltage output shall be current limited on the Module. In the
case in which the reference is shorted to ground, the current shall be 250
mA or less.
I/O Analog Twisted pair
signals for
external
transformer.
3.3VSB
GND min
3.3V max
Express-HL2 Page 17
3.3.5 Serial ATA
Signal Pin # Description I/O PU/PD Comment
SATA0_TX+
SATA0_TX-
SATA0_RX+
SATA0_RX-
SATA1_TX+*
SATA1_TX-*
SATA1_RX+*
SATA1_RX-*
SATA2_TX+
SATA2_TX-
SATA2_RX+
SATA2_RX-
SATA3_TX+
SATA3_TX-
SATA3_RX+
SATA3_RX-
(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity indicator, active low. O 3.3V
A16
Serial ATA channel 0, Transmit Output differential pair. O SATA AC coupled on Module
A17
A19
Serial ATA channel 0, Receive Input differential pair. I SATA AC coupled on Module
A20
B16
Serial ATA channel 1, Transmit Output differential pair. O SATA AC coupled on Module
B17
B19
Serial ATA channel 1, Receive Input differential pair. I SATA AC coupled on Module
B20
A22
Serial ATA channel 2, Transmit Output differential pair. O SATA AC coupled on Module
A23
A25
Serial ATA channel 2, Receive Input differential pair. I SATA AC coupled on Module
A26
B22
Serial ATA channel 3, Transmit Output differential pair. O SATA AC coupled on Module
B23
B25
Serial ATA channel 3, Receive Input differential pair. I SATA AC coupled on Module
PCI Express Reference Clock output for all PCI
Express and PCI Express Graphics Lanes.
I PCIE AC coupled off Module
O PCIE
3.3.7 Express Card
Signal Pin # Description I/O PU/PD Comment
EXCD0_CPPE#
EXCD1_CPPE#
EXCD0_PERST#
EXCD1_PERST#
A49
B48
A48
B47
PCI ExpressCard: PCI Express capable card request I 3.3V PU 10k 3.3V
PCI ExpressCard: reset O 3.3V
3.3.8 LPC Bus
Signal Pin # Description I/O PU/PD Comment
LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V
LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V
LPC_DRQ0#
LPC_DRQ1#
B8
B9
LPC serial DMA request I 3.3V
LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V PU 8k2 3.3V
LPC_CLK B10 LPC clock output - 33MHz nominal O 3.3V
Express-HL2 Page 19
3.3.9 USB
Signal Pin # Description I/O PU/PD Comment
USB0+
USB0-
USB1+
USB1-
USB2+
USB2-
USB3+
USB3-
USB4+
USB4-
USB5+
USB5-
USB6+
USB6-
USB7+
USB7-
USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up
A46
USB differential data pairs for Port 0 I/O 3.3VSB USB 1.1/ 2.0 compliant
A45
B46
USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant
B45
A43
USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant
A42
B43
USB differential data pairs for Port 2 I/O 3.3VSB USB 1.1/ 2.0 compliant
B42
A40
USB differential data pairs for Port 3 I/O 3.3VSB USB 1.1/ 2.0 compliant
A39
B40
USB differential data pairs for Port 4 I/O 3.3VSB USB 1.1/ 2.0 compliant
B39
A37
USB differential data pairs for Port 5 I/O 3.3VSB USB 1.1/ 2.0 compliant
A36
B37
USB differential data pairs for Port 6 I/O 3.3VSB USB 1.1/ 2.0 compliant
B37
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low. .
USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
Page 20Express-HL2
3.3.10 USB Root Segmentation
Express-HL2 Page 21
3.3.11 SPI (BIOS only)
Signal Pin # Description I/O PU/PD Comment
SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB
SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB
SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module –
nominally 3.3V.
The Module shall provide a minimum of 100mA on
SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER.
SPI_POWER shall only be used to power SPI devices on the
Carrier
BIOS_DIS0# A34 Selection strap to determine the BIOS boot device. I PU 10K 3.3V Carrier shall pull to GND or
BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. I PU 10K 3.3V Carrier shall pull to GND or
O P 3.3VSB
leave no- connect.
leave no- connect
3.3.12 Miscellaneous
Signal Pin # Description I/O PU/PD Comment
SPKR B32 Output for audio enunciator, the “speaker” in PC-AT
systems
WDT B27 Output indicating that a watchdog time-out event has
occurred.
THRM# B35 Input from off-module temp sensor indicating an over-
temp situation.
THERMTRIP# A35 Active low output indicating that the CPU has entered
thermal shutdown.
O 3.3V
O 3.3V
I 3.3V
O 3.3V PU 330 3.3V
FAN_PWMOUT B101 Fan speed control. Uses the Pulse Width Modulation
(PWM) technique to control the fan’s RPM.
FAN_TACHIN11 B102 Fan tachometer input for a fan with a two pulse output. I OD 3.3V PU 10k 3.3V
Active high. TPM chip has an internal pull down. This
signal is used to indicate Physical Presence to the TPM.
O OD 3.3V
I 3.3V
PD 10k 3.3V
PD is only placed when
TPM is installed on module
3.3.13 SMBus
Signal Pin # Description I/O PU/PD Comment
SMB_CK B13 System Management Bus bidirectional clock line. Power
sourced through 5V standby rail and main power rails.
SMB_DAT# B14 System Management Bus bidirectional data line. Power
sourced through 5V standby rail and main power rails.
SMB_ALERT# B15 System Management Bus Alert – active low input can be
used to generate an SMI# (System Management Interrupt) or
to wake the system. Power sourced through 5V standby rail
and main power rails.
Page 22Express-HL2
I/O OD
3.3VSB
I/O OD
3.3VSB
I 3.3VSB PU 10k
PU 2k2
3.3VSB
PU 2k2
3.3VSB
3.3VSB
3.3.14 I2C Bus
Signal Pin # Description I/O PU/PD Comment
I2C_CK B33 General purpose I²C port clock output/input I/O OD 3.3VSB PU 2k2 3.3VSB
I2C_DAT B34 General purpose I²C port data I/O line I/O OD 3.3VSB PU 2k2 3.3VSB
3.3.15 General Purpose I/O (GPIO)
Signal Pin # Description I/O PU/PD Comment
GPO[0] A93 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET
output low
GPO[1] B54 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET
output low
GPO[2] B57 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET
output low
GPO[3] B63 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET
GPI[0] A54 General purpose input pins.
Pulled high internally on the module.
GPI[1] A63 General purpose input pins.
Pulled high internally on the module.
GPI[2] A67 General purpose input pins.
Pulled high internally on the module.
GPI[3] A85 General purpose input pins.
Pulled high internally on the module.
output low
I 3.3V PU 10K 3.3V
I 3.3V PU 10K 3.3V
I 3.3V PU 10K 3.3V
I 3.3V PU 10K 3.3V
3.3.16 Serial Interface Signals
Signal Pin # Description I/O PU/PD Comment
SER0_TX A98 General purpose serial port transmitter (TTL level output) O CMOS Power rail tolerance 5V /
12V
SER0_RX A99 General purpose serial port receiver (TTL level input) I CMOS Power rail tolerance 5V /
12V
SER1_TX A101 General purpose serial port transmitter (TTL level output) O CMOS Power rail tolerance 5V /
12V
SER1_RX A102 General purpose serial port receiver (TTL level input) I CMOS Power rail tolerance 5V /
12V
Express-HL2 Page 23
3.3.17 Power and System Management
Signal Pin # Description I/O PU/PD Comment
PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge. I 3.3VSB PU 10k
3.3VSB
SYS_RESET# B49 Reset button input. Active low request for module to reset and reboot. May
be falling edge sensitive. For situations when SYS_RESET# is not able to
reestablish control of the system, PWR_OK or a power cycle may be used.
CB_RESET# B50 Reset output from module to Carrier Board. Active low. Issued by module
chipset and may result from a low SYS_RESET# input, a low PWR_OK
input, a VCC_12V power input that falls below the minimum specification, a
watchdog timeout, or may be initiated by the module software.
PWR_OK B24 Power OK from main power supply. A high value indicates that the power is
good. This signal can be used to hold off Module startup to allow carrier
based FPGAs or other configurable devices time to be programmed.
SUS_STAT# B18 Indicates imminent suspend operation; used to notify LPC devices. O 3.3VSB
SUS_S3# A15 Indicates system is in Suspend to RAM state. Active-low output. An inverted
copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be
used to enable the non-standby power on a typical ATX power supply.
SUS_S4# A18 Indicates system is in Suspend to Disk state. Active low output. O 3.3VSB
SUS_S5# A24 Indicates system is in Soft Off state. O 3.3VSB
WAKE0# B66 PCI Express wake up signal. I 3.3VSB PU 10k
WAKE1# B67 General purpose wake up signal. May be used to implement wake-up on
PS/2 keyboard or mouse activity.
I 3.3VSB PU 10k
3.3VSB
O 3.3VSB
I 3.3V PU 100k
3.3VSB
O 3.3VSB
3.3VSB
I 3.3VSB PU 10k
3.3VSB
BATLOW# A27 Battery low input. This signal may be driven low by external circuitry to
signal that the system battery is low, or may be used to signal some other
external power-management event.
LID# LID button. Low active signal used by the ACPI operating system for a LID
switch.
SLEEP# Sleep button. Low active signal used by the ACPI operating system to bring
the system to sleep state or to wake it up again.
I 3.3VSB PU 10k
3.3VSB
I OD
3.3VSB
I OD
3.3VSB
PU 10k
3.3VSB
PU 10K
3.3VSB
3.3.18 Power and Ground
Signal Pin # Description I/O PU/PD Comment
VCC_12V A104-A109
B104-B109
VCC_5V_SBY B84-B87 Standby power input: +5.0V nominal. If VCC5_SBY is used, all
VCC_RTC A47 Real-time clock circuit-power input. Nominally +3.0V. P
Primary power input: +12V nominal (8.5 ~ 20V wide input).
All available VCC_12V pins on the connector(s) shall be used.
available VCC_5V_SBY pins on the connector(s) shall be used.
Only used for standby and suspend functions. May be left
unconnected if these functions are not used in the system design.
Ground - DC power and signal and AC signal return path. P
IDE_IOW# D9 I/O write line to IDE device. Data latched on trailing (rising) edge. O 3.3V
IDE_IOR# C14 I/O read line to IDE device. O 3.3V
IDE_REQ D8 IDE Device DMA Request. It is asserted by the IDE device to request a
IDE_ACK# D10 IDE Device DMA Acknowledge. O 3.3V
IDE_CS1# D16 IDE Device Chip Select for 1F0h to 1FFh range. O 3.3V
IDE_CS3# D17 IDE Device Chip Select for 3F0h to 3FFh range. O 3.3V
IDE_IORDY C13 IDE device I/O ready input. Pulled low by the IDE device to extend the
IDE_RESET# D18 Reset output to IDE device, active low. O 3.3V
IDE_IRQ D12 Interrupt request from IDE device. I 3.3V PD 10k
IDE_CBLID# D77 Input from off-module hardware indicating the type of IDE cable being
D7
C10
C8
C4
D6
D2
C3
C2
C6
C7
D3
D4
D5
C9
C12
C5
I 3.3V
data transfer.
I 3.3V PU 4k7 3.3V
cycle.
shall
I 3.3V
used. High indicates a 40-pin cable used for legacy IDE modes. Low
indicates that an 80-pin cable with interleaved grounds is used. Such a
cable is required for Ultra-DMA 66, 100 and 133 modes.
PCI_DEVSEL# C36 PCI bus Device Select, active low. I/O 3.3V PU 8k2
PCI_FRAME# D36 PCI bus Frame control line, active low. I/O 3.3V PU 8k2
PCI_IRDY# C37 PCI bus Initiator Ready control line, active low. I/O 3.3V PU 8k2
PCI_TRDY# D35 PCI bus Target Ready control line, active low. I/O 3.3V PU 8k2
PCI_STOP# D34 PCI bus STOP control line, active low, driven by cycle initiator. I/O 3.3V PU 8k2
PCI_PAR D32 PCI bus parity I/O 3.3V
PCI_PERR# C34 Parity Error:
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
D26
C33
C38
C44
C22
C19
C17
D20
PCI bus byte enable lines, active low I/O 3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
I/O 3.3V PU 8k2
An external PCI device drives PERR# when it receives data that
has a parity error.
PCI bus master request input lines, active low. I 3.3V PU 8k2
3.3V
3.3V
PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#
PCI_RESET# C23 PCI Reset output, active low. O 3.3V
PCI_LOCK# C35 PCI Lock control line, active low. I/O 3.3V PU 8k2
PCI_SERR# D33 System Error: SERR# may be pulsed active by any PCI device
PCI_PME# C15 PCI Power Management Event: PCI peripherals drive PME# to
PCI_CLKRUN# D48 Bidirectional pin used to support PCI clock run protocol for mobile
PCI_IRQA# C49 PCI interrupt request lines I 3.3V PU 8k2
C20
C18
C16
D19
PCI bus master grant output lines, active low. O 3.3V PCI_GNT[0..3]# are boot
strap signals
3.3V
that detects a system error condition.
wake system from low-power states S1–S5.
systems.
I/O 3.3V PU 8k2
3.3V
I 3.3VSB
I/O 3.3V PU 10k
3.3V
Page 26 Express-HL2
Signal Pin # Description I/O PU/PD Comment
PCI_IRQB#
PCI_IRQC#
PCI_IRQD#
PCI_CLK D50 PCI 33MHz clock output O 3.3V
C50
D46
D47
3.3V
3.4.3 Module Type Definition
Signal Pin # Description I/O Comment
TYPE0#
TYPE1#
TYPE2#
C54
C57
D57
The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented
on the module. The pins are tied on the module to either ground (GND) or are noconnects (NC). For Pinout Type 1, these pins are don’t care (X).
TYPE2# TYPE1# TYPE0#
X X X Pinout Type 1
NC NC NC Pinout Type 2
NC NC GND Pinout Type 3 (no IDE)
NC GND NC Pinout Type 4 (no PCI)
NC GND GND Pinout Type 5 (no IDE, no PCI)
GND NC NC Pinout Type 6 (no IDE, no PCI)
The Carrier Board should implement combinatorial logic that monitors the module
TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX
power supply) if an incompatible module pin-out type is detected. The Carrier
Board logic may also implement a fault indicator such as an LED.
¾ 40-pin Debug Connector Pin Definition on the COM Express Module
Pin Interface Signal Remark Pin Interface Signal Remark
SPI
1 VCC_SPI_IN SPI Power Input from flash tool
Program
interface
2 GND 22 RXD6
3 SPI_BIOS_CS0# 23 FUMD0
4 SPI_BIOS_CS1# 24 RESET_IN#
5 SPI_BIOS_MISO 25 DATA
6 SPI_BIOS_MOSI 26 CLK
7
8 3V3_LPC System power 3.3V provide from
LPC Bus
9 GND 29 PWRBTN#
10 BIOS_DIS0 30 SYS_RESET#
11 RST# 31 CB_RESET#
12 CLK33_LPC 32 CB_PWROK
13 LPC_FRAME# 33 SUS_S3#
SPI_BIOS_CLK 27 OCD0A Include a jumper to connect
to module. HW need add MOS
FET to switch SPI power for SPI
ROM
COM module
21 TXD6
28
BMC Program
interface
(continued)
OCD0A via 1K0 pull-up to
3.3V_BMC
OCD0B Include a jumper to connect
OCD0A via 1K0 pull-up to
3.3V_BMC
Test points
14 LPC_AD3 34 SUS_S4#
15 LPC_AD2 35
16 LPC_AD1 always power 3.3V provide from
COM module
17
BMC
18
Program
interface
19 3.3V_BMC always power 3.3V provide from
20
LPC_AD0 37 SEL_BIOS Connect to Jumper for
3.3V_BMC always power 3.3V provide from
COM module
COM module
GND 40 Reserved
36 POSTWDT_DIS# Connect to Jumper for
38 BIOS_MODE Connect to Jumper for
39
BMC Debug
signals
SUS_S5#
Debug
Debug
Debug
BMC_STATUS
Note: The pin description on the debug module is the inverse of that on the COM Express module.
Page 30 Express-HL2
4.2 Status LEDs
To facilitate easier maintenance, status LEDs are mounted on the board.
¾ LED Descriptions
Name Color Connection Function
LED1 Blue BMC output Power Sequence Status Code (BMC)
Power Changes, RESET
(see 5.1.4 Exception Codes below)
LED2 Green Power Source 3Vcc S0 LED ON
S3/S4/S5 LED OFF
ECO mode LED OFF
LED3 Red BMC output
and same signal as WDT
(B27) on BtB connector
Module power up WD LED = LED OFF
Watchdog counting WD LED = LED OFF
Watchdog timed out WD LED = LED ON
Watchdog RESET WD LED = LED ON
Rebooted after WD RESET WD LED = LED ON
Rebooted after PWRBTN WD LED = LED ON
Rebooted after RESET BTN WD LED = LED OFF
Note: only a RESET not initiated by the BMC can clear the WD LED (user action)
Express-HL2 Page 31
4.3 XDP Debug header
The debug port is a connection into a target-system environment that provides access to JTAG, run control, system control, and observation
resources. The XDP target system connector is a Samtec™ 60-pin BSH-030-01 series connector.
Pin XDP Signal Target Signal I/O Device Pin XDP Signal Target Signal I/O Device
1 GND GND NA 2 GND GND NA
3 OBSFN_A0 PREQ# I/O processor 4 OBSFN_C0 CFG[17]2 I processor
5 OBSFN_A1 PRDY# I/O processor 6 OBSFN_C1 CFG[16]2 I processor
To perform a hardware reset of BIOS default settings, perform the following steps:
1. Shut down the system.
2. Press the BIOS Setup Defaults RESET Button continuously and boot up the system. You can release the button when the BIOS
prompt screen appears
3. The BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system.
Express-HL2 Page 33
4.6 Express-HL2 Switch Settings
4.6.1 Switch Locations
Page 34 Express-HL2
4.6.2 SW1: PCI Express Configuration Switch
Switch SW1 allows you to configure the PCI Express x16 lanes from the CPU as 1 PCIe x16, 2 PCIe x8, or 1 PCIe x8 + 2 PCIe x4.
Mode Pin 1 Pin 2
1x PCIe x16 (default) Off Off
2x PCIe x8 On Off
1x PCIe x8 + 2x PCIe x4 On On
Reserved Off On
4.6.3 SW4: LVDS Panel Configuration Switch
Switch SW4 allows you to set the LVDS panel mode to 18-bit or 24-bit.
Mode Pin 2
18 bit LVDS panel mode (default) Off
24 bit LVDS panel mode On
4.6.4 SW3: BIOS Select and Mode Configuration Switch
Module has two BIOS chips and BIOS operation can be configured to "PICMG" and "Failsafe" modes using SW3, Pin 2.
Setting the module to PICMG mode will configure the BIOS chips on the module as SPI0 and SPI1. In PICMG mode, a BIOS chip CANNOT
be placed in SPI0 on the carrier.
In dual-BIOS Failsafe mode, both BIOS chips on the module are configured as SPI1. Only one of the two is connected to the SPI bus at any
given time. In case of BIOS failure of the primary SPI1 BIOS, the system will reboot and switch to the secondary SPI1 BIOS on the module.
In Failsafe mode, it is allowed to also have an SPI0 BIOS on the carrier.
In both modes, strapping can select whether to boot from SPI0 or SPI1 (SW3 Pin 1).
Mode Pin 1 Pin 2
Boot from SPI0 (Default) On —
Boot from SPI1 Off —
Set BIOS to PICMG mode — On
Set BIOS to Failsafe BIOS mode (Default) — Off
Express-HL2 Page 35
4.7 PCIe x16-to-two-x8 Adapter Card
The Express-HL can be used with the PCIe x16-to-two-x8 Adapter Card on the Express-BASE6 Reference Carrier to support bifurbication of
the CPU's PEG interface (PCIe x16). The card reroutes the PCIe x16 to two x8 and allows testing of two independent PCIe add-on cards
with x8/x4/x2/x1 width. To use the card, set SW1 to "2 x8 PCI Express" as above.
PCIex16-to-two-x8 Adapter Card
(Model: P16TO28, Part No.: 91-79301-0010)
Page 36Express-HL2
5 Smart Embedded Management Agent (SEMA)
The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality. The
microcontroller communicates via the System Management Bus with the CPU/chipset. The following functions are implemented:
• Total operating hours counter. Counts the number of hours the module has been run in minutes.
• On-time minutes counter. Counts the seconds since last system start.
• Temperature monitoring of CPU and board temperature. Minimum and maximum temperature values of CPU and board are stored
in flash.
• Power cycles counter
• Boot counter. Counts the number of boot attempts.
• Watchdog Timer (Type-II). Set / Reset / Disable Watchdog Timer. Features auto-reload at power-up.
• System Restart Cause. Power loss / BIOS Fail / Watchdog / Internal Reset / External Reset
• Fail-safe BIOS support. In case of a boot failure, hardware signals tell external logic to boot from fail-safe BIOS.
• Flash area. 1kB Flash area for customer data
• 128 Bytes Protected Flash area. Keys, IDs, etc. can be stored in a write- and clear-protectable region.
• Board Identify. Vendor / Board / Serial number / Production Date
• Main-current & voltage. Monitors drawn current and main voltages
For a detailed description of SEMA features and functionality, please refer to SEMA Technical Manual and SEMA Software Manual,
downloadable at:
http://www.adlinktech.com/sema/.
Express-HL2 Page 37
5.1 Board Specific SEMA Functions
5.1.1 Voltages
The BMC of the Express-HL2 implements a voltage monitor and samples several onboard voltages. The voltages can be read by calling the
SEMA function “Get Voltages”. The function returns a 16-bit value divided into high-byte (MSB) and low-byte (LSB).
The BMC of the Express-HL2 implements a current monitor. The current can be read by calling the SEMA function “Get Main Current”. The
function returns four 16-bit values divided in high-byte (MSB) and low-byte (LSB). These 4 values represent the last 4 currents drawn by the
board. The values are sampled every 250ms. The order of the 4 values is NOT in chronological order. Access by the BMC may increase the
drawn current of the whole system. In this case, there are still 3 samples not influenced by the read access.
Main Current = (MSB_n<<8 + LSB_n) x 8.06mA
5.1.3 BMC Status
This register shows the status of BMC controlled signals on the Express-HL2.
Status Bit Signal
0 WDT_OUT
1 LVDS_VDDEN
2 LVDS_BKLTEN
3 BIOS_MODE
4 POSTWDT_DISn
5 SEL_BIOS
6 BIOS_DIS0n
7 BIOS_DIS1n
Page 38Express-HL2
5.1.4 Excep tion Codes
In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags
register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore, a “Clear Exception
Code” command is not needed or supported.
Exception Code Error Message
0 NOERROR
2 NO_SUSCLK
3 NO_SLP_S5
4 NO_SLP_S4
5 NO_SLP_S3
6 BIOS_FAIL
7 RESET_FAIL
8 POWER_FAIL
9 LOW_VIN
11 VCORE
12 +P1V05_S
13 +P3V3_A
14 +VDDQ
15 +P5V_A
16 +P12V
18 CRITICAL_TEMP
19 NO_CB_PWROK
20 NO_SYS_GD
21
22 NO_XDP_PIN47
5.1.5 BMC Flags
The BMC Flags register returns the last detected Exception Code since power-up and shows the BIOS in use and the power mode.
Bit Description
[ 0 ~ 4 ] Exception Code
[ 6 ] 0 = AT mode
1 = ATX mode
[ 7 ] 0 = Standard BIOS
1 = Fail-safe BIOS.
Express-HL2 Page 39
6System Resources
6.1 System Memory Map
Address Range (decimal) Address Range (hex) Size Description
This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the
BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting
options are presented in bold, and the function of each setting is described in the right hand column of the respective table.
Main Advanced Boot Security Save & Exit
- System Information
- Processor Information
- PCH Information
- System ►
Management
- System Date
- System Time
- CPU ►
- Memory ►
- Graphics ►
- SATA ►
- USB ►
- Network ►
- PCI and PCIe ►
- Super IO ►
- ACPI and ►
Power
Management
- Sound ►
- Serial Port ►
Console
- Clock ►
- Thermal ►
- Miscellaneous ►
- Boot Configuration ►
-
CSM Parameters ►
- Password Description
- Secure Boot Menu ►
- Reset Options
- Save Options
Express-HL2 Page 47
7.2 Main
The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer
to the tables below the screen shot of this menu for details of the submenus and settings.
7.2.1 System Information
Feature Options Description
BIOS Version Info only ADLINK BIOS version.
Build Date and Time Info only ADLINK date the BIOS was build.
7.2.2 Pro cessor Information
Feature Options Description
CPU Brand String Info only Display CPU Brand Name.
Frequency Info only Display CPU Frequency.
Processor ID Info only Display CPU ID.
Stepping Info only Display CPU Stepping.
Number of Processors Info only Display number of Processors.
GT Info Info only Display GT info of Intel Graphics.
IGFX VBIOS Version Info only Display VBIOS Version.
Total Memory Info only Display installed memory size.
7.2.3 PCH Information
Feature Options Description
PCH Name Info only Display PCH name
PCH SKU Info only Display PCH SKU
Stepping Info only Display PCH stepping
ME FW Version Info only Display version of ME
ME Firmware SKU Info only Display ME Firmware Kit SKU number
System Management Submenu
7.2.3.1 PCH Information System Management
Feature Options Description
System Management Info only
Version Info only Display version.
Page 48Express-HL2
7.2.4 System Management
7.2.4.1 System Management > Board Information
Board Information Info only
SMC Firmware Read only Display SMC Firmware.
Build Date Read only Display SMC firmware build date.
SMC Boot loader Read only Display SMC boot loader.
Build Date Read only Display SMC boot loader build date.
Hardware Version Read only Display SMC hardware Version.
Serial Number Read only Display SMC serial Number.
Manufacturing Date Read only Display SMC manufacturing date.
Last Repair Date Read only Display SMC last repair date.
MAC ID Read only Display SMC MAC ID
SEMA Features Read only Display SEMA features
7.2.4.2 System Management > Temperatures and Fan Speed
Feature Options Description
Temperatures and Fan Speed Info only
CPU Temperature Info only
Current Read only Display CPU current temperature
Startup Read only Display CPU startup temperature
Min Read only Display CPU min temperature.
Max Read only Display CPU max temperature.
Board Temperatures Info only
Current Read only Display board current temperature
Startup Read only Display board startup temperature
Min Read only Display board min temperature.
Max Read only Display board max temperature.
.
.
.
.
CPU Fan Speed Read only Display CPU fan speed.
System Fan Speed Read only Display system fan speed.
7.2.4.3 System Management > Power Consumption
Feature Options Description
Power Consumption Info only
Current Input Current Read only Display input current
Current Input Power Read only Display input power
.
.
Express-HL2 Page 49
Feature Options Description
AIN0 Read only Display actual voltage of AIN0
V3.30 Read only Display actual voltage of 3.30 V
V1.05 Read only Display actual voltage of 1.05 V
V3.30 Read only Display actual voltage of 3.30 V
.
V1
35 Read only Display actual voltage of 1
.
V5
00 Read only Display actual voltage of 5
.
35 V
.
00 V
VIN Read only Display actual voltage of VIN
AIN7 Read only Display actual voltage of AIN7
7.2.4.4 System Management > Runtime Statistics
Feature Options Description
Runtime Statistics Info only
Total Runtime Read only The returned value specifies the total time in minutes the system
is running in S0 state
Current Runtime Read only The returned value specifies the time in seconds the system is
running in S0 state
This counter is cleared when the system is removed from the
external power supply.
Power Cycles Read only The returned value specifies the number of times the external
power supply has been shut down
Boot Cycles Read only The Bootcounter is increased after a HW- or SW-Reset or after a
successful power-up
.
.
.
Boot Reason Read only The boot reason is the event which causes the reboot of the
system
.
7.2.4.5 System Management > Flags
Feature Options Description
Flags Info only
BMC Flags Read only
BIOS Select Read only Display the selection of current BIOS ROM.
ATX/AT-Mode Read only Display ATX/AT-Mode.
Exception Code Read only System exception reason.
Page 50Express-HL2
7.2.4.6 System Management > Power Up
Feature Options Description
Power Up Info only
Power Up watchdog
Attention: F12 disables the Power Up
Enabled
Disabled
The Power-Up Watchdog resets the system after a certain
amount of time after power-up
Watchdog.
ECO Mode Disabled
Reduces the power consumption of the system.
Enable
Power-up Mode
Attention: The Power-Up Mode only has effect,
if the module is in ATX-Mode.
Turn on
Remain off
Last State
Turn On: The machine starts automatically when the power
supply is turned on
.
Remain Off :To start the machine the power button has to be
pressed.
Last State: when powered on during a power failure the system
will automatically power on when power is restored
7.2.4.7 System Management > LVDS Backlight
Feature Options Description
LVDS Backlight Info only
LVDS Backlight Bright 255 The value range starts by 0 and ends by 255.
7.2.4.8 System Management > Smart Fan
Feature Options Description
.
Smart Fan Info only
CPU Smart FanTemperature Source CPU Sensor
Select CPU smart fan source.
System Sensor
CPU Fan Mode AUTO (Smart Fan)
Select CPU Fan Mode.
Fan Off
Fan On
CPU Trigger Point 1 Read only
Trigger Temperature 15 Specifies the temperature threshold at which the BMC turns on
CPU fan with specific PWM level
.
PWM Level 30 Select PWM level.
CPU Trigger Point 2 Read only
Trigger Temperature 60 Specifies the temperature threshold at which the BMC turns on
CPU fan with specific PWM level
.
PWM Level 40 Select PWM level.
CPU Trigger Point 3 Read only
Trigger Temperature 70 Specifies the temperature threshold at which the BMC turns on
CPU fan with specific PWM level
.
PWM Level 63 Select PWM level.
CPU Trigger Point 4 Read only
Trigger Temperature 80 Specifies the temperature threshold at which the BMC turns on
CPU fan with specific PWM level
.
PWM Level 100 Select PWM level.
Express-HL2 Page 51
7.2.5 System Date and Time
Feature Options Description
System Date Weekday, MM/DD/YYYY Requires the alpha-numeric entry of the day of the week, day of the
month, calendar month, and all 4 digits of the year, indicating the
century and year (Fri XX/XX/20XX)
System Time HH/MM/SS Presented as a 24-hour clock setting in hours, minutes, and seconds
Page 52Express-HL2
7.3 Advanced
This menu contains the settings for most of the user interfaces in the system
7.3.1 CPU
Feature Options Description
CPU Info only Manufacturer, model, speed
CPU Signature Info only Display CPU Signature.
Processor Family Info only Display Processor Family.
Microcode Patch Info only Display Microcode Patch.
FSB Speed Info only Display FSB Speed
Max CPU speed Info only Display Max CPU speed.
Min CPU speed Info only Display Min CPU speed.
CPU Speed Info only Display CPU Speed.
Processor Cores Info only Display Processor Cores.
Intel HT Technology Info only Display Intel HT Technology support or not.
Intel VT-x Technology Info only Display Intel VT-x Technology support or not.
VT-d Capability Info only Display VT-d Capability support or not.
Intel SMX Technology Info only Display Intel SMX Technology support or not.
64-bit Info only Display 64-bit support or not.
L1 Data Cache Info only Display cache info.
L1 Code Cache Info only Display cache info.
L2 Cache Info only Display cache info.
L3 Cache Inf o only Display cache info.
Limit CPUID Maximum Disabled
Enabled
Execute Disable Bit Disabled
Enabled
When Enabled, the processor will limit the maximum CPUID input
value to 03h when queried, even if the processor supports a higher
CPUID input value
actual maximum CPUID input value
Enable/Disable the Execute Disable Bit (XD) of the processor.
With the XD bit set to enabled certain classes of malicious buffer
overflow attacks can be prevented when combined with a supporting
.
OS
.
When Disabled, the processor will return the
Intel Virtualization Technology Disabled
Enabled
VT-d Disabled
Enabled
SB CRID Disabled
Enabled
CPU Processor Power Managemnt (PPM) Info only
EIST Disabled
Enabled
Turbo Mode Disabled Enable/Disable turbo mode.
Enable/Disable support for the Intel virtualization technology.
Check to enable VT-d function on MCH.
Enable/Disable SB Compatible Revision ID.
Disabled: No SpeedStep, stick to CPU ratio
Enabled: CPU speed is controlled by the operating system
.
Express-HL2 Page 53
Feature Options Description
Enabled
CPU C3 Report Disabled
Enable/Disable CPU C3 report to OS.
Enabled
CPU C6 Report Disabled
Enable/Disable CPU C6 report to OS.
Enabled
CPU C7 Report Disabled
Enable/Disable CPU C7 report to OS.
CPU C7
CPU C7S
ACPI T State Disabled
Enable/Disable ACPI T state support.
Enabled
CPU DTS Disabled
Enable/Disable CPU DTS.
Enabled
7.3.2 Memory
Feature Options Description
Memory RC Version Info only Display Memory Reference Code Version.
Memory Frequency Info only Display Memory Frequency.
Total Memory Info only Display Total Memory.
Memory Voltage Info only Display Memory Voltage.
DIMM#0/1 Info only Display DIMM#0/1.
CAS Latency (tCL) Info only Display CAS Latency (tCL).
Minimum delay time Info only Display Minimum delay time.
CAS to RAS (tRCDmin) Info only Display CAS to RAS (tRCDmin).
Row Precharge (tRPmin) Info only Display Row Precharge (tRPmin).
Active to Precharge (tRASmin) Info only Display Active to Precharge (tRASmin).
XMP Profile 1 Info only Display XMP Profile 1 support or not.
XMP Profile 2 Info only Display XMP Profile 2 support or not.
SPD Write Protect Enabled
Enable:Writes to SMBus slave addresses A0h - AEh are disabled.
Disabled
Memory Frequency Limiter Auto Maximum Memory Frequency Selections in Mhz
Max TOLUD Dynamic Maximum Value of TOLUD
MRC Fast Boot Enabled
TOLUD automatically based on largest MMIO length of installed
graphic controller
Enable/Disable MRC fast boot.
.
.
Dynamic assignment would adjust
Disabled
Memory Remap Enabled
Enable/Disable e memory remap above 4G.
Disabled
Channel A DIMM Control Enabled
Enable/Disable DIMMs on channel A.
Disabled
.
Channel B DIMM Control Enabled
Enable/Disable DIMMs on channel B.
Disabled
Memory Thermal Management Enabled
Enable/Disable Memory Thermal Management.
Disabled
Page 54Express-HL2
7.3.3 Graphics
Feature Options Description
Graphics Configuration Info only
IGFX VBIOS Version Info only Display VBIOS Version.
IGfx Frequency Info only Display IGfx Frequency.
Graphics Turbo IMON Current Number entry field Graphics turbo IMON current values supported (14-31).
Primary Display Auto
IGFX
Select which of IGFX/PEG/PCI Graphics device should be Primary
Display Or select SG for Switchable Gfx
PEG
PCIE
Primary PEG Auto
PEG1
Select PEG0/PEG1/PEG2/PEG3 Graphics device should be Primary
.
PEG
PEG2
Primary PCIE Auto
PCIE1
Select PCIE0/PCIE1/PCIE2/PCIE3/PCIE4/PCIE5/PCIE6/PCIE7
Graphics device should be Primary PCIE
PCIE2
PCIE3
PCIE4
PCIE5
PCIE6
PCIE7
Internal Graphics Auto
Keep IGD enabled based on the setup options.
Disabled
Enable
Aperture Size 128MB
Select the Aperture Size.
256MB
512MB
DVMT Pre-Allocated XXM Select DVMT 5
by the Internal Graphics Device
DVMT Total Gfx Mem XXXM Select DVMT5
Graphics Device
.
.
.
0 Pre-Allocated (Fixed) Graphics Memory size used
.
0 Total Graphic Memory size used by the Internal
.
.
Gfx Low Power Mode Enabled
This option is applicable for SFF only.
Disabled
LVDS Backlight Mode BMC Mode
Select LVDS Backlight control function.
GTT Mode
GTT LVDS Backlight Control 0%
Actual backlight value in percent of the maximum setting.
20%
40%
60%
80%
100%
DDI function choose Display Port
Select DDI function choose to display port or HDMI.
HDMI
Primary IGFX Boot Display CRT Select the Video Device which will be activated during POS
ACPI Sleep State S3 only Select ACPI sleep state the system will enter when the SUSPEND
Emulation AT/ATX Emulation AT
ATX
Page 64 Express-HL2
Enables or Disables BIOS ACPI Auto Configuration.
Enables or Disables System ability to Hibernate (OS/S4 Sleep
.
This option may be not effective with some OS.
State)
.
button is pressed
Select Emulation AT or ATX function. If this option set to [Emulation
AT], BIOS will report no suspend functions to ACPI OS
XP, it will make OS show shutdown message during system
shutdown
.
In windows
.
7.3.10 Sound
Feature Options Description
Sound Info only
Azalia Disabled
Enabled
Auto
Control Detection of the Azalia device.
Disabled = Azalia will be unconditionally disabled
Enabled = Azalia will be unconditionally enabled.
Auto = Azalia will be enabled if present, disabled other.
Azalia Docking Support Enabled
Enable/Disable Azalia Docking Support of Audio Controller.
Disabled
Azalia PME Enabled
Enable/Disable Power Management capability of Audio Controller.
Disabled
7.3.11 Serial Port Console
Feature Options Description
Serial Port Console Info only
COM0 Info only
Console Redirection Enabled
Disabled
Console Redirection Settings Submenu
COM1 Info only
Console Redirection Enabled
Disabled
Console Redirection Settings Submenu
Console Redirection Enable or Disable.
Console Redirection Enable or Disable.
.
COM3 Info only
Console Redirection Enabled
Console Redirection Enable or Disable.
Disabled
Console Redirection Settings Submenu
COM4 Info only
Console Redirection Enabled
Console Redirection Enable or Disable.
Disabled
Console Redirection Settings Submenu
7.3.11.1 Serial Port Console > Console Redirection Settings
VT100+: Extends VT100 to support color, function keys, etc.
set
VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or
more bytes
Selects serial port transmission speed.
.
Express-HL2 Page 65
Feature Options Description
Data Bits 7
8
Parity None
Even
Odd
Mark
Space
Stop Bits 1
2
Flow Control None
Hardware RTS/CTS
VT-UTF8 Combo Key Support Disabled
Enable
Recorder Mode Disabled
Enable
Resolution 100x31 Disabled
Enable
Legacy OS Redirection 80x24
80x25
Putty KeyPad VT100
LINUX
XTERMR6
SCO
ESCN
VT400
Select Data Bits.
Select Parity.
Select number of stop bits.
Select flow control.
Enable VT-UTF8 Combination Key Support for ANSI/VT100
terminals
With this mode enabled only text will be sent. This is to capture
Terminal data
.
.
Enables or disables extended terminal resolution
On Legacy OS, the Number of Rows and Columns supported
redirection
Select FunctionKey and KeyPad on Putty.
Redirection After BIOS Post Always Enabled
BootLoader
The Settings specify if BootLoader is selected than Legacy
console redirection is disabled before booting to Legacy OS
Default value is Always Enable which means Legaacy console
Redirection is enabled for Legacy OS
7.3.12 Clock
Feature Options Description
Clock Info only
Use Watchdog Timer for ICC
Turn off unused PCI/PCIe clocks Disabled
ICC Locks After EOP Default
Clock Manipulation Info only
ICC Overclocking Lib Info only
CLKRUN# Logic Enabled
Enabled
Disabled
Enable
All Locked
All UnLocked
Disabled
Enable Watchdog Timer operation for ICC. If enabled, Watchdog
Timer will be started after ICC-related changes
platform instability caused by wrong clock settings
Disabled: all clocks turned on.
Enabled: clocks for empty PCI/PCIe slots will be turned off to save
.
power
Platform must be powered off for changes to take effect.
Lock ICC register after EOP.
Enable the CLKRUN# logic to stop the PCI clock.
.
.
This timer detects
.
.
Page 66Express-HL2
7.3.13 Thermal
Feature Options Description
Thermal Info only
Automatic Thermal Reporting
Enabled
Disabled
Configure _CRT, _PSV and _AC0 automatically based on values
recommended in BWG’s Thermal Reporting for Thermal
Management settings. Set to Disabled for manual conmfiguration.
Critical Trip Point Disabled
85 C
95 C
Active Trip Point Disabled
40 C
50 C
This value controls the temperature of the ACPI Critical Trip Point the point in which the OS will shut the system off
NOTE: 100C is the Plan Of Record (POR) for all Intel mobile
processors
.
.
This value controls the temperature of the ACPI Active Trip Point the point in which the OS will turn the processor fan on Active Trip
Point Fan Speed
.
60 C
70 C
BMC Default
Passive Trip Point Disabled
80 C
This value controls the temperature of the ACPI Passive Trip Point the point in which the OS will begin throttling the processor
.
90 C
Passive TC1 Value 1 This value sets the TC1 value for the ACPI Passive Cooling
Passive TC2 Value 5 This value value sets the TC2 value for the ACPI Passive Cooling
Formula
Formula
.
Range 1 – 16.
.
Range 1 - 16
Passive TSP Value 10 This item sets the TSP value for the ACPI Passive Cooling Formula
It represents in tenths of a second how often the OS will read the
temperature when passive cooling is enabled. Range 2 – 32.
Enables or Disables the High Precision Event Timer.
Enable or Disable the SMI Lock
BIOS Lock Enabled
Enable or Disable the BIOS lock enable (BLE) bit
Disabled
Express-HL2 Page 67
Feature Options Description
GPIO Lock Enabled
Disabled
BIOS Interface Lock Enabled
Disabled
RTC RAM Lock Enabled
Disabled
7.3.14.2 Miscellaneous > Trusted Computing
Feature Options Description
Security Device Support Enabled
Disabled
Enable or Disable the GPIO lockdown
Enable or Disable the BIOS interface lockdown
Enable or Disable bytes 38h-2Fh in the upper and lower 128byte bank of the RTC RAM lockdown
Enables or Disables BIOS support for security device.
When disabled OS wil not show Security Device
protocol and INT1A interface will not be available
.
TCG EFI
Page 68Express-HL2
7.4 Boot
7.4.1 Boot Configuration
Feature Options Description
Boot Configuration Info only
Setup Prompt Timeout 1 Enable/Disable the onboard SATA controllers
Bootup NumLock State On Select SATA controller mode
.
.
Quiet Boot Disabled
Enabled
Fast Boot Disabled
Enabled
Boot Option Priorities Info only
CSM16 Parameters Submenu
CSM16 Module Version Info only
GateA20 Active Upon Request
Always
Option ROM Messages Force BIOS
Keep Current
INT19 Trap Response Immediate
Postponed
CSM parameters Submenu
Enable/Disable the PATA port. In fact this enables or disables the
SATA channel on which the onboard SATA to PATA converter is
.
When set to enabled the system boot will be delayed for
attached
the time specified in PATA Port Detection Timeout if no PATA
device is connected.
.
Auto: Scan for PATA device and enable per default
Define the maximum time to wait for drive detection on PATA port.
UPON REQUEST - GA20 can be disabled using BIOS services.
ALWAYS - do not allow disabling GA20; this option is useful when
any RT code is executed above 1MB.
Set display mode for Option ROM.
BIOS reaction on INT19 trapping by Option ROM: IMMEDIATE execute the trap right away; POSTPONED - execute the trap during
legacy boot.
7.4.2 CSM para meters
Feature Options Description
Launch CSM Enabled
Disable
Boot Option filter UEFI and Legacy
Legacy only
UEFI only
Launch PXE OpROM policy Do not launch
Legacy only
UEFI only
Launch Storage OpROM policy Do not launch
UEFI only
Legacy only
Launch Video OpROM policy Do not launch
UEFI only
Legacy only
Other PCI device ROM priority UEFI OpROM
Legacy OpROM
Express-HL2 Page 69
This option controls if CSM will be launched.
This option controls what devices system can to boot
.
Controls the execution of UEFI and Legacy PXE OpROM.
Controls the execution of UEFI and Legacy Storage OpROM.
Controls the execution of UEFI and Legacy Video OpROM.
For PCI devices other than Network, Mass storage or Video defines
which OpROM to launch
.
7.5 Security
7.5.1 Password Description
Feature Options Description
Administrator Password Enter password
User Password Enter password
Secure Boot menu Submenu
7.5.2 Secure Bo ot Menu
Feature Options Description
System Mode Setup
Secure Boot Info only
Secure Boot Support Disabled
Enabled
Secure Boot Mode Standard
Custom
Secure Boot can be enabled if 1.System running in User mode with
enrolled Platform Key(PK) 2
Secure Boot mode selector. 'Custom' Mode enables users to change
Image Execution policy and manage Secure Boot Keys
7.6 Save & Exit
7.6.1 Reset Options
Feature Options Description
Save Changes and Reset Save changes and reset the
Discard Changes and Reset Reset the system without
.
system
saving any changes
.
7.6.2 Save Options
Feature Options Description
Save Changes and Reset
Discard Changes and Reset
.
CSM function is disabled.
.
Save Changes Save Changes done so far to any of the setup options.
Discard Changes Discard Changes done so far to any of the setup options.
Restore Defaults Restore/Load Default values for all the setup options.
Save as User Defaults Save the changes done so far as User Defaults.
Restore User Defaults Restore the User Defaults to all the setup options.
Page 70Express-HL2
8 BIOS Checkpoints, Beep Codes
This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are
inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions.
Checkpoints and Beep Codes Definition
A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self
Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the
preboot process.
Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been
initialized, and generated by the system board speaker.
Aptio Boot Flow
While performing the functions of the traditional BIOS, Aptio 5.x core follows the firmware model described by the Intel Platform Innovation
Framework for EFI (“the Framework”). The Framework refers the following “boot phases”, which may apply to various status code &
checkpoint descriptions:
• Driver Execution Environment (DXE) – main hardware initialization
1
2
•Boot Device Selection (BDS) – system setup, pre-OS user interface & selecting a bootable device (CD/DVD, HDD, USB, Network,
Shell, …)
Viewing BIOS Checkpoints
Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a OST Card or POST Diagnostic Card. These
are PCI add-in cards that show the value of I/O port 80h on a LED display.
Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only
displays checkpoints that occur after the video card has been activated.
Keep in mind that not all computers using AMI Aptio BIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing
AMI Aptio BIOS checkpoints.
1
Analogous to “bootblock” functionality of legacy BIOS
2
Analogous to “POST” functionality in legacy BIOS
Express-HL2 Page 71
8.1 Status Code Ranges
Status Code
Range
0x01 – 0x0F SEC Status Codes & Errors
0x10 – 0x2F PEI execution up to and including memory detection
0x30 – 0x4F PEI execution after memory detection
0x50 – 0x5F PEI errors
0x60 – 0xCF DXE execution up to BDS
0xD0 – 0xDF DXE errors
0xE0 – 0xE8 S3 Resume (PEI)
0xE9 – 0xEF S3 Resume errors (PEI)
0xF0 – 0xF8 Recovery (PEI)
0xF9 – 0xFF Recovery errors (PEI)
Description
8.2 Standard Status Codes
8.2.1 SEC Status Codes
Status Code Description
0x0 Not used
Progress Codes
0x1 Power on. Reset type detection (soft/hard).
0x2 AP initialization before microcode loading
0x3 North Bridge initialization before microcode loading
0x4 South Bridge initialization before microcode loading
0x5 OEM initialization before microcode loading
0x6 Microcode loading
0x7 AP initialization after microcode loading
0x8 North Bridge initialization after microcode loading
0x9 South Bridge initialization after microcode loading
0xA OEM initialization after microcode loading
0xB Cache initialization
SEC Error Codes
0xC – 0xD Reserved for future AMI SEC error codes
0xE Microcode not found
0xF Microcode not loaded
Page 72Express-HL2
8.2.2 SEC Beep Codes
None
8.2.3 PEI Status Codes
Status Code Description
Progress Codes
0x10 PEI Core is started
0x11 Pre-memory CPU initialization is started
0x12 Pre-memory CPU initialization (CPU module specific)
0x13 Pre-memory CPU initialization (CPU module specific)
0x14 Pre-memory CPU initialization (CPU module specific)
0x15 Pre-memory North Bridge initialization is started
0x16 Pre-Memory North Bridge initialization (North Bridge module specific)
0x17 Pre-Memory North Bridge initialization (North Bridge module specific)
0x18 Pre-Memory North Bridge initialization (North Bridge module specific)
0x19 Pre-memory South Bridge initialization is started
0x1A Pre-memory South Bridge initialization (South Bridge module specific)
0x1B Pre-memory South Bridge initialization (South Bridge module specific)
0x1C Pre-memory South Bridge initialization (South Bridge module specific)
0x1D – 0x2A OEM pre-memory initialization codes
0x2B Memory initialization. Serial Presence Detect (SPD) data reading
0x2D Memory initialization. Programming memory timing information
0x2E Memory initialization. Configuring memory
0x2F Memory initialization (other).
0x30 Reserved for ASL (see ASL Status Codes section below)
0x31 Memory Installed
0x32 CPU post-memory initialization is started
0x33 CPU post-memory initialization. Cache initialization
0x34 CPU post-memory initialization. Application Processor(s) (AP) initialization
0x35 CPU post-memory initialization. Boot Strap Processor (BSP) selection
0x36 CPU post-memory initialization. System Management Mode (SMM) initialization
0x37 Post-Memory North Bridge initialization is started
0x38 Post-Memory North Bridge initialization (North Bridge module specific)
0x39 Post-Memory North Bridge initialization (North Bridge module specific)
0x3A Post-Memory North Bridge initialization (North Bridge module specific)
0x3B Post-Memory South Bridge initialization is started
0x3C Post-Memory South Bridge initialization (South Bridge module specific)
0x3D Post-Memory South Bridge initialization (South Bridge module specific)
0x3E Post-Memory South Bridge initialization (South Bridge module specific)
0x3F-0x4E OEM post memory initialization codes
Express-HL2 Page 73
Status Code Description
0x4F DXE IPL is started
PEI Error Codes
0x50 Memory initialization error. Invalid memory type or incompatible memory speed
0x51 Memory initialization error. SPD reading has failed
0x52 Memory initialization error. Invalid memory size or memory modules do not match.
0x53 Memory initialization error. No usable memory detected
0x54 Unspecified memory initialization error.
0x55 Memory not installed
0x56 Invalid CPU type or Speed
0x57 CPU mismatch
0x58 CPU self test failed or possible CPU cache error
0x59 CPU micro-code is not found or micro-code update is failed
0x5A Internal CPU error
0x5B reset PPI is not available
0x5C-0x5F Reserved for future AMI error codes
S3 Resume Progress Codes
0xE0 S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)
0xE1 S3 Boot Script execution
0xE2 Video repost
0xE3 OS S3 wake vector call
0xE4-0xE7 Reserved for future AMI progress codes
0xE0 S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)
S3 Resume Error Codes
0xE8 S3 Resume Failed in PEI
0xE9 S3 Resume PPI not Found
0xEA S3 Resume Boot Script Error
0xEB S3 OS Wake Error
0xEC-0xEF Reserved for future AMI error codes
Recovery Progress Codes
0xF0 Recovery condition triggered by firmware (Auto recovery)
0xF1 Recovery condition triggered by user (Forced recovery)
0xF2 Recovery process started
0xF3 Recovery firmware image is found
0xF4 Recovery firmware image is loaded
0xF5-0xF7 Reserved for future AMI progress codes
Recovery Error Codes
0xF8 Recovery PPI is not available
0xF9 Recovery capsule is not found
0xFA Invalid recovery capsule
0xFB – 0xFF Reserved for future AMI error codes
Page 74Express-HL2
8.2.4 PEI Beep Codes
# of Beeps Description
1 Memory not Installed
1 Memory was installed twice (InstallPeiMemory routine in PEI Core called twice)
2 Recovery started
3 DXEIPL was not found
3 DXE Core Firmware Volume was not found
7 Reset PPI is not available
4 Recovery failed
4 S3 Resume failed
8.2.5 DXE Status Codes
Status Code Description
0x60 DXE Core is started
0x61 NVRAM initialization
0x62 Installation of the South Bridge Runtime Services
0x63 CPU DXE initialization is started
0x64 CPU DXE initialization (CPU module specific)
0x65 CPU DXE initialization (CPU module specific)
0x66 CPU DXE initialization (CPU module specific)
0x67 CPU DXE initialization (CPU module specific)
0x68 PCI host bridge initialization
0x69 North Bridge DXE initialization is started
0x6A North Bridge DXE SMM initialization is started
0x6B North Bridge DXE initialization (North Bridge module specific)
0x6C North Bridge DXE initialization (North Bridge module specific)
0x6D North Bridge DXE initialization (North Bridge module specific)
0x6E North Bridge DXE initialization (North Bridge module specific)
0x6F North Bridge DXE initialization (North Bridge module specific)
0x70 South Bridge DXE initialization is started
0x71 South Bridge DXE SMM initialization is started
0x72 South Bridge devices initialization
0x73 South Bridge DXE Initialization (South Bridge module specific)
0x74 South Bridge DXE Initialization (South Bridge module specific)
0x75 South Bridge DXE Initialization (South Bridge module specific)
0x76 South Bridge DXE Initialization (South Bridge module specific)
Express-HL2 Page 75
Status Code Description
0x77 South Bridge DXE Initialization (South Bridge module specific)
0x78 ACPI module initialization
0x79 CSM initialization
0x7A – 0x7F Reserved for future AMI DXE codes
0x80 – 0x8F OEM DXE initialization codes
0x90 Boot Device Selection (BDS) phase is started
0x91 Driver connecting is started
0x92 PCI Bus initialization is started
0x93 PCI Bus Hot Plug Controller Initialization
0x94 PCI Bus Enumeration
0x95 PCI Bus Request Resources
0x96 PCI Bus Assign Resources
0x97 Console Output devices connect
0x98 Console input devices connect
0x99 Super IO Initialization
0x9A USB initialization is started
0x9B USB Reset
0x9C USB Detect
0x9D USB Enable
0x9E – 0x9F Reserved for future AMI codes
0xA0 IDE initialization is started
0xA1 IDE Reset
0xA2 IDE Detect
0xA3 IDE Enable
0xA4 SCSI initialization is started
0xA5 SCSI Reset
0xA6 SCSI Detect
0xA7 SCSI Enable
0xA8 Setup Verifying Password
0xA9 Start of Setup
0xAA Reserved for ASL (see ASL Status Codes section below)
0xAB Setup Input Wait
0xAC Reserved for ASL (see ASL Status Codes section below)
0xAD Ready To Boot event
0xAE Legacy Boot event
Page 76 Express-HL2
Status Code Description
0xAF Exit Boot Services event
0xB0 Runtime Set Virtual Address MAP Begin
0xB1 Runtime Set Virtual Address MAP End
0xB2 Legacy Option ROM Initialization
0xB3 System Reset
0xB4 USB hot plug
0xB5 PCI bus hot plug
0xB6 Clean-up of NVRAM
0xB7 Configuration Reset (reset of NVRAM settings)
0xB8 – 0xBF Reserved for future AMI codes
0xC0 – 0xCF OEM BDS initialization codes
DXE Error Codes
0xD0 CPU initialization error
0xD1 North Bridge initialization error
0xD2 South Bridge initialization error
0xD3 Some of the Architectural Protocols are not available
0xD4 PCI resource allocation error. Out of Resources
0xD5 No Space for Legacy Option ROM
0xD6 No Console Output Devices are found
0xD7 No Console Input Devices are found
0xD8 Invalid password
0xD9 Error loading Boot Option (LoadImage returned error)
0xDA Boot Option is failed (StartImage returned error)
0xDB Flash update is failed
0xDC Reset protocol is not available
8.2.6 DXE Beep Codes
# of Beeps Description
4 Some of the Architectural Protocols are not available
5 No Console Output Devices are found
5 No Console Input Devices are found
1 Invalid password
6 Flash update is failed
7 Reset protocol is not available
8 Platform PCI resource requirements cannot be met
Express-HL2 Page 77
8.2.7 ACPI/ASL Checkpoint
Status Code Description
0x01 System is entering S1 sleep state
0x02 System is entering S2 sleep state
0x03 System is entering S3 sleep state
0x04 System is entering S4 sleep state
0x05 System is entering S5 sleep state
0x10 System is waking up from the S1 sleep state
0x20 System is waking up from the S2 sleep state
0x30 System is waking up from the S3 sleep state
0x40 System is waking up from the S4 sleep state
0xAC System has transitioned into ACPI mode. Interrupt controller is in PIC mode.
0xAA System has transitioned into ACPI mode. Interrupt controller is in APIC mode.
8.3 OEM-Reserved Checkpoint Ranges
Status Code Description
0x05 OEM SEC initialization before microcode loading
0x0A OEM SEC initialization after microcode loading
0x1D – 0x2A OEM pre-memory initialization codes
0x3F – 0x4E OEM PEI post memory initialization codes
0x80 – 0x8F OEM DXE initialization codes
0xC0 – 0xCF OEM BDS initialization codes
Page 78Express-HL2
9Mechanical Information
9.1 Board-to-Board Connectors
To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When
5 mm receptacles are chosen, the carrier board should be free of components.
Tyco 3-1827253-6
Foxconn QT002206-2131-3H
• 220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm.
• This connector can be used with 5 mm through-hole standoffs (SMT type).
Tyco 3-6318491-6
Foxconn QT002206-4141-3H
• 220-pin board-to-board connector with 0.5mm for a stacking height of 8 mm.
• This connector can be used with 8 mm through-hole standoffs (SMT type).
Common Specifications
• Current capacity: 0.5A per pin
• Rated voltage: 50 VAC
• Insulation resistance: 100M or greater @ 500 VDC
The function of the heat spreader is to ensure an identical mechanical profile for all COM Express modules. By using a heat spreader, the
thermal solution that is built on top of the module is compatible with all COM Express modules.
9.2.2 Heat Sinks
A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless, depending on the
thermal requirements.
9.2.3 Installation
Install a heat spreader or heat sink using the following instructions.
Step 1: Before mounting the heatsink, install the required memory modules onto the SODIMM socket(s) on the COM Express module.
Step 2: Remove the protective membranes from the thermal pads.
Step 3: Assemble the heatsink onto the COM Express module.
Page 80Express-HL2
Step 4: Use the four M2.5, L=6mm screws provided to fasten the heatsink to the module.
Step 5: Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown.
Then press down on the module until it is firmly seated on the carrier board.
Step 6: Use the five M2.5, L=16mm screws provided to secure the COM Express module to the carrier board from the solder side.
Step 7: If you are installing a heatsink with a fan, plug the fan connector into the carrier board as shown.
Express-HL2 Page 81
9.3 Mounting Methods
There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the choice of
5 mm or 8mm board-to-board connectors, there is the choice of Top and Bottom mounting. In Top mounting, the threaded standoffs are on
the carrier board and the thermal solution is equipped with through-hole standoffs. In Bottom mounting, the threaded standoffs are on the
thermal solution and the carrier board has through-hole standoffs.
Page 82Express-HL2
9.4 Standoff Types
The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and throughhole standoffs are SMT type. Other types not listed are available upon request.
Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and
operating instructions for future use.
• Please read these safety instructions carefully.
• Please keep this User‘s Manual for later reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables.
• To avoid electrical shock and/or damage to equipment:
Keep equipment away from water or liquid sources.
Keep equipment away from high heat or high humidity.
Keep equipment properly ventilated (do not block or cover ventilation openings).
Make sure to use recommended voltage and power source settings.
Always install and operate equipment near an easily accessible electrical socket-outlet.
Secure the power cord (do not place any object on/over the power cord).
Only install/attach and operate equipment on stable surfaces and/or recommended mountings.
If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.
• Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.
Page 84 Express-HL2
Getting Service
ADLINK Technology, Inc.
Address: 9F, No.166 Jian Yi Road, Zhonghe District
New Taipei City 235, Taiwan