ADLINK DAQe-2214 User Manual

DAQ-/DAQe-2213/2214

16-CH High Performance

Low-Cost Data Acquisition Card

User’s Manual

Manual Rev. 2.00

Revision Date: March 22, 2007

Part No: 50-11222-2000

Advance Technologies; Automate the World.

Copyright 2007 ADLINK TECHNOLOGY INC.

All Rights Reserved.

The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, spe­cial, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.

This document contains proprietary information protected by copy­right. All rights are reserved. No part of this manual may be repro­duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.

Trademarks

Product names mentioned herein are used for identification pur­poses only and may be trademarks and/or registered trademarks
of their respective companies.

Getting service

Customer satisfaction is our top priority. Contact us should you
require any service or assistance.

ADLINK TECHNOLOGY INC.

Web Site http://www.adlinktech.com
Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address 9F No. 166 Jian Yi Road, Chungho City,

Taipei Hsien 235, Taiwan, ROC

ADLINK TECHNOLOGY AMERICA, INC.

Sales & Service [e-mail]
Toll-Free +1-866-4-ADLINK (235465)
Fax No. [phone]
Mailing Address 8900 Research Drive, Irvine,

CA 92618, USA

ADLINK TECHNOLOGY EUROPEAN SALES OFFICE

Sales & Service [e-mail]
Toll-Free [phone]
Fax No. [phone]
Mailing Address Nord Carree 3, 40477 Düsseldorf, Germany

ADLINK TECHNOLOGY SINGAPORE PTE LTD

Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address 84 Genting Lane #07-02A,

Cityneon Design Center, Singapore 349584

ADLINK TECHNOLOGY INDIA LIAISON OFFICE

Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address No. 1357, Ground Floor, "Anupama",

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Bangalore - 560078

ADLINK TECHNOLOGY BEIJING

Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address 4F, Kostech Building, 262-2,

Yangjae-Dong, Seocho-Gu,
Seoul, 137-130, South Korea

ADLINK TECHNOLOGY BEIJING

Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address Room 801, Building E, Yingchuangdongli

Plaza, No.1 Shangdidonglu,
Haidian District, Beijing, China

ADLINK TECHNOLOGY SHANGHAI

Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address Floor 4, Bldg. 39, Caoheting Science and

Technology Park, No.333 Qinjiang Road,
Shanghai, China

ADLINK TECHNOLOGY SHENZHEN

Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address C Block, 2nd Floor, Building A1,

Cyber-tech Zone, Gaoxin Ave. 7.S,
High-tech Industrial Park S.,
Nanshan District, Shenzhen,
Guangdong Province, China

Using this manual

1.1 Audience and scope

This manual guides you when using ADLINK multi-function DAQ-/
DAQe-2213/2214 card. The card’s hardware, signal connections,
and calibration information are provided for faster application
building. This manual is intended for computer programmers and
hardware engineers with advanced knowledge of data acquisition
and high-level programming.

1.2 How this manual is organized

This manual is organized as follows:

Chapter 1 Introduction: This chapter intoduces the DAQ-/
DAQe-2213/2214 card including its features, specifications and
software support information.

Chapter 2 Installation: This chapter presents the card’s lay­out, package contents, and installation.

Chapter 3 Signal Connections: This part describes the DAQ­/DAQe-2213/2214 card signal connections.

Chapter 4 Operation Theory: The operation theory of the
DAQ-/DAQe-2213/2214 card functions including A/D conver­sion, D/A conversion, and programmable function I/O are dis­cussed in this chapter.

Chapter 5 Calibration: The chapter offers information on how
to calibrate the DAQ-/DAQe-2213/2214 card for accurate data
acquisition and output.

Warranty Policy: This presents the ADLINK Warranty Policy
terms and coverages.

1.3 Conventions

Take note of the following conventions used throughout the man­ual to make sure that you perform certain tasks and instructions
properly.

NOTE Additional information, aids, and tips that help you per-

form particular tasks.

IMPORTANT Critical information and instructions that you MUST perform to

WARNING Information that prevents physical injury, data loss, mod-

complete a task.

ule damage, program corruption etc. when trying to com­plete a particular task.

Table of Contents

Table of Contents..................................................................... i

List of Tables.......................................................................... iii

List of Figures ......................................................................... v

1 Introduction ........................................................................ 1

1.1 Features............................................................................... 2

1.2 Applications ......................................................................... 3

1.3 Specifications....................................................................... 4

1.4 Software Support ............................................................... 11

Programming Library .................................................... 11

DAQ-LVIEW PnP: LabVIEW Driver .............................. 12

D2K-OCX: ActiveX Controls ......................................... 12

2 Installation ........................................................................ 13

2.1 Contents of Package ......................................................... 13

2.2 Unpacking.......................................................................... 14

2.3 Card Layout ....................................................................... 15

DAQe-2213/2214 .......................................................... 15

DAQ-2213/2214 ............................................................ 16

2.4 PCI Configuration .............................................................. 17

Plug and Play ............................................................... 17

Configuration ................................................................ 17

Troubleshooting ............................................................ 17

3 Signal Connections.......................................................... 19

3.1 Connectors Pin Assignment .............................................. 19

CN1 Connector ............................................................. 20

CN2 Connector ............................................................. 21

SSI Connector .............................................................. 24

...................................................................................... 24

3.2 Analog Input Signal Connection ........................................ 26

Types of Signal Sources ............................................... 26

Input Configurations ...................................................... 26

Table of Contents i

4 Operation Theory .............................................................. 29

4.1 A/D Conversion.................................................................. 29

DAQ-/DAQe-2213/2214 AI Data Format ...................... 30

Software Conversion with Polling Data

Transfer Acquisition Mode (Software Polling) .... 31

Programmable Scan Acquisition Mode ......................... 32

Specifying Channels, Gains, and Input

Configurations in the Channel Gain Queue ........ 34

Trigger Modes ............................................................... 35

Bus-mastering DMA Data Transfer ............................... 45

4.2 D/A Conversion.................................................................. 47

Software Update ........................................................... 48

Timed Waveform Generation ........................................ 49

Trigger Modes ............................................................... 51

Iterative Waveform Generation ..................................... 53

Stop Modes of Scan Update ......................................... 55

4.3 Digital I/O ........................................................................... 57

4.4 General Purpose Timer/Counter Operation ....................... 57

The Basics of Timer/Counter Functions ....................... 58

General Purpose Timer/Counter Modes ....................... 58

4.5 Trigger Sources ................................................................. 64

Software-Trigger ........................................................... 64

External Analog Trigger ................................................ 64

4.6 User-controllable Timing Signals ....................................... 70

DAQ Timing Signals ..................................................... 71

Auxiliary Function Inputs (AFI) ...................................... 73

System Synchronization Interface ................................ 76

5 Calibration ......................................................................... 79

5.1 Loading Calibration Constants........................................... 79

5.2 Auto-calibration .................................................................. 80

5.3 Saving Calibration Constants............................................. 80

Warranty Policy ..................................................................... 81

ii Table of Contents

List of Tables

Table 1-1: Programmable Input Range ..................................... 4

Table 1-2: Bandwidth ................................................................. 5

Table 1-3: System Noise ........................................................... 5

Table 1-4: CMRR (DC to 60 Hz) ................................................ 5

Table 1-5: Settling Time to Full Scale Step ............................... 6

Table 3-1: CN1 Pin Assignment for DAQ-/DAQe-2213/2214 .. 20

Table 3-2: CN2 Pin Assignment for DAQ-/DAQe-2213 ........... 21

Table 3-3: CN2 Pin Assignment for DAQ-/DAQe-2214 ........... 22

Table 3-4: CN1/CN2 Signal Description .................................. 23

Table 3-5: SSI Connector Pin Assignment for

DAQ-/DAQe-2213 ................................................... 24

Table 3-6: SSI Connector Pin Assignment for

DAQ-/DAQe-2214 ................................................... 24

Table 3-7: SSI Connector Legend ........................................... 25

Table 4-1: Bipolar Analog Input Range and

Output Digital Code for DAQ/DAQe/PXI-2205/2206 30
Table 4-2: Unipolar Analog Input Range and

Output Digital Code for DAQ/DAQe/PXI-2205/2206 30

Table 4-3: Bipolar Output Code Table ..................................... 47

Table 4-4: Unipolar Output Code Table ................................... 48

Table 4-5: Analog Trigger SRC1 (EXTATRIG)

Ideal Transfer Characteristic .................................. 65

Table 4-6: User-controllable Timing Signals and

Functionalities ......................................................... 71

Table 4-7: Auxiliary Function Input Signals and

Functionalities ......................................................... 73

Table 4-8: SSI Timing Signal and Functions ........................... 76

List of Tables iii

List of Figures

Figure 2-1: DAQe-2213/2214 Card Layout ................................ 15

Figure 2-2: DAQ-2213/2214 Card Layout .................................. 16

Figure 3-1: Floating Source and RSE Input Connections .......... 27

Figure 3-2: Ground-referenced Sources and

NRSE Input Connections......................................... 27

Figure 3-3: Ground-referenced Source and Differential Input.... 28

Figure 3-4: Floating Source and Differential Input ..................... 28

Figure 4-1: Scan Timing............................................................. 33

Figure 4-2: Pre-trigger (Trigger occurs after M scans) ............... 36

Figure 4-3: Pre-trigger (Trigger with scan in progress) .............. 37

Figure 4-4: Pre-trigger with M_enable=0

(Trigger occurs before M scans).............................. 38

Figure 4-5: Pre-trigger with M_enable=1 ................................... 39

Figure 4-6: Middle-Trigger with M_enable = 1 ........................... 40

Figure 4-7: Middle-Trigger (Trigger occurs when a scan is in

progress).................................................................. 41

Figure 4-8: Post-trigger .............................................................. 42

Figure 4-9: Delay trigger ............................................................ 43

Figure 4-10: Post trigger with Re-trigger ...................................... 44

Figure 4-11: Scatter/gather DMA for Data Transfer ..................... 46

Figure 4-12: Typical D/A Timing of Waveform Generation .......... 50

Figure 4-13: Post-trigger Waveform Generation .......................... 51

Figure 4-14: Delay Trigger Waveform Generation ....................... 52

Figure 4-15: Re-triggered Waveform Generation with

Post-Trigger (DLY2_Counter=0).............................. 52

Figure 4-16: Finite Iterative Waveform Generation with

Post-trigger (DLY2_Counter = 0) ............................. 53

Figure 4-17: Infinite Iterative Waveform Generation with

Post-trigger (DLY2_Counter = 0) ............................. 54

Figure 4-18: Stop Mode I ............................................................. 55

Figure 4-19: Stop Mode II ............................................................ 56

Figure 4-20: Stop Mode III ........................................................... 56

Figure 4-21: Mode1 Operation ..................................................... 59

Figure 4-22: Mode2 Operation ..................................................... 60

Figure 4-23: Mode3 Operation ..................................................... 60

Figure 4-24: Mode4 Operation ..................................................... 61

Figure 4-25: Mode5 Operation ..................................................... 62

Figure 4-26: Mode6 Operation ..................................................... 62

iv List of Figures

Figure 4-27: Mode7 Operation..................................................... 63

Figure 4-28: Mode8 Operation..................................................... 63

Figure 4-29: Analog Trigger Block Diagram................................. 64

Figure 4-30: Below-Low Analog Trigger Condition ...................... 66

Figure 4-31: Above-High Analog Trigger Condition ..................... 66

Figure 4-32: Inside-Region Analog Trigger Condition.................. 67

Figure 4-33: High-Hysteresis Analog Trigger Condition .............. 68

Figure 4-34: Low-Hysteresis Analog Trigger Condition ............... 68

Figure 4-35: External Digital Trigger ............................................ 69

Figure 4-36: DAQ Signals Routing............................................... 70

List of Figures v

1 Introduction

The DAQ-/DAQe-2213/2214 is a 16-CH low cost, high-perfor­mance multi-function data acquisition card that can sample up to
16 analog input channels with different gain settings and scan
sequences, making it ideal for analog signals with various input
ranges and sampling speeds.

Offering differential modes for up to eight AI channels, the DAQ/
DAQ-/DAQe-2213/2214 card achieves the most efficient noise
elimination. The DAQ-/DAQe-2213/2214 card has 2-CH 12-bit
analog output with waveform generation capabilities and also fea­tures analog and digital triggering, 24-CH programmable digital I/
O lines, and 2-CH 16-bit general-purpose timers/counters.

Similar to all other members of the DAQ-/DAQe-2000 family, multi­ple DAQ-/DAQe-2213/2214 cards can be synchronized using the
system synchronization interface (SSI) bus. In addition, the auto­calibration feature adjusts the gain and offset within specified
accuracies, thus eliminating the need to manually adjust trimpots.

Introduction 1

1.1 Features

The DAQ/DAQe-2213/2214 advanced data acquisition card has
the following features:

X 32-bit PCI bus (DAQ model) or PCI Express bus (DAQe

model), plug and play

X Up to 16 single-ended inputs or 8 differential inputs support-

ing combinations of SE and DI analog input signals

X 512-word analog input Channel Gain Queue configuration

size

X 16-bit analog input resolution with up to 250 kHz sampling

rate

X Programmable bipolar/unipolar analog input

X Programmable gain: x1, x2, x4, x8

X A/D FIFO size: 1024 samples

X Versatile trigger sources: Software trigger, external digital

trigger, analog trigger, and trigger from System Synchroni­zation Interface (SSI)

X A/D data transfer: Software polling and bus-mastering DMA

with scatter/gather functionality

X Four A/D trigger modes including post-trigger, delay-trigger,

pre-trigger and middle-trigger

X Two-channel D/A outputs with waveform generation capa-

bility (only on DAQ-/DAQe-2214)

X 1024 word length output data FIFO for D/A channels (only

on DAQ-/DAQe-2214)

X Supports System Synchronization Interface (SSI)

X Full A/D and D/A auto-calibration

X Jumper-free and software-configurable

2Introduction

1.2 Applications

X Automotive Testing

X Cable Testing

X Transient signal measurement

X ATE

X Laboratory Automation

X Biotech measurement

Introduction 3

1.3 Specifications

Analog Input (AI)

X Programmable channels: 16 single-ended (SE) or 8 differ-

ential input (DI)

X A/D converter: A/D7663 or equivalent

X Maximum sampling rate: 250 kS/s

X Resolution: 16-bit, no missing code

X Input coupling: DC

X Programmable input range:

Device Bipolar input range Unipolar input range

±10 V 0 V to 10 V

2204/

2208

Table 1-1: Programmable Input Range

X Operational common mode voltage range: ±11V

X Overvoltage protection:

Z Power on: Continuous ±30 V

Z Power off: Continuous ±15 V

X FIFO buffer size: 1024 samples

X Data transfers:

Z Programmed I/O

Z Bus-mastering DMA with scatter/gather

X Channel Gain Queue configuration size: 512 words

±5 V 0 V to 5 V

±2.5 V 0 V to 2.5 V

±1.25 V 0 V to 1.25 V

4Introduction

X Bandwidth (Typical 25ºC):

Device Input range

Small signal

bandwidth

(-3dB)

Large signal

bandwidth

(1% THD)

±10 V 0 V to 10 V 760 kHz 280 kHz

2206

±5 V 0 V to 5 V 720 kHz 300 kHz

±2.5 V 0 V to 2.5 V 610 kHz 310 kHz

±1.25 V 0 V to 1.25 V 450 kHz 330 kHz

Table 1-2: Bandwidth

X System Noise (LSBrms, including Quantization, Typical,

25°C)

Device Input Range

System

Noise

±10 V 0.8 LSBrms 0 V to 10 V 0.9 LSBrms

2206

±5 V 0.85 LSBrms 0 V to 5 V 1.0 LSBrms

±2.5 V 0.85 LSBrms 0 V to 2.5 V 1.0 LSBrms

±1.25 V 0.9 LSBrms 0 V to 1.25 V 1.2 LSBrms

Table 1-3: System Noise

X Input impedance:

Z Normal power on: 1 GΩ/100 pF

Z Power off: 820Ω

Z Overload: 820Ω

X CMRR (DC to 60 Hz, Typical)

Input Range

System

Noise

Input Range CMRR Input Range CMRR

±10 V 83 dB 0 V to 10 V 87 dB

±5 V 87 dB 0 V to 5 V 90 dB

±2.5 V 90 dB 0 V to 2.5 V 92 dB

±1.25 V 92 dB 0 V to 1.25 V 93 dB

Table 1-4: CMRR (DC to 60 Hz)

Introduction 5

X Settling time to full-scale step (Typical, 25°C):

Input Range Condition Settling time

• Multiple channels,

All Ranges

multiple ranges.

• All samples in unipolar/

4 µs to 0.01% error

bipolar mode.

• Multiple channels,

All Ranges

multiple ranges.

• All samples in unipolar

4 µs to 0.01% error

and/or bipolar mode.

Table 1-5: Settling Time to Full Scale Step

X Time-base source: Internal 40 MHz or external clock Input

(f

: 40 MHz, f

max

X Trigger modes: Post-trigger, delay-trigger, pre-trigger and

: 1 MHz, 50% duty cycle)

min

middle-trigger

X Offset error:

Z Before calibration: ±60 mV max

Z After calibration: ±1 mV max

X Gain error (relative to calibration reference):

Z Before calibration: 0.06% of output max

Z After calibration: 0.01% of output max

6Introduction

Analog Output (AO)

NOTE The DAQ-/DAQe-2213 does not support this function.

X Channels: Two-channel analog voltage output

X DA converter: LTC7545 or equivalent

X Max update rate: 1 MS/s

X Resolution: 12-bit

X FIFO buffer size:

Z 512 samples per channel when both channels are

enabled for timed DA output

Z 1024 samples when only one channel is used for timed

DA output

X Data transfers:

Z Programmed I/O

Z Bus-mastering DMA with scatter/gather

X Output range: ±10 V, 0 V to 10 V, ±AOEXTREF, 0 to AOEX-

TREF

X Settling time: 3 µS to 0.5 LSB accuracy

X Slew rate: 20 V/µS

X Output coupling: DC

X Protection: Short-circuit to ground

X Output impedance: 0.01Ω (typical)

X Output driving current: ±5 mA max

X Stability: Any passive load, up to 1500 pF

X Power-on state: 0 V steady-state

X Power-on glitch: ±1.5 V/500 µS

X Relative accuracy: ±0.5 LSB typical, ±1 LSB max

X DNL: ±0.5 LSB typical, ±1.2 LSB max

X Offset error:

Z Before calibration: ±80 mV max

Z After calibration: ±1 mV max

X Gain error:

Z Before calibration: ±0.8% of output max

Z After calibration: ±0.02% of output max

Introduction 7

General Purpose Digital I/O (G.P. DIO, 82C55A)

X Channels: 24 programmable input/output

X Compatibility: TTL

X Input voltage:

Z Logic Low: VIL=0.8 V max; IIL=0.2 mA max

Z High: VIH=2.0 V max; IIH=0.02 mA max

X Output voltage:

Z Low: VOL=0.5 V max; IOL=8 mA max

Z High: VOH=2.7 V min; IOH=400 µA

X Synchronous Digital Inputs (SDI)

Z Channels: 4 digital inputs sampled simultaneously with

the analog signal input

Z Compatibility: TTL/CMOS

Z Input voltage:

Logic Low: VIL=0.8 V max; IIL=0.2 mA max

Logic High: VIH=2.0 V min; IIL=0.02 mA max

General Purpose Timer/Counter (GPTC)

NOTE The DAQ-/DAQe-/PXI-2208 does not support this func-

tion.

X Channels: 2 independent up/down timer/counters

X Resolution: 16-bit

X Compatibility: TTL

X Clock source: Internal or external

X Max source frequency: 10 MHz

8Introduction

Analog Trigger (A.Trig)

X Source:

Z All analog input channels

Z External analog trigger (EXTATRIG)

X Level: ±Full-scale, internal; ±10 V external

X Resolution: 8-bit

X Slope: Positive or negative (software-selectable)

X Hysteresis: Programmable

X Bandwidth: 400 kHz

External Analog Trigger Input (EXTATRIG)

X Input Impedance: 20 kΩ

X Coupling: DC

X Protection: Continuous ±35 V maximum

Digital Trigger (D.Trig)

X Compatibility: TTL/CMOS

X Response: Rising or falling edge

X Pulse Width: 10 ns min

System Synchronous Interface (SSI)

X Trigger lines: 7

Stability

X Recommended warm-up time: 15 minutes

X On-board calibration reference:

Z Level: 5.000 V

Z Temperature coefficient: ±2 ppm/°C

Z Long-term stability: 6 ppm/1000 Hr

Physical

X Dimensions: 175 mm x 107 mm

X I/O connector: 68-pin female VHDCI type (e.g. AMP-

787254-1)

Introduction 9

Power Requirement (typical)

X +5 VDC: 1.2 A

X +12 VDC:

Z 260 mA for DAQe-2213

Z 470 mA for DAQe-2214

X +3.3 VDC:

Z 730 mA for DAQe-2213

Z 700 mA for DAQe-2214

Operating Environment

X Ambient temperature: 0°C to 55°C

X Relative humidity: 10% to 90% non-condensing

Storage Environment

X Ambient temperature: -20°C to 70°C

X Relative humidity: 5% to 95% non-condensing

10 Introduction

1.4 Software Support

ADLINK provides versatile software drivers and packages for
users’ different approach to building up a system. ADLINK not only
provides programming libraries such as DLL for most Windows­based systems, but also provide drivers for other software pack­ages such as LabVIEW

All software options are included in the ADLINK CD. Non-free soft­ware drivers are protected with licensing codes. Without the soft­ware code, you can install and run the demo version for two hours
for trial/demonstration purposes. Contact ADLINK dealers to pur­chase the software license.

Programming Library

For customers who are writing their own programs, we provide
function libraries for many different operating systems, including:

X D2K-DASK: Include device drivers and DLL for Windows

98/NT/2000/XP. DLL is binary compatible across Windows
98/NT/2000/XP. This means all applications developed with
D2K-DASK are compatible across Windows 98/NT/2000/
XP. The developing environment can be VB, VC++, Delphi,
BC5, or any Windows programming language that allows
calls to a DLL. The user’s guide and function reference
manual of D2K-DASK are in the CD. (\\Manual\Software
Package\D2K-DASK)

X D2K-DASK/X: Include device drivers and shared library for

Linux. The developing environment can be Gnu C/C++ or
any programming language that allows linking to a shared
library. The user's guide and function reference manual of
D2K-DASK/X are in the CD. (\\Manual\Software Pack­age\D2K-DASK-X.)

®

.

®

Introduction 11

DAQ-LVIEW PnP: LabVIEW Driver

DAQ-LVIEW PnP contains the VIs, which are used to interface
with NI’s LabVIEW software package. The DAQ-LVIEW PnP sup­ports Windows 98/NT/2000/XP. The LabVIEW drivers is shipped
free with the card. You can install and use them without a license.
For detailed information about DAQ-LVIEW PnP, refer to the
user’s guide in the CD. (\\Manual\Software Package\DAQ-LVIEW
PnP)

D2K-OCX: ActiveX Controls

Customers who are familiar with ActiveX controls and VB/VC++
programming are suggested to use D2K-OCX ActiveX control
component libraries for developing applications. D2K-OCX is
designed for Windows 98/NT/2000/XP. For more details on D2K­OCX, refer to the user's guide in the CD. (\\Manual\Software Pack­age\D2K-OCX)

The above software drivers are shipped with the card. Refer to the
Software Installation Guide in the package to install these drivers.

In addition, ADLINK provides the DAQBench ActiveX control soft­ware. DAQBench is a collection of ActiveX controls for measure­ment or automation applications. With DAQBench, you can easily
develop custom user interfaces to display your data, analyze data
you acquired or received from other sources, or integrate with
popular applications or other data sources. For more detailed
information about DAQBench, refer to the user's guide in the CD.
(\\Manual\Software Package\DAQBench Evaluation)

You can also get a free 4-hour evaluation version of DAQBench
from the CD. DAQBench is not free. Contact ADLINK or your
dealer to purchase the software license.

12 Introduction

2 Installation

This chapter describes how to install the DAQ-/DAQe-2213/2214
card. The contents of the package and unpacking information that
you should be aware of are outlined first.

The DAQ-/DAQe-2213/2214 card performs an automatic configu­ration of the IRQ and port address. You can use the PCI_SCAN
software utility to read the system configuration.

2.1 Contents of Package

In addition to this User's Manual, the package includes the follow­ing items:

X DAQ-/DAQe-2213/2214 multi-function data acquisition card

X ADLINK All-in-one CD

X Software Installation Guide

If any of these items are missing or damaged, contact the dealer
from whom you purchased the product. Save the shipping materi­als and carton in case you want to ship or store the product in the
future.

Installation 13

2.2 Unpacking

Your DAQ-/DAQe-2213/2214 card contains electro-static sensitive
components that can be easily be damaged by static electricity.

Therefore, the card should be handled on a grounded anti-static
mat. The operator should be wearing an anti-static wristband,
grounded at the same point as the anti-static mat.

Inspect the card package for obvious damages. Shipping and han­dling may cause damage to the card. Be sure there are no ship­ping and handling damages on the modules carton before
continuing.

After opening the card module carton, extract the system module
and place it only on a grounded anti-static surface with component
side up.

Again, inspect the module for damages. Press down on all the
socketed IC's to make sure that they are properly seated. Do this
only with the module place on a firm flat surface.

You are now ready to install your DAQ-/DAQe-2213/2214 card.

NOTE DO NOT APPLY POWER TO THE CARD IF IT HAS

BEEN DAMAGED.

14 Installation

2.3 Card Layout

DAQe-2213/2214

Figure 2-1: DAQe-2213/2214 Card Layout

Installation 15

DAQ-2213/2214

Figure 2-2: DAQ-2213/2214 Card Layout

16 Installation

2.4 PCI Configuration

Plug and Play

With support for plug and play, the card requests an interrupt num­ber via its PCI controller. The system BIOS responds with an inter­rupt assignment based on the card information and on known
system parameters. These system parameters are determined by
the installed drivers and the hardware load seen by the system.

Configuration

The board configuration is done on a board-by-board basis for all
PCI boards in the system. Because configuration is controlled by
the system and software, there is no jumper setting required for
base address, DMA, and interrupt IRQ.

The configuration is subject to change with every boot of the sys­tem as new boards are added or removed.

Troubleshooting

If your system doesn’t boot or if you experience erratic operation
with your PCI board in place, it is likely caused by an interrupt con­flict. The BIOS Setup may be incorrectly configured. Consult the
BIOS documentation that comes with your system to solve this
problem.

Installation 17

18 Installation

3 Signal Connections

This chapter describes DAQ-/DAQe-2213/2214 card connectors
and the signal connection between the DAQ-/DAQe-2213/2214
card and external devices.

3.1 Connectors Pin Assignment

The DAQ-/DAQe-2213/2214 card is equipped with two 68-pin
VHDCI-type connector (AMP-787254-1) and a 20-pin ribbon male
connector. These are used for digital input/output, analog input/
output, timer/counter signals, and SSI (System Synchronous Inter­face). The pin assignments of the connectors are defined in
Table 3-1, Table 3-2, and Table 3-3.

Signal Connections 19

CN1 Connector

AI0 (AIH0) 135 (AIL0) AI8
AI1 (AIH1) 236 (AIL1) AI9
AI2 (AIH2) 337 (AIL2) AI10
AI3 (AIH3) 438 (AIL3) AI11
AI4 (AIH4) 539 (AIL4) AI12
AI5 (AIH5) 640 (AIL5) AI13
AI6 (AIH6) 741 (AIL6) AI14
AI7 (AIH7) 842 (AIL7) AI15

NC 943NC
NC 10 44 NC
NC 11 45 NC
NC 12 46 NC
NC 13 47 NC
NC 14 48 NC
NC 15 49 NC
NC 16 50 NC

AISENSE 17 51 AIGND

NC 18 52 NC
NC 19 53 NC
NC 20 54 NC
NC 21 55 NC
NC 22 56 NC
NC 23 57 NC
NC 24 58 NC
NC 25 59 NC
NC 26 60 NC
NC 27 61 NC
NC 28 62 NC
NC 29 63 NC
NC 30 64 NC
NC 31 65 NC
NC 32 66 NC
NC 33 67 NC

EXTATRIG 34 68

Table 3-1: CN1 Pin Assignment for DAQ-/DAQe-2213/2214

* Symbols in “()” are for differential mode connection.

AIGND

20 Signal Connections

CN2 Connector

RESERVED 640 DGND

RESERVED 943 DGND
RESERVED 10 44 DGND
RESERVED 11 45 DGND

GPTC0_SRC 13 47 DGND

GPTC0_GATE 14 48 DGND

GPTC0_UPDOWN 15 49 DGND

GPTC0_OUT 16 50 DGND
GPTC1_SRC 17 51 DGND

GPTC1_GATE 18 52 DGND

GPTC1_UPDOWN 19 53 DGND

GPTC1_OUT 20 54 DGND

EXTTIMEBASE 21 55 DGND

Table 3-2: CN2 Pin Assignment for DAQ-/DAQe-2213

NC 135NC
NC 236NC
NC 337NC
NC 438 NC

DGND 539 DGND

EXTDTRIG 741 DGND

SSHOUT 842 DGND

AFI0 12 46 DGND

PB7 22 56 PB6
PB5 23 57 PB4
PB3 24 58 PB2

PB1 25 59 PB0
PC7 26 60 PC6
PC5 27 61 PC4

DGND 28 62 DGND

PC3 29 63 PC2
PC1 30 64 PC0
PA7 31 65 PA6
PA5 32 66 PA4
PA3 33 67 PA2
PA1 34 68

PA0

Signal Connections 21

DA0OUT 135 AOGND
DA1OUT 236 AOGND

AOEXTREF 337 AOGND

NC 438 NC

DGND 539 DGND

EXTWFTRIG 640 DGND

EXTDTRIG 741 DGND

SSHOUT 842 DGND
RESERVED 943 DGND
RESERVED 10 44 DGND

AFI1 11 45 DGND
AFI0 12 46 DGND

GPTC0_SRC 13 47 DGND

GPTC0_GATE 14 48 DGND

GPTC0_UPDOWN 15 49 DGND

GPTC0_OUT 16 50 DGND
GPTC1_SRC 17 51 DGND

GPTC1_GATE 18 52 DGND

GPTC1_UPDOWN 19 53 DGND

GPTC1_OUT 20 54 DGND

EXTTIMEBASE 21 55 DGND

PB7 22 56 PB6
PB5 23 57 PB4
PB3 24 58 PB2
PB1 25 59 PB0
PC7 26 60 PC6
PC5 27 61 PC4

DGND 28 62 DGND

PC3 29 63 PC2
PC1 30 64 PC0
PA7 31 65 PA6
PA5 32 66 PA4
PA3 33 67 PA2
PA1 34 68

Table 3-3: CN2 Pin Assignment for DAQ-/DAQe-2214

PA0

22 Signal Connections

CN1/CN2 Connector Signal Description

Signal Name Reference Direction Description

Analog ground for AI. All three ground

AIGND — —

AI<0..63/95> AIGND Input

AISENSE AIGND Input

EXTATRIG AIGND Input External AI analog trigger

DA0OUT AOGND Output AO channel 0

DA1OUT AOGND Output AO channel 1

AOEXTREF AOGND Input

AOGND — — Analog ground for AO

EXTWFTRIG DGND Input External AO waveform trigger

EXTDTRIG DGND Input External AI digital trigger

RESERVED — Output Reserved. Leave these open.

GPTC<0,1>_SRC DGND Input Source of GPTC<0,1>

GPTC<0,1>_GATE DGND Input Gate of GPTC<0,1>

GPTC<0,1>_OUT DGND Input Output of GPTC<0,1>

GPTC<0,1>_UPDOWN DGND Input Up/Down of GPTC<0,1>

EXTTIMEBASE DGND Input External Timebase

DGND — — Digital ground

PB<7,0> DGND PIO* Programmable DIO of 8255 Port B

PC<7,0> DGND PIO* Programmable DIO of 8255 Port C

PA<7,0> DGND PIO* Programmable DIO of 8255 Port A

AFI0 DGND Input

AFI1 DGND Input

Table 3-4: CN1/CN2 Signal Description

references (AIGND, AOGND, and
DGND) are connected together on
board.

Analog Input Channels 0 - 16. Each
channel pair, AI<i, i+8> (I=0..7) can be
configured on either two single-ended
inputs or one differential input pair
(marked as AIH<0..8> and AIL<0..8>).

Analog Input Sense. This pin is the
reference for any channels AI<0..63>
in NRSE input configuration.

External reference for AO
channels

Auxiliary Function Input 0
(ADCONV, AD_START)

Auxiliary Function Input 1 (DAWR,
DA_START)

Signal Connections 23

SSI Connector

SSI_TIMEBASE 1 2 DGND

SSI_ADCONV 3 4 DGND

RESERVED 5 6 DGND

SSI_SCAN_START 7 8 DGND

RESERVED 9 10 DGND

SSI_AD_TRIG 11 12 DGND

RESERVED 13 14 DGND

RESERVED 15 16 DGND

RESERVED 17 18 DGND

RESERVED 19 20 DGND

Table 3-5: SSI Connector Pin Assignment for DAQ-/DAQe-2213

SSI_TIMEBASE 1 2 DGND

SSI_ADCONV 3 4 DGND

SSI_DAWR 5 6 DGND

SSI_SCAN_START 7 8 DGND

RESERVED 9 10 DGND

SSI_AD_TRIG 11 12 DGND

SSI_DA_TRIG 13 14 DGND

RESERVED 15 16 DGND

RESERVED 17 18 DGND

RESERVED 19 20 DGND

Table 3-6: SSI Connector Pin Assignment for DAQ-/DAQe-2214

24 Signal Connections

SSI Connector Signal Description:

SSI Timing Signal Setting Function

Master Send the TIMEBASE out

SSI_TIMEBASE

SSI_ADCONV

SSI_SCAN_START

SSI_AD_TRIG

SSI_DAWR

SSI_DA_TRIG

Slave

Master Send the ADCONV out

Slave

Master Send the SCAN_START out

Slave

Master Send the internal AD_TRIG out

Slave Accept the SSI_AD_TRIG as the digital trigger signal.

Master Send the DAWR out.

Slave

Master Send the DA_TRIG out.

Slave Accept the SSI_DA_TRIG as the digital trigger signal.

Accept the SSI_TIMEBASE to replace the internal
TIMEBASE signal.

Accept the SSI_ADCONV to replace the internal
ADCONV signal.

Accept the SSI_SCAN_START to replace the internal
SCAN_START signal.

Accept the SSI_DAWR to replace the internal DAWR
signal.

Table 3-7: SSI Connector Legend

Signal Connections 25

3.2 Analog Input Signal Connection

The DAQ-/DAQe-2213/2214 card provides up to 16 single-ended
or eight differential analog input channels. You can fill the Channel
Gain Queue to get desired combination of the input signal types.
The analog signal can be converted to digital values by the A/D
converter. To avoid ground loops and get more accurate measure­ments from the A/D conversion, it is important to understand the
signal source type and how to connect the analog input signals.

Types of Signal Sources

Floating Signal Sources

A floating signal source means it is not connected in any way to
the buildings ground system. A device with an isolated output is a
floating signal source, such as optical isolator outputs, transformer
outputs, and thermocouples.

Ground-Referenced Signal Sources

A ground-referenced signal means it is connected in some way to
the building system. That is, the signal source is already con­nected to a common ground point with respect to the DAQ-/DAQe­2213/2214 card, assuming that the computer is plugged into the
same power system. Non-isolated out-puts of instruments and
devices that plug into the buildings power system are ground-ref­erenced signal sources.

Input Configurations

Single-Ended Connections

A single-ended connection is used when the analog input signal is
referenced to a ground that can be shared with other analog input
signals. There are two types of single-ended connections: RSE
and NRSE. In RSE configuration, the DAQ-/DAQe-2213/2214
card provides the grounding point for the external analog input sig­nals and is suitable for floating signal sources. In the NRSE config­uration the board does not provide the grounding point, the
external analog input signal provides its own reference grounding
point and is suitable for ground-referenced signals.

26 Signal Connections

Referenced Single-ended (RSE) Mode

A

A

A

A

A

A

In referenced single-ended mode, all input signals are con­nected to the ground provided by the DAQ-/DAQe-2213/2214
card. This is suitable for connections with floating signal
sources. Figure 3-1 shows an illustration. Note that when more
than two floating sources are connected, these sources will be
referenced to the same common ground.

CN1

Input Multipexer

In

Instrumentation

mplifier

Floating
Signal
Source

V1

n = 0, ...,63

V2

IGND

-

To A /D
Converter

-

Figure 3-1: Floating Source and RSE Input Connections

Non-Referenced Single-ended (NRSE) Mode

To measure ground-referenced signal sources, which are con­nected to the same ground point, you can connect the signals
in NRSE mode. Figure 3-2 illustrates the connection. The sig­nals local ground reference is connected to the negative input
of the instrumentation Amplifier (AISENSE pin on CN1 connec­tor), and the common-mode ground potential between signal
ground and the ground on board will be rejected by the instru­mentation amplifier.

Input Multipexer

Instrumentation

mplifier

-

To A / D

-

Converter

Ground­Referenced
Signal Source

Common­mode noise &
Ground
potential

V1

V

cm

V2

n = 0, ...,63

In

ISENSE

Figure 3-2: Ground-referenced Sources and NRSE Input Connections

Signal Connections 27

Differential Input Mode

A

A

x

A

A

A

A

x

A

A

The differential input mode provides two inputs that respond to
signal voltage difference between them. If the signal source is
ground-referenced, the differential mode can be used for the com­mon-mode noise rejection. Figure 3-3 shows the connection of
ground-referenced signal sources under differential input mode.

Ground
Referenced
Signal
Source

Common­mode noise &
Ground
potential

V

= 0, ..., 31

cm

IxH

IxL

Input Multipexer

+

-

IGND

Instrumentation

mplifier

To A / D
Converter

-

Figure 3-3: Ground-referenced Source and Differential Input

Ground-referenced Source and Differential Input

Figure 3-4 shows how to connect a floating signal source to the
DAQ-/DAQe-2213/2214 card in differential input mode. For
floating signal sources, you need to add a resistor at each
channel to provide a bias return path. The resistor value should
be about 100 times the equivalent source impedance. If the
source impedance is less than 100ohms, you can simply con­nect the negative side of the signal to AIGND as well as the
negative input of the Instrumentation Amplifier without any
resistors. In differential input mode, less noise couples into the
signal connections than in single-ended mode.

IxH

IxL

Input Multipexer

+

-

Instrumentation

mplifier

To A / D
Converter

-

= 0, ..., 31

Ground
Referenced
Signal
Source

IGND

Figure 3-4: Floating Source and Differential Input

28 Signal Connections

4 Operation Theory

The operation theory of the DAQ-/DAQe-2213/2214 card functions
are described in this chapter. The functions include the A/D con­version, D/A conversion, digital I/O, and general purpose counter/
timer. The operation theory can help you understand how to con­figure and program the DAQ-/DAQe-2213/2214 card.

4.1 A/D Conversion

When using an A/D converter, you must know about the properties
of the signal to be measured. You may decide which channel to
use and how to connect the signals to the card. Refer to section

3.4. In addition, users should define and control the A/D signal
configurations, including channels, gains, and polarities (unipolar/
bipolar).

The A/D acquisition is initiated by a trigger source and you must
decide how to trigger the A/D conversion. The data acquisition will
start once a trigger condition is matched.

After the end of an A/D conversion, the A/D data is buffered in a
Data FIFO. The A/D data can now be transferred into the system
memory for further processing.

Operation Theory 29

DAQ-/DAQe-2213/2214 AI Data Format

The data format of the acquired 16-bit A/D data is two's comple­ment coding. Table 4-1 and Table 4-2 illustrate the valid input

ranges and the ideal transfer characteristics.

Description Bipolar Analog Input Range

Full-scale Range ±10 V ±5 V ±2.5 V ±1.25 V —

Least significant bit 305.2 µV 152.6 µV 76.3 µV 38.15 µV —

FSR-1LSB 9.999695 V 4.999847 V 2.499924 V 1.249962 V 7FFF

Midscale +1LSB 305.2 µV 152.6 µV 76.3 µV 38.15 µV 0001

Midscale 0 V0 V0 V0 V0000

Midscale -1LSB -305.2 µV -152.6 µV -76.3 µV -38.15 µV FFFF

-FSR -10 V -5 V -2.5 V -1.25 V 8000

Table 4-1: Bipolar Analog Input Range and Output Digital Code for DAQ/DAQe/

PXI-2205/2206

Description Unipolar Analog Input Range

Full-scale Range 0V to 10 V 0 to +5 V 0 to +2.5 V 0 to +1.25 V —

Least significant bit 152.6 µV 76.3 µV 38.15 µV 19.07 µV —

FSR-1LSB 9.999847 V 4.999924 V 2.499962 V 1.249981 V 7FFF

Midscale +1LSB 5.000153 V 2.500076 V 1.250038 V 0.625019 V 0001

Midscale 5 V 2.5 V 1.25 V 0.625 V 0000

Midscale -1LSB 4.999847 V 2.499924 V 1.249962 V 0.624981 V FFFF

Table 4-2: Unipolar Analog Input Range and Output Digital Code for DAQ/DAQe/

PXI-2205/2206

Digital

code

Digital

code

30 Operation Theory

Software Conversion with Polling Data Transfer Acquisi­tion Mode (Software Polling)

This is the easiest way to acquire a single A/D data. The A/D con­verter starts one conversion whenever the dedicated software
command is executed. Then the software would poll the conver­sion status and read the A/D data back when it is available.

This method is very suitable for applications that needs to process
A/D data in real time. Under this mode, the timing of the A/D con­version is fully controlled by the software. However, it is difficult to
control the A/D conversion rate.

Specifying Channel, Gain, and Input Configurations in the
Channel Gain Queue

In Software Polling and Programmable Scan Acquisition mode,
the channel, gain, polarity, and input configuration (RSE,
NRSE, or DIFF) can be specified in the Channel Gain Queue.
You can fill the channel number in the Channel Gain Queue in
any order. The channel order of acquisition will be the same as
the order you set in the Channel Gain Queue. Therefore, you
can acquire data with user-defined channel orders and with dif­ferent settings on each channel.

When the specified channels have been sampled from the first
data to the last data in the Channel Gain Queue, the settings in
Channel Gain Queue are maintained. You do not need to re­configure the Channel Gain Queue if you want to keep on sam­pling data in the same order. The maximum number of entries
you can set in the Channel Gain Queue is 512.

Example:

First you can set entries in Channel Gain Queue:

X Ch3 with bipolar ±10V, RSE connection

X Ch1 with bipolar ±2.5V, DIFF connection

X Ch2 with unipolar 5V, NRSE connection

X Ch1 with bipolar ±2.5V, DIFF connection

If you read 10 data by software polling method, then the acqui­sition sequence of channels is 3, 1, 2, 1, 3, 1, 2, 1, 3, 1.

Operation Theory 31

Programmable Scan Acquisition Mode

Scan Timing and Procedure

It is recommended that you use this mode if your applications
need a fixed and precise A/D sampling rate. You can accu­rately program the period between conversions of individual
channels. There are at least four counters which need to be
specified:

X SI_counter (24-bit): Specify the Scan Interval = SI_counter /

Timebase

X SI2_counter (16-bit): Specify the data Sampling Interval =

SI2_counter/Timebase

X PSC_counter (24-bit): Specify Post Scan Counts after a

trigger event

X NumChan_counter (9-bit): Specify the number of samples

per scan

The acquisition timing and the meanings of the counters are
illustrated in Figure 4-1.

TIMEBASE Clock Source

In scan acquisition mode, all the A/D conversions start on the
output of counters, which use TIMEBASE as the clock source.
Using a software, you can specify the TIMEBASE to be either
an internal clock source (onboard 40 MHz clock) or an external
clock input (EXTTIMEBASE) on CN2 connector. The external
TIMEBASE is useful when you want to acquire data at rates
not available with the internal A/D sample clock. The external
clock source should generate TTL-compatible continuous
clocks and with a maximum frequency of 40 MHz while the
minimum should be 1 MHz. Refer to section 4.6 for information
on user-controllable timing signals.

32 Operation Theory

(

)(p

)

3 Scans, 4 Samples per scan
(PSC_Counter=3, NumChan_Counter=4)

Scan_start

AD_conversion

Scan_in_progress

SSHOUT

in8 on CN2

Acquisition_in_progress

( channel sequences are specified in Channel Gain Queue)

Ch2

Ch3

Ch1

Ch0

Ch2

Ch3

Ch1

Ch0

Ch2

Ch3

Ch1

Ch0

Sampling Interval t=
SI2_COUNTER/TimeBase

Scan Interval T=
SI_COUNTER/TimeBase

Figure 4-1: Scan Timing

There are four trigger modes to start the scan acquisition. Refer to
section 4.1 for details. The data transfer mode is discussed in the
following section.

NOTES The maximum A/D sampling rate is 250 MHz. Therefore,

the minimum setting of SI2_counter is 160 when using
the internal TIMEBASE.

The SI_counter is a 24-bit counter and the SI2_counter is
a 16-bit counter. The maximum scan interval using the in­ternal Timebase = 2
mum sampling interval between two channels using the
internal Timebase = 2

24

/40 Ms = 0.419 s, and the maxi-

16

/40 Ms = 1.638 ms.

The scan interval may not be smaller than the product of
the data sampling interval and the NumChan_counter
value. The relationship can be represented as:
SI_counter>=SI2_counter * NumChan_counter.

Operation Theory 33

Scan with SSH

You can send the SSHOUT signal on CN2 to external S&H cir­cuits to sample and hold all signals if you want to simulta­neously sample all channels in a scan, as illustrated in
Figure 4-1.

NOTE The SSHOUT signal is sent to external S&H circuits to

hold the analog signal. You must implement external
S&H circuits on their own to carry out the S&H function.
There are no onboard S&H circuits.

Specifying Channels, Gains, and Input Configurations in the Channel Gain Queue

Like software polling acquisition mode, the channel, gain, and
input configurations can be specified in the Channel Gain Queue
under the scan acquisition mode. Note that in scan acquisition
mode, the number of entries in the Channel Gain Queue is nor­mally equivalent to the value of NumChan_counter (that is, the
number of samples per scan).

Example: Set

X SI2_counter = 160

X SI_counter = 640

X PSC_counter = 3

X NumChan_counter = 4

X Timebase = Internal clock source

X Channel entries in the Channel Gain Queue: ch1, ch2, ch0,

ch2

Then

X Acquisition sequence of channels: 1, 2, 0, 2, 1, 2, 0, 2, 1, 2,

0, 2

X Sampling interval: 160/40 Ms = 4 µs

X Scan interval: 640/40 Ms = 16 µs

X Equivalent sampling rate of ch0, ch1: 62.5 kHz

X Equivalent sampling rate of ch2: 125 kHz

34 Operation Theory

Trigger Modes

The DAQ-/DAQe-2213/2214 card provides four trigger sources
(internal software trigger, external analog trigger, and digital trig­ger sources). You must select one of them as the source of the
trigger event. A trigger event occurs when the specified condition
is detected on the selected trigger source. For example, a rising
edge on the external digital trigger input. Refer to section 4.6 for
more information on SSI signals.

There are four trigger modes (pre-trigger, post-trigger, middle-trig­ger, and delay-trigger) working with the three trigger sources to ini­tiate different scan data acquisition timing when a trigger event
occurs. They are described in the following sections. For informa­tion on trigger sources, refer to section 4.5.

Operation Theory 35

Pre-Trigger Acquisition

Use pre-trigger acquisition in applications where you want to
collect data before a trigger event. The A/D starts to sample
when you execute the specified function calls to begin the pre­trigger operation, and it stops when the trigger event occurs.
Users must program the value M in M_counter (16 bits) to
specify the amount of the stored scans before the trigger event.
If an external trigger occurs, the program only stores the last M
scans of data converted before the trigger event, as illustrated
in Figure 4-4, where M_counter = M =3, PSC_counter = 0. The
post scan count is 0 because there is no sampling after the trig­ger event in pre-trigger acquisition. The total stored amount of
data = Number of enabled channels * M_counter.

AD_conversion

Scan_in_progress
(SSHOUT)(pin8 on CN2)

Acquisition_in_progress

(M_counter = M = 3, NumChan_counter=4, PSC_counter=0)

Trigger

Scan_start

Operation start

Figure 4-2: Pre-trigger (Trigger occurs after M scans)

Aquired data

Acquired & stored data
(M scans)

36 Operation Theory

Note that if a trigger event occurs when a scan is in progress, the
data acquisition won't stop until the scan completes, and the
stored M scans of data includes the last scan. Therefore, the first
stored set of data will always be the first channel entry of a scan
(that is, the first channel entry in the Channel Gain Queue if the
number of entries in the Channel Gain Queue is equivalent to the
value of NumChan_counter), no matter when a trigger signal
occurs, as illustrated in Figure 16, where M_counter = M =3,
NumChan_counter = 4, PSC_counter = 0.

(M_counter = M = 3, NumChan_counter =4, PSC_counter=0)

Trigger

Scan_start

AD_conversion

Scan_in_progress
(SSHOUT)(pin8 on CN2)

Acquisition_in_progress

Figure 4-3: Pre-trigger (Trigger with scan in progress)

Aquired data

Operation start

Acquired & stored data
(M scans)

Trigger occurs

Data acquisition
won’t stop until a
scan completes

Operation Theory 37

When the trigger signal occurs before the first M scans of data are
converted, the amount of stored data could be fewer than the orig­inally specified amount in NumChan_counter * M_counter, as
illustrated in Figure 4-4. This situation can be avoided by setting
M_enable. If M_enable is set to 1, the trigger signal will be ignored
until the first M scans of data are converted, and it assures you M
scans of data under pre-trigger mode, as illustrated in Figure 4-5.
However, if M_enable is set to 0, the trigger signal will be
accepted any time, as shown in Figure 4-4. Note that the total
amount of stored data will always be equal to the number in the
M_counter because data acquisition does not stop until a scan is
completed.

(M_Counter = M = 3, NumChan_Counter=4, PSC_Counter=0)

Trigger

Scan_start

AD_conversion

Scan_in_progress
(SSHOUT)(pin8 on CN2)

Acquisition_in_progress

Acquired & stored data
(2 scans)

Operation start

Figure 4-4: Pre-trigger with M_enable=0 (Trigger occurs before M scans)

38 Operation Theory

AD_conversion

Scan_in_progress
(SSHOUT)(pin2 on CN2)

Acquisition_in_progress

(M_counter = M = 3, NumChan_counter=4, PSC_counter=0)

Trigger

Scan_start

The first M scans

Trigger signals which occur in the shadow
region(the first M scans) will be ignored

Aquired data

Operation start

Acquired & stored data
(M scans)

Figure 4-5: Pre-trigger with M_enable=1

NOTE The PSC_counter is set to 0 in pre-trigger acquisition

mode.

Operation Theory 39

Middle-Trigger Acquisition

Use middle-trigger acquisition in applications where you want
to collect data before and after a trigger event. The number of
scans (M) stored before the trigger is specified in M_counter,
while the number of scans (N) after the trigger is specified in
PSC_counter.

Like pre-trigger mode, the number of stored data could be less
than the specified amount of data [NumChan_counter *(M+N)],
if an external trigger occurs before M scans of data are con­verted. The M_enable bit in middle-trigger mode takes the
same effect as in pre-trigger mode. If M_enable is set to 1, the
trigger signal will be ignored until the first M scans of data are
converted, and it assures you with (M+N) scans of data under
middle-trigger mode. However, if M_enable is set to 0, the trig­ger signal will be accepted at any time. Figure 4-6 shows the
acquisition timing with M_enable=1.

Figure 4-6: Middle-Trigger with M_enable = 1

40 Operation Theory

If the trigger event occurs when a scan is in progress, the stored N
scans of data would include this scan, as illustrated in Figure 4-7.

Figure 4-7: Middle-Trigger (Trigger occurs when a scan is in progress)

Operation Theory 41

Post-Trigger Acquisition

Use post-trigger acquisition in applications where you want to
collect data after a trigger event. The number of scans after the
trigger is specified in PSC_counter, as illustrated in Figure 4-8.
The total acquired data length = NumChan_counter *
PSC_counter.

AD_conversion

Scan_in_progress
(SSHOUT)(pin8 on CN2

Acquisition_in_progress

(NumChan_Counter=4, PSC_Counter=3)

Trigger

Scan_start

Operation start

Figure 4-8: Post-trigger

Acquired & stored data
(3 scans)

42 Operation Theory

Delay Trigger Acquisition

Use delay trigger acquisition in applications where you want to
delay the data collection after the occurrence of a specified trig­ger event. The delay time is controlled by the value, which is
pre-loaded in the Delay_counter (16-bit). The counter counts
down on the rising edge of the Delay_counter clock source
after the trigger condition is met. The clock source can be soft­ware-programmed either by the TIMEBASE clock (40 MHz) or
A/D sampling clock (TIMEBASE / SI2_counter). When the
count reaches 0, the counter stops and the card starts to
acquire data. The total acquired data length =
NumChan_counter * PSC_counter.

AD_conversion

Scan_in_progress
(SSHOUT)(pin8 on CN2)

Acquisition_in_progress

(NumChan _Counter=4, PSC_Counter=3)

Trigger

Scan_start

Delay until
Delay_Counter
reaches 0

Operation start

Acquired & stored data
(3 scans)

Figure 4-9: Delay trigger

NOTE When the Delay_counter clock source is set to TIME-

BASE, the maximum delay time is 216/40 Ms or 1.638 ms.
When the source is set to A/D sampling clock, the maxi­mum delay time may be higher than 2

16

* SI2_counter /

40M.

Operation Theory 43

Post-Trigger or Delay-trigger Acquisition with re-trigger

Use post-trigger or delay-trigger acquisition with re-trigger
function in applications where you want to collect data after
several trigger events. The number of scans after each trigger
is specified in PSC_counter, and users could program
Retrig_no to specify the re-trigger numbers. Figure 4-10 illus­trates an example. In this example, two scans of data is
acquired after the first trigger signal, then the card waits for the
re-trigger signal (re-trigger signals which occur before the first
two scans is completed will be ignored). When the re-trigger
signal occurs, two more scans are performed. The process
repeats until specified amount of re-trigger signals are
detected. The total acquired data length = NumChan_counter *
PSC_counter * Re-trig_no.

Scan_in_progress
(SSHOUT)(pin8 on CN2)

Acquisition_in_progress

(NumChan _Counter=4, PSC_Counter=2, retrig_no=3)

Trigg er

Scan_start

AD_conversion

Acquired & stored data
(6 scans)

Operation start

Figure 4-10: Post trigger with Re-trigger

44 Operation Theory

Bus-mastering DMA Data Transfer

PCI bus-mastering DMA is necessary for high speed DAQ in order
to utilize the maximum PCI bandwidth. The bus-mastering control­ler, which is built in the PLX IOP-480 PCI controller, controls the
PCI bus when it becomes the master of the bus. Bus mastering
reduces the size of the on-board memory and reduces the CPU
loading because data is directly transferred to the computer’s
memory without host CPU intervention.

Bus-mastering DMA provides the fastest data transfer rate on PCI­bus. Once the analog input operation starts, control returns to your
program. The hardware temporarily stores the acquired data in the
onboard AD Data FIFO and then transfers the data to a user­defined DMA buffer memory in the computer. Note that even when
the acquired data length is less than the Data FIFO, the AD data is
not kept in the Data FIFO but directly transferred into host memory
by the bus-mastering DMA.

The DMA transfer mode is complicated to program. We recom­mend using a high-level program library to configure this card. If
users would like to know more about software programs that can
handle the DMA bus master data transfer, visit to http://www.plx­tech.com for more information on PCI controllers.

By using a high-level programming library for high speed DMA
data acquisition, you simply need to assign the sampling period
and the number of conversion into your specified counters. After
the AD trigger condition is matched, the data is transferred to the
system memory by the bus-mastering DMA.

The PCI controller also supports the function of scatter/gather bus
mastering DMA, which helps you transfer large amounts of data
by linking all the memory blocks into a continuous linked list.

In a multi-user or multi-tasking OS, like Windows, Linux, etc, it is
difficult to allocate a large continuous memory block to do the
DMA transfer. Therefore, the PLX IOP-480 provides the function
of scatter/gather or chaining mode DMA to link the non-continuous
memory blocks into a linked list so that you can transfer very large
amounts of data without being limited by the fragment of small size
memory. You can configure the linked list for the input DMA chan­nel or the output DMA channel.

Operation Theory 45

Figure 4-11 shows a linked list that is constructed by three DMA
descriptors. Each descriptor contains a PCI address, a local
address, a transfer size, and the pointer to the next descriptor.
You can allocate many small size memory blocks and chain their
associative DMA descriptors altogether by their application pro­grams. The DAQ-/DAQe-2213/2214 card software driver provides
simple settings for the scatter/gather function, including some
sample programs in the ADLINK All-in-One CD.

Figure 4-11: Scatter/gather DMA for Data Transfer

In non-chaining mode, the maximum DMA data transfer size is 2
M double words (8M bytes). However, there is no limitation on the
DMA data transfer size when using scatter/gather chaining mode.
You can also link the descriptor nodes circularly to achieve a multi­buffered mode DMA.

46 Operation Theory

4.2 D/A Conversion

NOTE The DAQ-/DAQe-2213 card does not support this func-

tion.

There are two 12-bit D/A output channels available in the DAQ-/
DAQe-/PXI-2204/2205/2206 card. When using D/A converters,
you should assign and control the D/A converter reference
sources for the D/A operation mode and D/A channels. You could
also set the output polarity to unipolar or bipolar.

The reference selection control lets you utilize in full the multiply­ing characteristics of the D/A converters. Internal 10V reference
and external reference inputs are available in the DAQ-/DAQe­2214 card. The range of the D/A output is directly related to the
reference. The digital codes that are updated to the D/A convert­ers will multiply with the reference to generate the analog output.
While using internal 10V reference, the full range would be –10V
to +9.9951V in the bipolar output mode, and 0V to 9.9976V in the
unipolar output mode. While using an external reference, you can
reach different output ranges by connecting different references.
For example, if connecting a DC –5V with the external reference,
then you can get a full range from –4.9976V to +5V in the bipolar
output with inverting characteristics due to the negative reference
voltage. You could also have an amplitude modulated (AM) output
by feeding a sinusoidal signal into the reference input. The range
of the external reference should be within ±10V. Table 4-3 and
Table 4-4 illustrates the relationship between digital code and out­put voltages with Vref=10V and if internal reference is selected.

Digital Code Analog Output

111111111111 Vref * (2047/2048)

100000000001 Vref * (1/2048)

100000000000 0V

011111111111 -Vref * (1/2048)

000000000000 -Vref

Table 4-3: Bipolar Output Code Table

Operation Theory 47

Digital Code Analog Output

111111111111 Vref * (4095/4096)

100000000000 Vref * (2048/4096)

000000000001 Vref * (1/4096)

000000000000 0V

Table 4-4: Unipolar Output Code Table

The D/A conversion is initiated by a trigger source. You must
decide how to trigger the D/A conversion. The data output will start
when a trigger condition is met. Before the start of D/A conversion,
D/A data is transferred from the computer’s main memory to a
buffering Data FIFO.

Two D/A conversion modes are available: Software Update and
Timed Waveform Generation. These are described below, includ­ing the timing, trigger source control, trigger modes, and data
transfer methods. Either mode may be applied to D/A channels
independently. You can simultaneously software update DA CH0
while generating timed waveforms on CH1.

Software Update

This is the easiest way to generate D/A output. To do this:

1. Specify the D/A output channels.

2. Set output polarity (unipolar or bipolar) and reference
source (internal 10V or external AOEXTREF).

3. Update the digital values into D/A data registers through
a software output command.

48 Operation Theory

Timed Waveform Generation

This mode can provide your applications with a precise D/A output
with a fixed update rate. It can be used to generate an infinite or
finite waveform. You can accurately program the update period of
the D/A converters.

The D/A output timing is provided through a combination of
counters in the FPGA on board. There are a total of five counters
to be specified. These counters include:

X UI_counter (24 bits): Specify the DA update interval is equal

to CHUI_counter/TIMEBASE

X UC_counter (24 bits): Specify the total update counts in a

single waveform

X IC_counter (24 bits): Specify the iteration counts of wave-

form

X DA_DLY1_counter (16 bits): Specify the delay from the trig-

ger to the first update start

X DA_DLY2_counter (16 bits): Specify the delay between two

consecutive waveform generations

Figure 4-12 shows a typical D/A timing diagram assuming the data
in the data buffer are 2V, 4V, -4V, 0V. D/A updates its output on
each rising edge of DAWR. The meaning of the counters enumer­ated above are discussed in the following sections.

Operation Theory 49

Trigger

DAWR

WFG_in_progress

4 update counts, 3 iterations

(UC _Counter=4, IC_Counter=3)

UC_Counter=4

Output Waveform

Operation start

Delay until
DLY1_Counter
reaches 0

Delay until
DLY2_Counter
reaches 0

DA update_interval t=
UI_Counter/Timebase

-

A single waveform

IC_Counter = 3

Delay until
DLY2_Counter
reaches 0

Figure 4-12: Typical D/A Timing of Waveform Generation

NOTE The maximum D/A update rate is 1 MHz. Therefore, the

minimum setting of the UI_counter is 40 while using an in­ternal TIMEBASE (40 MHz).

50 Operation Theory

Trigger Modes

Post-trigger Generation

Use post-trigger when you want to perform DA waveform right
after a trigger event occurs. In this trigger mode DLY1_Counter
is ignored and not be specified. Figure 4-13 shows a single
waveform generated right after a trigger signal is detected and
assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, ­4V, -2V, and 4V. The trigger signal could come from a software
command, an analog trigger or a digital trigger. Refer to section

4.5 for detailed information.

Trigger

DAWR

WFG_in_progress

Output Waveform

8 update counts, 1 iteration

(UC _Counter=8, IC_Counter=1)

2

-

-

Operation start

Figure 4-13: Post-trigger Waveform Generation

Delay-trigger Generation

Use delay-trigger when you want to delay the waveform gener­ation after a trigger event. In Table 4-14, DA_DLY1_counter
determines the delay time from the trigger signal to the start of
the waveform generation, assuming the data in the data buffer
are 2V, 4V, 6V, 3V, 0V, -4V, -2V, and 4V. DLY1_counter
counts down on the rising edge of its clock source after the trig­ger condition is met. When the count reaches 0, the counter
stops and the DAQ-/DAQe-2214 card starts the waveform gen­eration. This DLY1_Counter is 16-bit wide and you can set the
delay time in units of TIMEBASE (delay time = DLY1_Counter/
TIMEBASE) or in units of update period (delay time =
DLY1_Counter * UI_counter/TIMEBASE), so the delay time
can reach a wider range.

Operation Theory 51

Figure 4-14: Delay Trigger Waveform Generation

Post-Trigger or Delay-Trigger with Re-trigger

Use post-trigger or delay-trigger with re-trigger function when
you want to generate waveform after more than one trigger
events. The re-trigger function can be enabled or disabled by
software setting. In Figure 4-15, each trigger signal will initiate
a waveform generation assuming the data in the data buffer
are 2V, 4V, 2V, and 0V. However, the trigger event would be
ignored while the waveform generation is ongoing.

Figure 4-15: Re-triggered Waveform Generation with Post-Trigger

(DLY2_Counter=0)

52 Operation Theory

Iterative Waveform Generation

Set IC_Counter in order to generate iterative waveforms from the
data of a single waveform. The counter stores the iteration number
and the iterations may be finite (Figure 4-16) or infinite (Figure 4-

17). Take note that in infinite mode the waveform generation does

not stop until software stop function is executed and IC_Counter is
still valid when stop mode III is selected. Both figures assume that
the data in the data buffer are 2V, 4V, 2V, and 0V.

An onboard data FIFO is used to buffer the digital data for DA out­put. If the data size of a single waveform you specified (That is,
Update Counts in UC_counter) is less than the FIFO size, after ini­tially transferring the data from the host PC memory to the FIFO
on board, the data in the FIFO will be automatically re-transmitted
whenever a single waveform is completed. Therefore, it does not
occupy the PCI bandwidth when repetitive waveforms are per­formed. However, if the size of a single waveform were larger than
that of the FIFO, it needs to be intermittently loaded from the host
PC’s memory via DMA, when a repetitive waveforms is performed
thus PCI bandwidth would be occupied.

The data FIFO size on the DAQ-/DAQe-2214 card is 1024 (words)
when one DA channel is enabled, or 512 (words) when both DA
channels are enabled.

Figure 4-16: Finite Iterative Waveform Generation with Post-trigger

(DLY2_Counter = 0)

Operation Theory 53

Figure 4-17: Infinite Iterative Waveform Generation with Post-trigger

(DLY2_Counter = 0)

Delay2 in Iterative Waveform Generation

To stretch out the flexibility of the D/A waveform generation, a
DLY2_Counter was added to separate two consecutive wave­forms in iterative waveform generation. The time between two
waveforms is assigned by setting the value of the
DLY2_Counter. The DLY2_Counter starts to count down after
a waveform generation finishes and the next waveform genera­tion starts right after it counts down to zero, as shown in
Figure 4-18. This DLY2_Counter is 16-bit wide and you may
set the delay time in unit of TIMEBASE (delay time =
DLY2_Counter/TIMEBASE) or in unit of update period (delay
time = DLY2_Counter * UI_Counter/TIMEBASE), so the delay
time can reach a wider range.

54 Operation Theory

Stop Modes of Scan Update

You can call software stop function to stop waveform generation
when it is still in progress. Three stop modes are provided for
timed waveform generation meant to stop the waveform genera­tion. You can apply these three modes to stop waveform genera­tion no matter infinite or finite waveform generation mode is
selected.

Figure 4-18 illustrates an example for stop mode I, assuming the
data in the data buffer are 2V, 4V, 2V, and 0V. In this mode, the
waveform stops immediately when software command is asserted.

.

Figure 4-18: Stop Mode I

Operation Theory 55

In stop mode II, after a software stop command is given, the wave­form generation does not stop until a complete single waveform is
finished. See Figure 4-19. Since the UC_counter is set to four, the
total DA update counts (number of pulses of DAWR signal) must
be a multiple of four (update counts = 20 in this example).

Figure 4-19: Stop Mode II

In stop mode III, after a software stop command is given, the
waveform generation does not stop until the performed number
of waveforms is a multiple of the IC_Counter. See Figure 4-20.
Since the IC_Counter is set to three, the total generated wave­forms must be a multiple of three (waveforms = 6 in this exam­ple), and the total DA update counts must be a multiple of 12
(UC_counter * IC_Counter). You can compare these three fig­ures to see the differences.

Figure 4-20: Stop Mode III

56 Operation Theory

4.3 Digital I/O

The DAQ-/DAQe-2213/2214 card contains 24 lines of general-pur­pose digital I/O (GPIO) which is provided through the 82C55A
chip.

The 24-line GPIO are separated into three ports: Port A, Port B
and Port C. High nibble (bit[7…4]), and low nibble (bit[3…0]) of
each port can be programmed individually to be either inputs or
outputs. Upon system startup or reset, all the GPIO pins are reset
to high impedance inputs.

4.4 General Purpose Timer/Counter Operation

NOTE The DAQ-/DAQe-/PXI-2208 card does not support this

function.

Two independent 16-bit up/down timer/counter are designed
within FPGA for various applications. They have the following fea­tures:

X Count up/down controlled by hardware or software

X Programmable counter clock source (internal or external

clock up to 10 MHz)

X Programmable gate selection (hardware or software con-

trol)

X Programmable input and output signal polarities (high active

or low active)

X Initial count can be loaded from software

X Current count value can be read-back by software without

affecting circuit operation

Operation Theory 57

The Basics of Timer/Counter Functions

Each timer/counter has three inputs that can be controlled via
hardware or software. These are clock input (GPTC_CLK), gate
input (GPTC_GATE), and up/down control input
(GPTC_UPDOWN). The GPTC_CLK input provides a clock
source input to the timer/counter. Active edges on the GPTC_CLK
input make the counter increment or decrement. The
GPTC_UPDOWN input controls whether the counter counts up or
down. The GPTC_GATE input is a control signal which acts as a
counter enable or a counter trigger signal under different applica­tions.

The output of timer/counter is GPTC_OUT. After power-up,
GPTC_OUT is pulled high by a pulled-up resister about 10K
ohms. Then GPTC_OUT goes low after the DAQ-/DAQe-2213/
2214 card is initialized.

All the polarities of input/output signals can be programmed by
software. In this chapter, for easy explanation, all GPTC_CLK,
GPTC_GATE, and GPTC_OUT are assumed to be active high or
rising-edge triggered in the figures.

General Purpose Timer/Counter Modes

Eight programmable timer/counter modes are provided. All modes
start operating following a software-start signal that is set by the
software. The GPTC software reset initializes the status of the
counter and re-loads the initial value to the counter. The operation
remains halted until the software-start is re-executed. The operat­ing theories under different modes are described in the following
sections.

58 Operation Theory

Mode1: Simple Gated-Event Counting

In this mode, the counter counts the number of pulses on the
GPTC_CLK after the software-start. Initial count can be loaded
from software. Current count value can be read-back by soft­ware any time without affecting the counting. GPTC_GATE is
used to enable/disable counting. When GPTC_GATE is inac­tive, the counter halts the current count value. Figure 4-21 illus­trates the operation with initial count = 5, countdown mode.

Figure 4-21: Mode1 Operation

Mode2: Single Period Measurement

In this mode, the counter counts the period of the signal on
GPTC_GATE in terms of GPTC_CLK. Initial count can be
loaded from software. After the software-start, the counter
counts the number of active edges on GPTC_CLK between
two active edges of GPTC_GATE. After the completion of the
period interval on GPTC_GATE, GPTC_OUT outputs high and
then current count value can be read-back by software.
Figure 4-22 illustrates the operation where initial count = 0,
count-up mode.

Operation Theory 59

Figure 4-22: Mode2 Operation

Mode3: Single Pulse-width Measurement

In this mode, the counter counts the pulse-width of the signal
on GPTC_GATE in terms of GPTC_CLK. Initial count can be
loaded from software. After the software-start, the counter
counts the number of active edges on GPTC_CLK when
GPTC_GATE is in its active state. After the completion of the
pulse-width interval on GPTC_GATE, GPTC_OUT outputs
high, then current count value can be read-back by software.
Figure 4-23 illustrates the operation where initial count = 0,
count-up mode.

Figure 4-23: Mode3 Operation

60 Operation Theory

Mode4: Single Gated Pulse Generation

This mode generates a single pulse with programmable delay
and programmable pulse-width following the software-start.
The two programmable parameters could be specified in terms
of periods of the GPTC_CLK input by software. GPTC_GATE
is used to enable/disable counting. When GPTC_GATE is inac­tive, the counter halts the current count value. Figure 4-24 illus­trates the generation of a single pulse with a pulse delay of two
and a pulse-width of four.

Figure 4-24: Mode4 Operation

Mode5: Single Triggered Pulse Generation

This function generates a single pulse with programmable
delay and pro-grammable pulse-width following an active
GPTC_GATE edge. You could specify these programmable
parameters in terms of periods of the GPTC_CLK input. Once
the first GPTC_GATE edge triggers the single pulse,
GPTC_GATE takes no effect until the software-start is re-exe­cuted. Figure 4-25 illustrates the generation of a single pulse
with a pulse delay of two and a pulse-width of four.

Operation Theory 61

Figure 4-25: Mode5 Operation

Mode6: Re-triggered Single Pulse Generation

This mode is similar to Mode5 except that the counter gener­ates a pulse following every active edge of GPTC_GATE. After
the software-start, every active GPTC_GATE edge triggers a
single pulse with programmable delay and pulse-width. Any
GPTC_GATE triggers that occur when the prior pulse is not
completed would be ignored. Figure 4-26 illustrates the gener­ation of two pulses with a pulse delay of two and a pulse-width
of four.

Figure 4-26: Mode6 Operation

62 Operation Theory

Mode7: Single Triggered Continuous Pulse Generation

This mode is similar to Mode5 except that the counter gener­ates continuous periodic pulses with programmable pulse inter­val and pulse-width following the first active edge of
GPTC_GATE. Once the first GPTC_GATE edge triggers the
counter, GPTC_GATE takes no effect until the software-start is
re-executed. Figure 4-27 illustrates the generation of two
pulses with a pulse delay of four and a pulse-width of three.

Figure 4-27: Mode7 Operation

Mode8: Continuous Gated Pulse Generation

This mode generates periodic pulses with programmable pulse
interval and pulse-width following the software-start.
GPTC_GATE is used to enable/disable counting. When
GPTC_GATE is inactive, the counter halts the current count
value. Figure 4-28 illustrates the generation of two pulses with
a pulse delay of four and a pulse-width of three.

Figure 4-28: Mode8 Operation

Operation Theory 63

4.5 Trigger Sources

ADLINK provides flexible trigger selections in the DAQ-/DAQe­2213/2214 card. In addition to the internal software trigger, the
DAQ-/DAQe-2213/2214 card also supports external analog, digital
triggers, and SSI triggers. You can configure the trigger source by
software for A/D and D/A processes individually.

Software-Trigger

This trigger mode does not need any external trigger source. The
trigger asserts right after you execute the specified function calls
to begin the operation.

External Analog Trigger

The analog trigger circuitry routing is shown in Figure 4-29. The
analog multiplexer can select either a direct analog input from the
EXTATRIG pin (SRC1) in the 68-pin connector or the input signal
of ADC (SRC2). That is, one of the four channel inputs you can
select as a trigger source. Both trigger sources can be used for all
trigger modes. The range of trigger level for SRC1 is ±10V and the
resolution is 78 mV (refer to Table 4-4), while the trigger range of
SRC2 is the full-scale range of the selected channel input and the
resolution is the desired range divided by 256. For example, if the
channel input selected to be the trigger source is set bipolar and
±5 V range, the trigger voltage would be 4.96V when the trigger
level code is set to 0xFF while -4.96V when the code is set to
0x01.

Figure 4-29: Analog Trigger Block Diagram

64 Operation Theory

Trigger level digital setting Trigger voltage

0xFF 9.92V

0xFE 9.84V

0x81 0.08V

0x80 0

0x7F -0.08V

0x01 -9.92V

Table 4-5: Analog Trigger SRC1 (EXTATRIG) Ideal Transfer Characteristic

The trigger signal is generated when the analog trigger condition
is satisfied. There are five analog trigger conditions in the DAQ-/
DAQe-2213/2214 card. The DAQ-/DAQe-2213/2214 card uses
two threshold voltages, Low_Threshold and High_Threshold to
build these different trigger conditions. You can conveniently con­figure the trigger conditions using a software application.

Operation Theory 65

Below-Low Analog Trigger Condition

Figure 4-30 shows the below-low analog trigger condition, the
trigger signal is generated when the input analog signal is less
than the Low_Threshold voltage, and the High_Threshold set­ting is not used in this trigger condition.

Figure 4-30: Below-Low Analog Trigger Condition

Above-High Analog Trigger Condition

Figure 4-31 shows the above-high analog trigger condition, the
trigger signal is generated when the input analog signal is
higher than the High_Threshold voltage, and the
Low_Threshold setting is not used in this trigger condition.

Figure 4-31: Above-High Analog Trigger Condition

66 Operation Theory

Inside-Region Analog Trigger Condition

Figure 4-32 shows the inside-region analog trigger condition,
the trigger signal is generated when the input analog signal
level falls in the range between the High_Threshold and the
Low_Threshold voltages.

NOTE The High_Threshold setting should be always higher

than the Low_Threshold voltage setting.

Figure 4-32: Inside-Region Analog Trigger Condition

High-Hysteresis Analog Trigger Condition

Figure 4-33 shows the high-hysteresis analog trigger condition,
the trigger signal is generated when the input analog signal
level is greater than the High_Threshold voltage, and the
Low_Threshold voltage determines the hysteresis duration.
Note the High_Threshold setting should be always higher then
the Low_Threshold voltage setting.

Operation Theory 67

Figure 4-33: High-Hysteresis Analog Trigger Condition

Low-Hysteresis Analog Trigger Condition

Figure 4-34 shows the low-hysteresis analog trigger condition,
the trigger signal is generated when the input analog signal
level is less than the Low_Threshold voltage, and the
High_Threshold voltage determines the hysteresis duration.
Note the High_Threshold setting should be always higher then
the Low_Threshold voltage setting.

Figure 4-34: Low-Hysteresis Analog Trigger Condition

68 Operation Theory

External Digital Trigger

An external digital trigger occurs when a rising edge or a falling
edge is detected on the digital signal connected to the EXT­DTRIG or the EXTWFTRG of the 68-pin connector for external
digital trigger. The EXTDTRIG is dedicated for A/D process,
and the EXTWFTRG is used for D/A process. You can program
the trigger polarity using the software drivers. Note that the sig­nal level of the external digital trigger signals should be TTL­compatible and the minimum pulse is 20 ns.

Figure 4-35: External Digital Trigger

Operation Theory 69

4.6 User-controllable Timing Signals

In order to meet the requirements for user-specific timing and
requirements for synchronizing multiple cards, the DAQ-/DAQe­2213/2214 card provides flexible user-controllable timing signals
to connect to external circuitry or additional cards.

The whole DAQ timing of the DAQ-/DAQe-2213/2214 card is com­posed of a bunch of counters and trigger signals in the FPGA.
These timing signals are related to the A/D, D/A conversions, and
Timer/Counter applications. These timing signals can be input to
or output from the I/O connectors, SSI connector, and the PXI bus.
Therefore, the internal timing signals can be used to control exter­nal devices or circuitry. Note that in other models of DAQ-/DAQe­2213/2214 card, the user-controllable timing signals may vary.
However, the SSI/PXI timing signals remain the same for every
DAQ-/DAQe-2213/2214 card.

We implemented signal multiplexers in the FPGA to individually
choose the desired timing signals for the DAQ operations, as
shown in the Figure 4-36.

Figure 4-36: DAQ Signals Routing

70 Operation Theory

You can utilize the flexible timing signals through our software
drivers, then simply and correctly connect the signals with the
DAQ-/DAQe-2213/2214 card. Here is the summary of the DAQ
timing signals and the corresponding functionalities for DAQ-/
DAQe-2213/2214 card.

Timing signal category Corresponding functionality

SSI/PXI signals Multiple cards synchronization

AFI signals

Table 4-6: User-controllable Timing Signals and Functionalities

Control DAQ-/DAQe-2213/2214 by external
timing signals

DAQ Timing Signals

NOTES Refer to section 4.1 for the internal timing signal defini-

tion.

1. TIMEBASE provides the TIMEBASE for all DAQ opera-

tions which could be from an internal 40 MHz oscillator,
EXTTIMEBASE from I/O connector or the
SSI_TIMEBASE. Note that the frequency range of the
EXTTIMEBASE is 1 MHz to 40 MHz, and the EXTTIME­BASE must be TTL-compatible.

2. AD_TRIG is the trigger signal for the A/D operation and

may come from external digital trigger, analog trigger,
internal software trigger, and SSI_AD_TRIG. Refer to
section 4.5 for detailed description.

3. SCAN_START is the signal to start a scan that would

bring the following ADCONV signals for AD conversion
and may come from the internal SI_counter, AFI[0] and
SSI_AD_START. This signal is synchronous to the
TIMEBASE. Note that the AFI[0] should be TTL-compat­ible and the minimum pulse width should be the pulse
width of the TIMEBASE to guarantee correct functional­ities.

4. ADCONV is the conversion signal to initiate a single con-

version and may be derived from internal counter, AFI[0]
or SSI_ADCONV. Note that this signal is edge-sensitive.

Operation Theory 71

When using AFI[0] as the external ADCONV source,
each rising edge of AFI[0] would bring an effective con­version signal. Also note that the AFI[0] signal should be
TTL-compatible and the minimum pulse width is 20 ns.

5. DA_TRIG is the trigger signal for the D/A operation and
may be derived from external digital trigger, analog trig­ger, internal software trigger, and SSI_AD_TRIG. Refer
to section 4.5 for detailed description.

6. DAWR is the update signal to initiate a single D/A con­version and may be derived from internal counter, AFI[1]
or SSI_DAWR. Note that this signal is edge-sensitive.
When using AFI[1] as the external DAWR source, each
rising edge of AFI[1] would bring an effective update sig­nal. Also note that the AFI[1] signal should be TTL-com­patible and the minimum pulse width is 20 ns.

NOTES The DA_TRIG and DAWR timing signals are available

only on DAQ-/DAQe-2214.

72 Operation Theory

Auxiliary Function Inputs (AFI)

You can use the AFI in applications that take advantage of exter­nal circuitry to directly control the DAQ-/DAQe-2213/2214 card.
The AFI includes two categories of timing signals: one group is the
dedicated input, and the other is the multi-function input. Table 4-7
illustrates this categorization.

Category Timing signal Functionality Constraints

Replace the

EXTTIMEBASE

internal TIME-

BASE

Dedi-

cated

input

EXTDTRIG

EXTWFTRG

(for DAQ-DAQe-

2214 only)

External digital

trigger input for

A/D operation

External digital

trigger input for

D/A operation

Replace the

internal

ADCONV

Replace the

internal

SCAN_START

Replace the

internal DAWR

Multi-

function

input

AFI[0]

(Dual-functions)

AFI[1]

(for DAQ-DAQe-

2214 only)

Table 4-7: Auxiliary Function Input Signals and Functionalities

• TTL-compatible

• 1 MHz to 40 MHz

• Affects on both A/D and D/A
operations.

• TTL-compatible

• Minimum pulse width = 20ns

• Rising edge or falling edge

• TTL-compatible

• Minimum pulse width = 20ns

• Rising edge or falling edge

• TTL-compatible

• Minimum pulse width = 20ns

• Rising–edge sensitive only

• TTL-compatible

• Minimum Pulse width > 2/
TIMEBASE

• TTL-compatible

• Minimum pulse width = 20ns

• Rising–edge sensitive only

Operation Theory 73

EXTDTRIG and EXTWFTRIG

EXTDTRIG and EXTWFTRIG are dedicated digital trigger input
signals for A/D and D/A operations. Refer to section 4.5 for
details.

EXTTIMEBASE

When the applications needs specific sampling frequency or
update rate that the card could not generate from its internal
TIMEBASE — the 40 MHz clock — you could utilize the EXT­TIMEBASE with internal counters to achieve the specific timing
intervals for both A/D and D/A operations. Note that once you
choose the TIMEBASE source, both A/D and D/A operations
will be affected because A/D and D/A operations share the
same TIMEBASE.

AFI[0]

Alternatively, you can also directly apply an external A/D con­version signal to replace the internal ADCONV signal. This is
another way to achieve customized sampling frequencies. The
external ADCONV signal can only be inputted from the AFI[0].
As section 4.1 describes, the SI_counter triggers the genera­tion of the A/D conversion signal, ADCONV, but when using
the AFI[0] to replace the internal ADCONV signal, the
SI_counter and the internally generated SCAN_START is not
effective. By controlling the ADCONV externally, you can sam­ple the data according to external events. In this mode, the
Trigger signal and trigger mode settings are not available.

AFI[0] could also be used as SCAN_START signal for A/D
operations. Refer to section 4.1 and section 4.6 for detailed
descriptions of the SCAN_START signal. When using external
signal (AFI[0]) to replace the internal SCAN_START signal, the
pulse width of the AFI[0] must be greater than two time of the
period of Timebase. This feature is suitable for the DAQ-2200/
DAQe-2200/PXI-2200 Series, which can scan multiple chan­nels data controlled by an external event. Note that the AFI[0]
is a multi-purpose input, and it can only be utilized for one func­tion at any one time.

74 Operation Theory

AFI[1] (DAQ-/DAQe-2214 only)

Regarding D/A operations, you can directly input the external
D/A update signal to replace the internal DAWR signal. This is
another way to achieve customized D/A update rates. The
external DAWR signal can only be inputted from the AFI[1].
Note that the AFI[1] is a multi-purpose input, and it can only be
utilized for one function at any one time. Currently, AFI[1] has
only one function. ADLINK reserves this for future develop­ment.

Operation Theory 75

System Synchronization Interface

The SSI (System Synchronization Interface) provides the DAQ
timing synchronization among multiple cards. In DAQ-/DAQe­2213/2214 card, a bi-directional SSI I/O provides a flexible con­nection among cards and allows one SSI master to output the sig­nal and up to three slaves to receive the SSI signal. The SSI
signals are designed for card synchronization only and not for
external devices.

SSI Timing Signal Setting Function

Master Send the TIMEBASE out

SSI_TIMEBASE

SSI_ADCONV

SSI_SCAN_START

SSI_AD_TRIG

SSI_DAWR

SSI_DA_TRIG

Slave

Master Send the ADCONV out

Slave

Master Send the SCAN_START out

Slave

Master Send the internal AD_TRIG out

Slave Accept the SSI_AD_TRIG as the digital trigger signal.

Master Send the DAWR out.

Slave

Master Send the DA_TRIG out.

Slave Accept the SSI_DA_TRIG as the digital trigger signal.

Table 4-8: SSI Timing Signal and Functions

In PCI form factor, there is a connector on the top right corner of
the card for the SSI. Refer to section 2.3 for the connector posi­tion. All the SSI signals are routed to the 20-pin connector from the
FPGA. To synchronize multiple cards, you can connect a special
ribbon cable (ACL-SSI) to all the cards in a daisy-chain configura­tion.

Accept the SSI_TIMEBASE to replace the internal
TIMEBASE signal.

Accept the SSI_ADCONV to replace the internal
ADCONV signal.

Accept the SSI_SCAN_START to replace the internal
SCAN_START signal.

Accept the SSI_DAWR to replace the internal DAWR
signal.

The four (DAQ-/DAQe-2213) or six (DAQ-/DAQe-2214) internal
timing signals could be routed to the SSI or the PXI trigger bus
through software drivers. Refer to section 4.6 for detailed informa-

76 Operation Theory

tion on the internal timing signals. Physically, the signal routings
are accomplished in the FPGA. Cards that are connected together
through the SSI trigger bus can still achieve synchronization on
the four/six timing signals.

The SSI Mechanism

The DAQ-/DAQe-2213/2214 adopts a master-slave configura­tion for SSI. In a system, for each timing signal, there shall be
only one master while all other cards are SSI slaves or with SSI
function disabled.

For each timing signal, the SSI master does not have to be in a
single card. For example, if you want to synchronize the A/D
operation through the ADCONV signal for four DAQ-/DAQe­2213/2214 cards, Card 1 is the master while Card 2, 3, and 4
are slaves. Card 1 receives an external digital trigger to start
the post trigger mode acquisition. The SSI setting could be:

X Set the SSI_ADCONV signal of Card 1 to be the master.

X Set the SSI_ADCONV signals of Card 2, 3, and 4 to be the

slaves.

X Set the external digital trigger for Card 1’s A/D operation.

X Set the SI_counter and the post scan counter (PSC) of all

other cards.

X Start DMA operations for all cards so all the cards are wait-

ing for the trigger event.

When the digital trigger condition of Card 1 occurs, Card 1
internally generates the ADCONV signal and outputs this
ADCONV signal to the SSI_ADCONV signal of Card 2, 3 and 4
through the SSI connector. Thus we can achieve 4-channel
simultaneous acquisition.

You could arbitrarily choose each of the six/four timing signals
as the SSI master from any one of the cards. The SSI master
can output the internal timing signals to the SSI slaves. With
the SSI, you can achieve better card-to-card synchronization.

Note that when power-up or reset, the DAQ timing signals are
reset to use the internal generated timing signals.

Operation Theory 77

78 Operation Theory

5 Calibration

This chapter introduces the calibration process to minimize AD
measurement errors and DA output errors.

5.1 Loading Calibration Constants

The DAQ-/DAQe-2213/2214 card is factory-calibrated before ship­ment. The associated calibration constants of the TrimDACs firm­ware to the onboard EEPROM. TrimDACs are devices containing
multiple DACs within a single package. TrimDACs do not have
memory capability. That means the calibration constants do not
retain their values after the system power is turned off. Loading
calibration constants is the process of loading the values of Trim­DACs firmware stored in the onboard EEPROM. ADLINK provides
a software utility that automatically reads the calibration constants
automatically, if necessary.

There is a dedicated space for storing calibration constants in the
EEPROM. In addition to the default bank of factory calibration con­stants, there is one user-utilization bank. This bank allows you to
load the TrimDACs firmware values either from the original factory
calibration or from a subsequently-performed calibration.

Because of the fact that measurements and outputs errors may
vary depending on time and temperature, it is recommended that
you calibrate the card when it is integrated in your computing envi­ronment. The auto-calibration function is presented in the follow­ing sections.

Calibration 79

5.2 Auto-calibration

Through the DAQ-/DAQe-2213/2214 card auto-calibration feature,
the calibration software measures and corrects almost all calibra­tion errors without any external signal connections, reference volt­age, or measurement devices.

The DAQ-/DAQe-2213/2214 card comes with an onboard calibra­tion reference to ensure the accuracy of auto-calibration. The ref­erence voltage is measured in the production line through a digital
potentiometer and compensated in the software. The calibration
constant is memorized after this measurement. We do not recom­mended adjustment of the onboard calibration reference except
when an ultra-precision calibrator is available.

NOTES

• Warm the card up for at least 15 minutes before initiating auto-cal­ibration.

• Remove the cable before auto-calibrating the card since the DA
outputs are changed during the process.

5.3 Saving Calibration Constants

When auto-calibration is completed, you can save the new calibra­tion constants to the user-configurable banks in the EEPROM.
The date and the temperature when you ran auto-calibration is
saved with the calibration constants. You can store three sets of
calibration constants according to three different environments
and re-load the calibration constants later.

80 Calibration

Warranty Policy

Thank you for choosing ADLINK. To understand your rights and
enjoy all the after-sales services we offer, please read the follow­ing carefully.

1. Before using ADLINK’s products please read the user man­ual and follow the instructions exactly. When sending in
damaged products for repair, please attach an RMA appli­cation form which can be downloaded from: http://
rma.adlinktech.com/policy/.

2. All ADLINK products come with a limited two-year war­ranty, one year for products bought in China:

X The warranty period starts on the day the product is

shipped from ADLINK’s factory.

X Peripherals and third-party products not manufactured

by ADLINK will be covered by the original manufactur­ers' warranty.

X For products containing storage devices (hard drives,

flash cards, etc.), please back up your data before send­ing them for repair. ADLINK is not responsible for any
loss of data.

X Please ensure the use of properly licensed software with

our systems. ADLINK does not condone the use of
pirated software and will not service systems using such
software. ADLINK will not be held legally responsible for
products shipped with unlicensed software installed by
the user.

X For general repairs, please do not include peripheral

accessories. If peripherals need to be included, be cer­tain to specify which items you sent on the RMA Request
& Confirmation Form. ADLINK is not responsible for
items not listed on the RMA Request & Confirmation
Form.

Warranty Policy 81

3. Our repair service is not covered by ADLINK's guarantee
in the following situations:

X Damage caused by not following instructions in the

User's Manual.

X Damage caused by carelessness on the user's part dur-

ing product transportation.

X Damage caused by fire, earthquakes, floods, lightening,

pollution, other acts of God, and/or incorrect usage of
voltage transformers.

X Damage caused by unsuitable storage environments

(i.e. high temperatures, high humidity, or volatile chemi­cals).

X Damage caused by leakage of battery fluid during or

after change of batteries by customer/user.

X Damage from improper repair by unauthorized ADLINK

technicians.

X Products with altered and/or damaged serial numbers

are not entitled to our service.

X This warranty is not transferable or extendible.

X Other categories not protected under our warranty.

4. Customers are responsible for shipping costs to transport
damaged products to our company or sales office.

5. To ensure the speed and quality of product repair, please
download an RMA application form from our company web­site: http://rma.adlinktech.com/policy. Damaged products
with attached RMA forms receive priority.

If you have any further questions, please email our FAE staff:
[e-mail].

82 Warranty Policy