ADLINK DAQe-2006 User Manual

DAQ-/DAQe-/PXI-

2016/2010/2006/2005

4-CH, Simultaneous, High Performance

Multi-Function Data Acquisition Card

User’s Manual

Manual Rev. 2.01
Revision Date: March 12, 2007
Part No: 50-11219-2000

Advance Technologies; Automate the World.

Copyright 2007 ADLINK TECHNOLOGY INC.
All Rights Reserved.

The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, spe­cial, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.

This document contains proprietary information protected by copy­right. All rights are reserved. No part of this manual may be repro­duced by any mechanical, elec tronic, or other means in a ny form
without prior written permission of the manufacturer.

Trademarks
Product names mentioned herein are used for identification pur-

poses only and may be trademarks and/or registered trademarks
of their respective companies.

Getting service

Customer satisfaction is our top priority. Contact us should you
require any service or assistance.

ADLINK TECHNOLOGY INC.

Web Site http://www.adlinktech.com
Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address 9F No. 166 Jian Yi Road, Chungho City,

Taipei Hsien 235, Taiwan, ROC

ADLINK TECHNOLOGY AMERICA, INC.

Sales & Service [e-mail]
Toll-Free +1-866-4-ADLINK (235465)
Fax No. [phone]
Mailing Address 8900 Research Drive, Irvine,

CA 92618, USA

ADLINK TECHNOLOGY EUROPEAN SALES OFFICE

Sales & Service [e-mail]
Toll-Free [phone]
Fax No. [phone]
Mailing Address Nord Carree 3, 40477 Düsseldorf, Germany

ADLINK TECHNOLOGY SINGAPORE PTE LTD

Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address 84 Genting Lane #07-02A,

Cityneon Design Center, Singapore 349584

ADLINK TECHNOLOGY INDIA LIAISON OFFICE

Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address No. 1357, Ground Floor, "Anupama",

Aurobindo Marg JP Nagar (Ph-1)
Bangalore - 560078

ADLINK TECHNOLOGY BEIJING

Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address 4F, Kostech Building, 262-2,

Yangjae-Dong, Seocho-Gu,
Seoul, 137-130, South Korea

ADLINK TECHNOLOGY BEIJING

Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address Room 801, Building E, Yingchuangdongli

Plaza, No.1 Shangdidonglu,
Haidian District, Beijing, China

ADLINK TECHNOLOGY SHANGHAI

Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address Floor 4, Bldg. 39, Caoheting Science and

Technology Park, No.333 Qinjiang Road,
Shanghai, China

ADLINK TECHNOLOGY SHENZHEN

Sales & Service [e-mail]
Telephone No. [phone]
Fax No. [phone]
Mailing Address C Block, 2nd Floor, Building A1,

Cyber-tech Zone, Gaoxin Ave. 7.S,
High-tech Industrial Park S.,
Nanshan District, Shenzhen,
Guangdong Province, China

Using this manual

1.1 Audience and scope

This manual guides you when using ADLINK multi-function DAQ-/
DAQe-/PXI-2016/2010/2006/2005 card. The card’s hardware, sig­nal connections, and calibration information are provided for faster
application building. This manual is intended for computer pro­grammers and hardware engineers with advanced knowledge of
data acquisition and high-level programming.

1.2 How this manual is organized

This manual is organized as follows:

Chapter 1 Introduction: This chapter intoduces the DAQ-/
DAQe-/PXI-2016/2010/2006/2005 card including its features,
specifications and software support information.

Chapter 2 Installation: This chapter presents the card’s lay­out, package contents, and installation.

Chapter 3 Signal Connections: This part describes the DAQ­/DAQe-/PXI-2016/2010/2006/2005 card signal connections.

Chapter 4 Operation Theory: The operation theory of the
DAQ-/DAQe-/PXI-2016/2010/2006/2005 card functions includ­ing A/D conversion, D/A conversion, and programmable func­tion I/O are discussed in this chapter.

Chapter 5 Calibration: The chapter offers information on how
to calibrate the DAQ-/DAQe-/PXI-2016/2010/2006/2005 card
for accurate data acquisition and output.

Warranty Policy: This presents the ADLINK Warranty Policy
terms and coverages.

1.3 Conventions

Take note of the following conventions used throughout the man­ual to make sure that you perform certain tasks and instructions
properly.

NOTE Additional information, aids, and tips that help you per-

form particular tasks.

IMPORTANTCritical information and instructions that you MUST perform to

WARNING Information that prevents physical injury, data loss, mod-

complete a task.

ule damage, program corruption etc. when trying to com­plete a particular task.

Table of Contents

Table of Contents..................................................................... i

List of Tables.......................................................................... iii

List of Figures........................................................................ iv

1 Introduction ........................................................................ 1

1.1 Features............................................................................... 2

1.2 Applications ......................................................................... 3

1.3 Specifications....................................................................... 4

1.4 Software Support............................................................... 13

Programming Library .................................................. .. 13

DAQ-LVIEW PnP: LabVIEW Driver ..............................14

D2K-OCX: ActiveX Controls ................................... .... .. 14

2 Installation ........................................................................ 15

2.1 Contents of Package ......................................................... 15

2.2 Unpacking.......................................................................... 15

2.3 Card Layout............................ .......................................... . 17

DAQe-2016/2010/2006/2005 ........................................ 17

DAQ-2016/2010/2006/2005 ........................................ ..18

PXI-2016/2010/2006/2005 ............................................ 18

2.4 PCI Configuration .............................................................. 19

Plug and Play ............................................................... 19

Configuration ................................................................ 19

Troubleshooting ................................ ............................ 19

3 Signal Connections.......................................................... 21

3.1 Connectors Pin Assignment .............................................. 21

VHDCI-type (68-pin) Connector ..................... ... ............22

SSI Connector (J3) .......................................................25

3.2 Analog Input Signal Connection ........................................ 26

Types of signal sources ................. ... ... ... ... .... ... ... .........26

Single-Ended Measurements .......................................26

Differential Measurements ............................................ 27

Table of Contents i

4 Operation Theory............................................................ .. 29

4.1 A/D Conversion.................................................................. 29

DAQ-/DAQe-/PXI-2010 AI Data Format .......................30

DAQ/DAQe/PXI-2005/2006/2016 AI Data Format ........33

Software Conversion with Polling Data Transfer Acqui-sition

Mode (Software Polling) .................................... .34

Programmable Scan Acquisition Mode .........................35

Trigger Modes ...............................................................37

4.2 D/A Conversion.................................................................. 47

Software Update ...........................................................48

Timed Waveform Generation ........................................49

Trigger Modes ...............................................................51

4.3 Digital I/O........................................................................... 57

4.4 General Purpose Timer/Counter Operation....................... 57

Timer/Counter functions basics ....................................57

General Purpose Timer/Counter modes ................... ... .58

4.5 Trigger Sources ................................................................. 63

Software-Trigger ........................................................... 63

External Analog Trigger ................................................63

4.6 User-controllable Timing Signals....................................... 68

DAQ timing signals .......................................................69

Auxiliary Function Inputs (AFI) ......................................70

System Synchronization Interface ................................72

AI_Trig_Out and AO_Trig_Out ................................. ... .75

5 Calibration......................................................................... 77

5.1 Loading Calibration Constants........................................... 77

5.2 Auto-calibration.................................................................. 78

5.3 Saving Calibration Constants............................................. 78

Warranty Policy ..................................................................... 79

ii Table of Contents

List of Tables

Table 1-1: -3dB Small Signal Bandwidth ................................... 5

Table 1-2: System Noise ........................................................... 5

Table 1-3: CMRR: (DC to 60 Hz) ............................................... 7

Table 3-1: VHDCI-type (68-pin) Connector Pin Assignment ... 22

Table 3-2: VHDCI-type (68-pin) Connector Legend ................ 23

Table 3-3: SSI Connector (JP3) Pin Assignment for

DAQ Models ........................................................... 25

Table 3-4: SSI Connector Legend ........................................... 25

Table 4-1: Bipolar Analog Input Range and

Output Digital Code on DAQ/DAQe/PXI-2010 ........ 31

Table 4-2: Unipolar Analog Input Range and

Output Digital Code on DAQ/DAQe/PXI-2010 ........ 32

Table 4-3: Bipolar Analog Input Range and

Output Digital Code for

DAQ/DAQe/PXI-2005/2006/2016 ........................... 33

Table 4-4: Unipolar Analog Input Range and

Output Digital Code for

DAQ/DAQe/PXI-2005/2006/2016 ........................... 33

Table 4-5: Bipolar Output Code Table ..................................... 47

Table 4-6: Unipolar Output Code Table ................................... 48

Table 4-7: Analog Trigger SRC1 (EXTATRIG)

Ideal Transfer Characteristic .................................. 64

Table 4-8: User-controllable Timing Signals and

Functionalities .................................... ................ ..... 69

Table 4-9: Auxiliary Function Input Signals and

Functionalities .................................... ................ ..... 70

Table 4-10: SSI Timing Signals Functionalities ......................... 73

List of Tables iii

List of Figures

Figure 2-1: DAQe-2016/2010/2006/2005 Card Layout.............. 17

Figure 2-2: DAQ-2016/2010/2006/2005 Card Layout................ 18

Figure 2-3: PXI-2016/2010/2006/2005 Card Layout.................. 18

Figure 3-1: Single-Ended Connections ...................................... 27

Figure 3-2: Ground-referenced Source and Differential Input.... 27

Figure 3-3: Floating Source and Differential Input ..................... 28

Figure 4-1: Synchronous Digital Inputs Block Diagram.............. 30

Figure 4-2: Synchronous Digital Inputs Timing .......................... 30

Figure 4-3: Scan Timing............................................................. 36

Figure 4-4: Pre-trigger................................................................ 38

Figure 4-5: Pre-trigger Scan Acquisition .................... ... .... ... ... ... 38

Figure 4-6: Pre-trigger with M_enable=0 ................................... 39

Figure 4-7: Pre-trigger with M_enable=1 ................................... 40

Figure 4-8: Middle-Trigger with M_enable = 1 ........................... 41

Figure 4-9: Middle-Trigger.......................................................... 41

Figure 4-10: Post trigger .............................................................. 42

Figure 4-11: Delay trigger ............................................................ 43

Figure 4-12: Post trigger with re-trigger ....................................... 44

Figure 4-13: Scatter/gather DMA for data transfer....................... 46

Figure 4-14: Typical D/A Timing of Waveform Generation .......... 50

Figure 4-15: Post Trigger Waveform Generation......................... 51

Figure 4-16: Delay Trigger Waveform Generation....................... 52

Figure 4-17: Re-triggered Waveform Generation......................... 52

Figure 4-18: Finite Iterative Waveform Generation with

Post-trigger and DLY2_Counter = 0 ........................ 53

Figure 4-19: Infinite Iterative Waveform Generation with

Post-trigger and DLY2_Counter = 0 ........................ 54

Figure 4-20: Stop Mode I ............................................................. 55

Figure 4-21: Stop Mode II ............................................................ 56

Figure 4-22: Stop Mode III ........................................................... 56

Figure 4-23: Mode 1 Operation.................................................... 58

Figure 4-24: Mode 2 Operation.................................................... 59

Figure 4-25: Mode 3 Operation.................................................... 60

Figure 4-26: Mode 4 Operation.................................................... 60

Figure 4-27: Mode 5 Operation.................................................... 61

Figure 4-28: Mode 6 Operation.................................................... 61

Figure 4-29: Mode 7 Operation.................................................... 62

Figure 4-30: Mode 8 Operation.................................................... 62

iv List of Figures

Figure 4-31: Analog Trigger Block Diagram................................. 64

Figure 4-32: Below-Low Analog Trigger Condition ...................... 65

Figure 4-33: Above-High Analog Trigger Condition..................... 65

Figure 4-34: Inside-Region Analog Trigger Condition.... ... ... ... ..... 66

Figure 4-35: High-Hysteresis Analog Trigger Condition .............. 66

Figure 4-36: Low-Hysteresis Analog Trigger Condition ............... 67

Figure 4-37: External Digital Trigger............................................ 67

Figure 4-38: DAQ signals routing................................................. 68

List of Figures v

1 Introduction

The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card is an advanced
data acquisition card based on the 32-bit PCI or PCI Express
architecture. High performance designs and state-of-the-art tech­nology make these cards ideal for data logging and signal analysis
applications in medical, process control, etc.

®

Introduction 1

1.1 Features

The DAQ-/DAQe-/PXI-2016/2010/2006/2005 advanced data
acquisition card has the following features:

X 32-bit PCI bus (DAQ/PXI models) or PCI Express (DAQe

model), plug and play

X 4-channel simultaneous differential analog input:

Z DAQ-/DAQe-/PXI-2010: 14-bit Analog input resolution

with sampling rate up to 2 MS/s

Z DAQ-/DAQe-/PXI-2005: 16-bit Analog input resolution

with sampling rate up to 500 KS/s

Z DAQ-/DAQe-/PXI-2006: 16-bit Analog input resolution

with sampling rate up to 250 KS/s

Z DAQ-/DAQe-/PXI-2016: 16-bit Analog input resolution

with sampling rate up to 800 kS/s

X Programmable bipolar/unipolar an al og input
X Programmable gain (x1, x2, x4, x8 for all DAQ-20XX)
X A/D FIFO

Z DAQ-/DAQe-/PXI-2010: Total 8 K samples
Z DAQ-/DAQe-/PXI-2005/2006/2016: Total 512 samples

X Versatile trigger sources: software trigger, external digital

trigger, analog trigger and trigger from System Synchroniza­tion Interface (SSI).

X A/D Data transfer: software polling & bus-mastering DMA

with Scatter/Gather functionality

X Four A/D trigger modes: post-trigger, delay-trigger, pre-trig-

ger and middle-trigger

X Two-channel DA outputs with waveform generation capabil-

ity

X 2 K samples output data FIFO for DA channels
X DA Data transfer: software update and bus-mastering DMA

with Scatter/Gather functionality

X System Synchronization Interface (SSI)
X Full A/D/DA auto-calibration
X Completely jumper-less and software- co nf igu ra ble

2Introduction

1.2 Applications

X Automotive Testing
X Cable Testing
X Transient signal measurement
X ATE
X Laboratory Automation
X Biotech measurement

Introduction 3

1.3 Specifications

Analog Input (AI)

X Number of channels: 4 differential
X A/D converter:

Z DAQ-/DAQe-/PXI-2010: LTC1414 or equivalent
Z DAQ-/DAQe-/PXI-2005: A/D7665 or equivalent
Z DAQ-/DAQe-/PXI-2006: A/D7663 or equivalent
Z DAQ-/DAQe-/PXI-2016: A/D7671 or equivalent

X Max sampling rate:

Z DAQ-/DAQe-/PXI-2010: 2MS/s
Z DAQ-/DAQe-/PXI-2016: 800kS/s
Z DAQ-/DAQe-/PXI-2005: 500kS/s
Z DAQ-/DAQe-/PXI-2006: 250kS/s

X Resolution:

Z DAQ-/DAQe-/PXI-2010: 14 bits, no missing code
Z DAQ-/DAQe-/PXI-2005/2006/2016: 16 bits, no missing

code

X FIFO buffer size:

Z DAQ-/DAQe-/PXI-2010: 8K samples
Z DAQ-/DAQe-/PXI-2005/2006/2016: 512 samples

X Programmable input range:

Z Bipolar: ±10V, ±5V, ±2.5V, ±1.25V

Z Unipolar: 0~10V, 0~5V, 0~2.5V, 0~1.25V
X Operational common mode voltage range: ±11V
X Overvoltage protection:

Z Power on: continuous ±30V

Z Power off: continuous ±15V
X Input impedance: 1GΩ/100pF

4Introduction

X -3dB small signal bandwidth: (Typical, 25°C)

Device Input Range Bandwidth (-3dB) Input Range Bandwidth (-3dB)

±10V 1170 kHz 0~10V 1090 kHz

2010

±5V 1050 kHz 0~5V 1020 kHz

±2.5V 800 kHz 0~2.5V 790 kHz

±1.25V 530 kHz 0~1.25V 530 kHz

±10V 1160 kHz 0~10V 1210 kHz

2005

±5V 1050 kHz 0~5V 1050 kHz

±2.5V 780 kHz 0~2.5V 770 kHz

±1.25V 520 kHz 0~1.25V 530 kHz

±10V 630 kHz 0~10V 640 kHz

2006

±5V 620 kHz 0~5V 620 kHz

±2.5V 540 kHz 0~2.5V 540 kHz

±1.25V 410 kHz 0~1.25V 420 kHz

±10V 840kHz 0~10V 900kHz

2016

±5V 825kHz 0~5V 800kHz

±2.5V 710kHz 0~2.5V 690kHz

±1.25V 530kHz 0~1.25V 530kHz

Table 1-1: -3dB Small Signal Bandwidth

X Large signal bandwidth (1% THD): 300 kHz

X System Noise: (Typical)

Device Input Range System noise Input Range System noise

±10V 0.6 LSBrms 0~10V 0.8 LSBrms

2010

±5V 0.6 LSBrms 0~5V 0.8 LSBrms

±2.5V 0.6 LSBrms 0~2.5V 0.9 LSBrms

±1.25V 0.6 LSBrms 0~1.25V 0.9 LSBrms

±10V 1.2 LSBrms 0~10V 1.9 LSBrms

2005

±5V 1.2 LSBrms 0~5V 2.0 LSBrms

±2.5V 1.3 LSBrms 0~2.5V 2.1 LSBrms

±1.25V 1.3 LSBrms 0~1.25V 2.2 LSBrms

Table 1-2: System Noise

Introduction 5

Device Input Range System noise Input Range System noise

±10V 1.0 LSBrms 0~10V 1.5 LSBrms

2006

2016

±5V 1.0 LSBrms 0~5V 1.6 LSBrms

±2.5V 1.1 LSBrms 0~2.5V 1.7 LSBrms

±1.25V 1.1 LSBrms 0~1.25V 1.8 LSBrms

±10V 1.6 LSBrms 0~10V 2.9 LSBrms

±5V 1.8 LSBrms 0~5V 3.2 LSBrms

±2.5V 1.8 LSBrms 0~2.5V 3.2 LSBrms

±1.25V 1.9 LSBrms 0~1.25V 3.4 LSBrms

Table 1-2: System Noise

6Introduction

X CMRR: (DC to 60 Hz, Typical)

Device Input Range CMRR Input Range CMRR

±10V 90 dB 0~10V 89 dB

2010

±5V 92 dB 0~5V 92 dB

±2.5V 95 dB 0~2.5V 94 dB

±1.25V 97 dB 0~1.25V 97 dB

±10V 86 dB 0~10V 85 dB

2005

±5V 88 dB 0~5V 88 dB

±2.5V 91 dB 0~2.5V 90 dB

±1.25V 93 dB 0~1.25V 93 dB

±10V 87 dB 0~10V 86 dB

2006

±5V 89 dB 0~5V 88 dB

±2.5V 91 dB 0~2.5V 91 dB

±1.25V 93 dB 0~1.25V 93 dB

±10V 85dB 0~10V 86dB

2016

±5V 88dB 0~5V 88dB

±2.5V 91dB 0~2.5V 92dB

±1.25V 95dB 0~1.25V 95dB

Table 1-3: CMRR: (DC to 60 Hz)

X Time-base source:

Z Internal 40MHz or External clock Input (fmax: 40 MHz,

fmin: 1 MHz, 50% duty cycle)

X Trigger modes:

Z Post-trigger, Delay-trigger, Pre-trigger and Mid dle-trigger

X Data transfers:

Z Programmed I/O, and bus-mastering DMA with scatter/

gather

X Input coupling: DC

X Offset error:

Z Before calibration: ±60mV max
Z After calibration: ±1mV max

Introduction 7

X Gain error:

Z Before calibration: ±0.6% of output max

Z After calibration: ±0.1% of output max for DAQ-/DAQe-/

PXI-2010, ±0.03% of output max for DAQ-/DAQe-/PXI­2005/2006/2016

8Introduction

Analog Output (AO)

X Number of channels: Two-channel voltage output

X DA converter: LTC7545 or equivalent

X Max update rate: 1 MS/s

X Resolution: 12 bits

X FIFO buffer size:

Z 1k samples per channel when both channels are

enabled for timed DA output

Z 2k samples when only one channel is used for timed DA

output

X Data transfers:

Z Programmed I/O
Z Bus-mastering DMA with scatter/gather

X Output range:

Z Bipolar: ±10V or ±AOEXTREF

Z Unipolar: 0~10V or 0~AOEXTREF
X Settling time: 3μS to 0.5 LSB accuracy
X Slew rate: 20V/μS
X Output coupling: DC
X Protection: Short-circuit to ground
X Output impedance: 0.3Ω typical
X Output driving current: ±5mA max.
X Stability: Any passive load, up to 1500pF
X Power-on state: 0V steady-state
X Power-on glitch: ±1.5V/500uS
X Relative accuracy:

Z ±0.5 LSB typical, ±1 LSB max
X DNL:

Z ±0.5 LSB typical, ±1.2 LSB max
X Offset error:

Z Before calibration: ±80mV max

Z After calibration: ±1mV max

Introduction 9

X Gain error:

Z Before calibration: ±0.8% of output max
Z After calibration: ±0.02% of output max

X General Purpose Digital I/O (G.P. DIO, 82C55A)
X Number of channels: 24 programmable input/output
X Compatibility: TTL/CMOS
X Input voltage:

Z Logic Low: VIL=0.8V max; IIL=0.2mA max
Z High: VIH=2.0V max; IIH=0.02mA max

X Output voltage:

Z Low: VOL=0.5V max; IOL=8mA max
Z High: VOH=2.7V min; IOH=400 μA

X Synchronous Digital Inputs (SDI, for DAQ-/DAQe-/PXI-2010

only)

X Number of channels: 8 digital inputs sampled simulta-

neously with the analog signal input

X Compatibility: TTL/CMOS
X Input voltage:

Z Logic Low: VIL=0.8V max; IIL=0.2mA max
Z Logic High: VIH=2.7V min; IIL=0.02mA max

General Purpose Timer/Counter (GPTC)

X Number of channel: 2 up/down timer/counters
X Resolution: 16 bits
X Compatibility: TTL
X Clock source: Internal or external
X Max source frequency: 10 MHz

10 Introduction

Analog Trigger (A.Trig)

X Source:

Z All analog input channels

Z External analog trigger (EXTATRIG)
X Level: ±Full-scale, internal; ±10 V external
X Resolution: 8 bits
X Slope: Positive or negative (software-selectable)
X Hysteresis: Programmable
X Bandwidth: 400 kHz

External Analog Trigger Input (EXTATRIG)

X Input Impedance:

Z 40 kΩ for DAQ-/DAQe-/PXI-2010

Z 2 kΩ for DAQ-/DAQe-/PXI-2005/2006/2016
X Coupling: DC
X Protection: Continuous ±35 V maximum

Digital Trigger (D.Trig)

X Compatibility: TTL/CMOS
X Response: Rising or falling edge
X Pulse Width: 10 ns min

System Synchronous Interface (SSI)

X Trigger lines: 7

Stability

X Recommended warm-up time: 15 minutes
X On-board calibration reference:

Z Level: 5.000 V

Z Temperature coefficient: ±2 ppm/°C

Z Long-term stability: 6 ppm/1000 Hr

Introduction 11

Physical

X Dimensions:

Z 175mm by 107mm for DAQ-/DAQe-2010/2000
Z Standard CompactPCI form factor for PXI-2010/2000

X I/O connector: 68-pin female VHDCI type (e.g. AMP-

787254-1)

Power Requirement (typical)

X +5VDC

Z 1.82 A for DAQ-/PXI-2010
Z 2.04 A for DAQ-/PXI-2005
Z 1.82 A for DAQ-/PXI-2006
Z 2.52 A for DAQ-/PXI-2016

X +12 VDC

Z 550 mA for DAQe-2005
Z 460 mA for DAQe-2006
Z 448 mA for DAQe-2010
Z 569 mA for DAQe-2016

X +3.3 VDC

Z 1.02 A for DAQe-2005
Z 1.02 A for DAQe-2005
Z 1.25 A for DAQ2-2010

Operating Environment

X Ambient temperature: 0°C to 55°C
X Relative humidity: 10% to 90% non-condensing

Storage Environment

X Ambient temperature: -20°C to 80°C
X Relative humidity: 5% to 95% non-condensing

Interface Connector

X 68-pin AMP-787254-1 or equivalent

12 Introduction

1.4 Software Support

ADLINK provides versatile software drivers and packages for
users’ different approach to building up a system. ADLINK not only
provides pro-gramming libraries such as DLL for most Windows­based systems, but also provide drivers for other software pack­ages such as LabVIEW

All software options are included in the ADLINK CD. Non-free soft­ware drivers are protected with licensing codes. Without the soft­ware code, you can install and run the demo version for two hours
for trial/demonstration purposes. Please contact ADLINK dealers
to purchase the formal license.

Programming Library

For customers who are writing their own programs, we provide
function libraries for many different operating systems, including:

X D2K-DASK: Include device drivers and DLL for Windows

98/NT/2000/XP. DLL is binary compatible across Windows

98/NT/2000/XP. This means all applications developed with

D2K-DASK are compatible across Windows 98/NT/2000/

XP. The developing environment can be VB, VC++, Delphi,

BC5, or any Windows programming language that allows

calls to a DLL. The user’s guide and function reference

manual of D2K-DASK are in the CD. (\\Manual\Software

Package\D2K-DASK)

X D2K-DASK/X: Include device drivers and shared library for

Linux. The developing environment can be Gnu C/C++ or

any programming language that allows linking to a shared

library. The user's guide and function reference manual of

D2K-DASK/X are in the CD. (\\Manual\Software Pack-

age\D2K-DASK-X.)

®

.

®

Introduction 13

DAQ-LVIEW PnP: LabVIEW Driver

DAQ-LVIEW PnP contains the VIs, which are used to interface
with NI’s LabVIEW software package. The DAQ-LVIEW PnP sup­ports Windows 98/NT/2000/XP. The LabVIEW drivers is shipped
free with the card. You can install and use them without a license.
For detailed information about DAQ-LVIEW PnP, refer to the
user’s guide in the CD. (\\Manual\Software Package\DAQ-LVIEW
PnP)

D2K-OCX: ActiveX Controls

Customers who are familiar with ActiveX controls and VB/VC++
programming are suggested to use D2K-OCX ActiveX control
component libraries for developing applications. D2K-OCX is
designed for Windows 98/NT/2000/XP. For more details on D2K­OCX, refer to the user's guide in the CD. (\\Manual\Software Pack­age\D2K-OCX)

The above software drivers are shipped with the card. Refer to the
Software Installation Guide in the package to install these drivers.

In addition, ADLINK supplies ActiveX control software DAQBench.
DAQBench is a collection of ActiveX controls for measurement or
automation applications. With DAQBench, you can easily develop
custom user interfaces to display your data, analyze data you
acquired or received from other sources, or integrate with popular
applications or other data sources. For more detailed information
about DAQBench, refer to the user's guide in the CD. (\\Man­ual\Software Package\DAQBench Evaluation)

You can also get a free 4-hour evaluation version of DAQBench
from the CD. DAQBench is not free. Contact ADLINK or your
dealer to purchase the software license.

14 Introduction

2 Installation

This chapter describes how to install the DAQ-/DAQe-/PXI-2016/
2010/2006/2005 card. The contents of the package and unpa cking
information that you should be aware of are outlined first.

The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card performs an
automatic configuration of the IRQ and port address. You can use
the PCI_SCAN software utility to read the system configuration.

2.1 Contents of Package

In addition to this User's Manual, the package includes the follow­ing items:

X DAQ-/DAQe-/PXI-2016/2010/2006/2005 multi-function data

acquisition card

X ADLINK All-in-one CD
X Software Installation Guide

If any of these items are missing or damaged, contact the dealer
from whom you purchased the product. Save the shipping materi­als and carton in case you want to ship or store the product in the
future.

2.2 Unpacking

Your DAQ-/DAQe-/PXI-2016/2010/2006/2005 card contains elec­tro-static sensitive components that can be easily be damaged by
static electricity.

Therefore, the card should be handled on a grounded anti-static
mat. The operator should be wearing an anti-static wristband,
grounded at the same point as the anti-static mat.

Inspect the card package for obvious damages. Shipping and han­dling may cause damage to the card. Be sure there are no ship­ping and handling damages on the modules carton before
continuing.

After opening the card module carton, extract the system module
and place it only on a grounded anti-static surface with component
side up.

Installation 15

Again, inspect the module for damages. Press down on all the
socketed IC's to make sure that they are properly seated. Do this
only with the module place on a firm flat surface.

You are now ready to install your DAQ-/DAQe-/PXI-2016/2010/
2006/2005 card.

NOTE DO NOT APPLY POWER TO THE CARD IF IT HAS

BEEN DAMAGED.

16 Installation

2.3 Card Layout

DAQe-2016/2010/2006/2005

Figure 2-1: DAQe-2016/2010/2006/2005 Card Layout

Installation 17

DAQ-2016/2010/2006/2005

Figure 2-2: DAQ-2016/2010/2006/2005 Card Layout

PXI-2016/2010/2006/2005

Figure 2-3: PXI-2016/2010/2006/2005 Card Layout

18 Installation

2.4 PCI Configuration

Plug and Play

With support for plug and play, the card requ ests an interru pt num­ber via its PCI controller. The system BIOS responds with an inter­rupt assignment based on the card information and on known
system parameters. These system parameters are determined by
the installed drivers and the hardware load seen by the system.

Configuration

The board configuration is done on a board-by-board basis for all
PCI boards in the system. Because configuration is controlled by
the system and software, th ere is no jumper setting required for
base address, DMA, and interrupt IRQ.

The configuration is subject to change with every boot of the sys­tem as new boards are added or removed.

Troubleshooting

If your system doesn’t boot or if you experience erratic operation
with your PCI board in place, it is likely caused by an interrupt con­flict. The BIOS Setup may be incorrectly configured. Consult the
BIOS documentation that comes with your system to solve this
problem.

Installation 19

20 Installation

3 Signal Connections

This chapter describes DAQ-/DAQe-/PXI-2016/2010/2006/2005
card connectors and the signal connection between the DAQ-/
DAQe-/PXI-2016/2010/2006/2005 card and external devices.

3.1 Connectors Pin Assignment

The DAQe-/PXI-2016/2010/2006/2005 card is equipped with one
68-pin VHDCI-type connector (AMP-787254-1). It is used for digi­tal input/output, analog input/output, timer/counter signals, etc.
One 20-pin ribbon male connector is used for SSI (System Syn­chronous Interface) in DAQ-2016/2010/2006/2005 card. The pin
assignments of the connectors are defined in Table 3-1 and
Table 3-2.

Signal Connections 21

VHDCI-type (68-pin) Connector

CH0+ 1 35 CH0­CH1+ 2 36 CH1­CH2+ 3 37 CH2­CH3+ 4 38 CH3-

EXTATRIG 5 39 AIGND

DA1OUT 6 40 AOGND
DA0OUT 7 41 AOGND

AOEXTREF 8 42 AOGND

SDI3_1 / NC* 9 43 SDI3_0 / NC*

SDI2_1 / NC* 10 44 SDI2_0 / NC*
SDI1_1 / NC* 11 45 SDI1_0 / NC*
SDI0_1 / NC* 12 46 SDI0_0 / NC*

AO_TRIG_OUT 13 47 EXTWFTRG

AI_TRIG_OUT 14 48 EXTDTRIG

GPTC1_SRC1549 DGND
GPTC0_SRC1650 DGND

GPTC0_GATE1751 GPTC1_GATE

GPTC0_OUT1852 GPTC1_OUT

GPTC0_UPDOWN 19 53 GPTC1_UPDOWN

EXTTIMEBASE 20 54 DGND

Table 3-1: VHDCI-type (68-pin) Connector Pin Assignment

AFI1 21 55 AFI0

PB7 22 56 PB6
PB5 23 57 PB4
PB3 24 58 PB2
PB1 25 59 PB0
PC72660 PC6
PC52761 PC4

DGND 28 62 DGND

PC32963 PC2
PC13064 PC0
PA7 31 65 PA6
PA5 32 66 PA4
PA3 33 67 PA2
PA1 34 68 PA0

*SDI for DAQ/DAQe/PXI-2010 only. NC for DAQ/DAQe/PXI-2005/

22 Signal Connections

Legend:

Pin # Signal Name Reference Direction Description

Differential positive

1~4 CH<0..3>+ CH0<0..3>- Input

5 EXTATRIG AIGND Input
6 DA0OUT AOGND Output AO channel 0

7 DA1OUT AOGND Output AO channel 1
8 AOEXTREF AOGND Input

9~12

13 AO_TRIG_OUT DGND Output AO trigger signal

14 AI_TRIG_OUT DGND Output AI trigger signal
15,16 GPTC<0,1>_SRC DGND Input
17,51 GPTC<0,1>_GATE DGND Input Gate of GPTC<0,1>
18,52 GPTC<0,1>_OUT DGND Input

19,53 GPTC<0,1>_UPDOWN DGND Input

20 EXTTIMEBASE DGND Input External TIMEBASE

21,28,49,

50,54,62

22,56,23,
57,24,58,

25,59

26,60,27,
61,29,63,

30,64

31,65,32,
66,33,67,

34,68

SDI<3..0>_1 (2010)

NC (2005/2006/2016)

DGND -------- -------- Digital ground

PB<7,0> DGND PIO*

PC<7,0> DGND PIO*

PA<7,0> DGND PIO*

Table 3-2: VHDCI-type (68-pin) Connector Legend

DGND Input

input for AI channel

<0..3>

External AI analog

trigger

External reference for

AO channels

Synchronous digital

inputs

Source of

GPTC<0,1>

Output of

GPTC<0,1>
Up/Down of

GPTC<0,1>

Programmable DIO

pins of 8255 Port B

Programmable DIO

pins of 8255 Port C

Programmable DIO

pins of 8255 Port A

Signal Connections 23

Pin # Signal Name Reference Direction Description

Differential negative

35~38 CH<0..3>- -------- Input

39 AIGND -------- -------- Analog ground for AI

40~42 AOGND -------- -------- Analog ground for AO
43~46

47 EXTWFTRIG DGND Input

trigger

48 EXTDTRIG DGND Input

55 AFI0 DGND Input

21 AFI1 DGND Input

SDI<3..0>_0 (2010)

NC (2005/2006/2016)

Table 3-2: VHDCI-type (68-pin) Connector Legend

DGND Input

input for AI channel

<0..3>

Synchronous digital

inputs

External AO wave-

form

External AI digital

trigger

Auxiliary Function

Input 0 (ADCONV,

AD_START)

Auxiliary Function

Input 1 (DAWR,

DA_START)

*PIO means programmable I/O

24 Signal Connections

SSI Connector (J3)

SSI_TIMEBASE 1 2 DGND

SSI_ADCONV 3 4 DGND

SSI_DAWR 5 6 DGND

SSI_SCAN_START 7 8 DGND

RESERVED 9 10 DGND
SSI_AD_TRIG 11 12 DGND
SSI_DA_TRIG 13 14 DGND

RESERVED 15 16 DGND

RESERVED 17 18 DGND

RESERVED 19 20 DGND

Table 3-3: SSI Connector (JP3) Pin Assignment for DAQ Models

Legend:

SSI timing signal Functionality

SSI master: send the TIMEBASE out

SSI_TIMEBASE

SSI_ADCONV

SSI_SCAN_START

SSI_AD_TRIG

SSI_DAWR

SSI_DA_TRIG

Table 3-4: SSI Connector Legend

SSI slave: accept the SSI_TIMEBASE to

replace the internal TIMEBASE signal.

SSI master: send the ADCONV out

SSI slave: accept the SSI_ADCONV to

replace the internal ADCONV signal.

SSI master: send the SCAN_START out

SSI slave: accept the SSI_SCAN_START to

replace the internal SCAN_START signal.

SSI master: send the internal AD_TRIG out
SSI slave: accept the SSI_AD_TRIG as the

digital trigger signal.

SSI master: send the DAWR out.

SSI slave: accept the SSI_DAWR t o replace

the internal DAWR signal.

SSI master: send the DA_TRIG out.

SSI slave: accept the SSI_DA_TRIG as the

digital trigger signal.

Signal Connections 25

3.2 Analog Input Signal Connection

The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card provides 4 dif­ferential analog input channels. The analog signal can be con­verted to digital values by the A/D converter. To avoid ground
loops and get more accurate measurements from the A/D conver­sion, it is quite important to understand the signal source type and
how to connect the analog input signals.

Types of signal sources

Ground-Referenced Signal Sources

A ground-referenced signal means it is connected in some way
to the building system. That is, the signal source is already
connected to a common ground point with respect to the DAQ­/DAQe-/PXI-2016/2010/2006/2005 card, assuming that the
computer is plugged into the same power system. Non-isolated
out-puts of instruments and devices that plug into the buildings
power system are ground-referenced signal sources.

Floating Signal Sources

A floating signal source means it is not connected in any way to
the buildings ground system. A device with an isolated output is
a floating signal source, such as optical isolator outputs, trans­former outputs, and thermocouples.

Single-Ended Measurements

For single-ended connection, the analog input signal is referenced
to the common ground of the system. In this case, all the negative
ends of analog input channels should be connected to the AIGND
on the connector in-stead of floating. Refer to Figure 3-1.

26 Signal Connections

Figure 3-1: Single-Ended Connections

In single-ended configurations, more electrostatic and magnetic
noise couples into the single connections than in differential con­figurations. Therefore, the single-ended connection is not recom­mended unless minimal wire connections are necessary.

Differential Measurements

Differential Connection for Grounded-Reference Signal
Sources

The differential analog input provides two inputs that respond
to the signal voltage difference between them. If the signal
source is ground-referenced, the differential mode can be used
for the common-mode noise rejection. Figure 3-2 shows the
connection of ground-referenced signal sources under the dif­ferential input mode.

Figure 3-2: Ground-referenced Source and Differential Input

Signal Connections 27

Differential Connection for Floating Signal Sources

Figure 3-3 shows how to connect a floating signal source to
DAQ-/DAQe-/PXI-2016/2010/2006/2005 card in differential
input mode. For floating signal sources, you need to add a
resistor at each channel to provide a bias return path. The
resistor value should be about 100 times the equivalent source
impedance. If the source impedance is less than 100 ohms,
you can simply connect the negative side of the signal to
AGND as well as the negative input of the Instrumentation
Amplifier, without any resistors a t all. I n diff er e ntia l in p ut m od e ,
less noise couples into the signal connections than in single­ended mode.

Figure 3-3: Floating Source and Differential Input

28 Signal Connections

4 Operation Theory

The operation theory of the DAQ-/DAQe-/PXI-2016/2010/2006/
2005 card functions are described in this chapter. The functions
include the A/D conversion, D/A conversion, digital I/O, and gen­eral purpose counter/timer. The operation theory can help you
understand how to configure and program the DAQ-/DAQe-/PXI­2016/2010/2006/2005 card.

The whole DAQ/DAQe/PXI card series, including the DAQ-/DAQe­/PXI-2010/2000 Series, DAQ/DAQe/PXI-2200 Series, and DAQ/
DAQe/PXI-2500 Series, are designed based on the same logic­timing template of DAQ/DAQe/PXI-22XX. In the DAQ/PXI-22XX
cards, all the A/D related timings are for multiplexing A/D sampling
based on scanning, so that DAQ-/DAQe-/PXI-2016/2010/2006/
2005 card also adopts the same concept, except there is only one
conversion signal in a scan which could generate up to four sam­ples from the four different channels at the same time. In the fol­lowing description, to conform to the original timing design, we still
use scan as the unit of A/D data acquisition. All the DA and GPTC
functions are the same in DAQ-/DAQe-/PXI-2016/2010/2006/2005
card and DAQ/DAQe/PXI-2200 Series, while DAQ/DAQe/PXI­2500 Series provides improved DA timing compared to the two
earlier series.

4.1 A/D Conversion

When using an A/D converter, you must know about the properties
of the signal to be measured. You may decide which channel to
use and how to connect the signals to the card. Refer to section

3.4. In addition, users should define and control the A/D signal
configurations, including channels, gains, and polarities (unipolar/
bipolar).

The A/D acquisition is initiated by a trigger source and you must
decide how to trigger the A/D conversion. The data acquisition will
start once a trigger condition is matched.

After the end of an A/D conversion, the A/D data is buffered in a
Data FIFO. The A/D data can now be transferred into the system
memory for further processing.

Operation Theory 29

DAQ-/DAQe-/PXI-2010 AI Data Format

Synchronous Digital Inputs (DAQ-/DAQe-/PXI-2010 only)

When each A/D conversion is completed, the 14-bits converted
digital data accompanied with 2 bits of SDI<1..0>_X per chan­nel from J5 will be latched into the 16-bit register and data
FIFO as shown in Figure 4-1 and Figure 4-2. Therefore, you
can simultaneously sample one analog signal with four digital
signals. The data format of every acquired 16-bit data is as fol­lows:

D13, D12, D11 ....... D1, D0, b1, b0

Where

D13, D12, D11 ....... D1, D0: 2’s complement A/D

14-bit data

b1, b0: Synchronous Digital Inputs SDI<1..0>

Figure 4-1: Synchronous Digital Inputs Block Diagram

Figure 4-2: Synchronous Digital Inputs Timing

30 Operation Theory

NOTE Since the analog signal is sampled when an A/D conver-

sion starts (falling edge of A/D_conversion signal), while
SDI<1..0> are sam-pled right after an A/D conversion
completes (rising edge of nADBUSY signal). Precisely
SDI<1..0> are sampled within 220 to 400ns lag to the an­alog signal, due to the variation of the conversion time of
the A/D converters.

Table 4-1and Table 4-2 illustrate the ideal transfer characteristics
of various input ranges of DAQ/DAQe/PXI-2000/2010 Series card.
The converted digital codes for DAQ/DAQe/PXI-2010 are 14-bit
and 2’s complement, and here we present the codes as hexadeci­mal numbers. Note that the last 2 bits of the transferred data,
which are the synchronous digital input (SDI), should be ignored
when retrieving the analog data, and that the last two digital codes
are SDI<1..0>)

Description Bipolar Analog Input Range Digital code

Full-scale Range ±10V ±5V ±2.5V ±1.25V

Least significant bit 1.22mV 0.61mV 0.305mV 0.153mV

FSR-1LSB 9.9988V 4.9994V 2.4997V 1.2499V 1FFF

Midscale +1LSB 1.22mV 0.61mV 0.305mV 0.153mV 0001

Midscale 0V 0V 0V 0V 0000

Midscale –1LSB -1.22mV -0.61mV -0.305mV -0.153mV 3FFF

-FSR -10V -5V -2.5V -1.25V 2000

Table 4-1: Bipolar Analog Input Range and Output Digital Code on DAQ/

DAQe/PXI-2010

Operation Theory 31

Description Unipolar Analog Input Range Digital code

Full-scale Range 0V to 10V 0 to +5V 0 to +2.5V 0 to +1.25V

Least significant bit 0.61mV 0.305mV 0.153mV 76.3uV

FSR-1LSB 9.9994V 4.9997V 2.9999V 1.2499V 1FFF

Midscale +1LSB 5.00061V 2.50031V 1.25015V 625.08mV 0001

Midscale 5V 2.5V 1.25V 625mV 0000

Midscale –1LSB 4.99939V 2.49970V 1.24985V 624.92mV 3FFF

-FSR 0V 0V 0V 0V 2000

Table 4-2: Unipolar Analog Input Range and Output Digital Code on DAQ/

DAQe/PXI-2010

32 Operation Theory

DAQ/DAQe/PXI-2005/2006/2016 AI Data Format

The data format of the acquired 16-bit A/D data is binary coding.
Table 4-3 and Table 4-4 illustrate the valid input ranges and the
ideal transfer characteristics. The converted digital codes for DAQ/
DAQe/PXI-2005/2006/2016 are 16-bit and direct binary, and here
the codes were presented as hexadecimal numbers.

Description Bipolar Analog Input Range Digital code

Full-scale Range ± 10V ±5V ±2.5V ±1.25V

Least significant bit 305.2uV 152.6uV 76.3uV 38.15uV

FSR-1LSB 9.999695V 4.999847V 2.499924V 1.249962V FFFF

Midscale +1LSB 305.2uV 152.6uV 76.3uV 38.15uV 8001

Midscale 0V 0V 0V 0V 8000

Midscale -1LSB -305.2uV -152.6uV -76.3uV -38.15uV 7FFF

-FSR -10V -5V -2.5V -1.25V 0000

Table 4-3: Bipolar Analog Input Range and Output Digital Code for DAQ/DAQe/

PXI-2005/2006/2016

Description Unipolar Analog Input Range Digital code

Full-scale Range 0V to 10V 0 to +5V 0 to +2.5V 0 to +1.25V

Least signifi-cant bit 152.6uV 76.3uV 38.15uV 19.07uV

FSR-1LSB 9.999847V 4.999924V 2.499962V 1.249981V FFFF

Midscale +1LSB 5.000153V 2.500076V 1.250038V 0.625019V 8001

Midscale 5V 2.5V 1.25V 0.625V 8000

Midscale -1LSB 4.999847V 2.499924V 1.249962V 0.624981V 7FFF

-FSR 0V 0V 0V 0V 0000

Table 4-4: Unipolar Analog Input Range and Output Digital Code for DAQ/DAQe/

PXI-2005/2006/2016

Operation Theory 33

Software Conversion with Polling Data Transfer Acqui­sition Mode (Software Polling)

This is the easiest way to acquire a single A/D data. The A/D con­verter starts one conversion whenever the dedicated software
command is executed. Then the software would poll the conver­sion status and read the A/D data back when it is available.

This method is very suitable for applications that needs to process
A/D data in real time. Under this mode, the timing of the A/D con­version is fully controlled by the software. However, it is difficult to
control the A/D conversion rate.

Specifying Channel, Gain, and Polarity

In both the Software Polling and programmable scan acquisi­tion mode, the channel, gain, and polarity for each channel can
be specified and selected. With this configuration, signal
sources must be connected to the right connector as the speci­fied settings.

When the specified channels have been sampled from the first
to the last data, the settings applied to each channel would be
the same until next change.

Example:

Typically you can set the input configuration for different chan­nels:

Ch1 with unipolar ±10V
Ch2 with bipolar ±2.5V
Ch3 with no signal input (disabled)
Ch4 with bipolar ±1.25V

34 Operation Theory

Programmable Scan Acquisition Mode

Scan Timing and Procedure

It's recommended that this mode be used if your applications
need a fixed and precise A/D sampling rate. You can accu­rately program the period between conversions of individual
channels. There are at least two counters which need to be
specified:

SI_counter (24 bit):Specify the Scan Interval =

SI_counter / TIMEBASE

PSC_counter (24 bit):Specify Post Scan Counts,

i.e. the total sample count after a trigger
event,

The acquisition timing and the mea nings of the 2 counters ar e
illustrated in Figure 4-3. The SCAN_START signal is derived
from the SI_counter, which will lead to the A/D conversion sig­nal generation. Note that the DAQ-/DAQe-/PXI-2016/2010/
2006/2005 card is a simultaneous sampling A/D card, so the
scan interval equals the sampling interval.

Example: Post-trigger acquisition

Set

SI_counter = 160
PSC_counter = 30
TIMEBASE = Internal clock source

Then
Scan Interval = 160/40M s = 4 us
Total acquisition time = 30 X 4 us = 120 us

TIMEBASE Clock Source

In scan acquisition mode, all the A/D conversions start on the
output of counters, which use TIMEBASE as the clock source.
By software you can specify the TIMEBASE to be either an
internal clock source (onboard 40 MHz clock) or an external
clock input (EXTTIMEBASE) on J5 connector (68-pin VHDCI).
The external TIMEBASE is useful when you want to acquire
data at rates not available wit h the internal A/D sample clock.
The external clock source should generate TTL-compatible
continuous clocks and with a maximum frequency of 40 MHz

Operation Theory 35

while the minimum should be 1 MHz. Refer to sectio n 4.6 for
information on user-controllable timing signals.

Figure 4-3: Scan Timing

There are four trigger modes to start the scan acquisition. Refer to
section 4.1 for details. The data transfer mode is discussed in the
following section.

NOTES The maximum A/D sampling rate is 2 MHz for DAQ/

DAQe/PXI-2010, 500 kHz for DAQ/DAQe/PXI-2005, 250
kHz for DAQ/DAQe/PXI-2006 and 800 kHz for DAQ/
DAQe/PXI-2016. Therefore, the minimum setting of
SI_counter is 20 for DAQ/DAQe/PXI-2010, 80 for DAQ/
DAQe/PXI-2005, 160 for DAQ/DAQe/PXI-2006 and 50
for DAQ/DAQe/PXI-2016 while using the internal TIME­BASE.

The SI_counter is a 24-bit counter. Therefore, the maxi­mum scan interval while using an internal TIMEBASE =
224/40 Ms = 0.419 s.

36 Operation Theory

Trigger Modes

The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card provides four
trigger sources (internal software trigger, external analog trigger,
external digital trigger, and SSI trigger signals). You must select
one of them as the source of the trigger event. A trigger event
occurs when the specified condition is detected on the selected
trigger source. For example, a ris ing edge on the external digital
trigger input. Refer to section 4.6 for more information on SSI sig­nals.

There are four trigger modes (pre-trigger, post-trigger, middle-trig­ger, and delay-trigger) working with the four trigger sources to ini­tiate different scan data acquisition timing when a trigger event
occurs. They are described in the following sections. For informa­tion on trigger sources, refer to section 4.5.

Pre-Trigger Acquisition

Use pre-trigger acquisition in applications where you want to
collect data before a trigger event. The A/D starts to sample
when you execute the specifie d function calls to begin the pre­trigger operation, and it stops when the trigger event occurs.
Users must program the value M in M_counter (16 bits) to
specify the amount of the stored scans before the trigger event.
If an external trigger occurs, the program only stores the last M
scans of data converted before the trigger event, as illustrated
in Figure 4-4, where M_counter = M =3, PSC_counter = 0. The
post scan count is 0 because there is no sampling after the trig­ger event in pre-trigger acquisition. The total stored amount of
data = Number of enabled channels * M_counter.

Operation Theory 37

Figure 4-4: Pre-trigger

Note that If the trigger event occurs when a conversion is in
progress, the data acquisition will not stop until this conversion is
completed and the stored M scans of data include the last scan,
as illustrated in Figure 4-5, where M_counter = M = 3,
PSC_counter = 0.

Figure 4-5: Pre-trigger Scan Acquisition

38 Operation Theory

When the trigger signal occurs before the first M scans of data are
converted, the amount of stored data could be fewer than the or ig­inally specified amount M_counter, as illustrated in Figure 4-6.
This situation can be avoided by setting M_enable. If M_enable is
set to 1, the trigger signal will be ignored until the first M scans of
data are converted, and it assures the user M scans of data under
pre-trigger mode, as illustrated in Figure 4-7. However, if
M_enable is set to 0, the trigger signal will be accepted any time,
as shown in Figure 4-6. Note that the total amount of stored data
will always be equal to the number in the M_counter because data
acquisition does not stop until a scan is completed.

Figure 4-6: Pre-trigger with M_enable=0

Operation Theory 39

Figure 4-7: Pre-trigger with M_enable=1

NOTE The PSC_counter is set to 0 in pre-trigger acquisition

mode.

Middle-Trigger Acquisition

Use middle-trigger acquisition in applications where you want
to collect data before and after a trigger event. The number of
scans (M) stored before the trigger is specified in M_counter,
while the number of scans (N) after the trigger is specified in
PSC_counter.

Like pre-trigger mode, the number of stored data could be less
than the specified amount of data (M+N), if an external trigger
occurs before M scans of data are converted. The M_ enable bit
in middle-trigger mode takes the same e ffect as in pre-trigger
mode. If M_enable is set to 1, the trigger signal will be ignored
until the first M scans of data are converted, and it assures the
user with (M+N) scans of data under middle-trigger mode.
However, if M_enable is set to 0, the trigger signal will be
accepted at any time. Figur e 4-8 shows the acquisition tim ing
with M_enable=1.

40 Operation Theory

Figure 4-8: Middle-Trigger with M_enable = 1

If the trigger event occurs when a scan is in progress, the stored N
scans of data would include this scan, as illustrated in Figure 4-9.

Figure 4-9: Middle-Trigger

Operation Theory 41

NOTE The M_counter defined in Middle-Trigger is different from

that of the Pre-Trigger. In Middle-Trigger, M_Counter
ends counting before the trigger event while in Pre-Trig­ger, M_Counter ends counting right at or before trigger
event. Refer to Figure 4-6 and Figure 4-9.

Post-Trigger Acquisition
Use post-trigger acquisition in applications where you want to col-

lect data after a trigger event. The number of scans after the trig­ger is specified in PSC_counter, as illustrated in Figure 4-10. The
total acquired data length = number of enable-channel *
PSC_counter.

Figure 4-10: Post trigger

42 Operation Theory

Delay Trigger Acquisition

Use delay trigger acquisition in applications where you wa nt to
delay the data collection after the occurrence of a specified trig­ger event. The delay time is controlled by the value, which is
pre-loaded in the Delay_counter (16-bit). The counter counts
down on the rising edge of the Delay_counter clock source
after the trigger condition is met. The clock source can be soft­ware-programmed either by the TIMEBASE clock (40 MHz) or
A/D sampling clock (TIMEBASE / SI_counter). When the count
reaches 0, the counter stops and the card starts to acquire
data. The total acquired data length = number of enable-chan­nel * PSC_counter.

Figure 4-11: Delay trigger

NOTE When the Delay_counter clock source is set to TIME-

BASE, the maximum delay time = 216/40M s = 1.638ms,
and the source is set to A/D sampling clock, the maxi­mum delay time may be higher than 216 * SI_counter /
40M.

Operation Theory 43

Post-Trigger or Delay-trigger Acquisition with re-trigger

Use post-trigger or delay-trigger acquisition with re-trigger
function in applications where you want to collect data after
several trigger events. The number of scans after each trigger
is specified in PSC_counter, and users could program
Retrig_no to specify the re-trigger numbers. Figure 4-12 illus­trates an example. In this example, two scans of data is
acquired after the first trigger signal, then the card waits for the
re-trigger signal (re-trigger signals which occur before the first
two scans is completed will be ignored). When the re-trigger
signal occurs, two more scans are performed. The process
repeats until specified amount of re-trigger signals are
detected. The total acquired data length = number of enable­channel * PSC_counter * Re-trig_no.

Figure 4-12: Post trigger with re-trigger

44 Operation Theory

Bus-mastering DMA Data Transfer

PCI bus-mastering DMA is necessary for high speed DAQ in
order to utilize the maximum PCI bandwidth. The bus-master­ing controller, which is built in the PLX IOP-480 PCI controller,
controls the PCI bus when it becomes the master of the bus.
Bus mastering reduces the size of the on-board memory and
reduces the CPU loading because data is directly transferred
to the computer’s memory without host CPU intervention.

Bus-mastering DMA provides the fastest data transfer rate on
PCI-bus. Once the analog input operation starts, control
returns to your program. The hardware temporarily stores the
acquired data in the onboard AD Data FIFO and then transfers
the data to a user-defined DMA buffer memory in the computer.
Note that even when the acquired data length is less than the
Data FIFO, the AD data is not kept in the Data FIFO but directly
transferred into host memory by the bus-mastering DMA.

The DMA transfer mode is complicated to program. We recom­mend using a high-level program library to configure this card.
If users would like to know more about software programs that
can handle the DMA bus master data transfer, visit to http://
www.plxtech.com for more information on PCI controllers.

By using a high-level programming library for high speed DMA
data acquisition, you simply need to assign the sampling period
and the number of conversion into your specified counters.
After the AD trigger condition is matched, the data is trans­ferred to the system memory by the bus-mastering DMA.

The PCI controller also supports th e function of scatter/gather
bus mastering DMA, which helps you transfer large amounts of
data by linking all the memory blocks into a continuous linked
list.

In a multi-user or multi-tasking OS, like Windows, Linux, etc, it
is difficult to allocate a large continuous memory block to do the
DMA transfer. Therefore, the PLX IOP-480 provides the func­tion of scatter/gather or chaining mode DMA to link the non­continuous memory blocks into a linked list so that you can
transfer very large amounts of data without being limited by the
fragment of small size memory. You can configure the linked

Operation Theory 45

list for the input DMA channel or the output DMA channel.
Figure 4-13 shows a linked list that is constructed by three
DMA descriptors. Each descriptor contains a PCI address, a
local address, a transfer size, and the pointer to the next
descriptor. You can allocate many small size memory blocks
and chain their associative DMA descriptors altogether by their
application programs. The DAQ-/DAQe-/PXI-2016/2010/2006/
2005 card software driver provides simple settings for the scat­ter/gather function, including some sample programs in the
ADLINK All-in-One CD.

Figure 4-13: Scatter/gather DMA for data transfer

In non-chaining mode, the maximu m DMA data transfer size is 2
M double words (8M bytes). However, by using chaining mode,
scatter/gather, there is no limitation on the DMA data transfer size.
You can also link the descriptor nodes circularly to achieve a multi­buffered mode DMA.

46 Operation Theory

4.2 D/A Conversion

There are two 12-bit D/A output channels available in the DAQ-/
DAQe-/PXI-2016/2010/2006/2005 card. When using D/A convert­ers, you should assign and control the D/A converter reference
sources for the D/A operation mode and D/A channels. You could
also set the output polarity to unipolar or bipolar.

The reference selection control lets you utilize in full the multiply­ing characteristics of the D/A converters. Internal 10V reference
and external reference inputs are available in the DAQ-/DAQe-/
PXI-2016/2010/2006/2005 card. The range of the D/A output is
directly related to the reference. The digital codes that are updated
to the D/A converters will multiply with the reference to generate
the analog output. While using internal 10V reference, the full
range would be –10V to +9.9951V in the bipolar output mode, and
0V to 9.9976V in the unipolar output mode. While using an exter­nal reference, you can reach different output ranges by connecting
different references. For example, if connecting a DC –5V with the
external reference, then you can get a full range from –4.9976V to
+5V in the bipolar output with inverting characteristics due to the
negative reference voltage. You could also have an amplitude
modulated (AM) output by feeding a sinusoidal signal into the ref­erence input. The range of the external reference should be within
±10V. Table 4-5 and 4-6 illustrates the relationship between digital
code and output voltages

selected

.

with Vref=10V and if internal reference is

Digital Code Analog Output

111111111111 Vref * (2047/2048)
100000000001 Vref * (1/2048)
100000000000 0V
011111111111 -Vref * (1/2048)
000000000000 -Vref

Table 4-5: Bipolar Output Code Table

Operation Theory 47

Digital Code Analog Output

111111111111 Vref * (4095/4096)
100000000000 Vref * (2048/4096)
000000000001 Vref * (1/4096)
000000000000 0V

Table 4-6: Unipolar Output Code Table

The D/A conversion is initiated by a trigger source. You must
decide how to trigger the D/A conversion. The data output will start
when a trigger condition is met. Before the start of D/A conversion,
D/A data is transferred from the computer’s main memory to a
buffering Data FIFO.

There are two modes of the D/A conversion: Software Update and
Timed Waveform Generation. These are described below, includ­ing the timing, trigger source control, trigger modes, and data
transfer methods. Either mode may be applied to D/A channels
independently. You can software update DA CH0 while generating
timed waveforms on CH1 at the same time.

Software Update

This is the easiest way to generate D/A output. To do this:

1. Specify the D/A output channels.

2. Set output polarity (unipolar or bipolar) and reference
source (internal 10V or external AOEXTREF).

3. Update the digital values into D/A data registers through
a software output command.

48 Operation Theory

Timed Waveform Generation

This mode can provide your applications with a precise D/A output
with a fixed update rate. It can be used to generate an infinite or
finite waveform. You can accurately program the update period of
the D/A converters.

The D/A output timing is provided through a combination of
counters in the FPGA on board. There are a total of five counters
to be specified. These counters include:

X UI_counter (24 bits): specify the DA Update Interval =

CHUI_counter/TIMEBASE

X UC_counter (24 bits): specify the total Update Counts in a

single waveform

X IC_counter (24 bits): specify the Iteration Counts of wave-

form

X DA_DLY1_counter (16 bits): specify the Delay from the trig-

ger to the first update start

X DA_DLY2_counter (16 bits): specify the Delay between two

consecutive waveform generations

Figure 4-14 shows a typical D/A timing diagram assuming the data
in the data buffer are 2V, 4V, -4V, 0V. D/A updates its output on
each rising edge of DAWR. The meaning of the counters enumer­ated above are discussed in the following sections.

Operation Theory 49

Figure 4-14: Typical D/A Timing of Waveform Generation

NOTE The maximum D/A update rate is 1 MHz. Therefore, the

minimum setting of the UI_counter is 40 while using an in­ternal TIMEBASE (40 MHz).

50 Operation Theory

Trigger Modes

Post-Trigger Generation

Use post-trigger when you want to perform DA waveform right
after a trigger event occurs. In this trigger mode DLY1_Counter is
ignored and not be specified. Figure 4-15 shows a single wave­form generated right after a trigger signal is detected assuming the
data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, and 4V.
The trigger signal could come from a software command, an ana­log trigger or a digital trigger. Refer to section 4.5 for detailed infor­mation.

Figure 4-15: Post Trigger Waveform Generation

Delay-Trigger Generation

Use delay trigger when you want to delay the waveform genera­tion after a trigger event. In Table 4-16, DA_DLY1_counter deter­mines the delay time from the trigger signal to the start of the
waveform generation, assuming the data in the data buffer are 2V,
4V, 6V, 3V, 0V, -4V, -2V, and 4V. DLY1_counter counts down on
the rising edge of its clock source after the trigger condition i s met.
When the count reaches 0, the counter stops and the DAQ-/
DAQe-/PXI-2016/2010/2006/2005 card starts the waveform gen­eration. This DLY1_Counter is 16-bit wide and you can set the
delay time in units of TIMEBASE (delay time = DLY1_Counter/
TIMEBASE) or in units of update period (delay time =

Operation Theory 51

DLY1_Counter * UI_counter/TIMEBASE), so the delay time can
reach a wider range.

Figure 4-16: Delay Trigger Waveform Generation

Post-Trigger or Delay-Trigger with Re-trigger

Use post-trigger or delay-trigger with re-trigger function when
you want to generate waveform after more than one trigger
events. The re-trigger function can be enabled or disabled by
software setting. In Figure 4-17, each trigger signal will initiate
a waveform generation assuming the data in the data buffer
are 2V, 4V, 2V, and 0V. However, the trigger event would be
ignored while the waveform generation is ongoing.

Figure 4-17: Re-triggered Waveform Generation

52 Operation Theory

Iterative Waveform Generation

Set IC_Counter in order to generate iterative waveforms from
the data of a single waveform. Th e counter stores the iteration
number and the iterations may be finite (Figure 4-18) or infinite
(Figure 4-19). Both figures assume that the data in the data
buffer are 2V, 4V, 2V, and 0V.

A data FIFO on board is used to buffer the digital data for DA
output. If the data size of a single waveform you specified (That
is, Update Counts in UC_counter) is less than the FIFO size,
after initially transferring the data from the host PC memory to
the FIFO on board, the data in the FIFO will be automatically
re-transmitted whenever a single waveform is completed.
Therefore, it won’t occupy the PCI bandwidth when repetitive
waveforms are performed. However, if the size of a single
waveform were larger than that of the FIFO, it needs to be
intermittently loaded from the host PC’s memory via DMA,
when a repetitive waveforms is performed thus PCI bandwidth
would be occupied.

The data FIFO size on DAQ/DAQe/PXI-2010 is 2k samples
and 512 samples on DAQ/DAQe/PXI-2005/2006/2016.

Figure 4-18: Finite Iterative Waveform Generation with Post-trigger and

DLY2_Counter = 0

Operation Theory 53

Figure 4-19: Infinite Iterative Waveform Generation with Post-trigger and

DLY2_Counter = 0

NOTES When running infinite iterative waveform generation, set-

ting IC_Counter is ineffective to the waveform genera­tion. It only makes a difference when setting Stop mode
III. Refer to Figure 4-22.

Setting finite and infinite iterative waveform gene ration is
not discussed in this manual. Refer to software documen­tation for related information.

Delay2 in Repetitive Waveform Generation

To diversify the D/A waveform generation, we add a DLY2
Counter to separate two consecutive waveforms in repetitive
waveform generation. The time between two waveforms is set
by the value of DLY2 Counter. The Delay2 counter starts to
count down after a waveform generation finishes and the next
waveform generation starts right after it counts down to zero,
as shown in Figure 4-20. This DLY2_Counter is 16-bit wide
and you may set the delay time in units of TIMEBASE (delay
time = DLY2_Counter/TIMEBASE) or in units of update period
(delay time = DLY2_Counter * UI_counter/TIMEBASE), so the
delay time can reach a wider range.

54 Operation Theory

Stop Modes of Scan Update

You can call software stop function to stop waveform genera­tion when it is still in progress. Three stop modes are provided
for timed waveform generation meant to stop the waveform
generation. You can apply these three modes to stop wave­form generation no matter infinite or finite waveform generation
mode is selected.

Figure 4-20 illustrates an example for stop mode I, assuming
the data in the data buffer are 2V, 4V, 2V, and 0V. In this
mode, the waveform stops immediately when software com­mand is asserted.

In stop mode II, after a software stop command is given, the
waveform generation does not stop until a complete single
waveform is finished. See Figure 4-21. Since the UC_counter
is set to four, the total DA update counts (number of pulses of
DAWR signal) must be a multiple of four (update counts = 20 in
this example).

In stop mode III, after a software stop command is given, the
waveform generation does not stop until the performed number
of waveforms is a multiple of the IC_Counter. See Figure 4-22.
Since the IC_Counter is set to three, the total generated wave­forms must be a multiple of three (waveforms = 6 in this exam­ple), and the total DA update counts must be a multiple of 12
(UC_counter * IC_Counter). You can compare th ese three fig­ures to see the differences.

Figure 4-20: Stop Mode I

Operation Theory 55

Figure 4-21: Stop Mode II

Figure 4-22: Stop Mode III

56 Operation Theory

4.3 Digital I/O

The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card contains 24
lines of general-purpose digital I/O (GPIO) which is provided
through the 82C55A chip.

The 24-line GPIO are separated into three ports: Port A, Port B
and Port C. High nibble (bit[7…4]), and low nibble (bit[3…0]) of
each port can be programmed individually to be either inputs or
outputs. Upon system startup or reset, all the GPIO pins are reset
to high impedance inputs.

The DAQ/DAQe/PXI-2010 also provides two digital inputs per
channel (SDI from J5), which are sampled simultaneously with an
analog signal input and is stored with the 14-bit AD data. Refer to
Figure 4.1 for the more details.

4.4 General Purpose Timer/Counter Operation

Two independent 16-bit up/down timer/counter are designed
within FPGA for various applications. They have the following fea­tures:

X Count up/down controlled by hardware or software
X Programmable counter clock source (internal or external

clock up to 10 MHz)

X Programmable gate selection (hardware or software con-

trol)

X Programmable input and output signal polarities (high active

or low active)

X Initial count can be loaded from software
X Current count value can be read-back by software without

affecting circuit operation

Timer/Counter functions basics

Each timer/counter has three inputs that can be controlled via
hardware or software. They are clock input (GPTC_CLK), gate
input (GPTC_GATE), and up/down control input
(GPTC_UPDOWN). The GPTC_CLK input provides a clock
source input to the timer/counter. Active edges on the GPTC_CLK
input make the counter increment or decrement. The

Operation Theory 57

GPTC_UPDOWN input controls whether the counter counts up or
down. The GPTC_GATE input is a control signal which acts as a
counter enable or a counter trigger signal under different applica­tions.

The output of timer/counter is GPTC_OUT. After power-up,
GPTC_OUT is pulled high by a pulled-up resister about 10K
ohms. Then GPTC_OUT goes low after the DAQ-/DAQe-/PXI­2016/2010/2006/2005 card is initialized.

All the polarities of input/output signals can be programmed by
software. In this chapter, for easy explanation, all GPTC_CLK,
GPTC_GATE, and GPTC_OUT are assumed to be active high or
rising-edge triggered in the figures.

General Purpose Timer/Counter modes

Eight programmable timer/co un te r mo d es ar e pr ov ide d. All m od e s
start operating following a softw are-start signal that is set by the
software. The GPTC software reset initializes the status of the
counter and re-loads the initial value to the counter. The operation
remains halted until the software-start is re-executed. The operat­ing theories under different modes are described as below.

Mode 1: Simple Gated-Event Counting

In this mode, the counter counts the number of pulses on the
GPTC_CLK after the software-sta rt. In itial count ca n be load ed
from software. Current count valu e can be read-back by soft­ware any time without affectin g the counting. GPTC_GATE is
used to enable/disable counting. When GP TC_GATE is inac­tive, the counter halts the current count value. Figure 4-23 illus­trates the operation with initial count = 5, countdown mode.

Figure 4-23: Mode 1 Operation

58 Operation Theory

Mode 2: Single Period Measurement

In this mode, the counter counts the period of the signal on
GPTC_GATE in terms of GPTC_CLK. Initial count can be
loaded from software. After the software-start, the counter
counts the number of active edges on GPTC_CLK between
two active edges of GPTC_GATE. After the completion of the
period interval on GPTC_GATE, GPTC_OUT outputs high and
then current count value can be read-back by software.
Figure 4-24 illustrates the operation where initial count = 0,
count-up mode.

Figure 4-24: Mode 2 Operation

Mode 3: Single Pulse-width Measurement

In this mode, the counter counts the pulse-width of the signal
on GPTC_GATE in terms of GPTC_CLK. Initial count can be
loaded from software. After the software-start, the counter
counts the number of active edges on GPTC_CLK when
GPTC_GATE is in its active state. After the completion of the
pulse-width interval on GPTC_GATE, GPTC_OUT outputs
high, then current count value can be read-back by software.
Figure 4-25 illustrates the operation where initial count = 0,
count-up mode.

Operation Theory 59

Figure 4-25: Mode 3 Operation

Mode 4: Single Gated Pulse Generation

This mode generates a single pulse with programmable delay
and programmable pulse-width following the software-start.
The two programmable parameters could be specified in terms
of periods of the GPTC_CLK input by software. GPTC_GATE
is used to enable/disable counting. When GPTC_GATE is inac­tive, the counter halts the current count value. Figure 4-26 illus­trates the generation of a single pulse with a pulse delay of two
and a pulse-width of four.

Figure 4-26: Mode 4 Operation

60 Operation Theory

Mode 5: Single Triggered Pulse Generation

This function generates a single pulse with programmable
delay and pro-grammable pulse-width following an active
GPTC_GATE edge. You could specify these programmable
parameters in terms of periods of th e GPTC_CLK input. Once
the first GPTC_GATE edge triggers the single pulse,
GPTC_GATE takes no effect until the software-start is re-exe­cuted. Figure 4-27 illustrates the generation of a single pulse
with a pulse delay of two and a pulse-width of four.

Figure 4-27: Mode 5 Operation

Mode 6: Re-triggered Single Pulse Generation

This mode is similar to Mode 5 except that the counter gener­ates a pulse following every active edge of GPTC_GATE. After
the software-start, every active GPTC_GATE edge triggers a
single pulse with programmable delay and pulse-width. Any
GPTC_GATE triggers that occur when the prior pulse is not
completed would be ignored. Figure 4-28 illustrates the gener­ation of two pulses with a pulse delay of two and a pulse-width
of four.

Figure 4-28: Mode 6 Operation

Operation Theory 61

Mode 7: Single Triggered Continuous Pulse Generation

This mode is similar to Mode 5 except that the counter gener­ates continuous periodic pulses with pro grammable pu lse inter­val and pulse-width following the first active edge of
GPTC_GATE. Once the first GPTC_GATE edge triggers the
counter, GPTC_GATE takes no effect until the software-start is
re-executed. Figure 4-29 illustrates the generation of two
pulses with a pulse delay of four and a pulse-width of three.

Figure 4-29: Mode 7 Operation

Mode 8: Continuous Gated Pulse Generation

This mode generates periodic pulses with programmable pulse
interval and pulse-width following the software-start.
GPTC_GATE is used to enable/disable counting. When
GPTC_GATE is inactive, the counter halts the current count
value. Figure 4-30 illustrates the generation of two pulses with
a pulse delay of four and a pulse-width of three.

Figure 4-30: Mode 8 Operation

62 Operation Theory

4.5 Trigger Sources

ADLINK provides flexible trigger selections in the DAQ-/DAQe-/
PXI-2010/2000 Series products. In addition to the internal soft­ware trigger, the DAQ-/DAQe-/PXI-2016/2010/2006/2005 card
also supports external analog, digital triggers, and SSI triggers.
You can configure the trigger source by software for A/D and D/A
processes individually. Note that the A/D and the D/A conversion
share the same analog trigger.

Software-Trigger

This trigger mode does not need any external trigger source. The
trigger asserts right after you execute the specified function calls
to begin the operation. A/D and D/A processes can receive an
individual software trigger.

External Analog Trigger

The analog trigger circuitry routing is shown in the Figure 4-31.
The analog multiplexer can select either a direct analog input from
the EXTATRIG pin (SRC1 in Figure 4-31) in the 68-pin connector
or the input signal of ADC (SRC2 in Figure 4-31). That is, one of
the four channel inputs you can select as a trigger source. Both
trigger sources can be used for all trigger modes. The range of
trigger level for SRC1 is ±10V and the resolution is 78mV (refer to
Table 4-6), while the trigger range of SRC2 is the full-scale range
of the selected channel input and the resolution is the desired
range divided by 256. For example, if the channel input selected to
be the trigger source is set bipolar and ±5V range, the trigger volt­age would be 4.96V when the trigger level code is set to 0xFF
while 0V when the code is set to 0x80.

Operation Theory 63

Figure 4-31: Analog Trigger Block Diagram

Trigger level digital setting Trigger voltage

0xFF 9.92V
0xFE 9.84V

--- --­0x81 0.08V
0x80 0
0x7F -0.08V

--- --­0x01 -9.92V

Table 4-7: Analog Trigger SRC1 (EXTATRIG) Ideal Transfer Characteristic

The trigger signal is generated when the analog trigger condition
is satisfied. There are five analog trigger conditions in the DAQ-/
DAQe-/PXI-2016/2010/2006/2005 card. The DAQ-/DAQe-/PXI­2016/2010/2006/2005 card uses two threshold voltages,
Low_Threshold and High_Threshold to build the five different trig­ger conditions. You could configure the trigger con ditions easily by
software.

64 Operation Theory

Below-Low Analog Trigger Condition

Figure 4-32 shows the below-low analog trigger condition, the
trigger signal is generated when the input analog signal is less
than the Low_Threshold voltage, and the High_Threshold set­ting is not used in this trigger condition.

Figure 4-32: Below-Low Analog Trigger Condition

Above-High Analog Trigger Condition

Figure 4-33 shows the above-high analog trigger condition, the
trigger signal is generated when the input analog signal is
higher than the High_Threshold voltage, and the
Low_Threshold setting is not used in this trigger condition.

Figure 4-33: Above-High Analog Trigger Condit ion

Inside-Region analog trigger condition

Figure 4-34 shows the inside-region analog trigger condition,
the trigger signal is generated when the input analog signal
level falls in the range between the High_Threshold and the
Low_Threshold voltages.

Operation Theory 65

NOTE The High_Threshold setting should be always higher

than the Low_Threshold voltage setting.

Figure 4-34: Inside-Region Analog Trigger Condition

High-Hysteresis analog trigger condition

Figure 4-35 shows the high-hysteresis analog trigger condition,
the trigger signal is generated when the input analog signal
level is greater than the High_Threshold voltage, and the
Low_Threshold voltage determines the hysteresis duration.
Note the High_Threshold setting should be alway s higher then
the Low_Threshold voltage setting.

Figure 4-35: High-Hysteresis Analog Trigger Condition

66 Operation Theory

Low-Hysteresis analog trigger condition

Figure 4-36 shows the low-hysteresis analog trigger con dition,
the trigger signal is generated when the input analog signal
level is less than the Low_Threshold voltage, and the
High_Threshold voltage determines the hysteresis duration.
Note the High_Threshold setting should be always higher then
the Low_Threshold voltage setting.

Figure 4-36: Low-Hysteresis Analog Trigger Condition

External Digital Trigger

An external digital trigger occurs when a rising edge or a falling
edge is detected on the digital signal connected to the EXT­DTRIG or the EXTWFTRG of the 68-pin connector for external
digital trigger. The EXTDTRIG is dedicated for A/D process,
and the EXTWFTRG is used for D/A process. You can program
the trigger polarity using the software drivers. Note that the sig­nal level of the external digital trigger signals should be TTL­compatible and the minimum pulse is 20 ns.

Figure 4-37: External Digital Trigger

Operation Theory 67

4.6 User-controllable Timing Signals

In order to meet the requirements for user-specific timing and
requirements for synchronizing multiple cards, the DAQ-/DAQe-/
PXI-2016/2010/2006/2005 card provides flexible user-controllable
timing signals to connect to external circuitry or additional cards.

The whole DAQ timing of the DAQ-/DAQe-/PXI-2016/2010/2006/
2005 card is composed of a bunch of counters and trigger signals
in the FPGA. These timing signals are related to the A/D, D/A con­versions, and Timer/Counter applications. These timing signals
can be input to or output from the I/O connectors, SSI connector,
and the PXI bus. Therefore, the internal timing signals can be
used to control external devices or circuitry. Note that in other
models of DAQ-/DAQe-/PXI-2016/2010/2006/2005 card, the user­controllable timing signals may vary. However, the SSI/PXI timing
signals remain the same for every DAQ-/DAQe-/PXI-2016/2010/
2006/2005 card.

We implemented signal multiplexers in the FPGA to individually
choose the desired timing signals for the DAQ operations, as
shown in the Figure 4-38

Figure 4-38: DAQ signals routing

You can utilize the flexible timing signals through our software
drivers, then simply and correctly connect the signals with the
DAQ-/DAQe-/PXI-2016/2010/2006/2005 cards. Here is the sum­mary of the DAQ timing signals and the corresponding functional­ities for DAQ-/DAQe-/PXI-2016/2010/2006/2005 card.

68 Operation Theory

Timing signal category Corresponding functionality

SSI/PXI signals Multiple cards synchronization

AFI signals Control DAQ-2000 by external timing signals

AI_Trig_Out,

AO_Trig_Out

Table 4-8: User-controllable Timing Signals and Functionalities

Control external circuitry or boards

DAQ timing signals

The user-controllable internal timing-signals contain (refer to sec­tion 4.1 for the internal timing signal definition) :

1. TIMEBASE, providing TIMEBASE for all DAQ opera­tions, which could be from internal 40 MHz oscillator,
EXTTIMEBASE from I/O connector or the
SSI_TIMEBASE. Note that the frequency range of the
EXTTIMEBASE is 1 MHz to 40 MHz, and the EXTTIME­BASE should be TTL-compatible.

2. AD_TRIG, the trigger signal for the A/D operation, which
could come from external digit al trigger, analog trigger,
internal software trigger, and SSI_AD_TRIG. Refer to
section 4.5 for detailed description.

3. SCAN_START, the signal to start a scan, which would
bring the following ADCONV signals for AD conversion,
and could come from the internal SI_counter, AFI[0] and
SSI_AD_START. This signal is synchronous to the
TIMEBASE. Note that the AFI[0] should be TTL-compat­ible and the minimum pulse width should be the pulse
width of the TIMEBASE to guarantee correct functional­ities.

4. ADCONV, the conversion signal to initiate a single con­version, which could be derived from internal counter,
AFI[0] or SSI_ADCONV. Note that this signal is edge­sensitive. When using AFI[0] as the external ADCONV
source, each rising edge of AFI[0] would bring an effec­tive conversion signal. Also note that the AFI[0] signal

Operation Theory 69

should be TTL-compatible and the minimum pulse width
is 20 ns.

5. DA_TRIG, the trigger signal for the D/A operation, which
could be derived from external digital trigger, analog trig­ger, internal software trigger, and SSI_AD_TRIG. Refer
to section 4.5 for detailed description.

6. DAWR, the update signal to initiate a single D/A conver­sion, which could be derived from internal counter,
AFI[1] or SSI_DAWR. Note that this signal is edge-sensi­tive. When using AFI[1] as the external DAWR source,
each rising edge of AFI[1] would bring an effective
update signal. Also note that the AFI[1] signal should be
TTL-compatible and the minimum pulse width is 20 ns.

Auxiliary Function Inputs (AFI)

You can use the AFI in applications that take advantage of exter­nal circuitry to directly control the DAQ-/DAQe-/PXI-2016/2010/
2006/2005 card. The AFI includes two catego ries of timing signals:
one group is the dedicated input, and the other is the multi-func­tion input. Table 4-9 illustrates this categorization.

Category Timing signal Functionality Constraints

Replace the

EXTTIMEBASE

Dedi­cated

input

Table 4-9: Auxiliary Function Input Sig nals and Functionalities

EXTDTRIG

EXTWFTRG

internal TIME-

BASE

External digital

trigger input for

A/D operation

External digital

trigger input for

D/A operation

1. TTL-compatible

2. 1MHz to 40MHz

3. Affects on both A/D and D/A
operations

1. TTL-compatible

2. Minimum pulse width = 20ns

3. Rising edge or falling edge

1. TTL-compatible

2. Minimum pulse width = 20ns

3. Rising edge or falling edge

70 Operation Theory

Category Timing signal Functionality Constraints

Replace the

internal

AFI[0]

Multi-

function

input

(Dual functions)

AFI[1]

Table 4-9: Auxiliary Function Input Signals and Functionalities

ADCONV

Replace the

internal

SCAN_START

Replace the

internal DAWR

1. TTL-compatible

2. Minimum pulse width = 20ns

3. Rising–edge sensitive only

1. TTL-compatible

2. Minimum Pulse width > 2/
TIMEBASE

1. TTL-compatible

2. Minimum pulse width = 20ns

3.Rising–edge sensitive only

EXTDTRIG and EXTWFTRIG

EXTDTRIG and EXTWFTRIG are dedicated digital trigger input
signals for A/D and D/A operations respectively. Refer to sec­tion 4.5 for details.

EXTTIMEBASE

When the applications needs specific sampling frequency or
update rate that the card could not generate from its internal
TIMEBASE — the 40 MHz clock — you could utilize the EXT­TIMEBASE with internal counters to achieve the specific timing
intervals for both A/D and D/A operations. Note that once you
choose the TIMEBASE source, both A/D and D/A operations
will be affected because A/D and D/A operations share the
same TIMEBASE.

AFI[0]

Alternatively, you can also directly apply an external A/D con­version signal to replace the internal ADCONV signal. This is
another way to achieve customized sampling frequencies. The
external ADCONV signal can only be inputted from the AFI[0].
As section 4.1 describes, the SI_counter triggers the genera­tion of the A/D conversion signal, ADCONV, but when using
the AFI[0] to replace the internal ADCONV signal, the
SI_counter and the internally generated SCAN_START is not
effective. By controlling the ADCONV externally, you can sam-

Operation Theory 71

ple the data according to external events. In this mode, the
Trigger signal and trigger mode settings are not available.

AFI[0] could also be used as SCAN_START signal for A/D
operations. Refer to section 4.1 and section 4.6 for detailed
descriptions of the SCAN_START signal. When using external
signal (AFI[0]) to replace the internal SCAN_START signal, the
pulse width of the AFI[0] must be greater than two time of the
period of Timebase. This feature is suitable for the DAQ-2200/
DAQe-2200/PXI-2200 Series, which can scan multiple chan­nels data controlled by an external event. Note that the AFI[0]
is a multi-purpose input, and it can only be utilized for one func­tion at any one time.

AFI[1]

Regarding the D/A operations, users could directly input the
external D/A update signal to replace the internal DAWR sig­nal. This is another way to achieve customized D/A update
rates. The external DAWR signal can only be inputted from the
AFI[1]. Note that the AFI[1] is a multi-purpose input, and it can
only be utilized for one function at any one time. AFI[1] cur­rently only has one function. ADLINK reserves it for future
development.

System Synchronization Interface

SSI (System Synchronization Interfac e) provides the DAQ timing
synchronization between multiple cards. In DAQ-/DAQe-/PXI­2016/2010/2006/2005 card, we designed a bi-directional SSI I/O
to provide flexible connection between cards and allow one SSI
master to output the signal and up to three slaves to receive the
SSI signal. Note that the SSI signals are design ed for card syn­chronization only and not for external devices.

72 Operation Theory

SSI timing signal Functionality

SSI master: send the TIMEBASE out
SSI slave: accept the SSI_TIMEBASE to

SSI_TIMEBASE

SSI_AD_TRIG

SSI_ADCONV

SSI_SCAN_START

SSI_DA_TRIG

SSI_DAWR

Table 4-10: SSI Timing Signals Functionalities

replace the internal TIMEBASE signal.
Note: Affected on both A/D and D/A

operations
SSI master: send the internal AD_TRIG out
SSI slave: accept the SSI_AD_TRIG as the

digital trigger signal.
SSI master: send the ADCONV out
SSI slave: accept the SSI_ADCONV to

replace the internal ADCONV signal.
SSI master: send the SCAN_START out
SSI slave: accept the SSI_SCAN_START to

replace the internal SCAN_START signal.
SSI master: send the DA_TRIG out.
SSI slave: accept the SSI_DA_TRIG as the

digital trigger signal.
SSI master: send the DAWR out.
SSI slave: accept the SSI_DAWR to replace

the internal DAWR signal.

In PCI form factor, there is a connector on the top right corner of
the card for the SSI. Refer to se ction 2.3 for the connector posi­tion. All the SSI signals are routed to the 20-pin connector from the
FPGA. To synchronize multiple cards, users can connect a special
ribbon cable (ACL-SSI) to all the cards in a daisy-chain configura­tion.

In PXI form factor, we utilize the PXI trigger bus built on the PXI
backplane to provide the necessary timing signal connections. All
the SSI signals are routed to the P2 connector. No add itional cable
is needed. For detailed information of the PXI specifications, refer
to the PXI Specification Revision 2.0 from PXI System Alliance
(www.pxisa.org).

Operation Theory 73

The six internal timing signals could be routed to the SSI or the
PXI trigger bus through software drivers. Refer to section 4.6 for
detailed information on the six inte rnal timing signals. Physically
the signal routings are accomplished in the FPGA. Cards that are
connected together through the SSI or the PXI trigger bus, will still
achieve synchronization on the six timing signals.

The mechanism of the SSI/PXI

X We adopt master-slave configuration for SSI/PXI. In a sys-

tem, for each timing signal, there shall be only one master,
and other cards are SSI slaves or with the SSI function dis­abled.

X For each timing signal, the SSI master does not have to be

in a single card.

For example:
We want to synchronize the A/D operation through the ADCONV

signal for four DAQ-/DAQe-/PXI-2016/2010/2006/2005 cards.
Card 1 is the master, and Card 2, 3, 4 are slaves. Card 1 rece ives
an external digital trigger to start the post trigger mode acquisition.
The SSI setting could be:

X Set the SSI_ADCONV signal of Card 1 to be the master.
X Set the SSI_ADCONV signals of Card 2, 3, 4 to be the

slaves.

X Set external digital trigger for Card 1’s A/D operation.
X Set the SI_counter and the post scan counter (PSC) of all

other cards.

X Start DMA operations for all cards, so all the cards are wait-

ing for the trigger event.

When the digital trigger condition of Card 1 occurs, Card 1 will
internally generate the ADCONV signal and output this ADCONV
signal to SSI_ADCONV signal of Card 2, 3 and 4 through the SSI/
PXI connectors. Thus we can achieve 16-channel acquisition
simultaneously.

You could arbitrarily choose each of the six timing signals as the
SSI master from any one of the cards. The SSI master can output
the internal timing signals to the SSI slaves. With the SSI, users
could achieve better card-to-card synchronization.

74 Operation Theory

Note that when power-up or reset, the DAQ timing signals are
reset to use the internal generated timing signals.

AI_Trig_Out and AO_Trig_Out

AI_Trig_Out (or AO_Trig_Out) is the signal output following one of
the four trigger sources: software trigger, analog trigger, digital
trigger, and SSI trigger selected by the user. That is, AI_Trig_Out
follows the A/D trigger source, and AO_Trig_Out follows the D/A
trigger source. These two signals can be used to control external
peripheral circuits or boards, or can be used as synchronization
control signals. The signal level of the AI_Trig_Out and
AO_Trig_Out are TTL-compatible.

NOTE AI_Trig_Out and AO_Trig_Out are output pins on J5 (68-

pin VHDCI). Connecting them to any signal source may
cause permanent damage to the card.

Operation Theory 75

76 Operation Theory

5 Calibration

This chapter introduces the calibration process to minimize AD
measurement errors and DA output errors.

5.1 Loading Calibration Constants

The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card is factory-cali­brated before shipment. The associated calibration constants of
the TrimDACs firmware to the onboard EEPROM. TrimDACs are
devices containing multiple DACs within a single package. Trim­DACs do not have memory capability. That means the calibration
constants do not retain their values after the system power is
turned off. Loading calibration constants is the process of loading
the values of TrimDACs firmware stored in the onboard EEPROM.
ADLINK provides a software utility that automatically reads the
calibration constants automatically, if necessary.

There is a dedicated space for storing calibration constants in the
EEPROM. In addition to the default bank of factory calibration con­stants, there is one user-utilization bank. This bank allows you to
load the TrimDACs firmware values either from the original factory
calibration or from a subsequently-performed calibration.

Because of the fact that measurements and outputs errors may
vary depending on time and temperature, it is recommended that
you calibrate the card when it is integrated in your computing envi­ronment. The auto-calibration function is presented in the follow­ing sections.

Calibration 77

5.2 Auto-calibration

Through the DAQ-/DAQe-/PXI-2016/2010/2006/2005 card auto­calibration feature, the calibration software measures and corrects
almost all calibration errors without any external signal connec­tions, reference voltage, or measurement devices.

The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card comes with an
onboard calibration reference to ensure the accuracy of auto-cali­bration. The reference volt age is measured in the produc tion line
through a digital potentiometer and compensated in the software.
The calibration constant is memorized after this measurement. We
do not recommended adjustment of the onboard calibration refer­ence except when an ultra-precision calibrator is available.

NOTES

• Warm the card up for at least 15 minutes before initiating auto-cal­ibration.

• Remove the cable before auto-calibrating the card since the DA
outputs are changed during the process.

5.3 Saving Calibration Constants

When auto-calibration is completed, you can save the new calibra­tion constants to the user-configurable banks in the EEPROM.
The date and the temperature when you ran auto-calibration is
saved with the calibration constants. You can store three sets of
calibration constants according to three different environments
and re-load the calibration constants later.

78 Calibration

Warranty Policy

Thank you for choosing ADLINK. To understand your rights and
enjoy all the after-sales services we offer, please read the follow­ing carefully.

1. Before using ADLINK’s products please read the user man­ual and follow the instructions exactly. When sending in
damaged products for repair, please attach an RMA appli­cation form which can be downloaded from: http://
rma.adlinktech.com/policy/.

2. All ADLINK products come with a limited two-year war­ranty, one year for products bought in China:

X The warranty period starts on the day the product is

shipped from ADLINK’s factory.

X Peripherals and third-party products not manufactured

by ADLINK will be covered by the original manufactur­ers' warranty.

X For products containing storage devices (hard drives,

flash cards, etc.), please back up your data before send­ing them for repair. ADLINK is not responsible for any
loss of data.

X Please ensure the use of properly licensed software with

our systems. ADLINK does not condone the use of
pirated software and will not service systems using such
software. ADLINK will not be held legally responsible for
products shipped with unlicensed software installed by
the user.

X For general repairs, please do not include peripheral

accessories. If peripherals need to be included, be cer­tain to specify which items you sent on the RMA Request
& Confirmation Form. ADLINK is not responsible for
items not listed on the RMA Request & Confirmation
Form.

Warranty Policy 79

3. Our repair service is not co vered by ADLINK's guarante e
in the following situations:

X Damage caused by not following instructions in the

User's Manual.

X Damage caused by carelessness on the user's part dur-

ing product transportation.

X Damage caused by fire, earthquakes, floo ds , light en in g,

pollution, other acts of God, and/or incorrect usage of
voltage transformers.

X Damage caused by unsuitable storage environments

(i.e. high temperatures, high humidity, or volatile chemi­cals).

X Damage caused by leakage of battery fluid during or

after change of batteries by customer/user.

X Damage from improper repair by unauthorized ADLINK

technicians.

X Products with altered and/or damaged serial numbers

are not entitled to our service.

X This warranty is not transferable or extendible.
X Other categories not protected under our warranty.

4. Customers are responsible for shipping costs to transport
damaged products to our company or sales office.

5. To ensure the speed and quality of product repair, please
download an RMA application form from our company web­site: http://rma.adlinktech.com/policy. Damaged products
with attached RMA forms receive priority.

If you have any further questions, please email our FAE staff:
[e-mail].

80 Warranty Policy