ADLINK CT-61 User Manual
CT-61
Rugged Conduction Cooled Low Power 6U CompactPCI
Processor Blade with Intel® Core™ i7 and Two PMC Sites
User’s Manual
Manual Rev. 1.00
Revision Date: September 25, 2014
Part No: 50-1Y002-1000
Advance Technologies; Automate the World.
Revision History
Revision Release Date Description of Change(s)
1.00 2014/09/25 Initial release
CT-61
Preface
Copyright 2014 ADLINK Technology Inc.
This document contains proprietary infor mation protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufa cturer.
In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global
environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE)
directive. Environmental protection is a top priority for ADLINK.
We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little
impact on the environment as possible. When products are at their
end of life, our customers are encouraged to dispose of them in
accordance with the product disposal and/or recovery programs
prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks
of their respective companies.
Preface iii
Conventions
Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.
Additional information, aids, and tips that help users perform
tasks.
NOTE:
NOTE:
Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to com-
CAUTION:
WARNING:
plete a task.
Information to prevent serious physical injury, component
damage, data loss, and/or program corruption when trying to
complete a specific task.
iv Preface
CT-61
Table of Contents
Revision History...................................................................... ii
Preface.................................................................................... iii
List of Tables......................................................................... vii
List of Figures........................................................................ ix
1 Overview ............................................................................. 1
1.1 Introduction.......................................................................... 1
1.2 Features............................................................................... 2
1.3 Block Diagram ..................................................................... 3
1.4 Product List............................. ... .......................................... 4
2 Specifications..................................................................... 5
2.1 CT-61 Specifications............................................................ 5
2.2 Power Requirements.................... ... .... ... ... ... ... .... ... ... ... .... ... 7
2.3 Thermal Management Features .......................................... 9
3 Functional Description .................................................... 11
3.1 Processor........................................................................... 11
3.2 Chipset............................................................................... 12
3.3 Super I/O ........................................................................... 13
3.4 Battery ............................................................................... 13
3.5 PMC/XMC Sites................................................................. 13
3.6 BIOS Recovery.................................................... .............. 14
4 Board Interfaces............................................................... 15
4.1 CT-61 Board Layout - Top Side......................................... 15
4.2 CT-61 Board Layout - Bottom Side.................................... 16
4.3 Connector Pin Assignments .............................................. 17
4.4 Switch and Jumper Settings.............................................. 25
Table of Contents v
5 Getting Started.................................................................. 29
5.1 CT-61 Blade Installation..................................................... 29
5.2 PMC/XMC Module Installation........................................... 30
6 Driver Installation.............................................................. 31
6.1 Driver Installation Procedure.............................................. 31
7 Utilities............................................................................... 33
7.1 Watchdog Timer................................................................. 33
7.2 Preboot Execution Environment (PXE).............................. 38
7.3 BIOS Recovery........................ .... ... ... ... .... ... ... ... ... ............. 39
7.4 Programming NT Mode EEPROM Map............................. 41
8 BIOS Setup Utility............................................................. 43
8.1 Starting the BIOS............................................................... 43
8.2 Main Setup......................................................................... 46
8.3 Advanced BIOS Setup....................................................... 47
8.4 Chipset Configuration ........................................................ 57
8.5 Boot Configuration............................................................. 60
8.6 Security Setup.................................................................... 62
8.7 Save & Exit ........................................................................ 63
9 IPMI User Guide ................................................................ 65
9.1 Introduction........................................................................ 65
9.2 Summary of Commands Supported by BMR-AVR-cPCI... 65
9.3 OEM Commands Summary Table............ ... ... ... ... ....... ... ... 69
9.4 CompactPCI Address Map ................................................ 73
9.5 Communications with IPMC............................................... 74
9.6 IPMI Sensors List............................................................... 74
9.7 Relevant Documents................................. ... ... ... ... .... ... ... ... 74
Important Safety Instructions............................................... 75
Getting Service...................................................................... 77
vi Table of Contents
CT-61
List of Tables
Table 2-1: CT-61 Specifications ................................................ 6
Table 2-2: CompactPCI Input Voltage Characteristics .............. 7
Table 2-3: Idle Mode Power Consumption ................................ 8
Table 2-4: 100% CPU Usage Power Consumption ................... 8
Table 4-1: XMC Connector Pin Definition ................................ 17
Table 4-2: PMC Connector Pin Definitions .............................. 18
Table 4-3: CompactPCI J1 Connector Pin Definition ............... 20
Table 4-4: CompactPCI J2 Connector Pin Definition ............... 21
Table 4-5: CompactPCI J3 Connector Pin Definition ............... 22
Table 4-6: CompactPCI J4 Connector Pin Definition ............... 23
Table 4-7: CompactPCI J5 Connector Pin Definition ............... 24
Table 4-8: Mode Switch Settings .. ... ... ... .... ... ... ... ... .... ... ... ... .... . 26
Table 4-9: PMC Bandwidth/Clock Switch Settings .................. 26
List of Tables vii
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viii List of Tables
CT-61
List of Figures
Figure 1-1: CT-61 Block Diagram ................................................ 3
Figure 4-1: CT-61 Board Layout - Top Side............................... 15
Figure 4-2: CT-61 Board Layout - Bottom Side ......................... 16
List of Figures ix
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xList of Figures
1Overview
1.1 Introduction
The CT-61 is a conduction cooled 6U CompactPCI single board
computer in single slot width (4HP) form factor supporting 32nm
Intel® Core™ i7 SV, LV, ULV processors with integrated graphics
and ECC memory controller onboard. The CT-61 provides up to
8GB of dual channel DDR3-800/1066 ECC memory soldered
onboard and implements the Mobile In tel® QM57 Express Chipset
to provide a full feature set and optimal performance per watt.
The CT-61 provides a 64bit/66MHz CompactPCI bus, up to two
PMC sites with 64-bit/133MHz PCI-X bus supporting rear I/O
(PIM), and one PCI Express x8 XMC site (shared with inner PMC
site). Rear I/O provides versatile additional I/O including two
PICMG 2.16 GbE, USB, COM, High Definition Audio, and SATA
interfaces.
For flexibility of use, the CT-61 can be installed in a standard CompactPCI system slot as system master, or peripheral slot as a PCI
device. Through hardware switch setting, the CT-61 optionally
supports operation in system or per ipheral slots as a standalone
blade. The CT-61 is ideally suited for military, aviation, communication and other industrial applications.
CT-61
Overview 1
1.2 Features
X 6U CompactPCI SBC in 4HP width form factor
X µFC-BGA package Intel® Core™ i7 processor, up to 2.53GHz
X Mobile Intel® BD82QM57 PCH (Platform Controller Hub)
X Dual Channel DDR3 ECC SDRAM at 800 or 1066MHz sol-
dered onboard, up to 8GB
X 64-bit/66MHz CompactPCI Interface based on PCI specifica-
tions, 3.3V and 5V signaling
X Supports operation in system slot as system master or in
peripheral slot with connectivity to CompactPCI bus* (optional
isolation from CompactPCI bus)
X Dual PMC sites with 64-bit/133MHz PCI bus
X Single XMC site with PCIe x8 lane (shared with inner PMC
site)
X -40°C to 85°C operating temperature (at wedge locks)
X RTM models available with multiple I/O options: SATA, HD
audio, COM, USB, Gigabit Ethernet, PS/2 KB/MS, PIM, SAS,
SCSI, CF, SD socket
X Hardware RAID on SCSI, SAS interfaces supported (depen-
dent on RTM module)
*See “Programming NT Mode EEPROM Map” on page 41 for
instructions on how to set the PCIe-to-PCI bridge on the CT-61
NOTE:
NOTE:
to NT-mode to allow operation in a peripheral slot.
2Overview
1.3 Block Diagram
Soldered w/ ECC, max. 4GB
Soldered w/ ECC, max. 4GB
DDR3 800/10 66
SPI
CT-61
BIOS
Pericom
PI7C9X13
PCI 64b/66M
Intel® Cor e™i7
PCIe x8
PCIe
Switch
PCIe x4
PCIe x4
Pericom
PI7C9X13
PCI-X 64b/133M
PMC 2
Rear I/O
XMC
PMC 1
2.5” HDD
PCIe x8
Rear I/O
DMI
SATA1
COM4
IPMB 0/1
ITE8783
BMC
SIO
LPC
KB/MS
2x COM
J1/J2 J3/J4/J5
Figure 1-1: CT-61 Block Diagram
QM57 PCH
Intel
82574L
6x USB
3x SAT A
HDA
5x GPIO
RTC
PCIe x4
LVDS
Intel
82574L
PCIe x1 PCIe x1
GbE3 GbE4
TMDSB
RGB
Overview 3
1.4 Product List
Products included in the CT-61 include:
Processor Blade
X CT-61: 4HP width (single-slot) 6U CompactPCI blade fea-
turing single Intel® Core™i7 processor, dual channel
DDR3-800/1066 soldered onboard SDRAM with ECC,
2x PMC
Rear Transition Modules
X cPCI-R6002: 4HP width RTM with DVI-I, 2x COM, 3x USB, 2x
GbE, 2xSATA
X cPCI-R6100: 4HP width RTM with 4x GbE, 4x USB, 2xSATA,
DVI, VGA, PS/2 KB/MS, CF & SD sockets
X cPCI-R6110: 4HP width RTM with 2x GbE, 4x USB, 3x SATA,
VGA, PS/2 KB/MS, CF, & SD sockets
X cPCI-R6200: 8HP width RTM with 2x GbE, 2x COM, 4x USB,
DVI-I, 3x SATA, Mic-in, Line-out, PS/2 KB/MS, 8x SAS
X cPCI-R6210: 4HP width RTM with 2xUSB, DVI-I, COM,
2x SATA, 2x PIM
The contents of non-standard CT-61 configurations may vary
depending on customer requests.
NOTE:
NOTE:
This product must be protected from static discharge and physical shock. Never remove any of the components except at a
CAUTION:
4Overview
static-free workstation. Use the anti-static bag shipped with the
product when putting the board on a surface. Wear an
anti-static wrist strap properly grounded on one of the system's
ESD ground jacks when installing or servicing system components.
2 Specifications
2.1 CT - 61 Specifications
PICMG® 2.0 CompactPCI® Rev. 3.0
CompactPCI
Standard
Mechanical
Processor
Chipset Intel® QM57 Platform Controller Hub (PCH)
Memory
CompactPCI Bus
PMC/XMC
Graphics
Ethernet
Serial Ports Two serial ports routed to rear I/O
BIOS AMI® EFI BIOS 64Mbit SPI flash memory
PICMG® 2.1 Hot Swap Specification Rev.2.0
PICMG® 2.9 System Management Bus Rev. 1.0
PICMG® 2.16 Packet Switching Backplane Rev.1.0
Standard 6U CompactPCI®
Board size: 233.23 mm x 160mm
Single slot (4HP, 20.32mm) width
CompactPCI® connectors J1, J2, J3, J4 and J5
µFC-BGA Intel® Core™i7-610E, 4MB L2 cache, 2.53GHz
µFC-BGA Intel® Core™i7-620LE, 4MB L2 cache, 2.0GHz
µFC-BGA Intel® Core™i7-620UE, 4MB L2 cache, 1.06GHz
Dual channel DDR3-800/1066 soldered onboard SDRAM
with un-buffered ECC
DDR3-800 for Core™i7-620UE processor
DDR3-1067 for Core™i7-610E/620LE processors
Maximum 8GB capacity
PCI 64-bit/ 66MHz; V(I/O) 3.3V and 5V signaling
Supports operation in system slot or in peripheral slot with
connectivity to CompactPCI bus (Universal Mode)
Optional Satellite mode by switch setting
Two PCI 64-bit/133MHz PMC sites, V(I/O) 3.3V (contact
ADLINK for 5V support)
One PCIe x8 XMC site (shared with inner PMC site)
Integrated in Intel® Core™i7 processor
Analog RGB signal to rear
DVI port routed to rear
Supports dual independent display
Analog RGB up to QXGA
PCIe x1 Intel® 82574L GbE controllers
Two 10/100/1000BASE-T ports to J3
CT-61
1
Specifications 5
Supports PICMG® 2.9 secondary system management bus
IPMI functions implemented as defined by IPMI Spec. v1.5 ;
IPMI Interface
ATmega128L-8AU Baseboard Management Controller
(BMC) with 128KB programmable in-system flash, 4KB
EEPROM, and 4KB internal SDRAM
Microsoft® Windows® 7 Ultimate
Microsoft® Windows® Vista Enterprise
Supported OS
Microsoft® Windows® XP Professional SP3
Fedora™ 12
Other OS support upon request
Operating
Temperature
Storage
temperature
-40°C to +85°C at wedge lock
-40°C to 85°C
Humidity 20% to 95% non-condensing
Shock 20G peak-to-peak, 11ms duration, non-operating
Vibration Operating: 20Grms. 5 to 500Hz, each axis
Compliance CE EN55022, FCC Class A
T able 2-1: CT-61 Specifications
Notes:
1. See 7.4 "Programming NT Mode EEPROM Map" on page 41
for instructions on how to set the PCIe-to-PCI bridge on the
CT-61 to Non-Transparent mode to allow operation in a peripheral slot.
Specifications are subject to change without prior notice.
NOTE:
NOTE:
6 Specifications
CT-61
2.2 Power Requirements
In order to guarantee a stable functionality of the system, it is recommended to provide more power than the system requires. An
industrial power supply unit should be able to provide at least
twice as much power as the entire system requires of each
voltage. An ATX power supply unit should be able to provide at
least three times as much power as the entire system requires.
The tolerance of the voltage lines described in the CompactPCI
specification (PICMG 2.0 R3.0) is +5%/ -3% for 5, 3.3 V and ±5%
for ±12V. This specification is for power delivered to each slot an d
it includes both the power supply and the backplane tolerance.
Voltage
5V +5.0 VDC +5% / -3% 50 mV
3.3V +3.3 VDC +5% / -3% 50 mV
+12V +12 VDC +5% / -5% 240 mV
-12V -12 VDC +5% / -5% 240 mV
V I/O (PCI I/O
Buffer Voltage)
GND
Table 2-2: Comp actPCI Input Voltage Characteristics
Nominal
Value
+3.3 VDC or
+5 VDC
Tolerance
+5% / -3% 50 mV
Max. Ripple
(P - P)
Specifications 7
Power Consumption
This section provides information on the power consumption of the
CT-61 with different CPUs, 2GB DDR3-800/1066 soldered memory, and 100GB SATA HDD. The system was tested in Idle Mode
and Full Load Mode under Windows XP running Burn-in Test 6.0.
The CT-61 is powered by 5V and 3.3V.
Idle Mode under Windows XP
CPU Core™ i7 610E Core™ i7 620LE Core™ i7 620UE
Voltage
+3.3 4.19 13.82 4.12 18.41 3.85 12.71
Total 19.51 23.76 17.96
100% CPU Usage under Windows XP
CPU Core™ i7 610E Core™ i7 620LE Core™ i7 620UE
Voltage
+3.3 6.09 20.10 5.83 19.25 5.31 17.52
Total 42.31 37.08 27.87
Current
(V)
+5 1.14 5.69 1.07 5.35 1.05 5.25
(V)
+5 4.44 22.21 3.57 17.83 2.07 10.35
(A)
Table 2-3: Idle Mode Power Consumption
Current
(A)
Power
(W)
Power
(W)
Current
(A)
Current
(A)
Power
(W)
Power
(W)
Current
(A)
Current
(A)
Power
(W)
Power
(W)
T able 2-4: 100% CPU Usage Power Consumption
8 Specifications
CT-61
2.3 Thermal Management Features
When the CPU temperature exceed s its maximum junction temperature (T
reduce power consumption (and thus performance) in an attempt
to reduce the core junction temperature. Use of the CPU’s thermal
management features is intended for short periods of time when
running power intensive applications. If the system is operated
under conditions below the TDP curves above, activation of the
thermal management features will be minimal and reduction in
CPU performance will be minor.
However, if the operating conditions are outside the limits set out
above, the CPU temperature may exceed T
periods, resulting in noticeable performance loss and reduced reliability of the processor.
In extreme situations, the thermal management features may be
incapable of cooling the processor. If the CPU temperature
exceeds approximately 130°C, a catastrophic cooling failure will
be detected and the processor will automatically shut down to prevent physical damage to the processor.
), the CPU’s thermal management features will
j,Max
for prolonged
j,Max
Prolonged operation above the CPU’s maximum junction temperature (Tj,Max=105°C) may damage the CPU and/or reduce
WARNING:
Specifications 9
its long term reliability. Be sure to follow the thermal guidelines
set out in this document.
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10 Specifications
3 Functional Description
The following sections describe the CT-61 features and functions.
3.1 Processor
Intel® Core™ i7 Processor
The Intel® Core™ i7-620LE/UE and i7-610E are 64-bit, multi-core
mobile processors built on a 32 nanometer process technology.
The processors are designed for a two-chip platform consisting of
a processor and the Platform Controller Hub (PCH) and enables
higher performance, lower cost, easier validation, and improved
x-y footprint. The Intel® Core™ i7-620LE/UE and i7-610E processors are offered in a BGA1288 package and include an integrated
graphics and memory controller die on the same package as the
processor core die.
The following table lists the processors supported by the CT-61
and their specifications.
Features SV Core i7-610E LV Core i7-620LE ULV Core i7-620UE
Clock 2.53GHz 2.0GHz 1.06GHz
Max. Turbo Freq. 3.2GHz 2.8GHz 2.13GHz
L2 cache 4MB 4MB 4MB
Max. Power (TDP1)
2
T
j,Max
Process 32nm 32nm 32nm
# of cores/threads 2/4 2/4 2/4
Notes:
1. The highest expected sustainable power while running known
power intensive applications. TDP is not the maximum power
that the processor can dissipate.
2. Maximum junction temperature (T
ported operating temperature.
35W 25W 18W
105°C 105°C 105°C
). The maximum sup-
j,Max
CT-61
Functional Description 11
System Memory Support
X Two channels of DDR3 memory soldered onboard
X Memory DDR3 data transfer rates of 800 and 1066 MT/s
X 64-bit wide channels (72-bit wide including ECC)
X Supports ECC unbuffered DDR3 memory
X Theoretical maximum memory bandwidth of:
Z
12.8 GB/s in dual-channel mode assuming DDR3 800 MT/s
Z
17.1 GB/s in dual-channel mode assuming DDR3 1066 MT/s
X 1-Gb and 2-Gb DDR3 DRAM technologies for x8 devices
X Using 2Gb device technologies, the largest memory capac-
ity is 8GB
3.2 Chipset
Mobile Intel® QM57 Express Chipset
The CT-61 incorporates the Mobile Intel® QM57 Express Chipset,
also referred to as PCH (Platform Controller Hub), to provide
extensive I/O support. Functions and capabilities include:
X PCI Express Base 2.0 Specification support for up to eight
ports
X 4 PCI Express x1 connected to LAN controllers
X 4 PCI Express x1 are configured to PCI Express x4 and
routed to J5 for I/O expansion
X ACPI Power Management Logic Support
X Two integrated SATA host controllers with up to six ports,
supporting independent DMA operation and dat a transfer
rates of up to 3.0GB/s (the CT-61 supports up to four SATA
ports)
X Supports Advanced Host Controller Interface (AHCI)
X Intel Rapid Storage Technology provides high performance
RAID 0, 1, 5, and 10 functionality
X High speed USB 2.0 allows data transfers up to 480 Mb/s
X Provides Intel Virtualization Technology with Directed I/O
(Intel VT-d) support.
12 Functional Description
CT-61
3.3 Super I/O
The ITE IT8783F Super I/O is on a Low Pin Count interface supporting PS/2 keyboard/mouse, 16C550-compatible serial ports,
floppy drive interface, hardware monitor function to monitor CPU
voltage, CPU temperature, power supply voltages and system temperature, and Watchdog Timer with time resolution from minimum 1
second or minute to maximum 65,535 se co nd s or minutes.
3.4 Battery
The CT-61 is p ro vided with a 3.0V/0.2F gold ca p for th e Rea l Time
Clock (RTC). The gold cap supports a 12-hour theoretically life.
3.5 PMC/XMC Sites
The CT-61 supports two PMC sites for front panel I/O expansion.
The PMC sites provides a maximum 64bit/133MHz PCI-X bus link
using a Pericom PI7C9X130 PCIe-to-PCI bridge and PCIe x4 link.
The PMC/XMC sites support +3.3V signaling and 5V VPWR by
default. For optional 5V signaling and 12V VPWR support, contact
your ADLINK sales representative.
The JN1/5 and JN2/6 connectors provide the signals for the 32-bit
PCI bus. The JN3/7 connector provides the 64 bit extension for the
PMC interface. The JN3/7 connectors support user defined I/O
signals and are routed to the CompactPCI J4/5 connectors to rear
I/O.
The CT-61 provides a PCIe x8 XMC interface sharing the same
space as the inner PMC site for high speed I/O e xpansion, such as
10GbE or high-end graphics.
Functional Description 13
3.6 BIOS Recovery
The CT-61 features AMI® EFI BIOS with BIOS recovery. If the
BIOS becomes corrupted and you are unable to boot your system,
follow the instructions in Section 7.3 “BIOS Recovery” on page 39.
14 Functional Description
4 Board Interfaces
This chapter describes the board layout, connector pin assignments, and jumper settings of the CT-61.
4.1 CT-61 Board Layout - Top Side
160
CT-61
JN5 JN7
J5
JN6 JN8
SW1
J4
SW2
CN8
JN1 JN3
JN2 JN4
J3
SW3
J2
J1
CN8 XMC conne ctor SW1 Reserved
J1-5 CompactPCI connectors SW2 Mode Switch
JN1-8 PMC connectors SW3 PMC Clock Switch
233.2
Figure 4-1: CT-61 Board Layout - Top Side
Board Interfaces 15
4.2 CT- 61 Board Layout - Bottom Side
SW6 SW4
SW4 Reserved SW6 Clear CMOS
Figure 4-2: CT-61 Board Layout - Bottom Side
16 Board Interfaces
CT-61
4.3 Connector Pin Assignments
Refer to “CT-61 Board Layout - Top Side” on page 15 and “CT-61
Board Layout - Bottom Side” on page 16 for connector locations.
XMC Connector (CN8)
Pin# A B C D E F
1 PETp0 PETn0 3.3V PETp1 PETn1 VPWR
2 GND GND TRST# GND GND MRSTI#
3 PETp2 PETn2 3.3V PETp3 PETn3 VPWR
4 GND GND TCK GND GND MRSTO#
5 PETp4 PETn4 3.3V PETp5 PETn5 VPWR
6 GND GND TMS GND GND +12V
7 PETp6 PETn6 3.3V PETp7 PETn7 VPWR
8 GND GND TDI GND GND -12V
9NC NCNCNCNCVPWR
10 GND GND TDO GND GND GA0
11 PERp0 PERn0 MBIST# PERp1 PERn1 VPWR
12 GND GND GA1 GND GND MPRESENT#
13 PERp2 PERn2 3.3V AUX PERp3 PERn3 VPWR
14 GND GND GA2 GND GND MSDA
15 PERp4 PERn4 NC PERp5 PERn5 VPWR
16 GND GND MVMRO GND GND MSCL
17 PERp6 PERn6 NC PERp7 PERn7 NC
18 GND GND NC GND GND NC
19 REFCLK+0 REFCLK-0 NC WAKE# ROOT0# NC
Table 4-1: XMC Connector Pin Definition
Board Interfaces 17
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