ADLINK cPCI-7300 User Manual

NuIPC

®

/ NuDAQ®

cPCI-7300A & PCI-7300A

80MB Ultra-High Speed 32-CH

Digital I/O Boards

User’s Guide

Recycle Paper

©Copyright 2002 ADLINK Technology Inc.
All Rights Reserved.

Manual Rev 2.31: 1 June, 2003

Part No.: 50-11106-101

The information in this document is subject to change without prior notice in
order to improve reliability, design and function and does not represent a
commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special,
incidental, or consequential damages arising out of the use or inability to
use the product or documentation, even if advised of the possibility of such
damages.

This document contains proprietary information protected by copyright. All
rights are reserved. No part of this manual may be reproduced by any
mechanical, electronic, or other means in any form without prior written
permission of the manufacturer.

Trademarks

NuDAQ

®

, NuIPC®, DAQBench® are registered trademarks of ADLINK

Technology Inc.,

Other product names mentioned herein are used for identification purposes
only and may be trademarks and/or registered trademarks of their
respective companies.

Getting service from ADLINK

• Customer Satisfaction is the most important priority for ADLINK Tech Inc. If
you need any help or service, please contact us.

ADLINK Technology Inc.

Web Site http://www.adlinktech.com

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Service

NuDAQ + USBDAQ [e-mail]

Technical

Support

TEL [phone] FAX [phone]

Address 9F, No. 166, Jian Yi Road, Chungho City, Taipei, 235 Taiwan.

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• Please email or FAX us of your detailed information for a prompt,

satisfactory and constant service.

Detailed Company Information

Company/Organization

Contact Person

E-mail Address

Address

Country

TEL FAX

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Product Model

OS:

Computer Brand:

M/B: CPU:

Environment to Use

Detail Description

Suggestions to ADLINK

Chipset: BIOS:

Video Card:

Network Interface Card:

Other:

[e-mail]

Questions

Table of Contents

Introduction............................................................................. 1

1.1 A

PPLICATIONS

1.2 F

EATURES

1.3 S

PECIFICATIONS

1.4 S

OFTWARE SUPPORTING

1.4.1 Programming Library ..........................................................5

1.4.2 PCIS-LVIEW: LabVIEW® Driver..........................................5

1.4.3 PCIS-VEE: HP-VEE Driver .................................................6

1.4.4 DAQBenchTM: ActiveX Controls..........................................6

.....................................................................................2

...........................................................................................2

..................................................................................3

......................................................................5

Installation............................................................................... 7

2.1 W

HAT YOU HAVE

2.2 U

NPACKING

2.3 D

EVICE INSTALLATION FOR WINDOWS SYSTEMS

2.4 PCI-7300A'S L

2.5 H

ARDWARE INSTALLATION OUTLINE

2.6 C

ONNECTOR PIN ASSIGNMENT

2.7

WIRING AND TERMINATION

2.8

DAUGHTER BOARD SUPPORTING

2.8.1 Connect with DIN-100S ....................................................14

2.8.2 Connect with DIN-502S ....................................................14

.................................................................................7

.........................................................................................8

.....................................8

.........................................................................9

AYOUT

.....................................................10

............................................................11

.................................................................13

........................................................14

Registers................................................................................15

3.1 I/O P

3.2 DI_CSR: DI C

3.3 DO_CSR: DO C

3.4 A

3.5 INT_CSR: I

3.6 DI_FIFO: DI FIFO

3.7 DO_FIFO: DO

3.8 FIFO_CR: FIFO

3.9 POL_CNTRL: C

3.10

ORT BASE ADDRESS

ONTROL & STATUS REGISTER

UXILIARY DIGITAL

NTERRUPT CONTROL AND STATUS REGISTER

EXTERNAL DATA

PLX PCI-9080 DMA C

ONTROL & STATUS REGISTER

ALMOST EMPTY/FULL REGISTER

ONTROL SIGNAL POLARITY CONTROL REGISTER

...................................................................16

.......................................17

....................................18

I/O R

EGISTER

DIRECT ACCESS PORT

ONTROL REGISTERS

........................................................20

.....................20

............................................21

FIFO

DIRECT ACCESS PORT

.................................23

.......................................24

.................22

..........23

Operation Theory.................................................................. 25

4.1 I/O C

4.2 B

LOCK DIAGRAM

ONFIGURATION

..........................................................................25

................................................................................26

Table of Contents • i

4.3 D

4.4 I

4.5 BUS-

4.6 S

4.7 C

4.8 S

4.9 A

4.10

DIGITAL INPUT OPERATION MODE

4.11

DIGITAL OUTPUT OPERATION MODE

4.12

AUXILIARY

I/O D

IGITAL

NPUT

MASTERING

CATTER/GATHER

LOCKING MODE

TARTING MODE

CTIVE TERMINATOR

4.10.1 Digital Input DMA in Internal Clock Mode .........................33

4.10.2 Digital Input DMA in External Clock Mode ........................35

4.10.3 Digital Input DMA in Handshaking Mode ..........................37

4.10.4 Continuous Digital Input....................................................39

4.11.1 Digital Output DMA in Internal Clock Mode ......................40

4.11.2 Digital Output DMA in Handshaking Mode .......................41

4.11.3 Digital Output DMA in Burst Handshaking Mode ..............43

4.11.4 Pattern Generator .............................................................44

ATA FLOW

FIFO

AND OUTPUT

DIO.................................................................................45

.....................................................................27

FIFO ..........................................................28

DMA .......................................................................29

DMA .....................................................................30

...............................................................................31

...............................................................................32

..........................................................................33

.......................................................33

...................................................40

C/C++ Libraries .....................................................................46

5.1 L

IBRARIES INSTALLATION

5.2 P

ROGRAMMING GUIDE

5.2.1 Naming Convention ..........................................................47

5.2.2 Data Types .......................................................................47

5.3 _7300_I

5.4 _7300_C

5.5 _7300_C

5.6 _7300_DI_M

5.7 _7300_DO_M

5.8 _7300_AUX_DI ...............................................................................53

5.9 _7300_AUX_DI_C

5.10

_7300_AUX_DO ............................................................................54

5.11

_7300_AUX_DO_C

5.12

_7300_A

5.13

_7300_F

5.14

_7300_DI_DMA_S

5.15

_7300_DI_DMA_S

5.16

_7300_DI_DMA_A

5.17

_7300_GETO

5.18

_7300_DO_DMA_S

..................................................................................48

NITIAL

..................................................................................49

LOSE

ONFIGURE

ODE

ODE

_DMA_MEM..............................................................55

LLOC

_DMA_MEM................................................................56

REE

VERRUNSTATUS

....................................................................46

........................................................................47

...........................................................................49

.............................................................................51

............................................................................52

HANNEL

...............................................................53

.............................................................54

HANNEL

..................................................................56

TART

................................................................59

TATUS

..................................................................59

BORT

...........................................................60

................................................................60

TART

ii • Table of Contents

5.19

_7300_DO_DMA_S

5.20

_7300_DO_DMA_A

5.21

_7300_DO_PG_S

5.22

_7300_DO_PG_S

5.23

_7300_DI_T

5.24

_7300_DO_T

5.25

_7300_INT_T

5.26

_7300_GET_S

5.27

_7300_SET_S

5.28

_7300_GETU

TART

TOP

............................................................................64

IMER

...........................................................................65

IMER

...........................................................................65

IMER

AMPLE

AMPLE

NDERRUNSTATUS

..............................................................62

TATUS

................................................................62

BORT

...................................................................63

.....................................................................64

.......................................................................66

.......................................................................67

.........................................................67

Appendix A 8254 Programmable Interval Timer ...............69

A.1 T

HE INTEL

A.2 T

HE CONTROL BYTE

A.3 M

ODE DEFINITION

(NEC) 8254......................................................................69

..........................................................................69

..............................................................................71

Warranty Policy..................................................................... 73

Table of Contents • iii

How to Use This Guide

This manual is designed to help you use the cPCI-7300 and PCI-7300A Rev.B.
The manual describes how to modify various settings on the PCI-7300A card
to meet your requirements. It is divided into five chapters:

Chapter 1,

•
applications, and specifications.

Chapter 2,

•
layout of PCI-7300A is shown, and the installation procedures, pin
assignment of connectors, and timer pacer generation are specified.

Chapter 3,

•
register structure and format of the PCI-7300A.

Chapter 4,

•
digital input and output on the PCI-7300A.

Chapter 5,

•
library functions. It will help you to programming in DOS, Win 3.11,
Win-95 and Win-NT environments.

Appendix A,

•
detailed structure and register format of 8254-timer/counter chip.

"Introduction", gives an overview of the product features,

"Installation", describes how to install the PCI-7300A. The

"Register Structure & Format", describes the low-level

"Operation Theory", describes how to use the operations of

"C/C++ & DLL Library", describes the high level C and DLL

"8254 Programmable Interval Timer", describes the

How to Use This Guide • iv

1

Introduction

The cPCI/PCI-7300A is cPCI/PCI form factor ultra-high speed digital I/O card,
it consists of 32 digital input or output channel. High performance designs and
the state-of-the-art technology make this card to be ideal for high speed digital
input and output applications.

The cPCI/PCI-7300A performs high-speed data transfers using bus mastering
DMA and scatter/gather via 32-bit PCI bus architecture. The maximum data
transfer rates can be up to 80MB per second. It is very suitable for interface
between high speed peripherals and your computer system.

The cPCI/PCI-7300A is configured as two ports, PORTA and PORTB, each
port controls 16 digital I/O lines. The I/O can configure as either input or output,
and 8-bit or 16-bit. According to outside device environment, users can
configure cPCI/PCI-7300A to meet all high speed digital I/O data transfer.

There are 4 different digital I/O operation modes are supported:

1. Internal Clock:

internal clock and transferred by bus mastering DMA.

2. External Clock:

signal ( DIREQ ) and transferred by bus mastering DMA.

3. Handshaking:

data can have simple handshaking data transfer.

4. Pattern Generation:

predetermined rate. The transfer rate is controlled by internal timer.

the digital input and output operations are paced by

the digital input operation is paced by external strobe

through REQ signal and ACK signal, the digital I/O

You can output a digital pattern repeatedly at a

Introduction • 1

1.1 Applications

• Interface to high-speed peripherals

• High-speed data transfers from other computers

• Automated test equipment (ATE)

• Electronic and logic testing

• Interface to external high-speed A/D and D/A converter

• Digital pattern generator

• Waveform and pulse generation

• Parallel digital communication

1.2 Features

The PCI-7300A Ultra-High Speed DIO card provides the following advanced
features:

• 32 digital input/output channels

• Extra 4-bit TTL digital input and output channels

• Transfer up to 80M Bytes per second

• SCSI active terminator for high speed and long distance data transfer

• 32-bit PCI bus

• Plug and Play

• Scatter/gatter DMA

• On-board internal clock generator

• Internal timer/external clock controls input sampling rate

• Internal timer control digital output rate

• ACK and REQ for handshaking

• TRIG signal controls start of data acquisition/pattern generation

• On-board 64KB FIFO

• 100-pin SCSI style connector

2 • Introduction

1.3 Specifications

Digital I/O (DIO)

♦

Numbers of Channel:

•

Device:

•

I/O Configurations:

•

16 DI & 16 DO

32 DI

32 DO

Input Voltage:

♦

• Low: Min. 0V; Max. 0.8V

• High: Min. +2.0V

Input Load:

♦

• Terminator OFF:

Low: +0.5V @ ±20 mA

High: +2.7V @ ±1 mA max.

• Terminator ON:

Termination resistor: 110 Ohms

Termination voltage: 2.9V

IDT 74FCT373

32 TTL compatible inputs and/or outputs

Low: +0.5V @ ±22.4mA

High: +2.7V @ ± 1mA max.

Output Voltage:

♦

• Low: Min. 0V; Max. 0.5V

• High: Min. +2.7V

Driving Capacity:

♦

• Low: Max. +0.5V at 48mA (Sink)

• High: Min. 2.4V at -8 mA (Source)

Hysteresis: 500mV

♦

Transfer Characteristic

♦

Introduction • 3

• Mode: Bus Mastering DMA with Scatter/Gather

• Data Transfers: 8/16/32-bit input or output (programmable)

DMA Transfer count:

♦

• 2M double words (8M bytes) for non-chaining mode DMA

• No limitation for chaining mode (scatter/gather) DMA

Max. Transfer rate:

♦

• DO: 80M Bytes/sec: 32-bit output @ 20 MHz

• DI: 80M Bytes/sec: 32-bit input @ 20 MHz

Programmable Counter:

♦

• Device: 82C54-10

• Digital Input Pacer: 20MHz, 10MHz, or clock output of Timer #0

• Digital Output Pacer: 20MHz, 10MHz, or clock output of Timer #1

• General Purpose Timer:

• General Specifications

Connector: one 100-pin male SCSI-II style cable connector

♦

Operating Temperature:

♦

Output of Timer #2

0° C ~ 60°C

Storage Temperature:

♦

Humidity: 5 ~ 95%, non-condensing

♦

Dimension: Compact size only 179mm(L) X 102mm(H)

♦

Power Consumption:

♦

• +5 V @ 830 mA max. with on-board terminator off

or

• +5 V @ 1.0A max. with on-board terminator on

4 • Introduction

-20° C ~ 80°C

1.4 Software Supporting

ADLINK provides versatile software drivers and packages for users’ different
approach to built-up a system. We not only provide programming library such
as DLL for many Windows systems, but also provide drivers for software

packages such as LabVIEW®, HP VEETM, DASYLabTM, InTouchTM,
InControl

All the software options are included in the ADLINK CD. The non-free software
drivers are protected with serial licensed code. Without the software serial
number, you can still install them and run the demo version for two hours for
demonstration purpose. Please contact with your dealer to purchase the
formal license serial code.

1.4.1 Programming Library

For customers who are writing their own programs, we provide function
libraries for many different operating systems, including:

♦ DOS Library: Borland C/C++ and Microsoft C++, the functions

♦ Windows 95 DLL: For VB, VC++, Delphi, BC5, the functions descriptions

TM

, ISaGRAFTM, and so on.

descriptions are included in this user’s guide.

are included in this user’s guide.

♦ PCIS-DASK: Include device drivers and DLL for Windows 98, Windows

NT and Windows 2000. DLL is binary compatible across Windows 98,
Windows NT and Windows 2000. That means all applications developed
with PCIS-DASK are compatible across Windows 98, Windows NT and
Windows 2000. The developing environment can be VB, VC++, Delphi,
BC5, or any Windows programming language that allows calls to a DLL.
The user’s guide and function reference manual of PCIS-DASK are in the
CD. Please refer the PDF manual files under
\\Manual_PDF\Software\PCIS-DASK

The above software drivers are shipped with the board. Please refer to the
“Software Installation Guide” to install these drivers.

1.4.2 PCIS-LVIEW: LabVIEW® Driver

PCIS-LVIEW contains the VIs, which are used to interface with NI’s LabVIEW®
software package. The PCIS-LVIEW supports Windows 95/98/NT/2000. The
LabVIEW
them without license. For detail information about PCIS-LVIEW, please refer
to the user’s guide in the CD.

(\\Manual_PDF\Software\PCIS-LVIEW)

®

drivers are free shipped with the board. You can install and use

Introduction • 5

1.4.3 PCIS-VEE: HP-VEE Driver

The PCIS-VEE includes the user objects, which are used to interface with HP
VEE software package. PCIS-VEE supports Windows 95/98/NT. The HP-VEE
drivers are free shipped with the board. You can install and use them without
license. For detail information about PCIS-VEE, please refer to the user’s
guide in the CD.

(\\Manual_PDF\Software\PCIS-VEE)

1.4.4 DAQBenchTM: ActiveX Controls

We suggest the customers who are familiar with ActiveX controls and
VB/VC++ programming use the DAQBench
library for developing applications. The DAQBench

TM

ActiveX Control components

TM

is designed under
Windows NT/98. For more detailed information about DAQBench, please refer
to the user’s guide in the CD.

(\\Manual_PDF\Software\DAQBench\DAQBench Manual.PDF)

6 • Introduction

2

Installation

This chapter describes how to install the cPCI/PCI-7300A. At first, the contents
in the package and unpacking information that you should be careful are
described. Because the PCI-7300A is following the PCI design philosophy, it
is no more jumpers and DIP switches setting for configuration. The Interrupt
and I/O port address are the variables associated with automatic configuration,
the resource allocation is managed by the system BIOS. Upon system
power-on, the internal configuration registers on the board interact with the
BIOS.

2.1 What You Have

In addition to this User's Manual, the package includes the following items:

• cPCI/PCI-7300A 80MB Ultra-High Speed 32-CH Digital I/O Card

• ADLINK All-in-one CD

• Software Installation Guide

If any of these items is missing or damaged, contact the dealer from whom you
purchased the product. Save the shipping materials and carton in case you
want to ship or store the product in the future.

Installation • 7

2.2 Unpacking

Your cPCI/PCI-7300A card contains sensitive electronic components that can
be easily damaged by static electricity.

The card should be placed on a grounded anti-static mat. The operator should
be wearing an anti-static wristband, grounded at the same point as the
anti-static mat.

Inspect the card module carton for obvious damage. Shipping and handling
may cause damage to your module. Be sure there are no shipping and
handling damages on the module before processing.

After opening the card module carton, extract the system module and place it
only on a grounded anti-static surface component side up.

Again inspect the module for damage. Press down on all the socketed IC's to
make sure that they are properly seated. Do this only with the module place on
a firm flat surface.

Note: DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN

DAMAGED.

You are now ready to install your cPCI/PCI-7300A.

2.3 Device Installation for Windows Systems

Once Windows 95/98/2000 has started, the Plug and Play function of Windows
system will find the new NuDAQ/NuIPC cards. If this is the first time to install
NuDAQ/NuIPC cards in your Windows system, you will be informed to input
the device information source. Please refer to the “Software Installation
Guide” for the steps of installing the device.

8 • Installation

2.4 PCI-7300A's Layout

Figure 2.1 PCI-7300A Layout Diagram

Figure 2.2 cPCI-7300A Layout Diagram

Installation • 9

2.5 Hardware Installation Outline

PCI configuration

The PCI cards (or CompactPCI cards) are equipped with plug and play PCI
controller, it can request base addresses and interrupt according to PCI
standard. The system BIOS will install the system resource based on the PCI
cards’ configuration registers and system parameters (which are set by system
BIOS). Interrupt assignment and memory usage (I/O port locations) of the PCI
cards can be assigned by system BIOS only. These system resource
assignments are done on a board-by-board basis. It is not suggested to assign
the system resource by any other methods.

PCI slot selection

Please note that the PCI slot must provide bus-mastering capability to operate
this board well.

Installation Procedures

1. Turn off your computer.

2. Turn off all accessories (printer, modem, monitor, etc.) connected to
your computer.

3. Remove the cover from your computer.

4. Select a 32-bit PCI slot. PCI slots are short than ISA or EISA slots, and
are usually white or ivory.

5. Before handling the PCI cards, discharge any static buildup on your
body by touching the metal case of the computer. Hold the edge and
do not touch the components.

6. Position the board into the PCI slot you selected.

7. Secure the card in place at the rear panel of the system.

10 • Installation

2.6 Connector Pin Assignment

The PCI-7300A comes equipped with one 100-pin SCSI type connector (CN1)
located on the rear mounting plate. The pin assignment of CN1 is illustrated in
the figure 2.2.

Legend:

Pins Signal Name Signal Type

1…50 GND GND

51..66 PB15…PB0 DATA I/O

67 DOACK CONTROL I

68 DOREQ CONTROL O

69 DOTRIG CONTROL I

70…73 AUXDO3…0 DATA O

85..100 PA15…PA0 DATA I/O

82 DIACK CONTROL O

83 DIREQ CONTROL I

84 DITRIG CONTROL I

78…81 AUXDI3…0 DATA I

74…77 TERMPWR POWER

Signal

Direction

Description

Ground – these lines are the ground
reference for all other signals
PortB bidirectional data liness-PB15
is the MSB, and PB0 is the LSB.
Digital output Acknowledge lines –
In handshaking mode, DOACK
carries handshaking status
information from the peripheral.
Request line – In handshaking
mode, DOREQ carries handshaking
control information to peripheral.
DO TRIG- can be used to control
the start of data output in all DO
modes and to control the stop of
pattern generation in pattern
generation mode.
AUX DO 3…0 – can be used as
extra output data or can be used as
extra control signals.
PortA bidirectional data liness-PA15
is the MSB, and PA0 is the LSB.
Digital output Acknowledge lines –
In handshaking mode, DIACK
carries handshaking status
information to the peripheral.
Request line – In handshaking
mode, DIREQ carries handshaking
control information from peripheral.
In external clock mode, DIREQ
carries the external clock input.
DI TRIG – can be used to control
the start of data acquisition in all DI
modes.
AUX DI 3…0 – can be used as extra
input data or can be used as extra
control signals.
TERMPWR -- 4.7V active
terminator power output

Installation • 11

Figure 2.2 CN1 Pin Assignment

12 • Installation

2.7 Wiring and Termination

Transmission line effects and environment noise, particularly on clock and
control lines, can lead to incorrect data transfers if you do not take care when
running signal wires to and from the devices.

Take the following precautions to ensure a uniform transformation line and
minimize noise pickup:

1. Use twisted-pair wires to connect digital I/O signals to the device. Twist each
digital I/O signal with a GND line. In PCI-7300A, 50 signals are used as
GND.

2. Place a shield around the wires connecting digital I/O signal to device.

3. Route signals to the devices carefully. Keep cabling away from noise
sources, such as video monitor.

For cPCI/PCI-7300A, it is important to terminate your cable properly to reduce
or eliminate signal reflections in the cable. The PCI-7300A support active
terminator on board, you can enable or disable the terminator by software
selection. This is a good way to include termination on the signal transmission.

Additional recommendations apply for all signal connection to your
cPCI/PCI-7300A are listed as follows:

1. Separate cPCI/PCI-7300A device signal lines from high-current or
high-voltage line. These lines are capable of inducing currents in or voltages
on the cPCI/PCI-7300A if they run in parallel paths at a close distance. To
reduce the magnetic coupling between lines, separate them by a
reasonable distance if they run in parallel, or run the lines at right angles to
each other.

2. Do not run signal lines through conducts that also contain power lines.

3. Protect signal lines from magnetic fields.

Installation • 13

2.8 Daughter Board Supporting

The cPCI/PCI-7300A can be connected with two daughter boards: DIN-100S
or DIN-502S. The functionality and connections are specified as follows.

2.8.1 Connect with DIN-100S

The DIN-100S is a direct connection for the add-on card that is equipped with
SCSI-100 connector. User can connect this daughter board by a 100-pin SCSI
type cable (ACL-102100) to the cPCI/PCI-7300A. It is suitable for the
applications of 32-bit digital input or 32-bit digital output.

2.8.2 Connect with DIN-502S

The DIN-502S with the cable ACL-10252 separates the 100-pin SCSI
connector into two 50-pin SCSI connectors. One 50 pin connector is for pin 1 ~
25 and pin 51~75 of CN1 while the other one is for pin 26 ~ 50 and pin 76~100
of CN1. That means the DIN-502S and the ACL-10252 make users easy to
connect the 16-bit digital inputs and 16-bit digital outputs by using two 50-pin
daughter boards respectively. The independent wiring of 16-bit DI and 16-bit
DO let users convenient to setup and maintain his systems.

14 • Installation

3

Registers

In this chapter, the registers’ format of the cPCI/PCI-7300A is described.
Please note that the registers’ map of the PCI-7300A Rev.B is different from
the PCI-7300A Rev.A

This information is quite useful for the programmers who wish to handle the
card by low-level programming. In addition, users can realize how to use
software driver to manipulate this card after understanding the registers'
structure of the cPCI/PCI-7300A

The cPCI/PCI-7300A functions as a 32-bit PCI master device on the PCI bus.
There are three types of registers on the cPCI/PCI-7300A: PCI Configuration
Registers (PCR), Local Configuration Registers (LCR) and cPCI/PCI-7300A’s
registers.

The PCR, which compliant to the PCI-bus specifications, is initialized and
controlled by the plug & play (PnP) PCI BIOS. User‘s can study the PCI BIOS
specification to understand the operation of the PCR. Please contact with
PCISIG to acquire the specifications of the PCI interface.

The LCR is specified by the PCI bus controller PLX PCI-9080, which is
provided by PLX technology Inc. (www.plxtech.com) . It is not necessary for
users to understand the details of the LCR if you use the software library. The
base address of the LCR is assigned by the PCI PnP BIOS. The assigned
address is located at offset 14h of PCR.

Registers • 15

3.1 I/O Port Base Address

The registers of the cPCI/PCI-7300A are shown in Table 3.1. The base
address of these registers is also assigned by the PCI P&P BIOS. The
assigned base address is stored at offset 18h of the PCR. Therefore, users
can read the PCR to know the base address by using BIOS function call. Note
that the cPCI/PCI-7300A registers are all 32 bits. Users should access these
registers by 32 bits I/O instructions.

The PCI-7300A occupies 8 consecutive 32-bit I/O addresses in the I/O
address space. Table 3.1 shows the I/O Map of the PCI-7300A rev.B.

Legend:

Caution:

1. I/O port is 32-bit width

2. 8-bit or 16-bit I/O access is not allowed.

Address Read Write

Base + 0 DI_CSR DI_CSR
Base + 4 DO_CSR DO_CSR
Base + 8 AUX_DIO AUX_DIO

Base + C INT_CSR INT_CSR
Base + 10 DI_FIFO DI_FIFO
Base + 14 DO_FIFO DO_FIFO
Base + 18 - FIFO_CR
Base + 1C POL_CTRL POL_CTRL
Base + 20 8254_COUNT0 8254_COUNT0
Base + 24 8254_COUNT1 8254_COUNT1
Base + 28 8254_COUNT2 8254_COUNT2

Base + 2C

DI_CSR: Digital input control & status register
DO_SCR: Digital output control & status register
AUX_DIO: Auxiliary digital I/O port
INT_CSR: Interrupt control and status register
DI_FIFO: DI FIFO direct access port
DO_FIFO: DO FIFO direct access port
FIFO_CR: FIFO almost empty/full programming register
POL_CTRL: Polarity control register for the control signals

8254_CONTROL 8254_CONTROL

16 • Registers

3.2 DI_CSR: DI Control & Status Register

Digital input control and status checking is done by this register.

Address: BASE + 00
Attribute:

READ/WRITE

Data Format:

Bit # 3~0 DI_HND_SHK DI_CLK_SEL DI_32

Bit # 7~4 0

Bit # 11~8 DI_FIFO_FULL DI_OVER DI_FIFO_CLR DI_EN
Bit # 15~12 - - - DI-FIFO_EMPTY
Bit # 31~16 Don’t Cared

(1) This bit is different between Rev.A and Rev.B.

DI_32 (R/W)

0: Input port is not 32-bit wide (16-bit or 8-bit wide)
1: Input port is 32-bit wide, PORTB is configured as the extension of PORTA.

That means PORTA is input lines 0…15, and PORTB is input lines 16…31.
All the PORTB control signals are disabled.

DI_CLK_SEL (R/W)

00: use timer0 output as input clock
01: use 20MHz clock as input clock
10: use 10MHz clock as input clock
11: use external clock (DI_REQ) as input clock

DI_HND_SHK (R/W)

0: No handshaking
1: REQ/ACK handshaking mode

DI_WAIT_TRIG (R/W)

0: start input sampling immediately
1: delay input sampling until DITRIG is active

PA_TERM_OFF (R/W)

0: PORTA terminator ON
1: PORTA terminator OFF

DI_EN (R/W)

0: Disable digital inputs
1: Enable digital inputs

PA_TERM_OFF DI_WAIT_TRI

G

-- (1)

Registers • 17