ADLINK Technology, Incorporated makes no representations or warranties with respect to the contents of
this manual or of the associated ADLINK products, and specifically disclaims any implied warranties of
merchantability or fitness for any particular purpose. ADLINK shall under no circumstances be liable for
incidental or consequential damages or related expenses resulting from the use of this product, even if it has
been notified of the possibility of such damages. ADLINK reserves the right to revise this publication from
time to time without obligation to notify any person of such revisions. If errors are found, please contact
ADLINK at the address shown at the bottom of this page.
TRADEMARKS
CoreModule and the Ampro logo are registered trademarks, and ADLINK, Little Board, LittleBoard,
MightyBoard, MightySystem, MilSystem, MiniModule, ReadyBoard, ReadyBox, ReadyPanel,
ReadySystem, and RuffSystem are trademarks of ADLINK Technology, Inc. All other marks are the
property of their respective companies.
REVISION HISTORY
RevisionReason for ChangeDate
1000Initial ReleaseNov/10
1010Replaced N450, D410, and D510 CPUs with N455 and D525; added
JP3 and JP4 to Tab le 2- 3 and removed JP1 (CMOS reset); changed
J10 to J19 in Tab le 3- 10 caption; revised Tab le 3- 9 caption to J10;
revised voltage of battery in Ta ble 3 -17 from 5V to 3.3V; changed
width in Tab le 2- 4 from 3.76" to 3.8"; added heatsink dwg and table;
changed pitch in Tab le 3- 15 to 0.079"; revised Ethernet Interface
description on page 27; added Gb Ethernet controller to table
Tab le 3- 14; revised Appendix A address information
1020Added airflow diagrams to “Thermal/Cooling Requirements” on
page 16; added details to descriptions of Copper and Aluminum
heatsink qualifications in Tab le 2-7 ; changed Serial Console to
Remote Access in Chapter 3; changed voltage of battery header to
This manual provides reference only for computer design engineers, including but not limited to hardware
and software designers and applications engineers. ADLINK Technology, Inc. assumes you are qualified to
design and implement prototype computer equipment.
iiReference ManualCoreModule 745
Contents
Chapter 1About This Manual ....................................................................................................1
Purpose of this Manual ....................................................................................................................1
Appendix ATechnical Support .................................................................................................. 45
Index .................................................................................................................................................. 49
List of Figures
Figure 2-1.Stacking PC/104-Plus Modules with the CoreModule 745 ...................................... 4
Table A-1.Technical Support Contact Information..................................................................45
CoreModule 745Reference Manualv
Contents
viReference ManualCoreModule 745
Chapter 1About This Manual
Purpose of this Manual
This manual is for designers of systems based on the CoreModule® 745 Single Board Computer (SBC). This
manual contains information that permits designers to create an embedded system based on specific design
requirements.
Information provided in this reference manual includes:
•Product Overview
•Hardware Specifications
•BIOS Setup information
•Technical Support Contact Information
Information not provided in this reference manual includes:
•Detailed chip specifications
•Internal component operation
•Internal registers or signal operations
•Bus or signal timing for industry standard busses and signals
•Pinout definitions for industry standard interfaces
References
The following list of references may help you successfully complete your custom design.
•Linear Technology and the LTC1334CG, RS-232/422/485 Serial Port transceiver
Web site: http://www.linear.com/products/rs485%7C422_transceivers
•Analog devices and the ADM213EARSZ, RS-232 Serial Port transceiver
Web site: http://www.analog.com/en/interface/rs-232/adm213e/products/product.h
tml
•Greenliant and the GLS85LP1004P Solid State Drive (SSD)
Web site: http://www.greenliant.com/products/?inode=46780
•Integrated Technology Express, Inc. and the PCI-to-ISA bridge, IT8888G-L
Web site: http://www.iteusa.com
NOTEIf you are unable to locate the datasheets using the links provided, go to the
manufacturer’s web site where you can perform a search using the chip datasheet
number or name listed.
or http://www.ite.com.tw
2Reference ManualCoreModule 745
Chapter 2Product Overview
This introduction presents general information about the PC/104 architecture and the CoreModule 745
Single Board Computer (SBC). After reading this chapter you should understand:
•PC/104 architecture
•Product description
•CoreModule 745 features
•Major components (ICs)
•Headers and Connectors
•Specifications
PC/104 Architecture
The PC/104 architecture affords a great deal of flexibility in system design. You can build a simple system
using only a CoreModule 745 SBC, input/output devices connected to the serial, USB, or SATA ports, and
the on-board Solid State Disk storage device. To expand a simple CoreModule system, simply add selfstacking PC/104 and PC/104-Plus expansion boards to provide additional capabilities, such as:
•Additional serial and parallel ports
•Analog or high-speed digital I/O
Data Acquisition (Analog In/Out)
USB 2.0 expansion modules
IEEE 1394 (FireWire) expansion modules
Standard VGA video output
PC/104 or PC/104-Plus expansion modules can be stacked with the CoreModule 745 avoiding the need for
large, expensive card cages and backplanes. The PC/104-Plus expansion modules can be mounted directly to
the PC/104 and PC/104-Plus connectors of the CoreModule 745. PC/104-compliant modules can be stacked
with an inter-board spacing of ~0.6 inches, so that a 3-module system fits in a 3.6" x 3.8" x 2.4" space. See
Figure 2-1.
One or more MiniModule products or other PC/104 modules can be installed on the CoreModule expansion
connectors, so that the expansion modules fit within the CoreModule outline dimensions. Most MiniModule
products have stackthrough connectors compatible with the PC/104-Plus Version 2.0 specification. Several
modules can be stacked on the CoreModule headers. Each additional module increases the thickness of the
package by ~17mm (0.66"). See Figure 2-1.
CoreModule 745Reference Manual3
Chapter 2Product Overview
CM745stackthru
Nuts (4)
or Chassis Standoffs
ISA Bus
Stackthrough
Connectors
Expansion
0.6 inch Spacers (4)
PCI Stack
Connectors
through
Screws (4)
0.6 inch Spacers (4)
PC/104 Module
0.6 inch Spacers (4)
PCI Stack
Connectors
through
PC/104-Plus Module
CoreModule 745
Figure 2-1. Stacking PC/104-Plus Modules with the CoreModule 745
Product Description
The CoreModule 745 SBC is an exceptionally high integration, high performance, Intel Atom™ N455 or
D525 processor based system, compatible with the PC/104 standard. This rugged and high quality singleboard system contains all the component subsystems of an ATX motherboard plus the equivalent of several
PCI expansion boards.
The Intel Atom N400 and D500 series CPUs integrate processor cores with Graphics and Memory Hubs
(GMHs), providing low-power, high-performance processors, memory controllers for up to 2GB DDR3
memory, and graphics controllers which provide LVDS and VGA signals for most LCD video panels and
CRT monitors.
The ICH8-M chipset provides controllers for the I/O Hub (Southbridge) featuring four USB ports, two
SATA ports, one Ultra DMA 33/66/100 IDE port supporting two IDE devices, one SMBus port, one SPI
port, one GPIO port, one PCIe bus for Gigabit Ethernet, and one PCI bus for PC/104 and PC/104-plus
devices. The CoreModule 745 provides legacy interfaces through the SMSC SCH3112I-NU Super I/O
featuring three serial ports and a PS/2 keyboard and mouse port.
The CoreModule 745 can be expanded through the PCI expansion bus using the PC/104 and PC/104-Plus
connectors for additional system functions. This bus offers compact, self-stacking, modular expandability.
The PC/104 bus is an embedded system version of the signal set provided on a desktop PC’s ISA bus. The
PC/104-Plus bus includes this signal set plus additional signals implementing a PCI bus, available on a
120-pin (4 rows of 30 pins) PCI expansion bus connector. This PCI bus operates at a clock speed of 33MHz.
The CoreModule 745 is particularly well suited to either embedded or portable applications and meets the
size, power consumption, temperature range, quality, and reliability demands of embedded system
applications. It can be stacked with ADLINK MiniModules™ or other PC/104-compliant expansion
modules, or it can be used as a powerful computing engine. The CoreModule 745 requires a single +5V AT
power source.
4Reference ManualCoreModule 745
Chapter 2Product Overview
Module Features
•CPU
Provides an Intel Atom 1.67GHz N455 or 1.83GHz D525 processor core
DMI (Direct Media Interface) with 1 GB/s of bandwidth in each direction
Enhanced SpeedStep® technology
On die 512-kB, 8-way L2 cache
•Memory
Single standard 204-pin DDR3 SODIMM socket
Supports +1.5V DDR3, 800MHz RAM up to 2GB
Supports non-ECC, unbuffered memory
•Interface Buses
PC/104 and PC/104-Plus Interfaces
PC/104 bus speeds up to 8MHz (16-bit ISA Bus)
PC/104-Plus bus speed at 33MHz (32-bit PCI Bus)
PCI 2.2 compliant
•IDE Channel
Supports one enhanced IDE controller
Supports on-board Solid State Drive (SSD) with default 4GB capacity
•SATA
Supports two SATA ports from the ICH8-M I/O Hub
Provides two standard SATA connectors
•Serial Ports
Provide three buffered serial ports with full handshaking
Provide 16550-equivalent controllers, each with a built-in 16-byte FIFO buffer
Support full modem capability
Support RS-232 operation
Support RS-232, RS-485, or RS-422 operation on two ports (COM1 and COM2)
Support programmable word length, stop bits, and parity
Support 16-bit programmable baud-rate generator and an interrupt generator
•USB Interface
Provides two root USB hubs
Provides up to four USB ports
Supports USB boot devices
Supports USB v2.0 EHCI and v1.1 UHCI
Supports over-current detection status
•Keyboard/Mouse Interface
Provides PS/2 keyboard interface
Provides PS/2 mouse interface
CoreModule 745Reference Manual5
Chapter 2Product Overview
•Ethernet Interface
Provides one fully independent Ethernet port
Provides integrated LEDs (Link/Activity and Speed)
Provides one Intel 82574IT controller chips
Provides header for LAN LED signals (gigabit only)
Supports IEEE 802.3 10/100BaseT and 10/100/1000BaseT compatible physical layers
Supports Auto-negotiation for speed, duplex mode, and flow control
Supports full duplex or half-duplex mode
•Full-duplex mode supports transmit and receive frames simultaneously
•Supports IEEE 802.3x Flow control in full duplex mode
Provide VGA outputs (resolutions up to 1400x1050 @ 60Hz for the N455 CPU and 2048x1536 @
60Hz for the D525 CPU)
Provide LVDS flat panel outputs (resolutions up to 1280x800 for the N455 CPU and 1366x768 for
the D525 CPU) [single channel, three differential signals]
•Utility Interface
Power Button
Reset Switch
Speaker
•Miscellaneous
Battery-less boot
Oops! Jumper support
Remote Access support
Watchdog Timer
Logo Screen (Splash)
6Reference ManualCoreModule 745
Chapter 2Product Overview
CM745BlkDiag_b
PC/104
PCI to ISA
Connector
Bridge
IT8888G-L
CPU
Intel Atom 1.67GHz
N455 or 1.83GHz D525
(with integrated
Northbridge)
PC/104-Plus
Connector
I/O Hub
Intel
ICH8-M
(Southbridge)
PS/2
Keyboard/
Mouse
Header
Super I/O
SCH3112I-NU
DDR3
SODIMM
Video Header
VGA
LVDS
Memory Bus
ISA Bus
LPC Bus
COM2
Header
(RS-232/485/422)
COM1
Header
(RS-232/485/422)
RS-232
Transceiver
(COM1
and COM2)
RS-485/422
Transceiver
(COM1
and COM2)
PCI Bus
DMI
USB
Header
USB
Header
USB (2)
USB (2)
Serial 1
Serial 2
Serial 3
PS/2
SPI Flash
GPIO
Header
SATA
SATA
IDE
SMBus
SPI
GPIO
SMBus
Header
Utility Header
Solid State
Drive
SATA 0
Connector
SATA 1
Connector
RS-232
Transceiver
(COM3)
COM3
Header
(RS-232)
Magnetics
Gigabit Ethernet
Controller
82574IT
Gigabit Ethernet
Header
MDI
PCIe Bus
Block Diagram
Figure 2-2 shows the functional components of the CoreModule 745.
Figure 2-2. Functional Block Diagram
CoreModule 745Reference Manual7
Chapter 2Product Overview
Major Component (ICs) Definitions
Table 2- 1 lists the major ICs, including a brief description of each, on the CoreModule 745. Figures 2-3 and
2-4 show the locations of the major ICs.
Table 2-1. Major Component Descriptions and Functions
Chip TypeMfg.ModelDescriptionFunction
CPU (U1)IntelAtom N455 or D5251.67GHz or 1.83GHz
processor with 8-way
L2 cache
I/O Hub (U2)Intel82801HBM
(ICH8-M)
Gigabit Ethernet
Controller (U4)
PCI-to-ISA Bridge
(U8)
Super I/O Hub
(U9)
RS-232 Transceiver
(U11 - on bottom
side) [see Figure 2-4]
RS-422/485
Transceiver (U12 on bottom side) [see
Figure 2-4]
CPLD (U17 - on
bottom side) [see
Figure 2-4]
SPI Flash (U32) - on
bottom side [see
Figure 2-4]
SSD (Solid State
Drive, U33 - on
bottom side [see
Figure 2-4])
Intel82574ITGigabit Ethernet
ITEITE8888G-LInterface between PCI
SMSCSCH3114I-NUSuper I/O controllerProvides
Analog
Devices
Linear
Technology
XilinxXC9536XLComplex
WinbondW25Q64BVSSIGSerial Peripheral
GreenliantGLS85LP1004PIndustrial-grade,
ADM213EARSZTransceiver for Serial 1
LTC1334CGTransceiver for Serial 1
I/O Hub for some
common user
interfaces
controller
bus and ISA bus
and Serial 2 RS-232
signals
and Serial 2 RS-485/
422 signals
Programmable Logic
Device (not user
programmable)
Interface Flash
Memory chip (for
firmware)
soldered solid-state
storage module
Integrates
Processor core
and Graphics
Memory
Controller Hub
Provides
Southbridge
interfaces and
off loads some
Northbridge
functions from
the CPU
Generates PCIe
10T/100TX/
1000T Ethernet
signals
Migrates legacy
ISA bus
complete legacy
Super I/O
functionality
Transmits and
receives RS-232
signals for
COM1 and
COM2
Transmits and
receives RS485/422 signals
for COM1 and
COM2
Provides control
for Power
Sequencing
Stores BIOS in
Flash Memory
Provides solid
state storage
through the IDE
channel
8Reference ManualCoreModule 745
Chapter 2Product Overview
CM745_Top_Comp_b
Key:
U1 - CPU
U2 - ICH8-M (Southbridge)
U4 - Gigabit Ethernet Controller
U8 - PCI-to-ISA Bridge
U9 - Super I/O
U33 - SSD (Solid State Drive)
T1 - Gigabit Ethernet Transformer
U1
U2
U4
T1
U8
U9
U33
Table 2-1. Major Component Descriptions and Functions (Continued)
RS-232 Transceiver
(U38 - on bottom
side) [see Figure 2-4]
Analog
Devices
ADM213EARSZTransceiver for Serial 3
RS-232 signals
Transmits and
receives RS-232
signals for
COM3
Ethernet Transformer
(T1)
Wurth
Elektronik
7490200110Gigabit Ethernet
Magnetics
Provides
electrical
isolation for
Gigabit Ethernet
controller
Table 2- 2 describes the headers and connectors of the CoreModule 745 shown in Figure 2-6.
Table 2-2. Module Header, Connector, and Socket Descriptions
Header #Board
J1 A, B, C, D –
PC/104-Plus
J2 A, B, C, D –
PC/104
J3 – COM1 SerialTop10-pin, 0.079" (2mm) shrouded header used for COM1 signals
J4 – COM2 SerialTop10-pin, 0.079" (2mm) shrouded header used for COM2 signals
J5 – COM3 SerialTop10-pin, 0.079" (2mm) shrouded header used for COM3 signals
J6 – BatteryTop2-pin, 0.049" (1.25mm) shrouded header for power from external
Figure 2-4. Component Locations (Bottom Side)
Description
Access
Top/Bottom120-pin, 0.079" (2mm) connector used for PC/104-Plus signals
Top/Bottom104-pin, connector used for PC/104 signals
battery
10Reference ManualCoreModule 745
Chapter 2Product Overview
1
234
5
678910
2030
1929
30-pin, two rows,
Odd/Even, (1, 2)
CM745_ConNum_b
Table 2-2. Module Header, Connector, and Socket Descriptions (Continued)
J7 – PowerTop10-pin, 0.100" (2.54mm), right-angle, shrouded header used for
external power connection
J8 – SATA0Top7-pin, 0.050" (1.27mm) standard connector used for SATA devices
J9 – SATA1 Top7-pin, 0.050" (1.27mm) standard connector used for SATA devices
J10 – EthernetTop10-pin, 0.079" (2mm) shrouded header used for Gigabit Ethernet
signals
J11 – Ethernet LEDTop4-pin, 0.049" (1.25mm) shrouded header used for Gigabit Ethernet
LED signals
J12 – NSBottomNot Supported
J14 – DNPTopDo Not Populate
J15 – Keyboard/MouseTop10-pin, 0.079" (2mm), shrouded header for PS/2 keyboard and
mouse signals
J16 – USB0 and USB1Top10-pin, 0.079" (2mm), shrouded header for USB0 and USB1
signals
J17 – USB2 and USB3Top10-pin, 0.079" (2mm), shrouded header for USB2 and USB3
signals
J18 – GPIOTop10-pin, 0.079" (2mm) header for General Purpose IO signals
J19 – VideoTop30-pin, 0.079" (2mm), shrouded header for LVDS and VGA video
signals
J20 – SMBUSTop5-pin, 0.079" (2mm), single-row header for SMBus signals
J22 – FanTop3-pin, 0.079" (2mm), shrouded header for System Fan signals
J23 – UtilityTop5-pin, 0.100" (2.54mm), single-row header for Power Button,
Reset Switch, and Speaker signals
J24 – DDR3 SODIMMTop204-pin, standard socket for DDR3 SODIMM
NOTEThe pinout tables in Chapter 3 of this manual identify pin sequence using the
following method: A 30-pin header with two rows of pins, using odd/even
numbering, where pin 2 is directly across from pin 1, is noted as 30-pin, 2 rows, odd/
even (1, 2) sequence. The second number in the parenthesis is always directly across
from pin 1. See Figure 2-5.
Figure 2-5. Connector Pin Sequences
CoreModule 745Reference Manual11
Chapter 2Product Overview
CM745_Top_Conn_b
Key:
J1 - PC/104 Plus
J2 - PC/104
J3 - Serial COM1
J4 - Serial COM2
J5 - Serial COM3
J6 - Battery
J7 - Power
J8 - SATA0
J9 - SATA1
J10 - Gigabit Ethernet
J11 - Gigabit Ethernet LED
J12 - Not supported (On bottom side)
J14 - Do Not Populate
J15 - Keyboard and Mouse
J16 - USB0 and USB1
J17 - USB2 and USB3
J18 - GPIO
J19 - Video (LVDS and VGA)
J20 - SMBus
J22 - Fan
J23 - Utility
J24 - DDR3 SODIMM
JP2 - LVDS Voltage Select (See jumper table)
JP3 - Serial 2 RS-485/422 Termination (See jumper table)
JP4 - Serial 1 RS-485/422 Termination (See jumper table)
J20
J11
J14
JP2
J23
J22
J7
J9J8
J18J6
JP3
JP4
J4J3J15J19
J5
J10
J16
J17
J1
J2
J24
DCBA
BA
CD
Figure 2-6. Header, Connector, and Socket Locations (Top Side)
12Reference ManualCoreModule 745
Chapter 2Product Overview
CM745_Top_Jmpr_b
Key:
JP2 - LVDS Voltage Select
JP3 - Serial 2 RS-485/422 Termination
JP4 - Serial 1 RS-485/422 Termination
JP2
JP3
JP4
Jumper Header Definitions
Table 2- 3 describes the jumper headers shown in Figure 2-7. All jumper headers provide 0.079" (2mm)
pitch.
Table 2-3. Jumper Settings
Jumper HeaderInstalledRemoved/Installed
JP2 – LVDS Voltage SelectionEnable +3.3V (Pins 1-2)
[Default]
JP3 – Serial 2 RS-485/422
Termination
JP4 – Serial 1 RS-485/422
Termination
Enable Termination
(Pins 1-2)
Enable Termination
(Pins 1-2)
Enable +5V (Pins 2-3)
Disable Termination (Removed)
[Default]
Disable Termination (Removed)
[Default]
Figure 2-7. Jumper Header Locations (Top Side)
CoreModule 745Reference Manual13
Chapter 2Product Overview
Specifications
Physical Specifications
Table 2- 4 provides the physical dimensions of the CoreModule 745.
Table 2-4. Weight and Footprint Dimensions
ItemDimension
Weight0.12 kg (0.25 lbs)
Height (overall)11.05 mm (0.435 inches)
Board thickness2.362 mm (0.093 inches)
Width 96.01 mm (3.78 inches)
Length 115.57 mm (4.55 inches)
NOTEOverall height is measured from the
upper board surface to the highest
permanent component (PC/104 bus
connector) on the upper board surface.
This measurement does not include the
heatsink, which can vary. The heatsink
could increase this dimension.
Component height should not exceed
0.345" (8.763mm) from the upper
surface of the board and 0.190"
(4.826mm) from the lower surface of the
board. See Figure 2-9 for the stack
heights of the heatsinks on the board.
14Reference ManualCoreModule 745
Chapter 2Product Overview
CM745_Top_Dmn_b
0.00
0.00
0.20 (5.08mm)
0.50 (12.7mm)
2.06 (52.45mm)
3.35 (85.09mm)
3.55 (90.17mm)
4.05 (102.87mm)
3.55 (90.17mm)
3.25 (82.55mm)
0.35 (8.89mm)
0.50 (12.70mm)
0.20 (5.09mm)
0.33 (8.26mm)
1.66 (42.04mm)
3.45 (87.63mm)
3.58 (90.81mm)
3.78 (95.89mm)
0.00
Mechanical Specifications
Figure 2-8. Mechanical Overview (Top Side)
NOTEAll dimensions are given in inches. Pin 1 is shown as a black square on headers and
connectors. Black squares on right-angle headers indicate pin 2 in top-side views and
pin 1 in bottom-side views.
CoreModule 745Reference Manual15
Chapter 2Product Overview
Power Specifications
Table 2- 5 provides the power requirements for the CoreModule 745.
Input TypeRegulated DC voltagesRegulated DC voltages
Typical In-rush Current
(Peak)
Typical Idle Current1.59A (7.96W)2.20A (10.98W)
BIT Current 2.76A (13.82W)3.73A (18.65W)
Operating configurations:
8.00A (40.00W)8.00A (40.00W)
•In-rush operating configuration includes video, 2GB DDR3 RAM, and power.
•Idle operating configuration includes In-rush configuration as well as connected one external SATA
HDD (Windows XP), one PS/2 keyboard, and one PS/2 mouse.
•BIT (Burn-In-Test) operating configuration includes Idle configuration as well as a second SATA HDD,
one Ethernet connection, two USB loop-back testers, one external USB CF reader, one USB flash
thumb drive, and three serial loop backs.
Environmental Specifications
Table 2- 6 provides the most efficient operating and storage condition ranges required for this module.
Table 2-6. Environmental Requirements
ParameterConditions
Temperature
Operating–20° to +70° C (–4° to +158° F)
Extended (Optional)–40° to +85° C (–40° to +185° F)
Storage –55° to +85° C (–67° to +185° F)
Humidity
Operating5% to 90% relative humidity, non-condensing
Non-operating5% to 95% relative humidity, non-condensing
Thermal/Cooling Requirements
The CPU and PCH are the primary sources of heat on the board. The CoreModule 745 is designed to operate
at the maximum speed of the CPU and requires various cooling solutions, depending on the CPU model. See
Table 2- 7 for descriptions of the cooling solution options. Figure 2-10 provides simulation charts of airflow
requirements for both heatsinks.
16Reference ManualCoreModule 745
Chapter 2Product Overview
0.39
0.44
0.60
Copper Passive Heatsink
Fan
CoreModule 745
CoreModule 745
CoreModule 745
0.11
1.50
0.98
Active Heatsink
0.39
0.44
0.60
Aluminum Passive Heatsink
Table 2-7. ADLINK Optional Cooling Solutions
Cooling SolutionDescription
Passive Heatsink - Copper
(without fan)
Qualified to maintain optimal performance between -40°C and +85°C.
CPU throttles to 1000MHz. (Note: The D525 CPU is qualified only for
-20°C to +70°C with a copper heatsink.)
Passive Heatsink - Aluminum
(without fan)
Qualified to maintain optimal performance between -20°C and +70°C.
Airflow requirement: 2 m/s. (Note: The D525 CPU is not qualified to
use an aluminum heatsink.)
Active Heatsink
(with fan)
Qualified to maintain optimal performance between -40°C and +85°C.
(Note: The D525 CPU requires an active heatsink for temperatures
between +70°C and +85°C.)
Figure 2-9. Stack Height of Cooling Assembly
NOTEAll heights are given in inches.
CoreModule 745Reference Manual17
Chapter 2Product Overview
Figure 2-10. Airflow Requirements
NOTE Airflow directions are from Top to Bottom.
18Reference ManualCoreModule 745
Chapter 3Hardware
Overview
This chapter discusses the chips and connectors of the module features in the following order:
•CPU
•Graphics
•Memory
•Interrupt Channel Assignments
•Memory Map
•I/O Address Map
•Serial Port Interfaces
•USB Interfaces
•Keyboard and Mouse Interface
•Ethernet Interface
•Video Interface
VGA
LV DS
•Power Interface
•GPIO Interface
•Utility Interface
Power Button
Reset Switch
Speaker
•SMBus Interface
•System Fan Interface
•Battery Interface
•Ethernet LED Interface
•Miscellaneous
SSD (IDE Solid State Drive)
Time of Day/RTC
Oops! Jumper
Remote Access
Watchdog Timer
CoreModule 745Reference Manual19
Chapter 3Hardware
NOTEADLINK Technology, Inc. only supports the features/options tested and listed in
this manual. The main chips used in the CoreModule 745 may provide more
features or options than are listed for the CoreModule 745, but some of these
features/options are not supported on the module and will not function as
specified in the chip documentation.
The pin-out tables only of non-standard headers and connectors are included in
this chapter. This chapter does not include pinout tables for standard headers and
connectors such as SATA, PC/104, and PC/104-Plus. Refer to references in
Chapter 1 for PC/104 and PC/104 Plus pin outs.
CPU
The CoreModule 745 offers two versions of the Intel Atom™ N400/D500 series CPU—the N455 and
D525—operating at 1.67GHz with 6.5W TDP, and 1.83GHz with 13W TDP, respectively. The N400/D500
integrates a low-power and high-performance x86 Processor Core with Memory Controller and 3D Graphics
Engine. This single chip is based on 45-nm, Hi-K process technology, ideal for deeply embedded
applications.
Graphics
The N400/D500 CPU provides a refresh of the Intel third generation graphics core—a 2D/3D graphics
engine that performs pixel shading and vertex shading within a single hardware accelerator, which
minimizes access to memory and improves render performance.
Memory
The CoreModule 745 supports one DDR3 SODIMM for up to 2GB of RAM. One 64-bit access channel
supports single- or double-sided DIMMs, allowing for up to two device ranks. Enhanced memory
technology on the board provides optimized bandwidth and reduced latency, increased efficiency of system
memory protocol, and a near continuous data flow to the processor.
20Reference ManualCoreModule 745
Chapter 3Hardware
Interrupt Channel Assignments
The interrupt channel assignments are shown in Table 3-1.
Table 3-1. Interrupt Channel Assignments
Device vs IRQ No.0123456789101112131415
Timer X
PS/2 KeyboardX
Secondary CascadeX
COM1OD
COM2DO
COM3OD
RTCX
IDED
Math CoprocessorX
PS/2 MouseX
PCI INTAAutomatically Assigned
PCI INTBAutomatically Assigned
PCI INTCAutomatically Assigned
PCI INTDAutomatically Assigned
USBAutomatically Assigned
VideoAutomatically Assigned
Legend: D = Default, O = Optional, X = Fixed
NOTEThe IRQs for USB and Video are automatically assigned by the BIOS Plug and
Play logic. Local IRQs assigned during initialization can not be used by external
devices.
Memory Map
The following table provides the common PC/AT memory allocations. These are DOS-level addresses. The
OS typically hides these physical addresses by way of memory management.
Table 3-2. Memory Map
Base AddressFunction
00000000h -0009FFFFhConventional Memory
000A0000h -000AFFFFhGraphics Memory
000B0000h -000B7FFFhMono Text Memory
000B8000h -000BFFFFhColor Text Memory
000C0000h -000CFFFFhStandard Video BIOS
000D0000h -000DFFFFhDVMT Memory
000E0000h -000EFFFFhPCI Express Base Memory
000F0000h -000FFFFFhSystem Flash and PCI Resources
CoreModule 745Reference Manual21
Chapter 3Hardware
I/O Address Map
Table 3- 3 shows the I/O address map. These are DOS-level addresses. The OS typically hides these physical
NOTE0A79h is the ISA PnP port used by the BIOS and an OS that supports this feature to
recognize ISA PnP (Plug and Play) cards.
The Intel I/O hub ICH-8 (ICH-6 or later) does not support ISA DMA.
22Reference ManualCoreModule 745
Chapter 3Hardware
CM745RS485jump_b
Or
1
35
7
9
24
6810
Serial Ports
COM1 and COM2
(J3 and J4)
Standard DB9 Serial
Port Connector (Female)
Rear View
5
4
3
2
1
9
8
7
6
Serial Interfaces
The CoreModule 745 provides three serial ports: two RS-232/485/422 ports (COM1 and COM2) and one
RS-232 port (COM3). The SCH3114I-NU SIO contains the circuitry for all three serial ports and delivers
the signals through three transceivers. The two RS-232/485/422 ports require two transceivers: one
ADM213EARSZ (U11) for RS-232 signals and one LTC1334CG (U12) for RS-485/422 signals. The third
serial port requires only one ADM213EARSZ transceiver (U38) for RS-232 signals. The serial ports support
the following features:
J3 - Serial Port 1 (COM1) supports RS-232/RS-485/RS-422 and full modem support
J4 - Serial Port 2 (COM2) supports RS-232/RS-485/RS-422 and full modem support
J5 - Serial Port 3 (COM3) supports RS-232 and full modem support
NOTEThe RS-485/RS-422 mode can be selected for the COM1 and COM2 serial ports
in BIOS Setup under the Advanced>Super IO Configuration menu. However,
the RS-232 mode is the default selection (Standard) for any serial port.
To implement the two-wire RS-485 mode on any serial port, you must tie together the equivalent pins for
each port.
For example, on Serial Port 1, tie pin 3 to 5 and pin 4 to 6 at the J3 header as shown in Figure 3-1. As an
alternate, tie pin 2 to 3 and pin 7 to 8 at the DB9 serial connector for Serial Port 1 as shown in Figure 3-1.
Refer also to the following tables for the specific pin signals on each connector.
NOTEThe RS-422 mode uses a four-wire interface and does not require any pins tied
together, but you must select RS-485 in BIOS Setup and make sure the
termination jumper is removed.
Figure 3-1. RS485 Serial Port Implementation
CoreModule 745Reference Manual23
Chapter 3Hardware
Table 3- 4 defines the pins and corresponding signals for serial ports 1 and 2 headers (J3 and J4), which each
consist of 10 pins, 2 rows, odd/even sequence (1, 2), and 0.079" (2mm) pitch.
Table 3-4. Serial Ports 1 & 2 Interface Pin Signal Descriptions (J3 and J4)
Pin #SignalDB9 #Description
1DCD*1Data Carrier Detect – Indicates external serial device is detecting a
carrier signal (i.e., a communication channel is currently open). In direct
connect environments, this input is driven by DTR as part of the
DTR/DSR handshake.
2DSR*6Data Set Ready – Indicates external serial device is powered, initialized,
and ready. Used as hardware handshake with DTR for overall readiness.
3RXD
2Receive Data – Serial port receive data input is typically held at a logic 1
(mark) when no data is being transmitted, and is held “Off” for a brief
interval after an “On” to “Off” transition on the RTS line to allow the
transmission to complete.
Rx Data –
4RTS*
7Request To Send – Indicates serial port is ready to transmit data. Used as
Serial Port 1 or 2 – If in RS-485 mode, this pin is Rx Data Negative.
hardware handshake with CTS for low level flow control.
Tx Data +
5TXD
3Transmit Data – Serial port transmit data output is typically held to a
Serial Port 1 or 2 – If in RS-485 mode, this pin is Tx Data Positive.
logic 1 when no data is being sent. Typically, a logic 0 (On) must be
present on RTS, CTS, DSR, and DTR before data can be transmitted on
this line.
Tx Data –
6CTS*
8Clear To Send – Indicates external serial device is ready to receive data.
Serial Port 1 or 2 – If in RS-485 mode, this pin is Tx Data Negative.
Used as hardware handshake with RTS for low level flow control.
Rx Data +
Serial Port 1 or 2 – If in RS-485 mode, this pin is Rx Data Positive.
7DTR*4Data Terminal Ready – Indicates serial port is powered, initialized, and
ready. Used as hardware handshake with DSR for overall readiness.
8RI*9Ring Indicator – Indicates external serial device is detecting a ring
condition. Used by software to initiate operations to answer and open the
communications channel.
9
GND5Ground
10Key/NCNCKey Pin/Not connected
Note: The shaded table cell denotes power or ground. The * symbol indicates the signal is Active Low.
24Reference ManualCoreModule 745
Chapter 3Hardware
Table 3- 5 describes the pin signals of the serial port 3 header, which consists of 10 pins, two rows, odd/even
(1, 2) pin sequence, and 0.079" (2mm) pitch.
Table 3-5. Serial Port 3 Interface Pin Signal Descriptions (J5)
Pin #SignalDB9 #Description
1DCD*1Data Carrier Detect – Indicates external serial device is detecting a
carrier signal (i.e., a communication channel is currently open). In direct
connect environments, this input is driven by DTR as part of the
DTR/DSR handshake.
2DSR*6Data Set Ready – Indicates external serial device is powered, initialized,
and ready. Used as hardware handshake with DTR for overall readiness.
3RXD2Receive Data – Serial port receive data input is typically held at a logic 1
(mark) when no data is being transmitted, and is held “Off” for a brief
interval after an “On” to “Off” transition on the RTS line to allow the
transmission to complete.
4RTS*7Request To Send – Indicates serial port is ready to transmit data. Used as
hardware handshake with CTS for low level flow control.
5TXD3Transmit Data – Serial port transmit data output is typically held to a
logic 1 when no data is being sent. Typically, a logic 0 (On) must be
present on RTS, CTS, DSR, and DTR before data can be transmitted on
this line.
6CTS*8Clear To Send – Indicates external serial device is ready to receive data.
Used as hardware handshake with RTS for low level flow control.
7DTR*4Data Terminal Ready – Indicates serial port is powered, initialized, and
ready. Used as hardware handshake with DSR for overall readiness.
8RI*9Ring Indicator – Indicates external serial device is detecting a ring
condition. Used by software to initiate operations to answer and open the
communications channel.
9
10Key/NCNCKey Pin – Not connected
GND5Ground
Note: The shaded table cell denotes power or ground. The * symbol indicates the signal is Active Low.
USB Interface
The CoreModule 745 contains two root USB hubs and four functional USB ports. The ICH8-M provides the
USB function including the following features:
•Supports USB v.2.0 EHCI and USB v.1.1 UHCI
•Provides over-current detection status
•Provides a fuse on board for over current protection
Table 3- 6 describes the pin signals of the USB0 and USB1 header which consists of 10 pins, in two rows,
with odd/even (1, 2) pin sequence, and 0.079" (2mm) pitch.
Table 3-6. USB0 and USB1 Interface Pin Signals (J16)
Pin #SignalDescription
1
2
3CONN_USB0_NUSB0 Port Data Negative
CoreModule 745Reference Manual25
USB-PWR_0USB0 Power – VCC (+5V +/-5%) power goes to the port through an
on-board fuse. Port is disabled if this input is low.
USB-PWR_1USB1 Power – VCC (+5V +/-5%) power goes to the port through an
on-board fuse. Port is disabled if this input is low.
Chapter 3Hardware
Table 3-6. USB0 and USB1 Interface Pin Signals (J16) (Continued)
4CONN_USB1_NUSB1 Port Data Negative
5CONN_USB0_PUSB0 Port Data Positive
6CONN_USB1_PUSB1 Port Data Positive
7
8
9
10
Note: The shaded table cells denote power or ground.
Table 3- 7 describes the pin signals of the USB2 and USB3 header, which consists of 10 pins in two rows,
with odd/even (1, 2) pin sequence, and 0.079" (2mm) pitch.
Table 3-7. USB2 and USB3 Interface Pin Signals (J17)
Pin #SignalDescription
1
2
3CONN_USB2_NUSB2 Port Data Negative
4CONN_USB3_NUSB3 Port Data Negative
5CONN_USB2_PUSB2 Port Data Positive
6CONN_USB3_PUSB3 Port Data Positive
7
8
9
10
USB_GND0USB0 Ground
USB_GND1USB1 Ground
USB_GND0USB0 Ground
USB_GND1USB1 Ground
USB-PWR_2USB2 Power – VCC (+5V +/-5%) power goes to the port through an
on-board fuse. Port is disabled if this input is low.
USB-PWR_3USB3 Power – VCC (+5V +/-5%) power goes to the port through an
on-board fuse. Port is disabled if this input is low.
USB_GND2USB2 Ground
USB_GND3USB3 Ground
USB_GND2USB2 Ground
USB_GND3USB3 Ground
Note: The shaded table cells denote power or ground.
Keyboard/Mouse Interface
The SCH3114I-NU super I/O provides the signals for the PS/2 keyboard and mouse header.
Table 3- 8 describes the pin signals of the keyboard/mouse header, which consists of 10 pins in two rows
with odd/even (1, 2) pin sequence, and 0.079" (2mm) pitch.
Note: The shaded table cells denote power or ground.
KEY GNDKeyboard ground
Ethernet Interface
The CoreModule 745 supports one Gigabit Ethernet interface. The Ethernet interface is implemented from
the 82574IT Ethernet controller and provides one GLAN interface, which occupies PCI Express port 2. The
Ethernet function supports multi-speed operation at 10/100/1000 Mbps and operates in full-duplex at all
supported speeds or half duplex at 10/100 Mbps while adhering to the IEEE 802.3x flow control
specification.
The Ethernet interface offers the following features:
•Full duplex or half duplex support at 10 Mbps, 100 Mbps, or 1000 Mbps
•In full duplex mode, the Ethernet controller adheres to the IEEE 802.3x Flow Control specification
•In half duplex mode, performance is enhanced by a proprietary collision reduction mechanism
•IEEE 802.3 compatible physical layer to wire transformer
•IEEE 802.3u Auto-Negotiation support
•Fast back-to-back transmission support with minimum interframe spacing (IFS)
•IEEE 802.3x auto-negotiation support for speed and duplex operation
Table 3- 9 describes the pin signals of the Ethernet header which consists of 10 right-angle pins, two rows,
odd/even (1,2) pin sequence, and 0.079" (2mm) pitch.
Table 3-9. Ethernet Interface Pin Signal Descriptions (J10)
Pin #SignalDescription
1
2
3MDI0+Media Dependent Interface 0 +/-
4MDI0-
5MDI1+Media Dependent Interface 1 +/-
6MDI1-
7MDI2+Media Dependent Interface 2 +/-
8MDI2-
9MDI3+Media Dependent Interface 3 +/-
10MDI3-
Note: The shaded table cells denote ground.
GNDGround
GND
NOTEThe magnetics (isolation transformer, T1) for the Ethernet header is included on
the CoreModule 745.
CoreModule 745Reference Manual27
Chapter 3Hardware
Video (VGA/LVDS) Interface
The CPU provides the graphics control and video signals to the traditional glass CRT monitors and LCD flat
panel displays. The video features are listed below:
VGA features:
•Supports maximum resolutions of 1400x1050 at 60Hz or 2048x1536 at 60Hz
•Provides 2D registers for added color, depth, resolution, and hardware acceleration
•Provides integrated 3 x 8-bit DAC with R, G, and B signals to the monitor
LVDS features:
•Integrated single LVDS channel supporting resolution up to 1280x800 or 1366x768
•Supports 1 x 18 data format
•Supports transmit clock frequency ranges from 25 MHz to 112 MHz
Table 3-10 lists the pin signals of the video (LVDS/VGA) header, which provides 30 pins, 2 rows, odd/even
pin sequence (1, 2) with 0.079" (2mm) pitch.
Table 3-10. Video Interface Pin Signals (J19)
Pin #SignalDescription
1
2
3
4
5LA_CLK_PLVDS Clock Positive
6LA_CLK_NLVDS Clock Negative
7LA_DAT2_PLVDS DATA Positive Line 2
8LA_DAT2_NLVDS DATA Negative Line 2
9LA_DAT1_PLVDS DATA Positive Line 1
10LA_DAT1_NLVDS DATA Negative Line 1
11LA_DAT0_PLVDS DATA Positive Line 0
12LA_DAT0_NLVDS DATA Negative Line 0
13LBKLT_CTLPanel Backlight Control
14LVDD_ENEnable Panel Power
15LDDC_CLKDisplay Data Channel Clock
16LDDC_DATADisplay Data Channel Data
17LBKLT_ENEnable Backlight Inverter
18NCNot Connected
19CON_DAC_SDADigital to Analog Converter DDC (Display Data Channel) - Data
20CON_DAC_SCLDigital to Analog Converter DDC (Display Data Channel) - Clock
21CON_DAC_REDDigital to Analog Converter – Red Output to the CRT
22
23CON_DAC_GREENDigital to Analog Converter – Green Output to the CRT
24
25CON_DAC_BLUEDigital to Analog Converter – Blue Output to the CRT
26
27CRT_HSYNCHorizontal Sync – Digital Horizontal Sync Output to the CRT
+12V+12 volts for flat panel and backlight
VCC_LVDS_CONNJP2 determines LVDS voltage (+3.3V or +5V)
GNDGround
GNDGround
RED_RETURNVGA Ground for Red Output
GREEN_RETURNVGA Ground for Green Output
BLUE_RETURNVGA Ground for Blue Output
28Reference ManualCoreModule 745
Chapter 3Hardware
Table 3-10. Video Interface Pin Signals (J19) (Continued)
Pin #SignalDescription
28
29CRT_VSYNCVertical Sync – Digital Vertical Sync Output to the CRT
30
Note: The shaded table cells denote power or ground.
GND VGAVGA Ground
VCC_CON_DAC+5V Power and Ground for Digital to Analog Converter
Power Interface
The CoreModule 745 requires one +5 volt DC power source and provides a shrouded 10-pin, right-angle
header with 2 rows, odd/even pin sequence (1, 2), and 0.100" (2.54mm) pitch. If the +5VDC power drops
below ~4.65V, a low voltage reset is triggered, resetting the system.
The power input header (J7) supplies the following voltage and ground directly to the module:
•5.0VDC +/- 5%
Table 3-11. Power Interface Pin Signals (J7)
PinSignalDescriptions
1
2
3
4
5
6
7
8
9
10
GND Ground
+5V+5 Volts
GNDGround
+12V +12 Volts routed to PC/104, PC/104-Plus, and LVDS interfaces
GNDGround
+3.3V_PCI+3.3 Volts routed to PCI
GNDGround
+5V+5 Volts
GNDGround
+5V+5 Volts
Note: The shaded table cells denote power or ground.
CoreModule 745Reference Manual29
Chapter 3Hardware
User GPIO Interface
The CoreModule 745 provides GPIO pins for customer use, routing the signals from the ICH8-M chipset to
the J18 header. An example test application and source code reside in each BSP directory of the
CoreModule 745 Support Software QuickDrive.
For instructions on using the example applications, refer to the GPIO Readme in each BSP directory of the
QuickDrive. For more information about the GPIO pin operation, refer to the ICH8-M datasheet at:
Table 3-12 describes the pin signals of the GPIO interface, which consists of a 10-pin header with 2 rows,
odd/even pin sequence (1, 2), and 0.079" (2mm) pitch.
Table 3-12. User GPIO Interface Pin Signal Descriptions (J18)
Pin #Signal from ICH8-MDescription
1 - GPI1GPIO1User defined
2 - GPO1GPIO17User defined
3 - GPI2GPIO6User defined
4 - GPO2GPIO18User defined
5 - GPI3GPIO7User defined
6 - GPO3GPIO20User defined
7 - GPI4GPIO8User defined
8 - GPO4GPIO27User defined
9
10
GNDGround
GNDGround
Note: The shaded table cells denote ground.
Utility Interface
The Utility interface provides three I/O signals on the module and consists of a 5-pin, 0.100" (2.54mm),
single-row header (J23). The ICH8-M drives the Power Button and Speaker signals on the Utility interface.
A separate Power Management microprocessor drives the Reset Switch signal. Table 3-13 provides the
signal definitions.
•Power Button
•Reset Switch
•Speaker
Power Button
The Utility header provides a signal for an external Power Button through pins 1 and 2. The Power Button
allows the user to shut down and power on the system. To shut down the system, press and hold the Power
Button for four seconds. Press the Power Button for one second to power on the system.
Reset Switch
Pins 2 and 3 on the Utility header provide the signal for an external reset button which allows the user to reboot the system.
Speaker
The speaker signal provides sufficient signal strength to drive a 1W 8 “Beep” speaker at an audible level
through pins 4 and 5 on the Utility header. The speaker signal is driven from an on-board amplifier and the
ICH8-M.
30Reference ManualCoreModule 745
Chapter 3Hardware
Table 3-13 describes the pin signals of the Utility interface, which uses a 5-pin, single-row header with
0.100" (2.54mm) pitch.
Table 3-13. Utility Interface Pin Signals (J23)
Pin #SignalDescription
1/PWR_BTN*External Power Button (Pins 1-2)
2
GNDGround
3/RESET SW*External Reset Switch signal (Pins 2-3)
4
5V+5 Volts Power
5SPKR_CONNSpeaker Output (Pins 4-5)
Note: The shaded table cells denote power or ground. The * symbol indicates the signal is Active Low.
System Management Bus (SMBus)
The ICH8-M chip contains a host SMBus port. The host port allows the CPU access to the SMBus slaves
through header, J20. The SMBus slaves include the SODIMM EPROM, Clock Buffer, Clock Generator, and
the Gb Ethernet Controller. Table 3-14 lists the device names and corresponding reserved binary addresses
on the SMBus. Tab le 3- 15 lists the SMBus pin signals, which are routed through a 5-pin, single-row header
with 0.049" (2 mm) pitch.
Table 3-14. SMBus Reserved Addresses
Component Address Binary
SODIMM EPROM1010,000x
Clock Generator 1101,001x
Clock Buffer1101,110x
Gb Ethernet Controller1100,001x
Table 3-15. SMBus Pin Signals (J20)
b
b
b
b
Pin #SignalDescription
1SMB_CLKSMBus Clock
2
GNDGround
3SMB_DATASMBus Data
4
VSM+3.3V standby voltage
5/SMB_ALERT*SMBus Alert
Note: The shaded table cells denote power or ground. The * symbol indicates the signal is Active Low.
System Fan
Table 3-16 lists the pin signals of the optional System Fan header, which provides 3 pins with 0.079" (2mm)
pitch.
Table 3-16. Optional System Fan Pin Signals (J22)
Pin #SignalDescription
1
2
3
VCC+5.0 volts DC +/- 5%
NCNot Connected
GND Ground
Note: The shaded table cells denote power or ground.
CoreModule 745Reference Manual31
Chapter 3Hardware
Battery
Table 3-17 lists the pin signals of the External Battery Input header for backup CMOS RAM and RTC (Real
Time Clock), which uses 2 pins, single row, with 0.049" (1.25mm) pitch.
Table 3-17. External Battery Input Header (J6)
Pin #SignalDescription
1
2
Note: The shaded table cells denote power or ground.
VBAT_EXT+3.0 volts DC
GND Ground
Ethernet External LED
This header provides signals for an external LED that indicates Ethernet links and activity using a single row
of 4 pins with 0.049" (1.25mm) pitch.
Table 3-18. Ethernet External LED Pin Signals (J11)
Pin #SignalDescription
1
2ETH_ACT_LEDEthernet Activity
3ETH_LINK100_LEDFast Ethernet Link with +3 volts power (Pins 3-4 for Bi-Color
4ETH_LINK1000_LEDGigabit Ethernet Link
V3.3_CONN+3 volts – Provides +3 volts to external LED (Pins 1-2 for Green
LED)
LED)
Note: The shaded table cell denotes power.
Miscellaneous
SSD (Solid State Drive)
The CoreModule 745 provides a standard SSD, which is a storage IC soldered directly onto the board. For
more information, refer to the SSD data sheet: http://www.greenliant.com/products/?inode=46780
Real Time Clock (RTC)
The CoreModule 745 contains a Real Time Clock (RTC). The RTC can be backed up with a battery. If the
battery is not present, the board BIOS has a battery-less boot feature to complete the boot process.
.
32Reference ManualCoreModule 745
Chapter 3Hardware
CM745_Oopsjump
Standard DB9 Serial
Port Connector (Male)
Front View
5
4
32
1
9
87
6
CM745_HotCable
Standard DB9 Serial
Port Connector (Female)
Rear View
5
4
32
1
9
8
7
6
Oops! Jumper (BIOS Recovery)
The Oops! jumper function is provided in the event the BIOS settings you have selected prevent you from
booting the system. By using the Oops! jumper you can prevent the current BIOS settings in flash from
being loaded, allowing you to boot using default settings.
Use a jumper to connect the DTR pin (4) to the RI pin (9) on Serial Port 1 (COM 1) prior to boot up to
prevent the present BIOS settings from loading. After booting with the Oops! jumper in place, remove the
Oops! jumper and return to BIOS Setup. You must now load factory defaults by selecting Load Optimal Defaults from the Exit menu. Then select Save Changes and Exit to reboot the system. Now you can modify
the default settings to your desired values. Ensure you save the changes before rebooting the system.
To convert a standard DB9 connector to an Oops! jumper, short together the DTR (4) and RI (9) pins on the
front of the connector as shown in Figure 3-2 on the Serial Port 1 DB9 connector.
Figure 3-2. Oops! Jumper Serial Port (DB9)
Remote Access
The CoreModule 745 BIOS supports Remote Access (or console redirection). This I/O function can be
utilized through an ANSI-compatible serial terminal or the equivalent terminal emulation software running
on another system. This can be very useful when setting up the BIOS on a production line for systems that
are not connected to a keyboard and display.
Remote Access Setup
The Remote Access feature is implemented by connecting a standard null modem cable or modified serial
cable (“Hot Cable”) between one of the serial ports (Serial 1 or 2) and the serial terminal or a PC with
communications software. The BIOS Setup Utility controls the Remote Access settings on the
CoreModule 745. Refer to “Remote Access Configuration” on page 40 for the settings of the Remote
Access feature.
Hot (Serial) Cable
To convert a standard serial cable to a “Hot Cable”, certain pins must be shorted together at the Serial port
header or on the DB9 connector. Short together the RTS (7) and RI (9) pins on either serial port DB9
connector as shown in Figure 3-3.
Figure 3-3. Remote Access Jumper
CoreModule 745Reference Manual33
Chapter 3Hardware
Watchdog Timer
The Watchdog Timer (WDT) restarts the system if a mishap occurs, ensuring proper start-up after the
interruption. Possible problems include failure to boot properly, the application software’s loss of control,
failure of an interface device, unexpected conditions on the bus, or other hardware or software malfunctions.
The WDT (Watchdog Timer) can be used both during the boot process and during normal system operation.
•During the Boot process – If the operating system fails to boot in the time interval set in the BIOS, the
system will reset.
Enable the WDT using Boot Settings Configuration of the Boot menu in BIOS Setup. Set the WDT for
a time-out interval in seconds, between 1 and 255, in one-second increments in the Boot Setting
Configuration screen. Ensure you allow enough time for the boot process to complete and for the OS to
boot. The OS or application must tickle the WDT as soon as it comes up. This can be done by accessing
the hardware directly or through a BIOS call.
•During System Operation – An application can set up the WDT hardware through a BIOS call, or by
accessing the hardware directly. Some ADLINK Board Support Packages provide an API interface to
the WDT. The application must tickle the WDT in the time set when the WDT is initialized or the
system will be reset. You can use a BIOS call to tickle the WDT or access the hardware directly.
The BIOS implements interrupt 15 function 0C3h to manipulate the WDT.
•Watchdog Code examples – ADLINK has provided source code examples on the CoreModule 745
Support Software QuickDrive illustrating how to control the WDT. The code examples can be easily
copied to your development environment to compile and test the examples, or make any desired
changes before compiling. Refer to the WDT Readme file on the CoreModule 745 Support Software
QuickDrive.
34Reference ManualCoreModule 745
Chapter 4BIOS Setup
Introduction
This section assumes the user is familiar with general BIOS Setup. Refer to the appropriate PC reference
manuals for information about the on-board ROM-BIOS software interface. If ADLINK has added to or
modified the standard functions, these functions will be described.
Entering BIOS Setup (Local Video Display)
To enter BIOS Setup using a local video display for the CoreModule 745:
1.Turn on the display and the power supply to the CoreModule 745.
2.Start Setup by pressing the [Del] key when the following message appears on the boot screen.
Press DEL to run Setup
NOTEIf the setting for Quick Boot is [Enabled], you may not see this prompt appear on
screen. If this happens, press the <Del> key early in the boot sequence to enter
BIOS Setup.
3.Follow the instructions on the right side of the screen to navigate through the selections and modify any
settings.
Entering BIOS Setup (Remote Access)
This section describes how to enable the Remote Access in VGA mode and enter the BIOS setup through a
serial terminal or PC.
1.Turn on the power supply to the CoreModule 745 and enter the BIOS Setup Utility in VGA mode.
2.Set the BIOS feature Remote Access to [Enabled] under the Advanced menu.
3.Accept the default options or make your own selections for the balance of the Remote Access fields and
record your settings.
4.Ensure you select the type of remote serial terminal you will be using and record your selection.
5.Select Save Changes and Exit and then shut down the CoreModule 745.
6.Connect the remote serial terminal (or the PC with communications software) to the COM port you
selected and recorded earlier in the BIOS Setup Utility.
7.Turn on the remote serial terminal or PC and set it to the settings you selected in the BIOS Setup Utility.
The default settings for the CoreModule 745 are:
COM1
115200
8 bits
no parity
1 stop bit
no flow control (None)
[Always] for Redirection After BIOS POST
8.Restore power to the CoreModule 745.
CoreModule 745Reference Manual35
Chapter 4BIOS Setup
9.Press the F4 key to enter Setup (early in the boot sequence if Quick Boot is set to [Enabled].)
If Quick Boot is set to [Enabled], you may never see the screen prompt.
10. Use the <Enter> key to select the screen menus listed in the Opening BIOS screen.
NOTEThe serial console port is not hardware protected. Diagnostic software that
probes hardware addresses may cause a loss or failure of the serial console
functions.
PCI-ISA Bridge Mapping
The CoreModule 745 supports ISA bus based modules with an on-board PCI-ISA bridge. The PCI-ISA
bridge optionally maps the IRQs to ISA based modules.
The CoreModule 745 system BIOS, maps the above resources based on information provided in the BIOS
Setup screens. By default, IRQs to be mapped to ISA modules must be explicitly specified by the user in the
BIOS Setup screens.
The IRQs are mapped with the “PCIPnP/IRQx” fields in BIOS setup (where x specifies the IRQ number.)
The IRQs 3, 4, 5, 7, 9, 10, 11, 14, and 15 can be mapped to ISA based modules by changing the default
setting for these IRQs from “Available” to “Reserved”.
OEM Logo Utility
The CoreModule 745 BIOS supports a graphical logo utility, which can be customized by the user and
displayed when enabled through the BIOS Setup Utility. The graphical image can be a company logo or any
custom image the user wants to display during the boot process. The custom image can be displayed as the
first image on screen and remain there while the OS boots, depending on the options selected in BIOS Setup.
Logo Image Requirements
The user’s image may be customized with any image editing tool, and the system will automatically convert
the image into an acceptable format to the tools (files and utilities) provided by ADLINK. The
CoreModule 745 OEM Logo utility supports the following image formats:
•Bitmap image
16-Color, 640x480 pixels
256-Color, 640x480 pixels
•JPG image
16-Color, 640x480 pixels
•PCX image
256-Color, 640x480 pixels
•A file size no larger than the sample image
36Reference ManualCoreModule 745
Chapter 4BIOS Setup
Main Advanced Power Boot Security Exit
BIOS Setup Utility
System Overview
AMIBIOS
Version : XX.XX.XX
Build Date: XX/XX/XX
BIOS Rev : XXXXXXX
Processor
Type : Intel(R) CPU XXXX @ X.XXGHz
Speed : XXXXMHz
Count : 1
System Memory
System Time [XX:XX:XX]
System Date [Fri XX/XX/20XX]
Size : XXXXMB
Use [ENTER], [TAB]
or [SHIFT-TAB] to
select a field.
Use[ + ] or [ - ] to
configure system time.
Select Screen
Select Item
+ - Change field
Tab Select Field
F1 General Help
F10 Save and Exit
ESC Exit
VXX.XX (C) Copyright 1985-20XX, American Megatrends, Inc.
CM745_BIOS_Main_a
BIOS Setup Menus
This section provides illustrations of the six main setup screens in the CoreModule 745 BIOS Setup Utility.
Below each illustration is a bullet list of the screen’s submenus and setting selections. The setting selections
are presented in brackets after each submenu or menu item and the optimal default settings are presented in
bold. For more detailed definitions of the BIOS settings, refer to the AMIBIOS8 manual:
http://www.ami.com/support/doc/MAN-EZP-80.pdf
Table 4-1. BIOS Setup Menus
BIOS Setup Utility MenuItem/Topic
Main Date and Time
Advanced CPU, IDE, USB, Chipset, Video Function, Super IO, PCI PnP,
Remote Access, Watchdog Timer
Power Power Management (APM) and Resume Power conditions
BootBoot up Settings, Boot Order, Removable Drives
Security Setting or changing Passwords, Boot Sector Virus Protection
ExitExiting with or without changing settings, Loading Optimal or Failsafe
conditions
.
BIOS Main Setup Screen
•Date & Time
System Time (hh:mm:ss) – This is a 24-hour clock setting in hours, minutes, and seconds.
System Date (day of week, mm:dd:yyyy) – This field requires the alpha-numeric entry of the day of
Figure 4-1. BIOS Main Setup Screen
week, day of the month, calendar month, and all 4 digits of the year, indicating the century plus
year (Fri XX/XX/20XX).
CoreModule 745Reference Manual37
Chapter 4BIOS Setup
Main Advanced Power Boot Security Exit
BIOS Setup Utility
Advanced Settings
Select Screen
Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
VXX.XX (C) Copyright 1985-20XX, American Megatrends, Inc.
CPU Configuration
Chipset Configuration
Video Function Configuration
IDE Configuration
Super IO Configuration
USB Configuration
PCI PnP Configuration
Remote Access Configuration
Watchdog Timer Configuration
Configure CPU
CM745_BIOS_Advanced_a
BIOS Advanced Setup Screen
Figure 4-2. BIOS Advanced Setup Screen
•CPU Configuration
Manufacture: Intel
Brand String: Intel® Atom processor X.XXGHz
Frequency: X.XXGHz
FSB Speed: XXXMHz
Cache L1: XXkB
Cache L2: XXXXkB
Ratio Actual Value: XX
Max CPUID Limit [Disabled; Enabled]
Execute - Disable Bit Capability [Disabled; Enabled]
Hyper Threading Technology [Disabled; Enabled]
Intel (R) Speed Step (TM) Technology [Disabled; Enabled] - (Available only on the N455 model)
Intel (R) C-State Technology [Disabled; Enabled] - (Available only on the N455 model)
•Chipset Configuration
Enhanced C-States [Disabled; Enabled] - (Available only on the N455 model)
North Bridge Chipset Configuration
•PCIMMIO Allocation: XGB to XXXXMB
•DRAM Frequency [Auto; Max MHz]
•Configure DRAM Timing by SPD [Enabled; Disabled]
38Reference ManualCoreModule 745
Chapter 4BIOS Setup
South Bridge Chipset Configuration
•SMBUS Controller [Enabled; Disabled]
•Onboard Ethernet Controller [Enabled; Disabled]
•Video Function Configuration
Initiate Graphic Adapter [PCI/IGD; IGD]
Internal Graphics Mode Select [Enabled, 8MB]
DVMT Mode Select [DVMT Mode; Fixed Mode]
•DVMT/Fixed Memory [128MB; 256MB; Maximum DVMT]
Boot Display Device [CRT; LVDS; CRT + LVDS]
Flat Panel Type [640x480; 800x600; 1024x768; 1280x800; 1366x768]
Enter Change
F1 General Help
F10 Save and Exit
ESC Exit
VXX.XX (C) Copyright 1985-20XX, American Megatrends, Inc.
Supervisor Password: Not installed
User Password: Not installed
Change Supervisor Password
Change User Password
Install or change
the password
CM745_BIOS_Security_a
Removable Drives
•1st Drive [Not Installed]
CD/DVD Drives
•1st Drive [Not Installed]
USB Drives
•1st Drive [Not Installed]
Network drives
•1st Drive [Not Installed]
Onboard Lan Boot ROM [Disabled; Enabled]
BIOS Security Setup Screen
Figure 4-5. BIOS Security Setup Screen
•Security Settings
CoreModule 745Reference Manual43
Supervisor Password [Not Installed]
User Password [Not Installed]
Change Supervisor Password
Change User Password
Chapter 4BIOS Setup
Main Advanced Power Boot Security Exit
BIOS Setup Utility
Exit Options
Select Screen
Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
VXX.XX (C) Copyright 1985-20XX, American Megatrends, Inc.
Save Changes and Exit
Discard Changes and Exit
Discard Changes
Load Optimal Defaults
Load Failsafe Defaults
Exit System Setup
after saving the
changes.
F10 key can be used
for this operation
CM745_BIOS_Exit_a
BIOS Exit Setup Screen
Figure 4-6. BIOS Exit Setup Screen
•Exit Options
Save Changes and Exit (F10 key can be used for this operation.)
Discard Changes and Exit (ESC key can be used for this operation.)
Discard Changes (F7 key can be used for this operation.)
Load Optimal Defaults (F9 key can be used for this operation.)
Load Failsafe Defaults (F8 key can be used for this operation.)
44Reference ManualCoreModule 745
Appendix ATechnical Support
Contact us should you require any service or assistance.
ADLINK Technology, Inc.
Address: 9F, No.166 Jian Yi Road, Zhonghe District
New Taipei City 235, Taiwan
ᄅקؑխࡉ৬ԫሁ 166 ᇆ 9 ᑔ
Tel: +886-2-8226-5877
Fax: +886-2-8226-5717
Email: service@adlinktech.com
Ampro ADLINK Technology, Inc.
Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA
Tel: +1-408-360-0200
Toll Free: +1-800-966-5200 (USA only)
Fax: +1-408-360-0222
Email: info@adlinktech.com
ADLINK Technology (China) Co., Ltd.
Address: Ϟ⍋Ꮦ⌺ϰᮄᓴ∳催⾥ᡔು㢇䏃 300 ো(201203)
300 Fang Chun Rd., Zhangjiang Hi-Tech Park,
Pudong New Area, Shanghai, 201203 China
Tel: +86-21-5132-8988
Fax: +86-21-5132-3588
Email: market@adlinktech.com
ADLINK Technology, Inc. provides a number of methods for contacting Technical Support listed below in
Table A- 1. Requests for support through the Ask an Expert are given the highest priority, and usually will be
addressed within one working day.
•ADLINK’s Ask an Expert – This is a comprehensive support center designed to meet all your technical
needs. This service is free and available 24 hours a day through the ADLINK web page at
ttp://www.adlinktech.com/AAE/. This includes a searchable database of Frequently Asked Questions,
h
which will help you with the common information requested by most customers. This is a good source
of information to look at first for your technical solutions. However, you must register online if you
wish to use the Ask a Question feature.
ADLINK strongly suggests that you register with the web site. By creating a profile on the ADLINK
web site, you will have a portal page called “My ADLINK” unique to you with access to exclusive
services and account information.
•Personal Assistance – You may also request personal assistance by creating an Ask an Expert account
and then going to the Ask a Question feature. Requests can be submitted 24 hours a day, 7 days a week.
You will receive immediate confirmation that your request has been entered. Once you have submitted
your request, you must log in to go to My Stuff area where you can check status, update your request,
and access other features.
•Download Service – This service is also free and available 24 hours a day at
http://www.adlinktech.com
register online before you can log in to this service.
. For certain downloads such as technical documents and software, you must
Table A-1. Technical Support Contact Information
MethodContact Information
Ask an Experthttp://www.adlinktech.com/AAE/
Web Sitehttp://www.adlinktech.com
Standard Mail
CoreModule 745Reference Manual45
Appendix ATechnical Support
ADLINK Technology Beijing
Address: ࣫ҀᏖ⍋⎔Ϟഄϰ䏃 1 োⲜ߯ࡼ E ᑻ 801 ᅸ(100085)
Rm. 801, Power Creative E, No. 1,
Shang Di East Rd., Beijing, 100085 China
Tel: +86-10-5885-8666
Fax: +86-10-5885-8626
Email: market@adlinktech.com
ADLINK Technology Shenzhen
Address: ⏅ഇᏖቅ⾥ᡔು催ᮄϗ䘧᭄ᄫᡔᴃು
A1 2 ὐ C (518057)
2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7,
High-Tech Industrial Park S., Shenzhen, 518054 China
Tel: +86-755-2643-4858
Fax: +86-755-2664-6353
Email: market@adlinktech.com