ADLINK CoreModule 435 User Manual

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CoreModule

435

(PC/104 Single Board Computer)

Reference Manual

P/N 50-1Z085-1010

Notice Page

DISCLAIMER

ADLINK Technology, Incorporated makes no representations or warranties with respect to the contents of this manual or of the associated ADLINK products, and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose. ADLINK shall under no circumstances be liable for incidental or consequential damages or related expenses resulting from the use of this product, even if it has been notified of the possibility of such damages. ADLINK reserves the right to revise this publication from time to time without obligation to notify any person of such revisions. If errors are found, please contact ADLINK at the address listed below on the Notice page of this document.

TRADEMARKS

CoreModule and the Ampro logo are registered trademarks, and ADLINK, Little Board, LittleBoard, MightyBoard, MightySystem, MilSystem, MiniModule, ReadyBoard, ReadyPanel, ReadySystem, and RuffSystem are trademarks of ADLINK Technology, Inc. All other marks are the property of their respective companies.

REVISION HISTORY

Revision Reason for Change Date

1000 Initial Release Jul/11

1010 Removed PXE Boot, Secondary IDE Master and Slave, SB LPT

Parallel Port, Multi-Finction Ports 1 and 2, Redundancy Control LPT

Port and GPIO Ports 1 and 2 from BIOS setup in Ch 4; changed

IRQ15 default to “Reserved” in BIOS setup;

updated Tech Support addresses in Appendix A

Sept/11

ADLINK Technology, Incorporated 5215 Hellyer Avenue, #110 San Jose, CA 95138-1007 Tel. 408 360-0200 Fax 408 360-0222

http://www.adlinktech.com

Audience

This manual provides reference only for computer design engineers, including but not limited to hardware and software designers and applications engineers. ADLNK Technology, Inc. assumes you are qualified to design and implement prototype computer equipment.

ii Reference Manual CoreModule 435

Contents

Chapter 1 About This Manual ....................................................................................................1

Purpose of this Manual ....................................................................................................................1

References ......................................................................................................................................1

Chapter 2 Product Overview......................................................................................................3

PC/104 Architecture ........................................................................................................................3

Product Description..........................................................................................................................4

Module Features ........................................................................................................................4

Block Diagram ............................................................................................................................7

Major Component (IC) Definitions....................................................................................................8

Header, Connector, and Socket Definitions ..................................................................................10

Jumper Header Definitions ............................................................................................................13

Specifications.................................................................................................................................15

Physical Specifications .............................................................................................................15

Mechanical Specifications ........................................................................................................16

Power Specifications ................................................................................................................17

Environmental Specifications....................................................................................................17

Thermal/Cooling Requirements ................................................................................................17

Chapter 3 Hardware..................................................................................................................19

Overview ........................................................................................................................................19

CPU ..............................................................................................................................................20

Graphics.........................................................................................................................................20

Memory and Flash .........................................................................................................................20

System Memory .......................................................................................................................20

Video Memory...........................................................................................................................20

SPI Flash ..................................................................................................................................20

Interrupt Channel Assignments .....................................................................................................21

Memory Map ..................................................................................................................................22

I/O Address Map ...........................................................................................................................22

Serial Interface ..............................................................................................................................23

USB Interface ................................................................................................................................26

Utility Interface ..............................................................................................................................27

Keyboard ..................................................................................................................................27

Mouse .......................................................................................................................................27

Battery ......................................................................................................................................27

Reset Switch.............................................................................................................................27

Speaker ....................................................................................................................................27

Fast Ethernet Interface .................................................................................................................28

Gigabit Ethernet Interface .............................................................................................................29

Gigabit Ethernet External LED Interface...................................................................................30

Video (TFT/VGA) Interface ...........................................................................................................30

Serial Peripheral Interface (SPI) ....................................................................................................32

Low Pin Count Interface (LPC) ......................................................................................................32

Miscellaneous ................................................................................................................................33

Real Time Clock (RTC) ............................................................................................................33

User GPIO Interface .................................................................................................................33

Oops! Jumper (BIOS Recovery) ...............................................................................................34

Serial Console ..........................................................................................................................34

CoreModule 435 Reference Manual iii

Contents

Serial Console BIOS Setup................................................................................................. 34

Hot (Serial) Cable .............................................................................................................. 34

Watchdog Timer....................................................................................................................... 35

Power Interface ............................................................................................................................ 35

Chapter 4 BIOS Setup .............................................................................................................. 37

Introduction.................................................................................................................................... 37

Entering BIOS Setup (VGA Display) ........................................................................................ 37

Entering BIOS Setup (Remote Access) .................................................................................. 37

OEM Logo Utility ........................................................................................................................... 38

Logo Image Requirements....................................................................................................... 38

BIOS Setup Menus........................................................................................................................ 39

BIOS Main Setup Screen ......................................................................................................... 39

BIOS Advanced Setup Screen................................................................................................. 40

BIOS PCIPnP Setup Screen .................................................................................................... 42

BIOS Boot Setup Screen ......................................................................................................... 43

BIOS Security Setup Screen.................................................................................................... 44

BIOS Chipset Setup Screen..................................................................................................... 45

BIOS Exit Setup Screen........................................................................................................... 48

Appendix A Technical Support .................................................................................................. 49

Index .................................................................................................................................................. 51

List of Figures

Figure 2-1. Stacking PC/104 Modules with the CoreModule 435 .............................................. 3

Figure 2-2. Block Diagram ......................................................................................................... 7

Figure 2-3. Component Locations (Top Side)............................................................................ 9

Figure 2-4. Component Locations (Bottom Side) .................................................................... 10

Figure 2-5. Header Pin Sequence Identification ...................................................................... 11

Figure 2-6. Header and Connector Locations (Top Side) ........................................................ 12

Figure 2-7. Header and Socket Locations (Bottom Side) ........................................................ 13

Figure 2-8. Jumper Header Locations (Top Side) ................................................................... 14

Figure 2-9. Mechanical Dimensions (Top View) ...................................................................... 16

Figure 3-1. RS-485 Serial Port Implementation....................................................................... 24

Figure 3-2. Oops! Jumper........................................................................................................34

Figure 3-3. Hot Cable Jumper ................................................................................................. 34

Figure 4-1. BIOS Main Setup Screen ...................................................................................... 39

Figure 4-2. BIOS Advanced Setup Screen .............................................................................. 40

Figure 4-3. BIOS PCIPnP Setup Screen ................................................................................. 42

Figure 4-4. BIOS Boot Setup Screen....................................................................................... 43

Figure 4-5. BIOS Security Setup Screen ................................................................................. 44

Figure 4-6. BIOS Chipset Setup Screen.................................................................................. 45

Figure 4-7. BIOS Exit Setup Screen ........................................................................................ 48

iv Reference Manual CoreModule 435

List of Tables

Table 2-1. Major Component (IC) Descriptions and Functions .................................................8

Table 2-2. Header, Connector, and Socket Descriptions........................................................10

Table 2-3. Jumper Settings ................................................................................................13

Table 2-4. Weight and Footprint Dimensions..........................................................................15

Table 2-5. Power Supply Requirements .................................................................................17

Table 2-6. Environmental Requirements.................................................................................17

Table 3-1. Interrupt Channel Assignments..............................................................................21

Table 3-2. DMA Map ...............................................................................................................21

Table 3-3. Memory Map - Vortex 86SX/DX Processor ...........................................................22

Table 3-4. I/O Address Map ....................................................................................................22

Table 3-5. Serial Port 1 (J3) & Port 2 (J9) Interface Pin Signals.............................................24

Table 3-6. Serial Port 3 (J14) & Port 4 (J13) Interface Pin Signals.........................................25

Table 3-7. USB0 Interface Pin Signals (J10) ..........................................................................26

Table 3-8. USB1 Interface Pin Signals (J17) ..........................................................................26

Table 3-9. Utility Interface Pin Signals (J5) .............................................................................27

Table 3-10. Fast Ethernet Interface Pin Signals (J2) ................................................................28

Table 3-11. Gigabit Ethernet Interface Pin Signals (J23)..........................................................29

Table 3-12. Gigabit Ethernet External LED Pin Signals (J22)...................................................30

Table 3-13. Video Interface Pin Signals (J11)...........................................................................31

Table 3-14. SPI Interface Pin Signals (J19) ..............................................................................32

Table 3-15. LPC Interface Pin Signals (J20) .............................................................................32

Table 3-16. User GPIO Interface Pin Signals (J8) ....................................................................33

Table 3-17. Power Interface Pin Signal (J7) .............................................................................35

Table 4-1. BIOS Setup Menus ................................................................................................39

Table A-1. Technical Support Contact Information..................................................................49

Contents

CoreModule 435 Reference Manual v

Contents

vi Reference Manual CoreModule 435

Chapter 1 About This Manual

Purpose of this Manual

This manual is for designers of systems based on the CoreModule™ 435 PC/104 Single Board Computer (SBC) module. This manual contains information that permits designers to create an embedded system based on specific design requirements.

Information provided in this reference manual includes:

• Product Overview

• Hardware Specifications

• BIOS Setup information

• Technical Support Contact Information

Information not provided in this reference manual includes:

• Detailed chip specifications (refer to the References section of this chapter)

• Internal component operation

• Internal registers or signal operations

• Bus or signal timing for industry standard busses and signals

• Pin-signal definitions for industry-standard interfaces

References

The following references may help you successfully complete your custom design.

Specifications

• PC/104 Specification Revision 2.5, November 2003

For latest revision of the PC/104 specifications, contact the PC/104 Consortium, at:

Web site: http://www.pc104.org

• PCI Specification Revision 2.2

Web site: http://www.pcisig.com/specifications/conventional/conventional_pci

• AMI BIOS Core 8 User’s Guide

Web site: http://www.ami.com/support/doc/MAN-EZP-80.pdf

Chip Specifications

The following chip specifications are used in the CoreModule 435 processor module:

• DMP Electronics Inc. and the Vortex 86SX/DX CPU

Web site: http://www.vortex86sx.com/?page_id=3tw/

• Sis Corporation and the Volari Z9s PCI Graphics Controller

Data sheet: http://ms-n.org/DataSheets/XGI/databook_z9s_v20.pdf

• Hynix Semiconductor, Inc. and the DDR2 on-board System and Video Memory

Web site: http://www.hynix.com/gl/products/consumer/consumer_info.jsp

CoreModule 435 Reference Manual 1

Chapter 1 About This Manual

• Intel Corporation and the 82541PI Gigabit Ethernet controller

Data sheet: http://download.intel.com/design/network/datashts/318138.pdf

NOTE If you are unable to locate the datasheets using the links provided, search the

internet to find the manufacturer’s web site and locate the documents you need.

2 Reference Manual CoreModule 435

Chapter 2 Product Overview

This overview presents general information about the PC/104 architecture and the CoreModule 435 Single Board Computer (SBC). After reading this chapter you should understand:

• PC/104 architecture

• CoreModule 435 product description

• CoreModule 435 features

• Major components

• Header definitions

• Specifications

PC/104 Architecture

The PC/104 architecture affords a great deal of flexibility in system design. You can build a simple system using only a CoreModule Single Board Computer (SBC) with input/output devices connected to its serial or USB ports and a Compact Flash card in the Compact Flash socket. To expand a simple CoreModule system, simply add self-stacking ADLINK MiniModules or 3rd party PC/104 expansion boards to provide additional capabilities, such as:

• Additional I/O ports

• Analog or digital I/O interfaces

PC/104 expansion modules can be stacked with the CoreModule 435 avoiding the need for card cages and backplanes. The PC/104 expansion modules can be mounted directly to the PC/104 bus connector of the CoreModule 435. PC/104-compliant modules can be stacked with an inter-board spacing of ~0.66" (16.7 mm) so that a 3-module system fits in a 3.6" x 3.8" x 2.4" space. See Figure 2-1.

One or more MiniModule products or other PC/104 modules can be installed on the CoreModule expansion connectors. When installed on the PC/104 headers, the expansion modules fit within the CoreModule outline dimensions. Most MiniModule products have stack-through connectors compatible with the PC/104 Version

2.5 specification. Several modules can be stacked on the CoreModule headers. Each additional module increases the thickness of the package by 0.60" (15 mm). See Figure 2-1.

4-40 nut (4)

0.6 inch spacer (4)

4-40 screw (4)

PC/104 Module

CoreModule 435

PC/104 Module

Stackthrough Expansion Bus Headers

CM435stack

Figure 2-1. Stacking PC/104 Modules with the CoreModule 435

CoreModule 435 Reference Manual 3

Chapter 2 Product Overview

Product Description

The CoreModule 435 SBC is an exceptionally high integration, x86-based PC compatible system in the PC/104 form factor. This rugged and high quality single board system contains all the component subsystems of a PC/AT motherboard plus the equivalent of several PC/AT expansion boards.

In addition, the CoreModule 435 SBC includes a comprehensive set of system extensions and enhancements that are specifically designed for embedded systems. These enhancements—such as Watchdog Timer and Oops! Jumper—ensure fail-safe embedded system operation. The CoreModule 435 is designed to meet the size, power consumption, temperature range, quality, and reliability demands of embedded applications. The CoreModule 435 requires a single +5V power source.

The CoreModule 435 SBC is particularly well suited to either embedded or portable applications. Its flexibility makes system design quick and easy. It can be stacked with ADLINK MiniModules or other PC/104-compliant expansion boards, or it can be used as the computing engine in a fully customized application.

Module Features

• CPU

♦

Provides x86 based DMP Vortex SX (300 MHz) or DX (800 MHz) processor

♦

Provides integrated Northbridge and Southbridge

♦

Fully supports PC compatible architecture

♦

Provides 8 kB Unified Instruction and Data Cache

♦

Provides Parallel Processing Integrated Floating Point Unit (only in DX version)

♦

Provides Low Power and System Management Modes

• Memory

♦

Provides up to 256 MB standard DDR2 system RAM (soldered on the board)

♦

Provides up to 512 MB standard DDR2 video RAM (soldered on the board)

♦

Supports Memory Bus Speeds of 166 MHz on the SX CPU and 333MHz on the DX CPU

• PC/104 Bus Interface

♦

Provides standard PC/104 connector

♦

Supports clock speeds up to 8 MHz ISA

• IDE Interface

♦

Provides one IDE channel

♦

Supports two enhanced IDE devices

♦

Provides Fast ATA-capable interface for high-speed modes

• PIO modes (0 to 4)

• DMA modes (0 to 6)

♦

Supports ATAPI and DVD peripherals

♦

Supports IDE native and ATA compatibility modes

• Compact Flash Socket

♦

Provides Compact Flash socket (Type I or II)

♦

Supports IDE Compact Flash cards

♦

Attached to Primary IDE bus

4 Reference Manual CoreModule 435

Chapter 2 Product Overview

• Serial Ports

♦

Provides four 10-pin headers and four buffered RS-232 serial ports with full handshaking and modem capability

♦

Provides 16C550 or 16C552 UARTs, each with a built-in 16-byte FIFO buffer

♦

Supports RS-232 or RS-485 operation on ports 1 and 2

♦

Supports programmable word length, stop bits, and parity

♦

Supports 16-bit programmable baud-rate generator and an interrupt generator

• Ethernet

♦

Provides two fully independent Ethernet ports

♦

Supports IEEE 802.3 10BaseT/100BaseTx and 10BaseT/100BaseTx/1000BaseT compatible physical layers

♦

Provides Ethernet LED header for Gigabit Ethernet

♦

Provides one Intel 82541PI Gigabit Ethernet controller and one Fast Ethernet controller internal to the CPU

♦

Supports Auto-negotiation for speed, duplex mode, and flow control

♦

Supports full-duplex or half-duplex mode

• Full-duplex mode supports transmit and receive frames simultaneously

• Supports IEEE 802.3x Flow control in full duplex mode

• Half-duplex mode supports enhanced proprietary collision reduction mode

• Utility Interface

♦

Provides PS/2 Keyboard and PS/2 Mouse Interfaces

♦

Supports external battery for Real Time Clock operation

♦

Supports standard external 8Ω speaker interface

♦

Supports external reset switch

• USB Ports

♦

Provides one root USB hub

♦

Provides two USB ports

♦

Supports USB v2.0 and USB v1.1

• Video (LCD/CRT) Display

Enhanced 2D graphics accelerator

♦

Supports BitBLT implementation for all 256 raster operations

♦

Provides hardware command queue

♦

Provides Direct Draw accelerator

♦

Provides GDI 2000 accelerator

♦

Supports transparent BitBLT with source and destination keys

♦

Supports rectangle clipping

♦

Supports fast line draw engine with styled pattern

♦

Supports fast rectangle fill engine

♦

Supports 64x64x2 bit-mapped mono hardware cursor

♦

Supports 256MB frame buffer with linear addressing

CoreModule 435 Reference Manual 5

Chapter 2 Product Overview

VGA Interface

♦

VGA Controller with 230 MHz triple RAMDACs for 1600 x 1200 x 85 Hz display

♦

Supports 24-bit pixel depth

♦

Interlaced or non-interlaced output

TFT Interface

♦

Supports VESA Flat Panel Display interface

♦

Supports programmable panel size up to 1600x1200 pixel display resolution

♦

Supports internal VGA controller for display mode settings

♦

Supports 12-, 18-, and dual 12-bit interface (1 Pixel/Clock)

♦

Supports 3.3V or 5V LCD panels; jumper selectable

• Miscellaneous

♦

Provides Real Time Clock and CMOS RAM, with support for battery-free operation

♦

Provides General Purpose I/O (GPIO) interface

♦

Supports Oops! Jumper (BIOS Recovery)

♦

Supports Serial Console (Console Redirection)

♦

Supports customizable Splash Screen

♦

Supports Watchdog Timer (WDT)

6 Reference Manual CoreModule 435

Chapter 2 Product Overview

Block Diagram

Figure 2-2 shows the functional components of the module.

SPI Header

COM3 & COM4

Headers

COM1 & COM2

Headers

Video Memory Chip

(Soldered On Board)

SPI Flash

PC/104 Connector

Transceivers (X2)

Transceiver (X1)

Utility Interface

DDR2

RS-232

and

RS-422/485

Header

LPC

Header

GPIO

Header

ISA

SiS

Z9s

Volari

PCI Graphics Controller

DMP Vortex

86DX/SX

CPU

PCI Bus

VGA and TFT

Header

DDR2

System Memory Chip

(Soldered On Board)

DDR2

System Memory Chip

(Soldered On Board)

USB0 and USB1

Headers (X2)

IDE

Compact Flash

Socket

Ethernet

Transformer

RTC

CM435blkdiag_b

44-Pin IDE

Header

10/100 Ethernet

Header

Gigabit

Ethernet

Controller

Figure 2-2. Block Diagram

Ethernet

Transformer

Ethernet

LED Header

10/100/1000

Ethernet

Header

CoreModule 435 Reference Manual 7

Chapter 2 Product Overview

Major Component (IC) Definitions

Table 2- 1 describes the major ICs on the CoreModule 435, and Figures 2-3 and 2-4 show the locations of the

major ICs on the board.

Table 2-1. Major Component (IC) Descriptions and Functions

Chip Type Mfg. Model Description Function

CPU (U1) DMP

Electronics, Inc.

DDR2 Memory (U2 - on bottom side) [see

Figure 2-4])

DDR2 Memory (U3)

RS-232 Transceiver (U4

- on bottom side) [see

Figure 2-4]

RS-232 Transceiver (U5)

SPI Flash (U6) PCT PCT25VF016B-75-

RS-232 Transceiver (U7)

RS-485/422 Transceiver (U9

- on bottom side) [see

Figure 2-4]

Ethernet Transfomer (U12)

PCI Graphics Controller (U13)

DDR2 Memory (U14)

Ethernet Controller (U19)

Hynix H5PS1G83EFR-Y5 On-board DDR2

Analog Devices

Linear Technology

Pulse H1102NL-T Fast Ethernet

Sis Corporation

Hynix H5PS5162GFR-Y5C On-board DDR2

Intel 82541PI Gigabit Ethernet

Vortex 86SX/DX x86 32-bit processor Integrates Processor

Core, Memory Controller, and I/O Hub

Provides high-speed

System memory

ADM213EARSZ RS-232 Transceiver

for COM3

ADM213EARSZ RS-232 Transceiver

for COM4

Serial Peripheral

4I-S2AF

ADM213EARSZ RS-232 Transceiver

LTC1334CG#PBF RS-485/422

Volari Z9S-A1BBHF

Interface 16 Mbit Flash Memory

for COM1 and COM2

Transceiver for COM1 and COM2

Magnetics

PCI graphics controller

Vid eo memory

Controller

data transfer

Provides high-speed data transfer

Transmits and receives RS-232 signals for COM3

Transmits and receives RS-232 signals for COM4

Stores data in flash memory

Transmits and receives RS-232 signals for COM1 and COM2

Transmits and receives RS-485/422 signals for COM1 and COM2

Provides electrical isolation for Fast Ethernet controller

Integrates 2D Engine and PCI controller

Provides high-speed data transfer

Generates PCI 10T/100TX/1000T Ethernet signals

8 Reference Manual CoreModule 435

Chapter 2 Product Overview

Table 2-1. Major Component (IC) Descriptions and Functions (Continued)

Ethernet EEPROM (U20)

Atmel AT93C46DN-SH Three-Wire Serial

EEPROM for Gigabit Ethernet Controller

Provides storage for MAC addresses, serial numbers, and pre-boot configuration data

Ethernet Transformer (T1 - on bottom

Wurth Elektronik

7490200110 Gigabit Ethernet

Magnetics

Provides electrical isolation for Gigabit

Ethernet controller side) [see

Figure 2-4])

Key: U1 - CPU U3 - DDR2 SDRAM - System Memory U5 - RS-232 Transceiver - COM4 U6 - SPI Flash - Data Storage U7 - RS-232 Transceiver - COM1 and COM2 U12 - 10/100 Ethernet Transformer U13 - PCI Graphics Controller U14 - DDR2 SDRAM - Video Memory U19 - 10/100/1000 Ethernet Controller U20 - 10/100/1000 Ethernet EEPROM

U14

U13

U20

U19

U12

Figure 2-3. Component Locations (Top Side)

CM435_comp_top_a

NOTE Black dots on vertical headers or connectors indicate pin 1 in all illustrations.

Black dots on right-angle headers or connectors indicate pin 1 in top-side views and pin 2 in bottom-side views (except for on the J7 Power header, which indicates pin 2 in top-side views and pin 1 in bottom-side views.)

CoreModule 435 Reference Manual 9

Chapter 2 Product Overview

Key: U2 - DDR2 SDRAM - System Memory U4 - RS-232 Transceiver - COM3 U9 - RS-422/485 Transceiver - COM1 and COM2 T1 - 10/100/1000 Ethernet Transformer

Figure 2-4. Component Locations (Bottom Side)

CM435_comp_bottom_a

Header, Connector, and Socket Definitions

Table 2- 2 describes the headers, connector, and socket shown in Figures 2-6 and 2-7.

Table 2-2. Header, Connector, and Socket Descriptions

Jack/Plug # Access Description

P1 – PC/104 Bus Top/

Bottom

J2 – Fast Ethernet Top 8-pin, 0.100" (2.54mm), right-angle header for

J3 – Serial 1 (COM1) Top 10-pin, 0.100" (2.54mm), right-angle header for Serial 1

J5 – Utility Top 10-pin, 0.100" (2.54mm), right-angle header for Utility

J6 – IDE Top 44-pin, 0.079" (2mm) header for standard IDE interface

10 Reference Manual CoreModule 435

104-pin, 0.100" (2.54mm) connector for standard PC/104 (ISA) bus

(10baseT/100baseTX) Fast Ethernet interface

interface

Chapter 2 Product Overview

Table 2-2. Header, Connector, and Socket Descriptions (Continued)

J7 – Power Top 10-pin, 0.100" (2.54mm), right-angle header for Power

connection

J8 – GPIO (User) Top 10-pin, 0.079" (2mm) header for User defined GPIO signals

J9 – Serial 2 (COM2) Top 10-pin, 0.100" (2.54mm), right-angle header for Serial 2

interface

J10 – USB0 Top 5-pin, 0.100" (2.54mm), right-angle header for USB0

interface

J11 – Video Top 44-pin, 0.079" (2mm), right-angle header for TTL/VGA

video interface

J12 – Compact Flash Bottom 50-pin, 0.050" (1.27mm) standard socket for Type I or II

Compact Flash cards

J13 – Serial 4 (COM4) Top 10-pin, 0.079" (2mm) header for Serial 4 interface

J14 – Serial 3 (COM3) Top 10-pin, 0.079" (2mm) header for Serial 3 interface

J17 – USB1 Top 5-pin, 0.079" (2mm) header for USB1 interface

J19 – SPI Top 6-pin, 0.100" (2.54mm) header used for data storage

J20 – LPC Bottom 10-pin, 0.050" (1.27mm) female header for LPC expansion

J22 – Gigabit Ethernet LED Top 4-pin, 0.049" (1.25mm) header for Gigabit Ethernet external

LED

J23 – Gigabit Ethernet Top 10-pin, 0.079" (2mm) header for 10BaseT/100BaseTX/

1000BaseT Gigabit Ethernet port

NOTE The pinout tables in Chapter 3 of this manual identify pin sequence using the

following method: A 10-pin header with two rows of pins, using odd/even numbering, where pin 2 is directly across from pin 1, is noted as 10-pin, 2 rows, odd/ even (1, 2). See Figure 2-5.

10-pin, two rows, Odd/Even, (1, 2)

678910

234

CM435_ConNum_a

Figure 2-5. Header Pin Sequence Identification

CoreModule 435 Reference Manual 11

Chapter 2 Product Overview

Key: J2 - Fast Ethernet J3 - COM1 J5 - Utility J6 - IDE J7 - Power J8 - GPIO J9 - COM2 J10 - USB0 J11 - TTL and VGA Video J13 - COM4 J14 - COM3 J17 - USB1 J19 - SPI 16 Mbit Data Storage J22 - Gigabit Ethernet LED J23 - Gigabit Ethernet JP1 - See jumper table JP2 - See jumper table JP5 - See jumper table JP6 - See jumper table JP7 - See jumper table JP8 - See jumper table P1 - PC/104

J23

J11

JP6

JP5

J14

J13

J19

JP7

JP8

J17

JP2

JP1

J22

J10

CM435_conn_top_a

Figure 2-6. Header and Connector Locations (Top Side)

NOTE Black dots on vertical headers or connectors indicate pin 1 in all illustrations.

12 Reference Manual CoreModule 435

Chapter 2 Product Overview

Key: J12 - Compact Flash J20 - LPC

J12

J20

Figure 2-7. Header and Socket Locations (Bottom Side)

Jumper Header Definitions

Table 2- 3 describes the jumper headers shown in Figure 2-6.

Table 2-3. Jumper Settings

Jumper # Installed Removed/Installed

JP1 – Serial Port 2 Termination

JP2 – Serial Port 1 Termination

JP5 – Backlight Voltage Select

JP6 – Flat Panel Voltage Select

JP7 – Compact Flash Voltage Select

JP8 – IDE Select Enable HDD master, CF slave (Pins 1-2)

Enable RS-485 Termination (Pins 1-2) Disable RS-485 Termination

+5 Volts (Pins 1-2) +12 Volts (Pins 2-3) Default

+3.3 Volts (Pins 1-2) Default +5 Volts (Pins 2-3)

+5 Volts (Pins 1-2) +3.3 Volts (Pins 2-3) Default

Default

CM435_conn_bottom_a

(Removed) Default setting

Enable HDD slave, CF master (Pins 2-3)

Note: All jumper headers use .079" (2mm) pitch.

CoreModule 435 Reference Manual 13

Chapter 2 Product Overview

Key: JP1 - Serial Port 2 Termination JP2 - Serial Port 1 Termination JP5 - Backlight Voltage Select JP6 - Flat Panel Voltage Select JP7 - Compact Flash Voltage Select JP8 - IDE Select

JP2

JP7

JP5

JP8

JP1

JP6

Figure 2-8. Jumper Header Locations (Top Side)

14 Reference Manual CoreModule 435

Chapter 2 Product Overview

Specifications

Physical Specifications

Table 2- 4 shows the physical dimensions of the module and Figure 2-9 shows the mounting dimensions.

Table 2-4. Weight and Footprint Dimensions

Item Dimension

Weight 0.10 kg. (0.20 lbs.)

Height (upper surface) 11.05mm (0.435")

Width 90.2mm (3.6")

Length 95.9mm (3.8")

Thickness 2.36mm (0.093")

NOTE Height is measured from the

upper board surface to the highest permanent component (PC/104 connector) on the upper board surface. This does not include the heatsink, which is required on the 800MHz CPU. The height of the board with the heatsink installed is

0.478" (12.19mm). Component height should not exceed 0.6" (15.24mm) from the upper surface of the board and 0.100" (2.54mm) from the lower surface of the board. See Note on page 16.

CoreModule 435 Reference Manual 15

Chapter 2 Product Overview

Mechanical Specifications

0.350

3.250

3.775

3.575

CM435_mech_dwg_top_a

0.200

Figure 2-9. Mechanical Dimensions (Top View)

3.350

3.550

NOTE All dimensions are given in inches. Black dots on vertical headers or connectors

indicate pin 1 in all illustrations. Black dots on right-angle headers or connectors indicate pin 1 in top-side views and pin 2 in bottom-side views (except for on the J7 Power header, which indicates pin 2 in top-side views and pin 1 in bottomside views).

The Compact Flash socket (J12) exceeds the PC/104 height limitation on the bottom side of the board by 0.2 inches.

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Chapter 2 Product Overview

Power Specifications

Table 2- 5 provides the power requirements for the 300 MHz and 800 MHz versions of the CoreModule 435.

Table 2-5. Power Supply Requirements

Parameter Characteristics for 300 MHz CPU Characteristics for 800 MHz CPU

Input Type Regulated DC voltages Regulated DC voltages

In-rush Current 14.80A (74.00W) 14.86A (74.30W)

Idle Power 1.30A (6.51W) 1.42A (7.12W)

BIT Current (Typical)

Operating configurations:

1.32A (6.58W) 1.44A (7.19W)

• In-rush operating configuration includes CRT video, 256MB DDR2 RAM, and power.

• Idle operating configuration includes the in-rush configuration as well as on-board Compact Flash with

64MB card, and one keyboard.

• BIT (Burn-In-Test) operating configuration includes idle configuration as well as two serial port loop-

backs, two Ethernet connections, and four USB Compact Flash readers with 64MB Compact Flash.

Environmental Specifications

Table 2- 6 provides the operating and storage condition ranges required for this module.

Table 2-6. Environmental Requirements

Parameter Conditions

Temperature

Operating –20° to +70° C (–4° to +158° F)

Extended (Optional) –40° to +85° C (–40° to +185° F)

Storage –55° to +85° C (–67° to +185° F)

Humidity

Operating 5% to 90% relative humidity, non-condensing

Non-operating 5% to 95% relative humidity, non-condensing

Thermal/Cooling Requirements

The CPU is the primary source of heat on the board. The 800 MHz version of the CoreModule 435 CPU is designed to operate at its maximum speed and requires a heatsink (provided). The 300 MHz version of the CoreModule 435 CPU also is designed to operate at its maximum speed but does not require a heatsink. See note on page 15 for height of the heatsink.

CoreModule 435 Reference Manual 17

Chapter 2 Product Overview

18 Reference Manual CoreModule 435

Chapter 3 Hardware

Overview

This chapter discusses the ICs and interfaces of the module features in the following order:

• CPU

• Graphics

• Memory and Flash

♦

System Memory

♦

Vid e o Memory

♦

SPI Flash

• Interrupt Channel Assignments

• Memory Map

• I/O Address Map

• Serial

• USB

• Utility

♦

Keyboard

♦

Mouse

♦

Battery

♦

Reset Switch

♦

Speaker

• Ethernet

• Vid eo

• SPI

• LPC

• Miscellaneous

♦

Time of Day/RTC

♦

User GPIO

♦

Oops! Jumper (BIOS Recovery)

♦

Watchdog Timer

• Power

CoreModule 435 Reference Manual 19

Chapter 3 Hardware

NOTE ADLINK Technology, Inc. only supports the features and options listed in this

manual. The main components used on the CoreModule 435 may provide more features or options than are listed in this manual. Some of these features/options are not supported on the module and will not function as specified in the chip documentation.

Only the pinout tables of non-standard headers and connectors are included in this chapter. This chapter does not include pinout tables for standard headers and connectors such as PC/104, 44-pin IDE, and Compact Flash.

CPU

The CoreModule 435 offers two versions of an embedded CPU—the DMP Vortex 86SX and 86DX—operating at 300 and 800 MHz, respectively, combining a powerful x86 core and a selection of peripheral interfaces onto one chip. The 86SX and 86DX integrate Processor Core, Memory Controller, and I/O Hub functions. This single chip supports logic including PC/104 and EIDE controllers and combines these with standard I/O interfaces to provide a PC compatible subsystem on a single chip.

Graphics

The CoreModule 435 provides a single PCI graphics controller chip which integrates a 2D engine and a PCI controller. The graphics controller incorporates a configurable 3.3V/2.5V DVO interface to support a third party TMDS transmitter and achieves high 2D performance with independent DDR2 memory.

Memory and Flash

The CoreModule 435 memory and flash consist of the following element(s):

• System Memory

• Vid e o Memory

• SPI Flash

System Memory

The CoreModule 435 provides two soldered 16-bit, DDR2 system memory chips of 128MB each for a total of 256MB.

Video Memory

The CoreModule 435 provides one soldered 16-bit, DDR2 video memory chip of 512MB.

SPI Flash

The CoreModule 435 features a 16Mbit SPI Flash chip for data storage. The board provides both the SPI Flash chip and an SPI header on the external SPI Bus.

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Chapter 3 Hardware

Interrupt Channel Assignments

The interrupt channel assignments are shown in Table 3-1.

Table 3-1. Interrupt Channel Assignments

Device vs IRQ No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Timer X

Keyboard X

Secondary Cascade X

COM1 O D

COM2 D O

COM3 O O O D

COM4 O O D O

RTC X

IDE D

Math Coprocessor (only in DX processor)

PS/2 Mouse X

PCI INTA Automatically Assigned

PCI INTB Automatically Assigned

PCI INTC Automatically Assigned

PCI INTD Automatically Assigned

USB Automatically Assigned

VGA Automatically Assigned

Ethernet Automatically Assigned

Legend: D = Default, O = Optional, X = Fixed

NOTE The IRQs for the Ethernet, Video, and Internal Local Bus (ISA) are

automatically assigned by the BIOS Plug and Play logic. Local IRQs assigned during initialization can not be used by external devices.

Table 3-2. DMA Map

DMA # Use

0-1, 5, 6, 7 Direct Memory Access

3 LPT 1, only in ECP mode (configurable)

4 DMA 1 cascade

CoreModule 435 Reference Manual 21

Chapter 3 Hardware

Memory Map

The following table provides the common PC/AT memory allocations. These are DOS-level addresses. The OS typically hides these physical addresses by way of memory management. Memory below 000500h is used by the BIOS.

Table 3-3. Memory Map - Vortex 86SX/DX Processor

Base Address Function

00000000h - 0009FFFFh Conventional Memory

000A0000h - 000AFFFFh Graphics Memory

000B0000h - 000B7FFFh Mono Text Memory

000B8000h - 000BFFFFh Color Text Memory

000C0000h - 000C7FFFh Standard Video BIOS

000D0000h - 000DFFFFh Reserved for Extended BIOS

000E0000h - 000EFFFFh Extended System BIOS Area

000F0000h - 000FFFFFh System BIOS Area (Storage and RAM Shadowing)

00100000h

FFFC0000h [for SX processor]

- Top of

DRAM

FFFFFFFFh System Flash

Main DRAM Range

FFE00000h [for DX processor]

I/O Address Map

Table 3- 4 shows the I/O address map. These are DOS-level addresses. The OS typically hides these physical

addresses by way of memory management.

Table 3-4. I/O Address Map

Address (hex) Subsystem

0000-000F Primary DMA Controller (#1)

0020-0021 Master Interrupt Controller (#1)

0040-0043 Programmable Interrupt Timer (Clock/Timer)

0060 Keyboard Controller

0061 ISA Standard Port B

0063 ISA Standard Port B alias

0064 Keyboard Controller

0065 ISA Standard Port B alias

0067 ISA Standard Port B alias

0069 ISA Standard Port B alias

006B ISA Standard Port B alias

006D ISA Standard Port B alias

006F ISA Standard Port B alias

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Chapter 3 Hardware

Table 3-4. I/O Address Map (Continued)

0070-0071 RTC/ NMI enable

0080-008F DMA Page

00A0-00A1 Slave Interrupt Controller (#2)

00C0-00DF Secondary DMA Controller (#2)

00F0-00FF Math Coprocessor (only in the DX processor)

01F0-01F7 IDE 0 (can be disabled)

02E8-2FF Serial Port 4 (COM4) (base configuration @

3F8h/2F8h/3E8h/2E8h/10)

02F8-02FF Serial Port 2 (COM2) (base configuration @

3F8h/2F8h/3E8h/2E8h/10)

03E8-3EF Serial Port 3 (COM3) (base configuration @

3F8h/2F8h/3E8h/2E8h/10)

03F6 IDE 0 (see 1F0)

03F8-03FF Serial Port 1 (COM1) (base configuration @

3F8h/2F8h/3E8h/2E8h/10)

0CF8 PCI Configuration Address

0CFC-0CFF PCI Configuration Data

Serial Interface

The Vortex CPU contains the circuitry for all four serial ports. The CoreModule 435 provides serial ports 1 and 2 through transceivers U7 and U9 (headers J3 and J9), serial port 3 through transceiver U4 (header J14) and serial port 4 through transceiver U5 (header J13). The serial ports support the following features:

• Programmable word length, stop bits and parity

• 16-bit programmable baud rate generator

• Interrupt generator

• Loop-back mode

• 16-bit FIFOs for each port

• Ports 1, 2, 3, and 4 are supported by the Vortex processor and are 16C550/16C552 compatible

♦

Serial 1 (J3, COM1) supports RS-232/RS-485 with full modem operation

♦

Serial 2 (J9, COM2) supports RS-232/RS-485 with full modem operation

♦

Serial 3 (J14, COM3) supports RS-232 with full modem operation

♦

Serial 4 (J13, COM4) supports RS-232 with full modem operation

NOTE The RS-232/RS-485 modes for Serial Port 1 (COM1) and Serial Port 2 (COM2)

are selected in BIOS Setup Utility. However, the RS-232 mode is the default (Standard) for any serial port.

RS-485 mode termination is selected with jumper JP2 Serial 1 (COM1) and JP1 Serial 2 (COM2) on the module. Refer to Table 2-3 for more information.

To implement the two-wire RS-485 mode on either serial port, you must tie together the equivalent pins for the selected port.

CoreModule 435 Reference Manual 23

Chapter 3 Hardware

For example, you must tie pin 3 (Rx Data –) to pin 5 (Tx Data –) and pin 4 (Tx Data +) to pin 6 (Rx Data +) at Serial Port 1 or 2 (J3 or J9) for the two-wire interface. As an alternate, you may short the equivalent pins on the DB9 connector attached to respective serial port, as shown in Figure 3-1. Refer also to the following tables for the specific pins on the connectors. The RS-422 mode uses a four-wire interface and does not require combining pins for its operation, but you must select RS-485 in BIOS Setup.

CM435RS485jump_a

Serial Ports (J3, J9) (COM1 or COM2)

Side View

Standard DB9 Serial

Port Connector (Female)

Rear View

6810

Figure 3-1. RS-485 Serial Port Implementation

Table 3- 5 provides the signals for the corresponding pins of the two independent serial interfaces: Serial 1 &

2. Tab le 3- 6 provides the signals for the corresponding pins of the two independent serial interfaces: Serial 3 & 4. Both interfaces use 10-pin, right-angle headers with 2 rows, odd/even sequence (1, 2), and 0.100" (2.54mm) pitch.

Table 3-5. Serial Port 1 (J3) & Port 2 (J9) Interface Pin Signals

Pin # Signal DB9 # Description

1 DCD* 1 Data Carrier Detect – Indicates external serial device is detecting a

carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input is driven by DTR as part of the DTR/ DSR handshake.

2 DSR* 6 Data Set Ready – Indicates external serial device is powered, initialized,

and ready. Used as hardware handshake with DTR for overall readiness.

3RXD

2 Receive Data – Serial port receive data input is typically held at a logic 1

(mark) when no data is being transmitted, and is held “Off” for a brief interval after an “On” to “Off” transition on the RTS line to allow the transmission to complete.

Rx Data –

4RTS*

7 Request To Send – Indicates serial port is ready to transmit data. Used as

Serial Port 1 or 2 – If in RS-485 mode, this pin is Rx Data Negative.

hardware handshake with CTS for low level flow control.

Tx Data +

5TXD

3 Transmit Data – Serial port transmit data output is typically held to a

Serial Port 1 or 2 – If in RS-485 mode, this pin is Tx Data Positive.

logic 1 when no data is being sent. Typically, a logic 0 (On) must be present on RTS, CTS, DSR, and DTR before data can be transmitted on this line.

Tx Data –

6CTS*

8 Clear To Send – Indicates external serial device is ready to receive data.

Serial Port 1 or 2 – If in RS-485 mode, this pin is Tx Data Negative.

Used as hardware handshake with RTS for low level flow control.

Rx Data +

Serial Port 1 or 2 – If in RS-485 mode, this pin is Rx Data Positive.

7 DTR* 4 Data Terminal Ready – Indicates serial port is powered, initialized, and

ready. Used as hardware handshake with DSR for overall readiness.

8 RI* 9 Ring Indicator – Indicates external serial device is detecting a ring

condition. Used by software to initiate operations to answer and open the communications channel.

GND 5 Ground

10 Key/NC NC Key Pin/Not connected

Note: The shaded table cells denote power or ground. The * symbol indicates the signal is Active Low.

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Chapter 3 Hardware

Table 3-6. Serial Port 3 (J14) & Port 4 (J13) Interface Pin Signals

Pin # Signal DB9 # Description

1 DCD* 1 Data Carrier Detect – Indicates external serial device is detecting a

carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input is driven by DTR as part of the DTR/ DSR handshake.

2 DSR* 6 Data Set Ready – Indicates external serial device is powered, initialized,

and ready. Used as hardware handshake with DTR for overall readiness.

3 RXD 2 Receive Data – Serial port receive data input is typically held at a logic 1

(mark) when no data is being transmitted, and is held “Off” for a brief interval after an “On” to “Off” transition on the RTS line to allow the transmission to complete.

4 RTS* 7 Request To Send – Indicates serial port is ready to transmit data. Used as

hardware handshake with CTS for low level flow control.

5 TXD 3 Transmit Data – Serial port transmit data output is typically held to a

logic 1 when no data is being sent. Typically, a logic 0 (On) must be present on RTS, CTS, DSR, and DTR before data can be transmitted on this line.

6 CTS* 8 Clear To Send – Indicates external serial device is ready to receive data.

Used as hardware handshake with RTS for low level flow control.

7 DTR* 4 Data Terminal Ready – Indicates serial port is powered, initialized, and

ready. Used as hardware handshake with DSR for overall readiness.

8 RI* 9 Ring Indicator – Indicates external serial device is detecting a ring

condition. Used by software to initiate operations to answer and open the communications channel.

GND 5 Ground

10 Key/NC NC Key Pin – Not connected

Note: The shaded table cells denote power or ground. The * symbol indicates the signal is Active Low.

CoreModule 435 Reference Manual 25

Chapter 3 Hardware

USB Interface

The CoreModule 435 contains one root USB (Universal Serial Bus) hub and two functional USB ports. The Vortex CPU provides the USB function including the following features:

• Provides one root hub with two USB ports

• Supports USB EHCI v.2.0 and USB OHCI v.1.1

• Provides over-current detection status

• Provides a fuse (F1, 1.5A) on board for over-current protection

Table 3- 7 describes the pin signals of the USB0 interface, which uses a single-row, 5-pin, right-angle header

with 0.100" (2.54mm) pitch.

Table 3-7. USB0 Interface Pin Signals (J10)

Pin # Signal Description

2 USB0N USB0 Port Data Negative

3 USB0P USB0 Port Data Positive

5SHIELDUSB0 Port shield

USB0PWR USB Power – VCC (+5V +/-5%) power goes to the port through an on-board

fuse. Port is disabled if this input is low.

GND USB0 Port ground

Note: The shaded table cells denote power or ground.

Table 3- 8 describes the pin signals of the USB1 interface, which uses a single-row, 5-pin, vertical header

with 0.079" (2mm) pitch.

Table 3-8. USB1 Interface Pin Signals (J17)

Pin # Signal Description

2 USB1N USB1 Port Data Negative.

3 USB1P USB1 Port Data Positive

5SHIELDUSB1 Port shield

Note: The shaded table cells denote power or ground.

USB1PWR USB Power – VCC (+5V +/-5%) power goes to the port through an on-board

fuse. Port is disabled if this input is low.

GND USB1 Port ground

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Chapter 3 Hardware

Utility Interface

The Utility interface provides various utility and I/O signals on the module and consists of a 10-pin, 0.1" (2.54mm) pitch header. The Vortex CPU drives the signals on the Utility interface, and Ta ble 3- 9 provides the signal definitions.

• PS/2 Keyboard and PS/2 Mouse

• Battery

• Reset Switch

• Speaker

Keyboard

The signal lines for a PS/2 keyboard are provided from the Vortex CPU to the Utility interface.

Mouse

The signal lines for a PS/2 mouse are provided from the Vortex CPU to the Utility interface.

Battery

An external battery input connection is provided through the Utility interface to support a battery backup for the CMOS RAM and the RTC (Real Time Clock).

Reset Switch

An external reset switch provides the reset signal through the Utility interface to a reset circuit, which drives the Vortex CPU.

Speaker

The speaker signal provides sufficient signal strength to drive a 1W 8 Ω “Beep” speaker through the Utility interface at an audible level. The speaker signal is driven from an on-board amplifier and the Vortex CPU.

Table 3- 9 describes the pin signals of the Utility interface, which uses a 10-pin, right-angle header with 2

rows, odd/even sequence (1, 2), and 0.100" (2.54mm) pitch.

Table 3-9. Utility Interface Pin Signals (J5)

Pin # Signal Description

1 SPKR Speaker Output

3 RESETSW* External Reset Switch signal

4 MDATA Mouse Data input

5 KBDATA Keyboard Data input

6 KBCLK Keyboard Clock input

10 MCLK Mouse Clock input

BATV- Ground return

GND Ground

KMPWR Keyboard /Mouse power (+5V) output

BATV+ Real time battery voltage (3.6V Type/ 4.0V Max) input

Note: The shaded table cells denote power or ground. The * symbol indicates the signal is Active Low.

CoreModule 435 Reference Manual 27

Chapter 3 Hardware

Fast Ethernet Interface

The Fast Ethernet solution originates from the Vortex 86SX/DX CPU and consists of both the Media Access Controller (MAC) and the Physical Layer (PHY) combined into a single component solution. The Vortex Fast Ethernet Control Unit is a 32-bit PCI controller that features enhanced scatter-gather bus mastering capabilities, which enables the processor to perform high-speed data transfers over the internal PCI bus. The bus master capabilities enable the component to process high-level commands and perform multiple operations, thereby off-loading communication tasks from the CPU. The Fast Ethernet interface offers the following features:

• Full duplex or half duplex support

• Full duplex support at 10 Mbps or 100 Mbps

• In full duplex mode, the Fast Ethernet controller adheres to the IEEE 802.3x Flow Control specification.

• In half duplex mode, performance is enhanced by a proprietary collision reduction mechanism.

• IEEE 802.3 10BaseT/100BaseTX compatible physical layer to wire transformer

• Two on-board LEDs support the speed and the link & activity status

• IEEE 802.3u Auto-Negotiation support

• Fast back-to-back transmission support with minimum interframe spacing (IFS).

• IEEE 802.3x auto-negotiation support for speed and duplex operation

• 3 kB transmit and 3 kB receive FIFOs (helps prevent data underflow and overflow)

• IEEE 802.3x 100BaseTX flow control support

• On-board magnetics (Ethernet isolation transformer)

Table 3-10 describes the pin signals of the Fast Ethernet interface, which uses a single-row, 8-pin header

with 0.100" (2.54mm) pitch.

Table 3-10. Fast Ethernet Interface Pin Signals (J2)

Pin # Signal Description

1 TX+ Analog Twisted Pair Ethernet Transmit Differential Pair – These pins transmit the

2TX-

3 RX+ Analog Twisted Pair Ethernet Receive Differential Pair – These pins receive the

6RX-

4 CT Center Tap – Connected through two 75 ohm resistors in series to center tap of

5CT

7 CT Center Tap – Connected through two 75 ohm resistors in series to center tap of

8CT

NOTE The magnetics (isolation transformer, U12) for the Ethernet connector is

serial bit stream through the isolation transformer.

isolation transformer and then to ground through common 1k PF capacitor.

included on the CoreModule 435.

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Chapter 3 Hardware

Gigabit Ethernet Interface

The Gigabit Ethernet solution originates from the 82541PI Gigabit Ethernet controller and consists of both the Media Access Controller (MAC) and the Physical Layer (PHY) combined into a single component solution. The Gigabit Ethernet controller is a 64-bit PCIe control unit that features enhanced scatter-gather bus mastering capabilities, which enable the processor to perform high-speed data transfers over the internal PCIe bus. The bus master capabilities enable the component to process high-level commands and perform multiple operations, thereby off-loading communication tasks from the CPU. The Gigabit Ethernet interface offers the following features:

• Full duplex or half duplex support at 10 Mbps, 100 Mbps, or 1000 Mbps

• In full duplex mode, the Ethernet controller adheres to the IEEE 802.3x Flow Control specification

• In half duplex mode, performance is enhanced by a proprietary collision reduction mechanism

• IEEE 802.3 compatible physical layer to wire transformer

• IEEE 802.3u Auto-Negotiation support

• Fast back-to-back transmission support with minimum interframe spacing (IFS)

• IEEE 802.3x auto-negotiation support for speed and duplex operation

• 3 kB transmit and 3 kB receive FIFOs (helps prevent data underflow and overflow)

• On-board magnetics (Ethernet isolation transformer)

Table 3-11 describes the pin signals of the Gigabit Ethernet header which consists of 10 right-angle pins,

two rows, odd/even (1,2) pin sequence, and 0.079" (2mm) pitch.

Table 3-11. Gigabit Ethernet Interface Pin Signals (J23)

Pin # Signal Description

3 MDI0+ Media Dependent Interface 0 +/-

4MDI0-

5 MDI1+ Media Dependent Interface 1 +/-

6MDI1-

7 MDI2+ Media Dependent Interface 2 +/-

8MDI2-

9 MDI3+ Media Dependent Interface 3 +/-

10 MDI3-

Note: The shaded table cells denote ground.

GND Ground

GND

NOTE The magnetics (isolation transformer, T1) for the Ethernet connector is included

on the CoreModule 435.

CoreModule 435 Reference Manual 29

Chapter 3 Hardware

Gigabit Ethernet External LED Interface

This header provides signals for an external LED that indicates Ethernet links and activity using a single row of 4 pins with 0.049" (1.25mm) pitch.

Table 3-12. Gigabit Ethernet External LED Pin Signals (J22)

Pin # Signal Description

1 /LINKA* Indicates link connectivity

2 /ACT_A* Indicates transmit or receive activity

3 /LINKA100* Indicates link activity at 100 Mbps

4 /LINKA1000* Indicates link activity at 1000 Mbps

Note: The * symbol indicates the signal is Active Low.

Video (TFT/VGA) Interface

The Volari Z9s graphics controller provides two graphics display ports for video signals to a flat panel display and traditional glass CRT monitor. The features are listed below:

• Enhanced 2D Graphics Accelerator

♦

Full BitBLT implementation for all 256 raster operations

♦

Hardware command queue

♦

Direct Draw accelerator

♦

GDI 2000 accelerator

♦

Supports transparent BitBLT with source and destination keys

♦

Rectangle clipping

♦

Fast line draw engine with styled pattern

♦

Fast rectangle fill engine

♦

256MB frame buffer with linear addressing

♦

64x64x2 bit-mapped mono hardware cursor

• VGA Interface

♦

VGA Controller with 135 MHz triple RAMDACs for 1280 x 1024 x 75 Hz display

♦

Supports 24-bit pixel depth

♦

Interlaced or non-interlaced output

• TFT Interface

♦

Conforms with VESA Flat Panel Display Interface FPDI-1B

♦

Supports up to 1600x1200 pixel display resolutions

♦

Uses Internal VGA Controller for display modes settings

♦

Supports 12-, 18-, and dual 12-bit Interface (1 pixel/clock)

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Chapter 3 Hardware

Table 3-13 describes the pin signals of the Video interface, which uses a 44-pin, right-angle header with 2

rows, odd/even sequence (1, 2), and 0.079" (2mm) pitch.

Table 3-13. Video Interface Pin Signals (J11)

Pin # Signal Description

1 TFTDClk TFT Shift Clock – This clock signal provides the timing for transferring digital

pixel data.

2 TFTDE TFT Data Enable – This signal indicates valid data on any of the FP [23:0] lines.

3 TFTLine TFT Line Pulse – This signal is the digital monitor equivalent of HSYNC.

4 TFTFrame TFT Frame Marker – This signal is the TFT monitor equivalent of VSYNC.

GND1 Ground 1

GND2 Ground 2

7 NC Not connected (FP0 = Flat Panel Data 0)

8 NC Not connected (FP1 = Flat Panel Data 1)

9 FP2 Flat Panel Data 2 – data output, Blue0 (18-bit)

10 FP3 Flat Panel Data 3 – data output, Blue1 (18-bit)

11 FP4 Flat Panel Data 4 – data output, Blue2 (18-bit)

12 FP5 Flat Panel Data 5 – data output, Blue3 (18-bit)

13 FP6 Flat Panel Data 6 – data output, Blue4 (18-bit)

14 FP7 Flat Panel Data 7 – data output, Blue5 (18-bit)

15 NC Not connected (FP8 = Flat Panel Data 8)

16 NC Not connected (FP9 = Flat Panel Data 9)

17 FP10 Flat Panel Data 10 – data output, Green0 (18-bit)

18 FP11 Flat Panel Data 11 – data output, Green1 (18-bit)

19 FP12 Flat Panel Data 12 – data output, Green2 (18-bit)

20 FP13 Flat Panel Data 13 – data output, Green3 (18-bit)

21 FP14 Flat Panel Data 14 – data output, Green4 (18-bit)

22 FP15 Flat Panel Data 15 – data output, Green5 (18-bit)

23 NC Not connected (FP16 = Flat Panel Data 16)

24 NC Not connected (FP17 = Flat Panel Data 17)

25 FP18 Flat Panel Data 18 – data output, Red0 (18-bit)

26 FP19 Flat Panel Data 19 – data output, Red1 (18-bit)

27 FP20 Flat Panel Data 20 – data output, Red2 (18-bit)

28 FP21 Flat Panel Data 21 – data output, Red3 (18-bit)

29 FP22 Flat Panel Data 22 – data output, Red4 (18-bit)

30 FP23 Flat Panel Data 23 – data output, Red5 (18-bit)

31 TFTEnVcc TFT Power Enable

32 TFTEnVee TFT Backlight Enable

+PNLVdd Panel Voltage (+3.3 or +5 volts ±5%) depending on setting of JP6

+12V Backlight Voltage (+5 or +12 volts ±5%) depending on setting of JP5

GND3 Ground 3

GND4 Ground 4

CoreModule 435 Reference Manual 31

Chapter 3 Hardware

Table 3-13. Video Interface Pin Signals (J11) (Continued)

37 HSYNC Horizontal Sync – This signal is used for the digital horizontal sync output to the

CRT. Also used (with VSYNC) to signal power management state information to the CRT per the VESA™ DPMS™ standard.

38 VSYNC Vertical Sync – This signal is used for the digital vertical sync output to the CRT.

Also used (with HSYNC) to signal power management state information to the CRT per the VESA™ DPMS™ standard.

40 RED Red – This pin provides the Red analog output to the CRT.

42 GREEN Green – This pin provides the Green analog output to the CRT.

44 BLUE Blue – This pin provides the Blue analog output to the CRT.

Note: The shaded table cells denote power or ground.

AGNDR Analog Ground for Red

AGNDG Analog Ground for Green

AGNDB Analog Ground for Blue

Serial Peripheral Interface (SPI)

The CoreModule 435 provides a 16Mbit SPI Flash controller (U6) for data storage. An SPI header (J19) provides user access to the SPI Flash controller through an external SPI Bus.

Table 3-14 describes the pin signals of the SPI interface, which uses a single-row, 6-pin header with 0.100"

(2.54mm) pitch.

Table 3-14. SPI Interface Pin Signals (J19)

Pin # Signal Description

1 EXT_CS SPI Chip Select

2 EXT_CLK SPI Clock

3 EXT_DO SPI Data Out

4EXT_DISPI Data In

Note: The shaded table cells denote power or ground.

V.3.3 +3.3 Volts Power

GND Ground

Low Pin Count Interface (LPC)

The LPC interface provides expansion for custom LPC devices.

Table 3-15 describes the pin signals of the LPC interface, which uses a 10-pin female header with 2 rows,

odd/even sequence (1, 2), and 0.050" (1.27mm) pitch.

Table 3-15. LPC Interface Pin Signals (J20)

Pin # Signal Description

3 DRQ DMA Request

4 AD3 Command, Address, and Data 3

5 SERIRQ Serial Interrupt Request

6 AD2 Command, Address, and Data 2

V.3.3 +3.3 Volts Power

GND Ground

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Chapter 3 Hardware

Table 3-15. LPC Interface Pin Signals (J20) (Continued)

7 CLK_PCI PCI Clock

8 AD1 Command, Address, and Data 1

9 FRAME Frame Signals - indicate start of new cycle or termination of broken cycle

10 AD0 Command, Address, and Data 0

Note: The shaded table cells denote power or ground.

Miscellaneous

Real Time Clock (RTC)

The CoreModule 435 contains a Real Time (time of day) Clock (RTC), which can be backed up with an external Lithium Battery. The CoreModule 435 will function without a battery in those environments which prohibit batteries. The CoreModule 435 will also continue to operate after the battery life has been exceeded. Under these conditions all setup information is restored from the on-board flash memory during POST along with the default date and time information.

NOTE Some operating systems require a valid default date and time to function.

User GPIO Interface

The CoreModule 435 provides GPIO pins for customer use, and the signals are routed to header J8. An example of how to use the GPIO pins resides in the Miscellaneous Source Code Examples on the CoreModule 435 Support Software QuickDrive.

The example program can be built by using the make.bat file. This produces a 16-bit DOS executable application, gpio.exe, which can be run on the CoreModule 435 to demonstrate the use of GPIO pins. For more information about the GPIO pin operation, refer to the Programming Manual for the Vortex processor at:

http://www.vortex86sx.com/?page_id=3.pdf

Table 3-16 describes the pin signals of the GPIO interface, which uses a 10-pin header with 2 rows, odd/

even sequence (1, 2), and 0.079" (2mm) pitch.

Table 3-16. User GPIO Interface Pin Signals (J8)

Pin # Signal Description

1 GPIO0 User defined

2 GPIO1 User defined

3 GPIO2 User defined

4 GPIO3 User defined

5 GPIO4 User defined

6 GPIO5 User defined

7 GPIO6 User defined

8 GPIO7 User defined

10 GND Ground

GND Ground

Note: The shaded table cells denote ground.

CoreModule 435 Reference Manual 33

Chapter 3 Hardware

Oops! Jumper (BIOS Recovery)

The Oops! jumper is provided in the event you have selected BIOS settings that prevent you from booting the system. By using the Oops! Jumper you can stop the current BIOS settings in the CMOS from being loaded, allowing you to proceed, using the default settings. Connect the DTR pin to the RI pin on Serial port 1 (COM 1) prior to boot up to prevent the present BIOS settings from loading. After booting with the Oops! Jumper in place, remove the Oops! Jumper and go into the BIOS Setup Utility. Change the desired BIOS settings, or select the default settings, and save changes before rebooting the system.

To convert a standard DB9 connector to an Oops! Jumper, short together the DTR (4) and RI (9) pins on the rear of the connector as shown in Figure 3-2 on the Serial Port 1 DB9 connector.

Standard DB9 Serial Port Connector (Female)

Rear View

Figure 3-2. Oops! Jumper

CM435_Oopsjump

Serial Console

The CoreModule 435 BIOS supports the serial console (or console redirection) feature. These I/O functions are provided by an ANSI-compatible serial terminal, or the equivalent terminal emulation software running on another system. This can be very useful when setting up the BIOS on a production line for systems that are not connected to a keyboard and display.

Serial Console BIOS Setup

The serial console (console redirection) feature is implemented by connecting a standard null-modem cable or a modified serial cable (or “Hot Cable”) from either serial port COM1 or COM2 (J3 or J9) to the serial terminal or a PC with communications software. The BIOS Setup Utility controls the serial console settings on the CoreModule 435. Refer to the BIOS Setup for the serial console option settings using a serial terminal or PC with communications software.

Hot (Serial) Cable

To convert a standard serial cable to a Hot Cable, certain pins must be shorted together at the Serial port header or at the DB9 connector. Short together the RTS (4) and RI (8) pins on either the COM1 or COM2 (J3 or J9) header. As an alternate, you can short the equivalent pins (pins 7 and 9) on the back of the respective DB9 connector as shown in Figure 3-3.

Serial Port Header (COM1 or COM2)

Standard DB9 Serial

Port Connector (Female)

6810

Figure 3-3. Hot Cable Jumper

Rear View (or Front View of Male Connector)

CM435_HotCable

34 Reference Manual CoreModule 435

Chapter 3 Hardware

Watchdog Timer

The Watchdog Timer (WDT) restarts the system if an error or mishap occurs, allowing the system to recover from the mishap, even though the error condition may still exist. Possible problems include failure to boot properly, loss of control by the application software, failure of an interface device, unexpected conditions on the bus, or other hardware or software malfunctions.

The WDT can be used both during the boot process and during normal system operation.

• During the Boot process – If the OS fails to boot in the time interval set in the BIOS, the system will

reset.

Enable the WatchDog Function (0 or 1) setting in the Chipset for a time-out interval in seconds, between 1 and 256, in one second increments. Ensure you allow enough time for the operating system (OS) to boot. The OS or application must tickle (reset) the WDT before the timer expires. This can be done by accessing the hardware directly or through a BIOS call.

• During System Operation – An application can set up the WDT hardware through a BIOS call, or by

accessing the hardware directly. Some ADLINK Board Support Packages provide an API to the WDT. The application must tickle (reset) the WDT before the timer expires or the system will be reset.

• Watchdog Code examples – ADLINK has provided source code examples on the CoreModule 435

Support Software QuickDrive illustrating how to control the WDT. The code examples can be easily copied to your development environment to compile and test the examples, or make any desired changes before compiling. Refer to the WDT Readme file in the Sample Code directory on the CoreModule 435 Support Software QuickDrive.

screen of the BIOS Setup. Set the WDT

Power Interface

The CoreModule 435 requires one +5 volt DC power source. If the +5VDC power drops below ~4.65V, a low voltage reset is triggered, resetting the system.

The power input header (J7) supplies the following voltages and ground directly to the module:

• 5.0VDC +/- 5% @ 1.35 Amps

Table 3-17 describes the pin signals of the Power interface, which uses a 10-pin, right-angle header with 2

rows, odd/even sequence (1, 2), and 0.100" (2.54mm) pitch.

Table 3-17. Power Interface Pin Signal (J7)

Pin Signal Descriptions

5 GND Ground

6 NC Not connected

8 +5V +5 Volts

GND Ground

+5V +5 Volts

Key/GND Key Pin on connector/Grounded on board

+12V +12 volts routed to PC/104

GND Ground

+5V +5 Volts

Note: The shaded table cells denote power or ground.

CoreModule 435 Reference Manual 35

Chapter 3 Hardware

36 Reference Manual CoreModule 435

Chapter 4 BIOS Setup

Introduction

This section assumes the user is familiar with general BIOS Setup and does not attempt to describe the BIOS functions. Refer to “BIOS Setup Menus” on page 39 in this chapter for a map of the BIOS Setup settings. If ADLINK has added to or modified any of the standard BIOS functions, these functions will be described.

Entering BIOS Setup (VGA Display)

To access BIOS Setup using a VGA display for the CoreModule 435:

1. Turn on the VGA monitor and the power supply to the CoreModule 435.

2. Start Setup by pressing the [Del] key when the following message appears on the boot screen.

Press DEL to run Setup

NOTE If the setting for Quick Boot is [Enabled], you may not see this prompt appear on

screen. If this happens, press the <Del> key earlier in the boot sequence to enter BIOS Setup.

3. Follow the instructions on the right side of the screen to navigate through the selections and modify any settings.

Entering BIOS Setup (Remote Access)

This section describes how to enable the Remote Access in VGA mode and enter the BIOS setup through a serial terminal or PC.

1. Turn on the power supply to the CoreModule 435 and enter the BIOS Setup Utility in VGA mode.

2. Set the BIOS feature Remote Access to [Enabled] under the Advanced menu.

3. Accept the default options or make your own selections for the balance of the Remote Access fields and record your settings.

4. Ensure you select the type of remote serial terminal you will be using and record your selection.

5. Select Save Changes and Exit and then shut down the CoreModule 435.

6. Connect the remote serial terminal (or the PC with communications software) to the COM port you selected and recorded earlier in the BIOS Setup Utility.

7. Turn on the remote serial terminal or PC and set it to the settings you selected in the BIOS Setup Utility.

The default settings for the CoreModule 435 are:

♦

COM1

♦

115200

♦

8 bits

♦

1 stop bit

♦

no parity

♦

no flow control

♦

[Always] for Redirection After BIOS POST

♦

[ANSI] for Terminal Type

♦

[Enabled] for VT-UTF8 Combo Key Support

CoreModule 435 Reference Manual 37

Chapter 4 BIOS Setup

♦

[No Delay] for Sredir Memory Display Delay

8. Restore power to the CoreModule 435.

9. Press the F4 key to enter Setup (early in the boot sequence if Quick Boot is set to [Enabled].)

If Quick Boot is set to [Enabled], you may never see the screen prompt.

10. Use the <Enter> key to select the screen menus listed in the Opening BIOS screen.

NOTE The serial console port is not hardware protected. Diagnostic software that

probes hardware addresses may cause a loss or failure of the serial console functions.

OEM Logo Utility

The CoreModule 435 BIOS supports a graphical logo utility, which allows the user to customize the boot screen image. The graphical image can be a company logo or any custom image the user wants to display during the boot process. The custom image can be displayed as the first image on screen during the boot process and remain there while the OS boots, depending on the options selected in BIOS Setup.

NOTE The Quiet Boot feature must be set to Enabled in the Boot screen of BIOS Setup

for the system to recognize the OEM Logo feature.

Logo Image Requirements

The user’s image may be customized with any image editing tool, and the system will automatically convert the image into an acceptable format to the tools (files and utilities) provided by ADLINK. The CoreModule 435 supports the following image formats:

• Bitmap image

♦

16-Color, 640x480 pixels

♦

256-Color, 640x480 pixels

• JPG image

♦

16-Color, 640x480 pixels

♦

256-Color, 800x600 pixels

♦

256-Color, 1024x768 pixels

• PCX image

♦

256-Color, 640x480 pixels

• A file size no larger than 20k

38 Reference Manual CoreModule 435

Chapter 4 BIOS Setup

BIOS Setup Menus

This section provides illustrations of the seven main setup screens in the CoreModule 435 BIOS Setup Utility. Below each illustration is a bullet list of the screen’s submenus and setting selections. The setting selections are presented in brackets after each submenu or menu item and the optimal default settings are presented in bold. For more detailed definitions of the BIOS settings, refer to the AMIBIOS8 manual: http://www.ami.com/support/doc/MAN-EZP-80.pdf

Table 4-1. BIOS Setup Menus

BIOS Setup Utility Menu Item/Topic

Main Settings Date and Time

Advanced Settings CPU settings, IDE Drive Configurations, Remote Access (Serial

Console), USB Configuration, and Southbridge LAN

PCIPnP (PCI, Plug n' Play) PCI settings, Plug & Play settings, Interrupt settings and DMA channel

settings, Reserved memory size

Boot Boot-up Settings

Security Setting or changing Passwords, Boot Sector Virus Protection

Chipset Northbridge and Southbridge settings

Exit Exiting with or without changing settings, Loading Optimal or Failsafe

conditions

BIOS Main Setup Screen

BIOS Setup Utility

Main Advanced PCIPnP Boot Security Chipset Exit

System Overview

AMIBIOS

Version : 08.XX.XX Build Date: XX/XX/XX ID : CM435-XX.X

Processor

Vortex A91XX Speed :XXX MHz

System Memory

Size :XXXMB Speed :XXXMHz

System Time [XX:XX:XX] System Date [Xxx XX/XX/20XX]

Select Screen

Select Item

+ - Change Tab Select Field F1 General Help F10 Save and Exit ESC Exit

Field

CM435_BIOS_MainScreen_b

Figure 4-1. BIOS Main Setup Screen

• Date & Time

♦

System Time (hh:mm:ss) – This is a 24-hour clock setting in hours, minutes, and seconds.

CoreModule 435 Reference Manual 39

Chapter 4 BIOS Setup

♦

System Date (day of week, mm:dd:yyyy) – This field requires the alpha-numeric entry of the day of week, day of the month, calendar month, and all 4 digits of the year, indicating the century plus year (Fri 10/21/2011).

BIOS Advanced Setup Screen

BIOS Setup Utility

Main Advanced PCIPnP Boot Security Chipset Exit

Advanced Settings

WARNING: Setting wrong values in below sections may cause system to malfunction.

Board Configuration CPU Configuration IDE Configuration Remote Access Configuration USB Configuration

SB LAN [Enabled] MAC Address XX XX XX XX XX XX

Select Screen

Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit

Figure 4-2. BIOS Advanced Setup Screen

Board Configuration

Chip Serial Number : XX XX XX XX XX XX

CPU Configuration

Manufacture:: DMP

Brand String:: Vortex A91XX

Frequency: : X00MHz

L1 Cache [Disabled; Enabled]

Cache L1 : XX KB

L2 Cache (only on DX model) [Disabled; Enabled]

Cache L2 : XXX KB

IDE Configuration

• OnBoard PCI IDE Controller – [Disabled; Primary; Secondary; Both]

♦

Primary IDE Master : [Not Detected]

• Type – [Not Installed; Auto; CD/DVD; ARMD]

CM435_BIOS_AdvancedScreen_b

• LBA/Large Mode – [Disabled; Auto]

• Block (Multi-Sector Transfer – [Disabled; Auto]

40 Reference Manual CoreModule 435

Chapter 4 BIOS Setup

• PIO Mode – [Auto; 0; 1; 2; 3; 4]

• DMA Mode – [Auto]

• S.M.A.R.T. – [Auto; Disabled; Enabled]

• 32Bit Data Transfer – [Disabled; Enabled]

♦

Primary IDE Slave : [Not Detected]

• Type – [Not Installed; Auto; CD/DVD; ARMD]

• LBA/Large Mode – [Disabled; Auto]

• Block (Multi-Sector Transfer) – [Disabled; Auto]

• PIO Mode – [Auto; 0; 1; 2; 3; 4]

• DMA Mode – [Auto]

• S.M.A.R.T. – [Auto; Disabled; Enabled]

• 32Bit Data Transfer – [Disabled; Enabled]

• Hard Disk drive Write Protect – [Disabled; Enabled]

• IDE Detect Time Out (Sec) – [0; 5; 10; 15; 20; 25; 30; 35]

• ATA (PI) 80Pin Cable Detection – [Host & Device; Host; Device]

• Hard Disk Delay – [Disabled; 1 Second; 2 Second; 4 Second; 8 Second]

• OnBoard IDE Operate Mode – [Legacy Mode; Native Mode]

• Not Program PIO mode – [Disabled; Primary Channel; Secondary Channel]

• Primary IDE Pin Select – [Parallel IDE; SD Card]

Remote Access Configuration

• Remote Access – [Hotcable; Enabled]

• Serial port number – [COM1; COM2]

Base Address, IRQ [3F8h, 4]

• Serial Port Mode – [115200 8, n, 1; 57600 8, n, 1; 38400 8, n, 1; 19200 8, n, 1; 09600 8, n, 1]

• Flow Control – [None; Hardware; Software]

• Redirection After BIOS POST – [Disabled; Boot Loader; Always]

• Terminal Type – [ANSI; VT100; VT-UTF8]

: If VT-UTF8 is selected, the following item disappears from the screen.

Note

• VT-UTF8 Combo Key Support – [Disabled; Enabled]

• Sredir Memory Display Delay – [No Delay; Delay 1 sec; Delay 2 sec; Delay 4 sec]

USB Configuration

• USB Port 0, 1 – [Enabled; Disabled]

• USB Port 2, 3 – [Enabled; Disabled]

• USB Device – [Enabled; Disabled]

• Legacy USB Support – [Disabled; Enabled; Auto]

: If Disabled is selected, the following item disappears from the screen.

Note

• USB 2.0 Controller Mode – [Full Speed; Hi Speed]

• BIOS EHCI Hand-Off – [Disabled; Enabled]

CoreModule 435 Reference Manual 41

Chapter 4 BIOS Setup

SB LAN [Enabled; Disabled]

MAC Address

XX XX XX XX XX XX

BIOS PCIPnP Setup Screen

BIOS Setup Utility

Main Advanced PCIPnP Boot Security Chipset Exit

Advance PCI/PnP Settings

WARNING: Setting wrong values in below sections may cause system to malfunction.

Clear NVRAM Plug & Play O/S PCI Latency Timer Allocate IRQ to PCI VGA Pallette Snooping PCI IDE BusMaster [Enabled] OffBoard PCI/ISA IDE Card [Auto]

IRQ3 [Reserved] IRQ4 [Reserved] IRQ5 [Available] IRQ6 [Available]

IRQ7 [Reserved] IRQ9 [Available] IRQ10 [Available] IRQ11 [Available] IRQ12 [Available] IRQ14 [Available] IRQ15 [Reserved]

DMA Channel 0 [Available] DMA Channel 1 [Available]

DMA Channel 3 [Available] DMA Channel 5 [Available] DMA Channel 6 [Available] DMA Channel 7 [Available]

Reserved Memory Size [Disabled]

[No] [No] [64]

[No]

[Disabled]

Select Screen

Select Item + - Change Option F1 General Help F10 Save and Exit ESC Exit

CM435_BIOS_PCIPnPScreen_b

Figure 4-3. BIOS PCIPnP Setup Screen

• Clear NVRAM – [No; Yes]

• Plug & Play O/S – [No; Yes]

• PCI Latency timer – [32; 64; 96; 128; 160; 192; 224; 248]

• Allocate IRQ to PCI VGA – [Yes; No]

• Palette Snooping – [Disabled; Enabled]

• PCI IDE BusMaster – [Disabled; Enabled]

• OffBoard PCI/ISA IDE card – [Auto; PCI Slot 1; PCI Slot 2; PCI Slot 3; PCI Slot 4; PCI Slot 5;

PCI Slot 6]

• IRQ3 – [Available; Reserved]

• IRQ4 – [Available; Reserved]

42 Reference Manual CoreModule 435

Chapter 4 BIOS Setup

• IRQ5 – [Available; Reserved]

• IRQ6 – [Available; Reserved]

• IRQ7 – [Available; Reserved]

• IRQ9 – [Available; Reserved]

• IRQ10 – [Available; Reserved]

• IRQ11 – [Available; Reserved]

• IRQ12 – [Available; Reserved]

• IRQ14 – [Available; Reserved]

• IRQ15 – [Available; Reserved]

• DMA Channel 0 – [Available; Reserved]

• DMA Channel 1 – [Available; Reserved]

• DMA Channel 3 – [Available; Reserved]

• DMA Channel 5 – [Available; Reserved]

• DMA Channel 6 – [Available; Reserved]

• DMA Channel 7 – [Available; Reserved]

• Reserved Memory – [Disabled; 16k; 32k; 64k]

BIOS Boot Setup Screen

BIOS Setup Utility

Main Advanced PCIPnP Boot Security Chipset Exit

Boot Settings

Boot Settings Configuration

Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit

Select Screen

CM435_BIOS_BootScreen_a

Figure 4-4. BIOS Boot Setup Screen

Boot Settings Configuration

• Quick Boot – [Disabled; Enabled]

CoreModule 435 Reference Manual 43

Chapter 4 BIOS Setup

• Quiet Boot – [Disabled; Enabled]

• Add On ROM Display Mode – [Force BIOS; Keep Current]

• Bootup Num-Lock – [Off; On]

• PS/2 Mouse Support – [Disabled; Enabled; Auto]

• Wait for 'F1' If Error – [Disabled; Enabled]

• Hit 'DEL' Message Display – [Disabled; Enabled]

• Interrupt 19 Capture – [Disabled; Enabled]

• Boot From LAN – [Disabled; Used INT 18h; Used INT 19h; PnP/BEV (BBS); RPL]

• Beep Function – [Disabled; Enabled]

• OnBoard Virtual Flash FDD – [Disabled; Enabled; Diskette Write Protect]

BIOS Security Setup Screen

BIOS Setup Utility

Main Advanced PCIPnP Boot Security Chipset Exit

Security Settings

Supervisor Password : Not installed User Password :Not installed

Change Supervisor Password Change User Password

Boot Sector Virus Protection [Disabled]

Figure 4-5. BIOS Security Setup Screen

• Supervisor Password – [Not Installed]

• User Password – [Not Installed]

• Change Supervisor Password

Select Screen

Select Item Enter Change F1 General Help F10 Save and Exit ESC Exit

CM435_BIOS_SecurityScreen_a

a. Select Change Supervisor Password from the Security Setup menu.

b. Press <Enter> to access the pop-up entry field, Enter New Password.

c. Type the password and press <Enter> again.

The screen will not display the password as you type.

44 Reference Manual CoreModule 435

Chapter 4 BIOS Setup

d. Re-type the password when prompted by the pop-up entry field and press <Enter> again.

If the password is not confirmed when you re-type it, an error message will appear. The password is stored in NVRAM if you have successfully entered the password.

• Change User Password

a. Select Change User Password from the Security Setup menu.

b. Press <Enter> to access the pop-up entry field, Enter New Password.

c. Type the password and press <Enter> again.

The screen will not display the password as you type.

d. Re-type the password when prompted by the pop-up entry field and press <Enter> again.

If the password is not confirmed when you re-type it, an error message will appear. The password is stored in NVRAM if you have successfully entered the password.

• Boot Sector Virus Protection – [Disabled; Enabled]

BIOS Chipset Setup Screen

BIOS Setup Utility

Main Advanced PCIPnP Boot Security Chipset Exit

Advance Chipset Settings

WARNING: Setting wrong values in below sections may cause system to malfunction.

NorthBridge Configuration

SouthBridge Configuration

Figure 4-6. BIOS Chipset Setup Screen

NorthBridge Configuration

• NorthBridge Chipset Configuration

Select Screen

Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit

CM435_BIOS_ChipsetScreen_a

♦

DRAM Timing Setting By – [Manual; BIOS]

♦

CPU Speed Setting By – [Divide By 1; Divide By 2; Divide By 3; Divide By 4; Divide By 5; Divide By 6; Divide By 7; Divide By 8]

CoreModule 435 Reference Manual 45

Chapter 4 BIOS Setup

SouthBridge Configuration

• SouthBridge Chipset Configuration

P.O.S.T. Forward To [Disabled; COM1]

♦

ISA Configuration

• ISA Clock – [8.3MHz; 16.6MHz]

• ISA 16bits I/O wait-state – [1 clock; 2 clock; 3 clock; 4 clock; 5 clock; 6 clock; 7 clock; 8 clock]

• ISA 8bits I/O wait-state – [1 clock; 2 clock; 3 clock; 4 clock; 5 clock; 6 clock; 7 clock; 8 clock]

• ISA 16bits Memory wait-state – [0 clock; 1 clock; 2 clock; 3 clock; 4 clock; 5 clock; 6 clock; 7 clock]

• ISA 8bits Memory wait-state – [1 clock; 2 clock; 3 clock; 4 clock; 5 clock; 6 clock; 7 clock; 8 clock]

♦

Serial Port Configuration

• SB Serial Port 1 – [Disabled; 3F8; 2F8; 3E8; 2E8; 10]

- Serial Port IRQ 1 [IRQ3; IRQ4; IRQ9; IRQ10; IRQ11]

- Serial Port Baud Rate [2400 BPS; 4800 BPS; 9600 BPS; 19200 BPS; 38400 BPS; 57600 BPS; 115200 BPS]

- Serial Port Type [RS232; RS485]

• SB Serial Port 2 – [Disabled; 3F8; 2F8; 3E8; 2E8; 10]

- Serial Port IRQ 2 [IRQ3; IRQ4; IRQ9; IRQ10; IRQ11]

- Serial Port Baud Rate [2400 BPS; 4800 BPS; 9600 BPS; 19200 BPS; 38400 BPS; 57600 BPS; 115200 BPS]

- Serial Port Type [RS232; RS485]

• SB Serial Port 3 – [Disabled; 3F8; 2F8; 3E8; 2E8; 10]

• SB Serial Port 4 – [Disabled; 3F8; 2F8; 3E8; 2E8; 10]

46 Reference Manual CoreModule 435

Chapter 4 BIOS Setup

♦

WatchDog Configuration

• WatchDog 0 Function – [Enabled; Disabled]

• WatchDog 1 Function – [Enabled; Disabled]

♦

Multi-Function Port Configuration

• Port0 Function – [GPIO; 8051 P0; PWM00 . . PWM07]

• Port0 Bit0 Direction – [IN; OUT]

• Port0 Bit1 Direction – [IN; OUT]

• Port0 Bit2 Direction – [IN; OUT]

• Port0 Bit3 Direction – [IN; OUT]

• Port0 Bit4 Direction – [IN; OUT]

• Port0 Bit5 Direction – [IN; OUT]

• Port0 Bit6 Direction – [IN; OUT]

• Port0 Bit7 Direction – [IN; OUT]

• Port3 Bit0 Function – [GPIO; 8051 P3; SPI]

- Direction – [IN; OUT]

• Port3 Bit1 Function – [GPIO]

- Direction – [IN; OUT]

• Port3 Bit2 Function – [GPIO]

- Direction – [IN; OUT]

• Port3 Bit3 Function – [GPIO]

- Direction – [IN; OUT]

• Port3 Bit4 Function – [GPIO; I2C]

- Direction – [IN; OUT]

• Port3 Bit5 Function – [GPIO]

- Direction – [IN; OUT]

• Port3 Bit6 Function – [GPIO; I2C]

- Direction – [IN; OUT]

• Port3 Bit7 Function – [GPIO]

- Direction – [IN; OUT]

♦

GPCS Configuration

• GPCS0 Function – [Enabled; Disabled]

• GPCS1 Function – [Enabled; Disabled]

♦

Redundancy Control Configuration

• Dual Port 4 KB SRAM – [Enabled; Disabled]

• SB Serial Port 9 – [Disabled; 3F8; 2F8; 3E8; 2E8; 10]

• WatchDog0 Condition – [Disabled; Enabled]

• WatchDog1 Condition – [Disabled; Enabled]

CoreModule 435 Reference Manual 47

Chapter 4 BIOS Setup

• Invalid OPCODE Condition – [Disabled; Enabled]

• KB/MS System Fail – [Normal; TRI-State]

• GPIO PORT0 System Fail – [Normal; TRI-State]

• UART1 System Fail – [Normal; TRI-State]

• UART2 System Fail – [Normal; TRI-State]

• UART3 System Fail – [Normal; TRI-State]

• UART4 System Fail – [Normal; TRI-State]

BIOS Exit Setup Screen

BIOS Setup Utility

Main Advanced PCIPnP Boot Security Chipset Exit

Exit Options

Save Changes and Exit Discard Changes and Exit Discard Changes

Load Optimal Defaults Load Failsafe Defaults

Figure 4-7. BIOS Exit Setup Screen

Save Changes and Exit

The < F10 > key can be used for this operation.

Discard Changes and Exit

The < ESC > key can be used for this operation.

Discard Changes

The < F7 > key can be used for this operation.

Load Optimal Defaults

Select Screen

Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit

CM435_BIOS_ExitScreen_a

The < F9 > key can be used for this operation.

Load Failsafe Defaults

The < F8 > key can be used for this operation.

48 Reference Manual CoreModule 435

Appendix A Technical Support

ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan

ᄅקؑխࡉ೴৬ԫሁ 166 ᇆ 9 ᑔ

Tel: +886-2-8226-5877 Fax: +886-2-8226-5717 Email: service@adlinktech.com

Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com

ADLINK Technology (China) Co., Ltd.

Address: Ϟ⍋Ꮦ⌺ϰᮄᓴ∳催⾥ᡔು㢇᯹䏃 300 ো(201203) 300 Fang Chun Rd., Zhangjiang Hi-Tech Park,

Pudong New Area, Shanghai, 201203 China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com

ADLINK Technology, Inc. provides a number of methods for contacting Technical Support listed in the

Table A- 1 below. Requests for support through the Ask an Expert are given the highest priority, and usually

will be addressed within one working day.

• ADLINK Ask an Expert– This is a comprehensive support center designed to meet all your technical

needs. This service is free and available 24 hours a day through the Ampro By ADLINK web page at

http://www.adlinktech.com/AAE/

which will help you with the common information requested by most customers. This is a good source of information to look at first for your technical solutions. However, you must register online if you wish to use the Ask a Question feature.

ADLINK strongly suggests that you register with the web site. By creating a profile on the ADLINK web site, you will have a portal page called “My ADLINK” unique to you with access to exclusive services and account information.

• Personal Assistance – You may also request personal assistance by creating an Ask an Expert account

and then going to the Ask a Question feature. Requests can be submitted 24 hours a day, 7 days a week. You will receive immediate confirmation that your request has been entered. Once you have submitted your request, you must log in to go to the My Question area where you can check status, update your request, and access other features.

• Download Service – This service is also free and available 24 hours a day at

http://www.adlinktech.com

. This includes a searchable database of Frequently Asked Questions,

. For certain downloads such as technical documents and software, you must

Table A-1. Technical Support Contact Information

Method Contact Information

Ask an Expert http://www.adlinktech.com/AAE/

Web Site http://www.adlinktech.com

Standard Mail

CoreModule 435 Reference Manual 49

Appendix A Technical Support

Table A-1. Technical Support Contact Information

ADLINK Technology Beijing

Address: ࣫ҀᏖ⍋⎔Ϟഄϰ䏃 1 োⲜ߯ࡼ࡯໻ E ᑻ 801 ᅸ(100085)

Rm. 801, Power Creative E, No. 1, B/D

Shang Di East Rd., Beijing, 100085 China Tel: +86-10-5885-8666 Fax: +86-10-5885-8625 Email: market@adlinktech.com

ADLINK Technology Shenzhen

Address: ⏅ഇᏖቅ⾥ᡔು催ᮄϗ䘧᭄ᄫᡔᴃು

A1 󰶀 2 ὐ C  (518057)

2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7,

High-Tech Industrial Park S., Shenzhen, 518054 China Tel: +86-755-2643-4858 Fax: +86-755-2664-6353 Email: market@adlinktech.com

ADLINK Technology (Europe) GmbH

Address: Nord Carree 3, 40477 Duesseldorf, Germany Tel: +49-211-495-5552 Fax: +49-211-495-5557 Email: emea@adlinktech.com

ADLINK Technology, Inc. (French Liaison Office)

Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com

ADLINK Technology Japan Corporation

Address: ͱ101-0045 ᵅҀ䛑ҷ⬄⼲⬄䤯ފ⬎ 3-7-4

⼲⬄ 374 ɛɳ 4F

KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho,

Chiyoda-ku, Tokyo 101-0045, Japan Tel: +81-3-4455-3722 Fax: +81-3-5209-6013 Email: japan@adlinktech.com

ADLINK Technology, Inc. (Korean Liaison Office)

Address: 昢殾柢昢爎割昢爎壟 1506-25 穢壊 B/D 2 猻

2F, Hando B/D, 1506-25, Seocho-Dong, Seocho-Gu,

Seoul 137-070, Korea Tel: +82-2-2057-0565 Fax: +82-2-2057-0563 Email: korea@adlinktech.com

ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre,

Singapore 349584 Tel: +65-6844-2261 Fax: +65-6844-2263 Email: singapore@adlinktech.com

ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: No. 1357, "Anupama", Sri Aurobindo Marg, 9th Cross, JP Nagar Phase I, Bangalore - 560078, India Tel: +91-80-65605817 Fax: +91-80-22443548 Email: india@adlinktech.com

50 Reference Manual CoreModule 435

Index

Numerics

1 to 256 settings Watchdog Timer (WDT) ......... 35

ANSI-compatible serial terminal ........................ 34

battery ................................................................. 27

external Lithium type function

header pin outs BIOS recovery BIOS Setup

console redirection

entering BIOS setup (VGA)

entering using serial console

Hot (Serial) Cable

serial terminal

setting menus

Splash Screen (OEM Logo) configuration

supported features

Watchdog Timer Block Diagram board features

......................................................... 33

...................................................... 6

................................................ 39

...................................................... 7

........................................................ 4

.................................... 33

.............................................. 27

........................................ 34

.......................... 37

......................... 37

......................................... 34

................................................ 34

... 38

......................................... 39

........................................... 35

Chip Specifications ............................................... 1

Compact Flash connectors

list

.................................................................. 10

locations

pin sequence definition console redirection CPU features current capability

...................................................... 4

........................................................ 10

................................. 11

.............................................. 34

...................................................4, 20

................................................ 35

dimensions .......................................................... 15

DMA map

........................................................... 21

Environmental specifications .............................. 17

Ethernet

Ethernet LED header

................................................................. 5

features

header

supported feature

.................................................... 28, 29

...................................................... 28, 29

........................................... 28

.......................................... 30

Gigabit Ethernet header ...................................... 29

GPIO Interface

.................................................... 33

header locations .................................................. 10

heatsink requirements height

.................................................................. 15

Hot cable

............................................................. 34

......................................... 17

IDE interface .........................................................4

Integrated Circuit (IC) specifications

web sites and data sheets integrated circuits (ICs) Interrupt (IRQs) list

.............................................21

.................................1

.........................................8

jumper settings ....................................................13

keyboard ......................................................... 5, 27

length ...................................................................15

Lithium battery

Real Time Clock (RTC) low voltage limit

..................................................35

................................33

mechanical dimensions ........................................16

memory memory map mouse

........................................................... 4, 20

........................................................22

.............................................................. 5, 27

null-modem serial cable ......................................34

OEM Logo screen

requirements Oops! jumper (BIOS recovery)

..................................................38

...................... 6, 34

PC/104 architecture ...............................................3

PC/104 interface pin sequence definition power interface header pin out power requirements product description

....................................................4

........................................11

............................35

.............................................17

................................................4

Real Time Clock ............................................. 6, 33

References reset switch RS-232/RS-485 support

.............................................................1

..........................................................27

......................................23

serial cable (modified) .........................................34

serial console serial interface serial port header pin outs serial ports serial terminal Single Board Computer (SBC) speaker pin signals specification references Splash Screen

.................................................. 6, 34

.......................................................5

...................................24

...........................................................23

......................................................34

..............................3

...............................................27

.........................................1

................................................. 6, 38

CoreModule 435 Reference Manual 51

Index

supported features

Compact Flash socket connector list console redirection DMA map Ethernet ports external battery external Ethernet LED external speaker GPIO interface GPIO signals Hot Cable IDE interface jumpers, on board keyboard major integrated circuits (ICs) mechanical dimensions memory memory map mouse Oops! jumper (BIOS recovery) PC/104 interface PS/2 mouse Real Time Clock reset switch RS-232/RS-485 selection serial console serial ports Splash Screen (OEM Logo) USB interface USB over current fuse USB ports Utility header video (CRT) interface video (LCD) interface video display Vortex CPU Watchdog Timer

................................................. 10

....................................6, 34

...................................................... 21

..................................... 5, 28, 29

..........................................5, 27

.............................................27

................................................ 6

.................................................33

...................................................... 34

................................................... 4

.......................................... 13

....................................................5, 27

.....................................................4, 20

.................................................. 22

............................................................ 27

.............................................. 4

......................................................5

....................................... 6, 33

....................................................27

.............................................6, 34

.................................................5, 23

................................................26

........................................................ 5

................................................. 27

...................................................5

...............................................4, 20

........................................6, 35

..................................... 4

................................... 30

........................ 8

................................. 16

.................6, 34

.............................. 23

......................6, 38

...................................26

...............................6, 30

Technical Support

Ask an Expert

contact methods terminal emulation software thermal cooling

heatsinks

................................................ 49

............................................ 49

............................... 34

........................................................ 17

USB

features

header pin outs

ports Utility header

battery connection

external speaker connection

keyboard connection

mouse connection

reset switch connection

.......................................................... 26

.............................................. 26

................................................................ 5

...................................................... 27

......................................... 27

.......................... 27

..................................... 27

......................................... 27

................................. 27

video displays ....................................................... 5

Video port

controller features

header

............................................................ 31

voltage requirements Vortex CPU

.......................................................... 4

......................................... 30

........................................... 35

Watchdog Timer .............................................6, 35

web sites

AMI BIOS 8 user’s guide

major chip specifications

PC/104 specification

PCI specification weight

................................................................. 15

............................................. 1

............................... 1

................................ 1

....................................... 1

52 Reference Manual CoreModule 435

ADLINK CoreModule 435 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Notice Page

Index