ADLINK cExpress-BT2 User Manual

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cExpress-BT2

User’s Manual

Manual Revision: 1.00 Revision Date: September 2 Part Number: 50-1J052-1000

4, 2014

Revision History

Revision Description Date By

1.00 Initial release 2014-09-24 JC

Page 2 cExpress-BT2

Preface

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not

represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

cExpress-BT2 Page 3

Revision History ............................................................................................................ 2

Preface............................................................................................................................ 3

1. Introduction......................................................................................................... 8

2. Specifications....................................................................................................... 9

2.1. Core System...........................................................................................................................9

2.2. Expansion Busses...................................................................................................................9

2.3. SEMA Board Controller..........................................................................................................9

2.4. Debug Headers ......................................................................................................................9

2.5. Video................................................................................................................................... 10

2.6. Audio................................................................................................................................... 10

2.7. LAN...................................................................................................................................... 10

2.8. Multi I/O and Storage ......................................................................................................... 10

2.9. TPM (Trusted Platform Module) ........................................................................................ 10

2.10. Power Specifications........................................................................................................... 11

2.11. Power Consumption ........................................................................................................... 11

2.12. Operating Temperatures .................................................................................................... 11

2.13. Environmental .................................................................................................................... 11

2.14. Specification Compliance.................................................................................................... 11

2.15. Operating Systems.............................................................................................................. 11

2.16. Functional Diagram............................................................................................................. 12

2.17. Mechanical Dimensions...................................................................................................... 13

3. Pinouts and Signal Descriptions......................................................................

3.1. AB / CD Pin Definitions ....................................................................................................... 14

3.2. Signal Description Terminology .......................................................................................... 17

3.3. AB Signal Descriptions ........................................................................................................ 18

3.3.1. Audio Signals .....................................................................................................................................18

3.3.2. Analog VGA........................................................................................................................................18

3.3.3. LVDS...................................................................................................................................................18

3.3.4. Gigabit Ethernet ................................................................................................................................19

3.3.5. SATA ..................................................................................................................................................19

3.3.6. PCI Express.........................................................................................................................................20

3.3.7. Express Card ......................................................................................................................................21

3.3.8. LPC bus ..............................................................................................................................................21

3.3.9. USB ....................................................................................................................................................21

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3.3.10. USB Root Segmentation ..................................................................................................................22

3.3.11. SPI (BIOS only) .................................................................................................................................22

3.3.12. Miscellaneous..................................................................................................................................23

3.3.13. SMBus..............................................................................................................................................23

3.3.14. I2C Bus .............................................................................................................................................23

3.3.15. General Purpose I/O (GPIO) ............................................................................................................23

3.3.16. Serial Interface Signals.....................................................................................................................24

3.3.17. Power And System Management....................................................................................................24

3.3.18. Power and Ground ..........................................................................................................................25

3.4. CD Signal Descriptions ........................................................................................................ 26

3.4.1. PATA IDE............................................................................................................................................26

3.4.2. PCI......................................................................................................................................................26

3.4.3. Module Type Definition.....................................................................................................................28

3.4.4. Power and Ground ............................................................................................................................28

4. Module interfaces ............................................................................................. 29

4.1. Connector, Switch and LED Locations ................................................................................ 29

4.1.1. cExpress-BT2 and the DB40 Module connected................................................................................29

4.2. 40-pin Multipurpose Connector ......................................................................................... 30

4.3. Status LEDs.......................................................................................................................... 31

4.4. XDP Debug Header ............................................................................................................. 32

4.5. Fan Connector .................................................................................................................... 32

4.6. BIOS Setup Defaults RESET Button ..................................................................................... 33

5. Smart Embedded Management Agent (SEMA) ............................................. 34

5.1. Board Specific SEMA Functions .......................................................................................... 35

5.1.1. Voltages.............................................................................................................................................35

5.1.2. Main Current .....................................................................................................................................35

5.1.3. BMC Status ........................................................................................................................................35

5.1.4. Exception Codes ................................................................................................................................36

5.1.5. BMC Flags ..........................................................................................................................................36

6. System Resources .............................................................................................. 37

6.1. System Memory Map ......................................................................................................... 37

6.2. I/O Map............................................................................................................................... 37

6.3. Interrupt Request (IRQ) Lines ............................................................................................. 38

6.3.1. PIC Mode ...........................................................................................................................................38

6.3.2. APIC Mode.........................................................................................................................................39

6.4. PCI Configuration Space Map ............................................................................................. 40

6.5. PCI Interrupt Routing Map.................................................................................................. 41

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6.6. PCI Interrupt Routing Map.................................................................................................. 41

7. BIOS Setup .........................................................................................................42

7.1. Menu Structure................................................................................................................... 42

7.2. Main.................................................................................................................................... 43

7.2.1. System Information ...........................................................................................................................43

7.2.2. Processor Information.......................................................................................................................43

7.2.3. VGA Firmware Version ......................................................................................................................43

7.2.4. Memory Information.........................................................................................................................43

7.2.5. SOC Information ................................................................................................................................43

7.2.6. System Management.........................................................................................................................44

7.2.7. System Date and Time.......................................................................................................................47

7.3. Advanced ............................................................................................................................ 47

7.3.1. CPU ....................................................................................................................................................47

7.3.2. Memory .............................................................................................................................................48

7.3.3. Graphics.............................................................................................................................................48

7.3.4. SATA ..................................................................................................................................................49

7.3.5. USB ....................................................................................................................................................49

7.3.6. Network.............................................................................................................................................50

7.3.7. PCI and PCIe.......................................................................................................................................51

7.3.8. Super IO.............................................................................................................................................53

7.3.9. ACPI and Power Management...........................................................................................................54

7.3.10. Sound...............................................................................................................................................54

7.3.11. Serial Port Console ..........................................................................................................................54

7.3.12. Thermal ...........................................................................................................................................55

7.3.13. Miscellaneous..................................................................................................................................56

7.4. Boot .................................................................................................................................... 57

7.4.1. Boot Configuration ............................................................................................................................57

7.5. Security ............................................................................................................................... 59

7.5.1. Password Description ........................................................................................................................59

7.6. Save & Exit .......................................................................................................................... 59

8. BIOS Checkpoints, Beep Codes........................................................................ 60

8.1. Checkpoint Ranges ............................................................................................................. 61

8.2. Standard Checkpoints......................................................................................................... 61

8.2.1. SEC Phase ..........................................................................................................................................61

8.2.2. SEC Beep Codes .................................................................................................................................62

8.2.3. PEI Phase ...........................................................................................................................................62

8.2.4. PEI Beep Codes..................................................................................................................................64

8.2.5. DXE Phase..........................................................................................................................................64

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8.2.6. DXE Beep Codes.................................................................................................................................67

8.2.7. ACPI/ASL Checkpoint.........................................................................................................................67

8.3. OEM-Reserved Checkpoint Ranges .................................................................................... 68

9. Mechanical Information ................................................................................... 69

9.1. Board-to-Board Connectors................................................................................................ 69

9.2. Thermal Solution ................................................................................................................ 70

9.2.1. Heat Spreaders ..................................................................................................................................70

9.2.2. Heat Sinks ..........................................................................................................................................70

9.2.3. Installation.........................................................................................................................................70

9.3. Mounting Methods............................................................................................................. 73

9.4. Standoff Types .................................................................................................................... 74

Safety Instructions ...................................................................................................... 75

Getting Service ............................................................................................................ 76

cExpress-BT2 Page 7

1. Introduction

The cExpress-BT2 is a COM Express® COM.0 R2.1 Type 2 module supporting the Intel® Atom™ E3800 processor and Intel® Celeron® processor, memory controller, and graphics processor on a single-chip design. The cExpress-BT2 is specifically designed for customers who need high-level processing and graphics performance with low power consumption in a long product life solution.

The cExpress-BT2 features the Intel® Atom™ E3800 processor and Intel® Celeron® processor supporting non-ECC type DDR3L dualchannel memory at 1066/1333 MHz to provide excellent overall performance.

Integrated Intel® 7 VC1, VP8 hardware decode. Graphics outputs include VGA and dual-channel 18/24-bit LVDS. The cExpress-BT2 is specifically designed for customers with high-performance graphics processing requirements who want to outsource the custom core logic of their systems for reduced development time.

The cExpress-BT2 has dual stacked SODIMM sockets for up to 8 GB non-ECC type DDR3L memory. In addition, an onboard eMCC memory is supported (optional, 8GB/16GB/32GB).

Generation HD Graphics includes features such as OpenGL 3.1, DirectX 11, OpenCL 1.1 support for H.264, MPEG2,

The cExpress-BT2 features a single onboard Gigabit Ethernet port, USB 2.0 ports, PATA and SATA 3 Gb/s ports, and PCI 2.3. Support is

provided for SMBus and I

C. The module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded features such as

remote console, CMOS backup, hardware monitor, and watchdog timer.

Page 8 cExpress-BT2

2. Specifications

2.1. Core System

¾ CPU: Single, dual or quad-core Intel® Atom™ or Celeron® Processor

• Atom™ E3845 1.91 GHz 542/792 (Turbo) 10W (4C/1333)

• Atom™ E3827 1.75 GHz 542/792 (Turbo) 8W (2C/1333)

• Atom™ E3826 1.46 GHz 533/667 (Turbo) 7W (2C/1066)

• Atom™ E3825 1.33 GHz 533 (No Turbo) 6W (2C/1066)

• Atom™ E3815 1.46 GHz 400 (No Turbo) 5W (1C/1066)

• Celeron® N2930 1.83/2.16 (Burst) GHz, 311/854 (Turbo) 7.5W (4C/1333)

• Celeron® J1900 2.0/2.42 (Burst) GHz, 688/854 (Turbo) 10W (4C/1333)

Single, dual or quad Out-of-Order Execution (OOE) processor cores Intel® VT-x, Intel® SSE4.1 and SSE4.2, Intel® 64 architecture, IA 32-bit, PCLMULQDQ Instruction DRNG, Intel® Thermal Monitor (TM1 & TM2) Note: the availability of the features may vary between processor SKUs.

Cache: Primary 32 KiB, 8-way L1 instruction cache and 24 KiB, 6-way L1 write-back data cache

¾ Memory: Dual channel non-ECC 1333/1066 MHz DDR3L memory up to 8GB in dual stacked SODIMM sockets (lower slot must be populated)

¾ Embedded BIOS: AMI EFI with CMOS backup in 8MB SPI BIOS

2.2. Expansion Busses

¾ 2 PCI Express x1 (AB): Lanes 0/1 ¾ 1 PCI (CD): PCI 2.3, 32-bit, 33MHz ¾ LPC bus, SMBus (system), I

C (user)

2.3. SEMA Board Controller

¾ Type: ADLINK Smart Embedded Management Agent (SEMA) ¾ Supports:

• Voltage/Current monitoring

• Power sequence debug support

• AT/ATX mode control

• Logistics and Forensic information

• Flat Panel Control

• General Purpose I2C

• Failsafe BIOS (dual BIOS )

• Watchdog Timer and Fan Control

2.4. Debug Headers

¾ 40-pin multipurpose flat cable connector used in combination with DB-40 debug module, providing BIOS POST code LED, BMC access,

SPI BIOS flashing, Power Testpoints, Debug LEDs

¾ 26-pin XDP header for ICE debug of SoC

cExpress-BT2 Page 9

2.5. Video

¾ GPU Feature Support: 7th generation graphics Intel core architecture with four execution units supporting two independent displays

• 3D graphics hardware acceleration

• Support for DirectX 11, OpenCL 1.1, OpenGL ES Halti/2.0/1.1, OpenGL 3.2

• Video decode hardware acceleration including support for H.264, MPEG2, MVC, VC-1, WMV9 and VP8 formats

• Video encode hardware acceleration including support for H.264, MPEG2 and MVC formats

• Playback of Blu-ray disc 3D content using HDMI (1.4a spec compliant with 3D)

Note: Availabililty of features may vary between operating systems.

¾ Display Interface Support

• Dual-channel 18/24-bit LVDS

Through eDP-to-LVDS bridge (use DDI0 signal of SoC)

• VGA

Analog VGA supporting resolutions of up to 2560x1600x24bpp @60Hz

2.6. Audio

¾ Integrated: Intel® HD Audio integrated in SoC ¾ Audio Codec: located on carrier Express-BASE2 (ALC886 standard support)

2.7. LAN

¾ Intel MAC/PHY: Intel® i210 (MAC/PHY) Ethernet controller ¾ Interface: 10/100/1000 GbE connection

2.8. Multi I/O and Storage

¾ Integrated in SoC ¾ USB: 7x USB 1.1/2.0 (USB 0/1/2/3/4/5/6, ports 3~6 from USB hub) ¾ SATA: one SATA 3Gb/s (SATA0)

build option two SATA 3GB/s (SATA0, SATA1) when PATA bridge is not used (lose PATA function)

¾ PATA: one PATA port (through SATA to PATA bridge) ¾ eMMC: soldered on module bootable eMMC flash storage 8GB or 16GB or 32GB (optional) ¾ GPIO: 4 GPO and 4 GPI with interrupt

2.9. TPM (Trusted Platform Module)

¾ Chipset: ATMELAT97SC3204 (optional) ¾ Type: TPM 1.2

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2.10. Power Specificatio ns

¾ Power Modes: AT and ATX mode (AT mode start controlled by SEMA) ¾ Standard Voltage Input: ATX = 12V±5% / 5Vsb ±5% or AT = 12V ±5% ¾ Wide Voltage Input: ATX = 5~20 V / 5Vsb ±5% or AT = 5 ~20V ¾ Power Management: ACPI 4.0 compliant, Smart Battery support ¾ Power States: supports C1-C6, S0, S3, S4, S5, S5 ECO mode (Wake-on-USB S3/S4, WoL S3/S4/S5) ¾ ECO mode: supports deep S5 (S5 ECO mode) for 5Vsb power saving

2.11. Power Consumption

TBD

2.12. Operating Temperatures

¾ Standard Operating Temperature: 0 to 60°C (Wide Voltage Input) ¾ Extreme Rugged™ Operating Temperature (optional)*: -40 to 85°C (Standard Voltage Input)

*Intel® Atom™ E3800 Series processors only

2.13. Environmental

¾ Humidity: 5-90% RH operating, non-condensing

5-95% RH storage (and operating with conformal coating).

¾ Shock and Vibration: IEC 60068-2-64 and IEC-60068-2-27

MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D

¾ HALT: Thermal Stress, Vibration Stress, Thermal Shock and Combined Test

2.14. Specification Compliance

¾ PICMG COM.0: Rev 2.1 Type 2, Compact size 95 x 95 mm

2.15. Operating Systems

¾ Standard Support: Windows 7/8 32/64-bit, Linux 32/64-bit ¾ Extended Support (BSP): WES7/8, WEC7, Linux, VxWorks

cExpress-BT2 Page 11

2.16. Functional Diagram

Page 12 cExpress-BT2

2.17. Mechanical Dimensions

Top V iew

Side View

All Ø tolerances ± 0.05 mm Other tolerances ± 0.2 mm

cExpress-BT2 Page 13

3. Pinouts and Signal Descriptions

3.1. AB / CD Pin Definitions

The cExpress-BT2 is a Type 2 module supporting PCI and PATA on the CD connector. All pins in the COM Express specification are described, including those not supported on the cExpress- BT2. Those not supported on the cExpress-BT2 module are crossed out

Row A Row B Row C Row D

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

A1 GND (FIXED) B1 GND (FIXED) C1 GND FIXED) D1 GND FIXED) A2 GBE0_MDI3- B2 GBE0_ACT# C2 IDE_D7 D2 IDE_D5 A3 GBE0_MDI3+ B3 LPC_FRAME# C3 IDE_D6 D3 IDE_D10 A4 GBE0_LINK100# B4 LPC_AD0 C4 IDE_D3 D4 IDE_D11 A5 GBE0_LINK1000# B5 LPC_AD1 C5 IDE_D15 D5 IDE_D12 A6 GBE0_MDI2- B6 LPC_AD2 C6 IDE_D8 D6 IDE_D4 A7 GBE0_MDI2+ B7 LPC_AD3 C7 IDE_D9 D7 IDE_D0 A8 GBE0_LINK# B8 LPC_DRQ0# C8 IDE_D2 D8 IDE_REQ A9 GBE0_MDI1- B9 LPC_DRQ1# C9 IDE_D13 D9 IDE_IOW# A10 GBE0_MDI1+ B10 LPC_CLK C10 IDE_D1 D10 IDE_ACK# A11 GND (FIXED) B11 GND (FIXED) C11 GND (FIXED) D11 GND (FIXED) A12 GBE0_MDI0- B12 PWRBTN# C12 IDE_D14 D12 IDE_IRQ A13 GBE0_MDI0+ B13 SMB_CK C13 IDE_IORDY D13 IDE_A0 A14 GBE0_CTREF B14 SMB_DAT C14 IDE_IOR# D14 IDE_A1 A15 SUS_S3# B15 SMB_ALERT# C15 PCI_PME# D15 IDE_A2 A16 SATA0_TX+ B16 SATA1_TX+ * C16 PCI_GNT2# D16 IDE_CS1# A17 SATA0_TX- B17 SATA1_TX- * C17 PCI_REQ2# D17 IDE_CS3# A18 SUS_S4# B18 SUS_STAT# C18 PCI_GNT1# D18 IDE_RESET# A19 SATA0_RX+ B19 SATA1_RX+ * C19 PCI_REQ1# D19 PCI_GNT3# A20 SATA0_RX- B20 SATA1_RX- * C20 PCI_GNT0# D20 PCI_REQ3# A21 GND (FIXED) B21 GND (FIXED) C21 GND (FIXED) D21 GND (FIXED) A22 SATA2_TX+ B22 SATA3_TX+ C22 PCI_REQ0# D22 PCI_AD1 A23 SATA2_TX- B23 SATA3_TX- C23 PCI_RESET# D23 PCI_AD3 A24 SUS_S5# B24 PWR_OK C24 PCI_AD0 D24 PCI_AD5 A25 SATA2_RX+ B25 SATA3_RX+ C25 PCI_AD2 D25 PCI_AD7 A26 SATA2_RX- B26 SATA3_RX- C26 PCI_AD4 D26 PCI_C/BE0# A27 BATLOW# B27 WDT C27 PCI_AD6 D27 PCI_AD9 A28 (S)ATA_ACT# B28 AC/HDA_SDIN2 C28 PCI_AD8 D28 PCI_AD11 A29 AC/HDA_SYNC B29 AC/HDA_SDIN1 C29 PCI_AD10 D29 PCI_AD13 A30 AC/HDA_RST# B30 AC/HDA_SDIN0 C30 PCI_AD12 D30 PCI_AD15 A31 GND (FIXED) B31 GND (FIXED) C31 GND (FIXED) D31 GND (FIXED) A32 AC/HDA_BITCLK B32 SPKR C32 PCI_AD14 D32 PCI_PAR A33 AC/HDA_SDOUT B33 I2C_CK C33 PCI_C/BE1# D33 PCI_SERR# A34 BIOS_DIS0# B34 I2C_DAT C34 PCI_PERR# D34 PCI_STOP#

Page 14 cExpress-BT2

Row A Row B Row C Row D

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

A35 THRMTRIP# B35 THRM# C35 PCI_LOCK# D35 PCI_TRDY# A36 USB6- B36 USB7- C36 PCI_DEVSEL# D36 PCI_FRAME# A37 USB6+ B37 USB7+ C37 PCI_IRDY# D37 PCI_AD16 A38 USB_6_7_OC# B38 USB_4_5_OC# C38 PCI_C/BE2# D38 PCI_AD18 A39 USB4- B39 USB5- C39 PCI_AD17 D39 PCI_AD20 A40 USB4+ B40 USB5+ C40 PCI_AD19 D40 PCI_AD22 A41 GND (FIXED) B41 GND (FIXED) C41 GND (FIXED) D41 GND (FIXED) A42 USB2- B42 USB3- C42 PCI_AD21 D42 PCI_AD24 A43 USB2+ B43 USB3+ C43 PCI_AD23 D43 PCI_AD26 A44 USB_2_3_OC# B44 USB_0_1_OC# C44 PCI_C/BE3# D44 PCI_AD28 A45 USB0- B45 USB1- C45 PCI_AD25 D45 PCI_AD30 A46 USB0+ B46 USB1+ C46 PCI_AD27 D46 PCI_IRQC# A47 VCC_RTC B47 EXCD1_PERST# C47 PCI_AD29 D47 PCI_IRQD# A48 EXCD0_PERST# B48 EXCD1_CPPE# C48 PCI_AD31 D48 PCI_CLKRUN# A49 EXCD0_CPPE# B49 SYS_RESET# C49 PCI_IRQA# D49 PCI_M66EN GND) A50 LPC_SERIRQ B50 CB_RESET# C50 PCI_IRQB# D50 PCI_CLK A51 GND (FIXED) B51 GND (FIXED) C51 GND (FIXED) D51 GND (FIXED) A52 PCIE_TX5+ B52 PCIE_RX5+ C52 PEG_RX0+ D52 PEG_TX0+ A53 PCIE_TX5- B53 PCIE_RX5- C53 PEG_RX0- D53 PEG_TX0- A54 GPI0 B54 GPO1 C54 TYPE0# D54 PEG_LANE_RV# A55 PCIE_TX4+ B55 PCIE_RX4+ C55 PEG_RX1+ D55 PEG_TX1+ A56 PCIE_TX4- B56 PCIE_RX4- C56 PEG_RX1- D56 PEG_TX1- A57 GND B57 GPO2 C57 TYPE1# D57 TYPE2# A58 PCIE_TX3+ B58 PCIE_RX3+ C58 PEG_RX2+ D58 PEG_TX2+ A59 PCIE_TX3- B59 PCIE_RX3- C59 PEG_RX2- D59 PEG_TX2- A60 GND (FIXED) B60 GND (FIXED) C60 GND (FIXED) D60 GND (FIXED) A61 PCIE_TX2+ B61 PCIE_RX2+ C61 PEG_RX3+ D61 PEG_TX3+ A62 PCIE_TX2- B62 PCIE_RX2- C62 PEG_RX3- D62 PEG_TX3- A63 GPI1 B63 GPO3 C63 RSVD D63 RSVD A64 PCIE_TX1+ B64 PCIE_RX1+ C64 RSVD D64 RSVD A65 PCIE_TX1- B65 PCIE_RX1- C65 PEG_RX4+ D65 PEG_TX4+ A66 GND B66 WAKE0# C66 PEG_RX4- D66 PEG_TX4- A67 GPI2 B67 WAKE1# C67 RSVD D67 GND A68 PCIE_TX0+ B68 PCIE_RX0+ C68 PEG_RX5+ D68 PEG_TX5+ A69 PCIE_TX0- B69 PCIE_RX0- C69 PEG_RX5- D69 PEG_TX5- A70 GND (FIXED) B70 GND (FIXED) C70 GND (FIXED) D70 GND (FIXED) A71 LVDS_A0+ B71 LVDS_B0+ C71 PEG_RX6+ D71 PEG_TX6+ A72 LVDS_A0- B72 LVDS_B0- C72 PEG_RX6- D72 PEG_TX6- A73 LVDS_A1+ B73 LVDS_B1+ C73 SDVO_DATA D73 SDVO_CLK A74 LVDS_A1- B74 LVDS_B1- C74 PEG_RX7+ D74 PEG_TX7+ A75 LVDS_A2+ B75 LVDS_B2+ C75 PEG_RX7- D75 PEG_TX7- A76 LVDS_A2- B76 LVDS_B2- C76 GND D76 GND A77 LVDS_VDD_EN B77 LVDS_B3+ C77 RSVD D77 IDE_CBLID# A78 LVDS_A3+ B78 LVDS_B3- C78 PEG_RX8+ D78 PEG_TX8+ A79 LVDS_A3- B79 LVDS_BKLT_EN C79 PEG_RX8- D79 PEG_TX8-

cExpress-BT2 Page 15

Row A Row B Row C Row D

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

A80 GND (FIXED) B80 GND (FIXED) C80 GND (FIXED) D80 GND (FIXED) A81 LVDS_A_CK+ B81 LVDS_B_CK+ C81 PEG_RX9+ D81 PEG_TX9+ A82 LVDS_A_CK- B82 LVDS_B_CK- C82 PEG_RX9- D82 PEG_TX9- A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C83 RSVD D83 RSVD A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84 GND D84 GND A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10+ D85 PEG_TX10+ A86 KBD_RST# B86 VCC_5V_SBY C86 PEG_RX10- D86 PEG_TX10- A87 KBD_A20GATE B87 VCC_5V_SBY C87 GND D87 GND A88 PCIE0_CK_REF+ B88 BIOS_DIS1# C88 PEG_RX11+ D88 PEG_TX11+ A89 PCIE0_CK_REF- B89 VGA_RED C89 PEG_RX11- D89 PEG_TX11- A90 GND (FIXED) B90 GND (FIXED) C90 GND (FIXED) D90 GND (FIXED) A91 SPI_POWER B91 VGA_GRN C91 PEG_RX12+ D91 PEG_TX12+ A92 SPI_MISO B92 VGA_BLU C92 PEG_RX12- D92 PEG_TX12- A93 GPO0 B93 VGA_HSYNC C93 GND D93 GND A94 SPI_CLK B94 VGA_VSYNC C94 PEG_RX13+ D94 PEG_TX13+ A95 SPI_MOSI B95 VGA_I2C_CK C95 PEG_RX13- D95 PEG_TX13- A96 GND B96 VGA_I2C_DAT C96 GND D96 GND A97 TYPE10# B97 SPI_CS# C97 RSVD D97 PEG_ENABLE# A98 RSVD B98 RSVD C98 PEG_RX14+ D98 PEG_TX14+ A99 RSVD B99 RSVD C99 PEG_RX14- D99 PEG_TX14- A100 GND (FIXED) B100 GND (FIXED) C100 GND (FIXED) D100 GND (FIXED) A101 RSVD B101 RSVD C101 PEG_RX15+ D101 PEG_TX15+ A102 RSVD B102 RSVD C102 PEG_RX15- D102 PEG_TX15- A103 RSVD B103 RSVD C103 GND D103 GND A104 VCC_12V B104 VCC_12V C104 VCC_12V D104 VCC_12V A105 VCC_12V B105 VCC_12V C105 VCC_12V D105 VCC_12V A106 VCC_12V B106 VCC_12V C106 VCC_12V D106 VCC_12V A107 VCC_12V B107 VCC_12V C107 VCC_12V D107 VCC_12V A108 VCC_12V B108 VCC_12V C108 VCC_12V D108 VCC_12V A109 VCC_12V B109 VCC_12V C109 VCC_12V D109 VCC_12V A110 GND (FIXED) B110 GND (FIXED) C110 GND (FIXED) D110 GND (FIXED)

Note: *Second SATA can be supported by BOM option with loss of PATA IDE

Page 16 cExpress-BT2

3.2. Signal Description Terminology

The following terms are used in the COM Express AB/CD Signal Descriptions below.

I Input to the Module O Output from the Module I/O Bi-directional input / output signal OD Open drain output I 3.3V Input 3.3V tolerant I 5V Input 5V tolerant O 3.3V Output 3.3V signal level O 5V Output 5V signal level I/O 3.3V Bi-directional signal 3.3V tolerant I/O 5V Bi-directional signal 5V tolerant I/O 3.3Vsb Input 3.3V tolerant active in standby state P Power Input/Output REF Reference voltage output that may be sourced from a module power plane. PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected.

The signal is used to indicate the PICMG module type to the Carrier Board. PU ADLINK implemented pull-up resistor on module PD ADLINK implemented pull-down resistor on module

cExpress-BT2 Page 17

3.3. AB Signal Descriptions

3.3.1. Audio Signals

Signal Pin # Description I/O PU/PD Comment

AC_RST# / HDA_RST#

AC_SYNC / HDA_SYNC

AC_BITCLK / HDA_BITCLK

AC _SDOUT / HDA_SDOUT

AC _SDIN[2:0] HDA_SDIN[2:0]

A30 Reset output to CODEC, active low. O 3.3V

A29 Sample-synchronization signal to the CODEC(s). O 3.3V

A32 Serial data clock generated by the external

CODEC(s).

A33 Serial TDM data output to the CODEC. O 3.3V

B28 B30

Serial TDM data inputs from up to 3 CODECs. AC_SDIN0: supported

I/O 3.3V

AC_SDIN1: supported AC_SDIN2: not supported

3.3.2. Analog VGA

Signal Pin # Description I/O PU/PD Comment

VGA_RED B89 Red for monitor.

Analog DAC output, designed to drive a

37.5-Ohm equivalent load.

VGA_GRN B91 Green for monitor

Analog DAC output, designed to drive a

37.5-Ohm equivalent load.

O Analog

PD 150R

shall also be terminated on the carrier with 150Ω resistor to ground close to VGA connector

VGA_BLU B92 Blue for monitor.

Analog DAC output, designed to drive a

37.5-Ohm equivalent load. VGA_HSYNC B93 Horizontal sync output to VGA monitor O 3.3V VGA_VSYNC B94 Vertical sync output to VGA monitor O 3.3V VGA_I2C_CK B95 DDC clock line (I²C port dedicated to identify

VGA monitor capabilities)

VGA_I2C_DAT B96 DDC data line. I/O OD 3.3V PU 2k2 3.3V

O Analog

I/O OD 3.3V PU 2k2 3.3V

PD 150R

shall also be terminated on the carrier with 150Ω resistor to ground close to VGA connector

3.3.3. LVDS

Signal Pin # Description I/O PU/PD Comment

LVDS_A0+ LVDS_A0- LVDS_A1+ LVDS_A1- LVDS_A2+ LVDS_A2- LVDS_A3+ LVDS_A3-

LVDS_A_CK+ LVDS_A_CK-

A71 A72 A73 A74 A75 A76 A78 A79

A81 A82

LVDS Channel A differential pairs O LVDS

LVDS Channel A differential clock O LVDS

Page 18 cExpress-BT2

Signal Pin # Description I/O PU/PD Comment

LVDS_B0+ LVDS_B0- LVDS_B1+ LVDS_B1- LVDS_B2+ LVDS_B2- LVDS_B3+ LVDS_B3-

LVDS_B_CK+ LVDS_B_CK-

LVDS_VDD_EN A77 LVDS panel power enable O 3.3V LVDS_BKLT_EN B79 LVDS panel backlight enable O 3.3V LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3.3V LVDS_I2C_CK A83 DDC lines used for flat panel detection and control. O 3.3V PU 2k2 3.3V LVDS_I2C_DAT A84 DDC lines used for flat panel detection and control. I/O 3.3V PU 2k2 3.3V

B71 B72 B73 B74 B75 B76 B77 B78

B81 B82

LVDS Channel B differential pairs O LVDS

LVDS Channel B differential clock O LVDS

PD 100K

3.3.4. Gigabit Ethernet

Gigabit Ethernet Pin # Description I/O PU/PD Comment

GBE0_MDI0+ GBE0_MDI0- GBE0_MDI1+ GBE0_MDI1- GBE0_MDI2+ GBE0_MDI2- GBE0_MDI3+ GBE0_MDI3-

GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. O 3.3VSB PU 10k

GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. O 3.3VSB GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low. O 3.3VSB GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low. O 3.3VSB GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics

A13

Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs

A11

0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes.

A10

Some pairs are unused in some modes according to the following:

1000 100 10

MDI[0]+/- B1_DA+/- TX+/- TX+/-

MDI[1]+/- B1_DB+/- RX+/- RX+/-

MDI[2]+/- B1_DC+/-

MDI[3]+/- B1_DD+/-

center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be 250 mA or less.

I/O Analog Twisted pair

3.3VSB

GND min

3.3V max

3.3.5. SATA

Signal Pin # Description I/O PU/PD Comment

signals for external transformer.

SATA0_TX+ SATA0_TX-

SATA0_RX+ SATA0_RX-

SATA1_TX+ SATA1_TX-

A16

Serial ATA channel 0, Transmit Output differential pair. O SATA AC coupled on Module

A17 A19

Serial ATA channel 0, Receive Input differential pair. I SATA AC coupled on Module

A20 B16

Serial ATA channel 1, Transmit Output differential pair. O SATA Optional supported

B17

second SATA by BOM

cExpress-BT2 Page 19

Signal Pin # Description I/O PU/PD Comment

SATA1_RX+ SATA1_RX-

B19

Serial ATA channel 1, Receive Input differential pair. I SATA

B20

loose PATA IDE AC coupled on Module

SATA2_TX+ SATA2_TX-

SATA2_RX+ SATA2_RX-

SATA3_TX+ SATA3_TX-

SATA3_RX+ SATA3_RX-

(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity indicator, active low. O 3.3V

A22

Serial ATA channel 2, Transmit Output differential pair. O SATA Not supported

A23 A25

Serial ATA channel 2, Receive Input differential pair. I SATA Not supported

A26 B22

Serial ATA channel 3, Transmit Output differential pair. O SATA Not supported

B23 B25

Serial ATA channel 3, Receive Input differential pair. I SATA Not supported

B26

3.3.6. PCI Express

Signal Pin # Description I/O PU/PD Comment

PCIE_TX0+ PCIE_TX0-

PCIE_RX0+ PCIE_RX0-

PCIE_TX1+ PCIE_TX1-

PCIE_RX1+ PCIE_RX1-

A68

PCI Express channel 0, Transmit Output

A69

differential pair.

B68

PCI Express channel 0, Receive Input

B69

differential pair.

A64

PCI Express channel 1, Transmit Output

A65

differential pair.

B64

PCI Express channel 1, Receive Input

B65

differential pair.

O PCIE AC coupled on Module

I PCIE AC coupled off Module

O PCIE AC coupled on Module

I PCIE AC coupled off Module

PCIE_TX2+ PCIE_TX2-

PCIE_RX2+ PCIE_RX2-

PCIE_TX3+ PCIE_TX3-

PCIE_RX3+ PCIE_RX3-

PCIE_TX4+ PCIE_TX4-

PCIE_RX4+ PCIE_RX4-

PCIE_TX5+ PCIE_TX5-

PCIE_RX5+ PCIE_RX5-

PCIE_CLK_REF+ PCIE_CLK_REF-

A61

PCI Express channel 2, Transmit Output

A62

differential pair.

B61

PCI Express channel 2, Receive Input

B62

differential pair.

A58

PCI Express channel 3, Transmit Output

A59

differential pair.

B58

PCI Express channel 3, Receive Input

B59

differential pair.

A55

PCI Express channel 4, Transmit Output

A56

differential pair.

B55

PCI Express channel 4, Receive Input

B56

differential pair.

A52

PCI Express channel 5, Transmit Output

A53

differential pair.

B52

PCI Express channel 5, Receive Input

B53

differential pair.

A88

PCI Express Reference Clock output for all PCI

A89

Express and PCI Express Graphics Lanes.

O PCIE Not supported

I PCIE Not supported

O PCIE Not supported

I PCIE Not supported

O PCIE

I PCIE

O PCIE

I PCIE

O PCIE

Not supported

Page 20 cExpress-BT2

3.3.7. Express Card

Signal Pin # Description I/O PU/PD Comment

EXCD0_CPPE# EXCD1_CPPE#

EXCD0_PERST# EXCD1_PERST#

A49 B48

A48 B47

PCI ExpressCard: PCI Express capable card request I 3.3V PU 10k 3.3V

PCI ExpressCard: reset O 3.3V

3.3.8. LPC bus

Signal Pin # Description I/O PU/PD Comment

LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V LPC_DRQ0#

LPC_DRQ1# LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V PU 8k2 3.3V LPC_CLK B10 LPC clock output –33MHz nominal O 3.3V Atom clock 33 MHz

B8 B9

LPC serial DMA request I 3.3V

Celeron clock 25 MHz

3.3.9. USB

Signal Pin # Description I/O PU/PD Comment

USB0+ USB0-

USB1+ USB1-

USB2+ USB2-

USB3+ USB3-

USB4+ USB4-

USB5+ USB5-

USB6+ USB6-

USB7+ USB7-

USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up

A46

USB differential data pairs for Port 0 I/O 3.3VSB USB 1.1/ 2.0 compliant

A45 B46

USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant

B45 A43

USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant

A42 B43

USB differential data pairs for Port 2 I/O 3.3VSB USB 1.1/ 2.0 compliant

B42 A40

USB differential data pairs for Port 3 I/O 3.3VSB

A39 B40

USB differential data pairs for Port 4 I/O 3.3VSB USB 1.1/ 2.0 compliant

B39 A37

USB differential data pairs for Port 5 I/O 3.3VSB USB 1.1/ 2.0 compliant

A36 B37

USB differential data pairs for Port 6 I/O 3.3VSB Not supported

B37

I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

USB 1.1/ 2.0 compliant

USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up

for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. .

I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier

cExpress-BT2 Page 21

Signal Pin # Description I/O PU/PD Comment

USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up

for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up

for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

3.3.10. USB Root Segmentation

EHCI Controller

P1 P2 P3 P4

USB Hub

P1-P4

I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier

XHCI Controller

HSIC 0

HSIC 1

SSP1P5

Port 0

(1.1/2.0)

USB0+/A46

USB0- / A4 5

Port 1

(1.1/2.0)

USB1+/B46

USB1- / B45

Port 2

(1.1/2.0)

USB2+ / A43

USB2- / A42

Port 3

(1.1/2.0)

USB3+ / B43

USB3- / B42

Port 4

(1.1/2.0)

USB4+ / A40

Port 5

(1.1/2.0)

USB5+ / B40

USB4- / A39

USB5- / B39

Port 6

(1.1/2.0)

USB6+ / A37

USB7+/B37

USB6- / A3 6

USB7- / B36

Row A/ B

3.3.11. SPI (BIOS only)

Signal Pin # Description I/O PU/PD Comment

SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB Only support CS0 SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module

– nominally 3.3V. The Module shall provide a minimum of 100mA on SPI_POWER. Carriers shall use less than 100mA of SPI_POWER. SPI_POWER shall only be used to power SPI devices on the Carrier

O P 3.3VSB

BIOS_DIS0# A34 Selection strap to determine the BIOS boot device. I PU 10K 3.3V Carrier shall pull to GND

or leave not- connected.

BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. I PU 10K 3.3V Carrier shall pull to GND

or leave not- connected

Page 22 cExpress-BT2

3.3.12. Miscellaneous

Signal Pin # Description I/O PU/PD Comment

SPKR B32 Output for audio enunciator, the “speaker” in PC-AT

systems

WDT B27 Output indicating that a watchdog time-out event has

occurred.

THRM# B35 Input from off-module temp sensor indicating an over-temp

situation.

THRMTRIP# A35 Active low output indicating that the CPU has entered

thermal shutdown.

FAN_PWMOUT B101 Fan speed control. Uses the Pulse Width Modulation

(PWM) technique to control the fan’s RPM.

FAN_TACHIN B102 Fan tachometer input for a fan with a two pulse output. I OD 3.3V PU 10k 3.3V

O 3.3V

I 3.3V

O 3.3V PU 10k 3.3V

O OD 3.3V

3.3.13. SMBus

Signal Pin # Description I/O PU/PD Comment

SMB_CK B13 System Management Bus bidirectional clock line. Power

sourced through 5V standby rail and main power rails.

SMB_DAT# B14 System Management Bus bidirectional data line. Power

sourced through 5V standby rail and main power rails.

I/O OD 3.3VSB PU 2k2 3.3VSB

SMB_ALERT# B15 System Management Bus Alert – active low input can

be used to generate an SMI# (System Management Interrupt) or to wake the system. Power sourced through 5V standby rail and main power rails.

I 3.3VSB PU 10k 3.3VSB

3.3.14. I2C Bus

Signal Pin # Description I/O PU/PD Comment

I2C_CK B33 General purpose I²C port clock output/input I/O OD 3.3VSB PU 2k2 3.3VSB I2C_DAT B34 General purpose I²C port data I/O line I/O OD 3.3VSB PU 2k2 3.3VSB

3.3.15. General Purpose I/O (GPIO)

Signal Pin # Description I/O PU/PD Comment

GPO[0] A93 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET

output low

GPO[1] B54 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET

output low

GPO[2] B57 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET

output low

GPO[3] B63 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET

output low

GPI[0] A54 General purpose input pins. I 3.3V PU 10K 3.3V

cExpress-BT2 Page 23

Signal Pin # Description I/O PU/PD Comment

Pulled high internally on the module.

GPI[1] A63 General purpose input pins.

Pulled high internally on the module.

GPI[2] A67 General purpose input pins.

Pulled high internally on the module.

GPI[3] A85 General purpose input pins.

Pulled high internally on the module.

I 3.3V PU 10K 3.3V

3.3.16. Serial Interface Signals

Signal Pin # Description I/O PU/PD Comment

SER0_TX A98 General purpose serial port transmitter (TTL level output) O CMOS Power rail tolerance 5V / 12V SER0_RX A99 General purpose serial port receiver (TTL level input) I CMOS Power rail tolerance 5V / 12V SER1_TX A101 General purpose serial port transmitter (TTL level output) O CMOS Power rail tolerance 5V / 12V SER1_RX A102 General purpose serial port receiver (TTL level input) I CMOS Power rail tolerance 5V / 12V

3.3.17. Power And System Management

Signal Pin # Description I/O PU/PD Comment

PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge. I 3.3VSB PU 10k

3.3VSB

SYS_RESET# B49 Reset button input. Active low request for module to reset and reboot. May

be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used.

CB_RESET# B50 Reset output from module to Carrier Board. Active low. Issued by module

chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.

PWR_OK B24 Power OK from main power supply. A high value indicates that the power is

good. This signal can be used to hold off Module startup to allow carrier

based FPGAs or other configurable devices time to be programmed. SUS_STAT# B18 Indicates imminent suspend operation; used to notify LPC devices. O 3.3VSB SUS_S3# A15 Indicates system is in Suspend to RAM state. Active-low output. An inverted

copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be

used to enable the non-standby power on a typical ATX power supply. SUS_S4# A18 Indicates system is in Suspend to Disk state. Active low output. O 3.3VSB SUS_S5# A24 Indicates system is in Soft Off state. O 3.3VSB

WAKE0# B66 PCI Express wake up signal. I 3.3VSB PU 10k

WAKE1# B67 General purpose wake up signal. May be used to implement wake-up on

PS/2 keyboard or mouse activity. BATLOW# A27 Battery low input. This signal may be driven low by external circuitry to

signal that the system battery is low, or may be used to signal some other

external power-management event.

I 3.3VSB PU 10k

3.3VSB

O 3.3VSB

I 3.3V PU 100k

3.3VSB

O 3.3VSB

3.3VSB

I 3.3VSB PU 10k

3.3VSB

I 3.3VSB PU 10k

3.3VSB

Not supported, connect to SUS_S4#

Not supported, connected to WAKE1#

Page 24 cExpress-BT2

Signal Pin # Description I/O PU/PD Comment

LID# LID button. Low active signal used by the ACPI operating system for a LID

switch. SLEEP# Sleep button. Low active signal used by the ACPI operating system to bring

the system to sleep state or to wake it up again.

I OD

3.3VSB I OD

3.3VSB

PU 10k

3.3VSB PU 10K

3.3VSB

Emulated on GPIO (BIOS)

3.3.18. Power and Ground

Signal Pin # Description I/O PU/PD Comment

VCC_12V A104-A109

B104-B109

VCC_5V_SBY B84-B87 Standby power input: +5.0V nominal. See section 7 “Electrical

VCC_RTC A47 Real-time clock circuit-power input. Nominally +3.0V. P GND A1, A11, A21, A31, A41, A51,

A57, A66, A80, A90, A96, A100, A110, B1, B11, B21,B31, B41, B51, B60, B70, B80, B90, B100, B110

Primary power input: +12V nominal (wide range 5 ~ 20V). All available VCC_12V pins on the connector(s) shall be used.

Specifications“ for allowable input range. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.

Ground - DC power and signal and AC signal return path. P

P 5~20 V

P 5Vsb ±5%

cExpress-BT2 Page 25

3.4. CD Signal Descriptions

3.4.1. PATA IDE

Signal Pin # Description I/O PU/PD Comment

IDE_D0 IDE_D1 IDE_D2 IDE_D3 IDE_D4 IDE_D5 IDE_D6 IDE_D7 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15

IDE_A0 D13 Address lines to IDE device. O 3.3V IDE_A1 D14 Address lines to IDE device. O 3.3V IDE_A2 D15 Address lines to IDE device. O 3.3V IDE_IOW# D9 I/O write line to IDE device. Data latched on trailing (rising) edge. O 3.3V IDE_IOR# C14 I/O read line to IDE device. O 3.3V IDE_REQ D8 IDE Device DMA Request. It is asserted by the IDE device to

IDE_ACK# D10 IDE Device DMA Acknowledge. O 3.3V IDE_CS1# D16 IDE Device Chip Select for 1F0h to 1FFh range. O 3.3V IDE_CS3# D17 IDE Device Chip Select for 3F0h to 3FFh range. O 3.3V IDE_IORDY C13 IDE device I/O ready input. Pulled low by the IDE device to extend

IDE_RESET# D18 Reset output to IDE device, active low. O 3.3V IDE_IRQ D12 Interrupt request from IDE device. I 3.3V PD 10k

IDE_CBLID# D77 Input from off-module hardware indicating the type of IDE cable

D7 C10 C8 C4 D6 D2 C3 C2 C6 C7 D3 D4 D5 C9 C12 C5

Bidirectional data to / from IDE device. I/O 3.3V

I 3.3V

request a data transfer.

I 3.3V PU 4k7 3.3V

the cycle.

shall

I 3.3V being used. High indicates a 40-pin cable used for legacy IDE modes. Low indicates that an 80-pin cable with interleaved grounds is used. Such a cable is required for Ultra-DMA 66, 100 and 133 modes.

3.4.2. PCI

Signal Pin # Description I/O PU/PD Comment

PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12

Page 26 cExpress-BT2

C24 D22 C25 D23 C26 D24 C27 D25 C28 D27 C29 D28 C30

PCI bus multiplexed address and data lines I/O

3.3V

Signal Pin # Description I/O PU/PD Comment

PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

D29 C32 D30 D37 C39 D38 C40 D39 C42 D40 C43 D42 C45 D43 C46 D44 C47 D45 C48

PCI_C/BE0# PCI_C/BE1# PCI_C/BE2# PCI_C/BE3#

PCI_DEVSEL# C36 PCI bus Device Select, active low. I/O

PCI_FRAME# D36 PCI bus Frame control line, active low. I/O

PCI_IRDY# C37 PCI bus Initiator Ready control line, active

PCI_TRDY# D35 PCI bus Target Ready control line, active

PCI_STOP# D34 PCI bus STOP control line, active low, driven

PCI_PAR D32 PCI bus parity I/O

PCI_PERR# C34 Parity Error:

PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3#

D26 C33 C38 C44

C22 C19 C17 D20

PCI bus byte enable lines, active low I/O

3.3V

3.3V I/O

low.

by cycle initiator.

An external PCI device drives PERR# when it receives data that has a parity error.

PCI bus master request input lines, active low.

3.3V I/O

3.3V

3.3V I/O

3.3V

I 3.3V PU 8k2

PU 8k2

3.3V PU 8k2

3.3V

PU 8k2

3.3V

PCI_GNT0# PCI_GNT1# PCI_GNT2# PCI_GNT3#

PCI_RESET# C23 PCI Reset output, active low. O 3.3V PCI_LOCK# C35 PCI Lock control line, active low. I/O

PCI_SERR# D33 System Error: SERR# may be pulsed active

PCI_PME# C15 PCI Power Management Event: PCI

C20 C18 C16 D19

PCI bus master grant output lines, active low. O 3.3V PCI_GNT[0..3]# are boot strap signals (see note

below)

by any PCI device that detects a system error condition.

peripherals drive PME# to wake system from low-power states S1–S5.

3.3V I/O

3.3V

3.3VSB

PU 8k2

3.3V PU 8k2

3.3V

cExpress-BT2 Page 27

Signal Pin # Description I/O PU/PD Comment

PCI_CLKRUN# D48 Bidirectional pin used to support PCI clock

run protocol for mobile systems.

PCI_IRQA# PCI_IRQB# PCI_IRQC# PCI_IRQD#

PCI_CLK D50 PCI 33MHz clock output O 3.3V

C49 C50 D46 D47

PCI interrupt request lines I 3.3V PU 8k2

I/O

3.3V

PU 10k

3.3V

3.4.3. Module Type Definition

Signal Pin # Description I/O Comment

TYPE0# TYPE1# TYPE2#

C54 C57 D57

The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are noconnects (NC). For Pinout Type 1, these pins are don’t care (X).

TYPE2# TYPE1# TYPE0# X X X Pinout Type 1

NC NC NC Pinout Type 2 NC NC GND Pinout Type 3 (no IDE) NC GND NC Pinout Type 4 (no PCI) NC GND GND Pinout Type 5 (no IDE, no PCI) GND NC NC Pinout Type 6 (no IDE, no PCI)

The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The Carrier Board logic may also implement a fault indicator such as an LED.

Type 2

3.4.4. Power and Ground

Signal Pin # Description I/O PU/PD Comment

VCC_12V C104-C109

D104-D109

GND C1, C11, C21, C31, C41,

C51, C60, C70, C76, C80, C84, C87, C90, C93, C96, C100, C103, C110, D1, D11, D21, D31, D41, D51, D60, D67, D70, D76, D80, D84, D87, D90, D93, D96, D100, D103, D110

Primary power input: +12V nominal (wide range 5 ~ 20V). All available VCC_12V pins on the connector(s) shall be used

Ground - DC power and signal and AC signal return path. All available GND connector pins shall be used and tied to carrier

board GND plane.

P 5 ~ 20V

Page 28 cExpress-BT2

4. Module interfaces

This chapter describes connectors and pinouts, LEDs and switches that are used on the module but are not included in the PICMG standard specification

4.1. Connector, Switch and LED Locations

4.1.1. cExpress-BT2 and the DB40 Module connected

cExpress-BT2 Page 29

4.2. 40-pin Multipurpose Connector

¾ FPC Connector type: FCI 59GF Flex 10042867 ¾ Pin orientation

1 40

¾ Pin Description on the module

Pin Interface Signal Remark Pin Interface Signal Remark

1 VCC_SPI_IN SPI Power Input from flash tool to

SPI Program interface

2 GND 22 RXD6

module. HW need add MOS FET to switch SPI power for SPI ROM

21 TXD6

BMC Program interface (continued)

3 SPI_BIOS_CS0# 23 FUMD0 4 SPI_BIOS_CS1# 24 RESET_IN# 5 SPI_BIOS_MISO 25 DATA 6 SPI_BIOS_MOSI 26 CLK 7

8 3V3_LPC System power 3.3V provide from

LPC Bus

9 GND 29 PWRBTN# 10 BIOS_DIS0 30 SYS_RESET# 11 RST# 31 CB_RESET# 12 CLK33_LPC 32 CB_PWROK 13 LPC_FRAME# 33 SUS_S3# 14 LPC_AD3 34 SUS_S4# 15 LPC_AD2 35 16 LPC_AD1 always power 3.3V provide from

SPI_BIOS_CLK 27 OCD0A Include a jumper to connect

OCD0A via 1K0 pull-up to

3.3V_BMC

COM module

Test points

36 POSTWDT_DIS# Connect to Jumper for

BMC Debug signals

OCD0B Include a jumper to connect

OCD0A via 1K0 pull-up to

3.3V_BMC

SUS_S5#

Debug

BMC

Program interface

19 3.3V_BMC always power 3.3V provide from

LPC_AD0 37 SEL_BIOS Connect to Jumper for

Debug

3.3V_BMC always power 3.3V provide from COM module

COM module

GND 40 Reserved

38 BIOS_MODE Connect to Jumper for

Debug

BMC_STATUS

Note: the pin description on the debug module is the inverse of that on the COM Express module.

Page 30 cExpress-BT2

4.3. Status LEDs

To facilitate easier maintenance, status LED’s are mounted on the board.

LED1 LED2 LED3

¾ LED Descriptions

Name Color Connection Function

LED1 Blue BMC output Power Sequence Status Code (BMC)

Power Changes, RESET (see 5.1.4 Exception Codes below)

LED2 Green Power Source 3Vcc S0 LED ON

S3/S4/S5 LED OFF ECO mode LED OFF

LED3 Red BMC output

and same signal as WDT (B27) on BtB connector

Module power up LED OFF Watchdog counting LED OFF Watchdog timed out LED ON Watchdog RESET LED ON Rebooted after WD RESET LED ON Rebooted after PWRBTN LED ON Rebooted after RESET BTN LED OFF

Note: only a RESET not initiated by the BMC can clear the WD LED (user action)

cExpress-BT2 Page 31

4.4. XDP Debug Header

The debug port is a connection into a target-system environment that provides access to JTAG, run control, system control, and observation resources. The XDP target system connector is a Molex 26-pin 52435-2671 connector. Specific plating types, locking clips, and alignment pin details of this connector can be obtained from Molex. No specific plating types, locking clipsor alignment pins are required for the XDP tool.

Pin XDP Signal Target Signal I/O Device Pin XDP Signal Target Signal I/O Device

1 OBSFN_A0 TAP_PREQ# I/O SoC 2 OBSFN_A1 TAP_PRDY# I/O SoC 3 GND GND NA 4 OBSDATA_A[0] DBG[0] I/O SoC 5 OBSDATA_A[1] DBG[1] I/O SoC 6 GND GND NA 7 OBSDATA_A[2] DBG[2] I/O SoC 8 OBSDATA_A[3] DBG[3] I/O SoC 9 GND GND NA 10 HOOK0 PMC_RSMRST# I SoC 11 HOOK1 PMIC_PWRBTN# O System 12 HOOK2 PMC_CORE_PW ROK I SoC 13 HOOK3 ILB_RTC_TEST# O SoC 14 HOOK4 Open NA 15 HOOK5 Open NA 16 VCCOBS_AB 1.8VS (SUS) I System 17 HOOK6 PMC_PLTRST# I SoC 18 HOOK7 PMC_RSTBTN# O SoC 19 GND GND NA 20 TDO TAP_TDO I SoC 21 TRSTn TAP_TRST# O SoC 22 TDI TAP_TDI O SoC 23 TMS TAP_TMS O SoC 24 TCK1 Open NA 25 GND GND NA 26 TCK0 TAP_TCK O SoC

Refer to the "Bay Trail M/D/I Platform” Debug Port Design Guide (DPDG), Document Number: 512816, Revision: 2.1

4.5. Fan Connector

¾ Connector Type: JVE 24W1125A-04M00 ¾ Pin orientation

1 2 3 4

¾ Pin Assignment

Pin Signal

1 FAN_PWMOUT 2 FAN_TACHIN 3 Ground 4 5V

Page 32 cExpress-BT2

4.6. BIOS Setup Defaults RESET Button

To perform a hardware reset of BIOS default settings, perform the following steps:

1. Shut down the system.

2. Press the BIOS Setup Defaults RESET Button continuously and boot up the system. You can release the button when the BIOS prompt screen appears

3. The BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system.

cExpress-BT2 Page 33

5. Smart Embedded Management Agent (SEMA)

The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality. The microcontroller communicates via the System Management Bus with the CPU/chipset. The following functions are implemented

¾ Total operating hours counter counts the number of hours the module has been run in minutes. ¾ On-time minutes counter counts the seconds since last system start. ¾ Temperature monitoring of CPU and board temperature minimum and maximum temperature values of CPU and board are stored in

flash.

¾ Power cycles counter ¾ Boot counter counts the number of boot attempts. ¾ Watchdog Timer (Type-II) Set / Reset / Disable Watchdog Timer. Features auto-reload at power-up. ¾ System Restart Cause Power loss / BIOS Fail / Watchdog / Internal Reset / External Reset ¾ Fail-safe BIOS support In case of a boot failure, hardware signals tells external logic to boot from fail-safe BIOS. ¾ Flash area 1kB Flash area for customer data ¾ 128 Bytes Protected Flash area Keys, IDs, etc. can be stored in a write- and clear-protectable region. ¾ Board Identify Vendor / Board / Serial number / Production Date ¾ Main-current & voltage monitors drawn current and main voltages

For a detailed description of SEMA features and functionality, please refer to the SEMA Technical Manual and SEMA Software Manual, downloadable at:

Note: Due to limitations of the Intel “Bay Trail” platform, SEMA can only obtain CPU temperature readings when the OS is running.

http://www.adlinktech.com/sema

Page 34 cExpress-BT2

5.1. Board Specific SEMA Functions

5.1.1. Voltages

The BMC of the cExpress-BT2 implements a voltage monitor and samples several onboard voltages. The voltages can be read by calling the SEMA function “Get Voltages”. The function returns a 16-bit value divided into high-byte (MSB) and low-byte (LSB).

ADC Channel Voltage Name Voltage Formul a [V]

0 CPU-Vcore (MSB<<8 + LSB) x 3.3 / 1024 1 GFX-Vcore (MSB<<8 + LSB) x 3.3 / 1024 2 +V1.05S (MSB<<8 + LSB) x 3.3 / 1024 3 Vmem (MSB<<8 + LSB) x 3.3 / 1024 4 +V1.0V (MSB<<8 + LSB) x 3.3 / 1024 5 +V3.3V (MSB<<8 + LSB) x 1.1 x 3.3 / 1024 6 +VIN (MSB<<8 + LSB) x 6.000 x 3.3 / 1024 7 (MAIN CURRENT) Use Main Current Function

5.1.2. Main Current

The BMC of the cExpress-BT2 implements a current monitor. The current can be read by calling the SEMA function “Get Main Current”. The function returns four 16-bit values divided in high-byte (MSB) and low-byte (LSB). These 4 values represent the last 4 currents drawn by the board. The values are sampled every 250ms. The order of the 4 values is NOT in chronological order. Access by the BMC may increase the drawn current of the whole system. In this case, there are still 3 samples not influenced by the read access.

Main Current = (MSB_n<<8 + LSB_n) x 8.06mA

5.1.3. BMC Status

This register shows the status of BMC controlled signals on the cExpress-BT2.

Status Bit Signal

0 WDT_OUT 1 LVDS_VDDEN 2 LVDS_BKLTEN 3 BIOS_MODE 4 POSTWDT_DISn 5 SEL_BIOS 6 BIOS_DIS0n 7 BIOS_DIS1n

cExpress-BT2 Page 35

5.1.4. Exception Codes

In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore, a “Clear Exception Code” command is not needed or supported.

Exception Code Error Message

0 NOERROR 2 NO_SUSCLK 3 NO_SLP_S5 4 NO_SLP_S4 5 NO_SLP_S3 6 BIOS_FAIL 7 RESET_FAIL 8 POWER_FAIL 9 LOW_VIN 10 VCORE 11 VGFX 12 V1P05S 13 VMEM 14 V1P0A 15 V3P3A 16 +P12V_5V 18 CRITICAL_TEMP 19 NO_CB_PWROK 20 NO_HW_PWORK 21 NO_V1P24A_PG

5.1.5. BMC Flags

The BMC Flags register returns the last detected Exception Code since power-up and shows the BIOS in use and the power mode.

Bit Description

[ 0 ~ 4 ] Exception Code [ 6 ] 0 = AT mode

1 = ATX mode

[ 7 ] 0 = Standard BIOS

1 = Fail-safe BIOS.

Page 36 cExpress-BT2

6. System Resources

6.1. System Memory Map

Address Range (decimal) Address Range (hex) Size Description

Start 128KB below 1MB 000E0000h-000FFFFFh Low BIOS Starts 20MB below 4GB FEC00000h-FEC0040h IO APIC Start 19MB below 4GB FED00000h-FED003FFh HPET Start 64 KB below 4GB FFFF0000h-FFFFFFFFh High BIOS 0K –1MB 1MB DOS DRAM

6.2. I/O Map

Hex Range Device

20h-21h, 24h-25h, 28h-29h, 2Ch-2Dh, 30h-31h, 34h-5h, 38h-39h, 3Ch-3Dh

40h-43h, 50h-53h 8254s 60h, 64h PS2 Control 61h, 63h, 65h, 67h NMI Controller 70h-77h RTC 80h-83h Port 80h 92h Init Register A0h-A1h, A4h-A5h, A8h-A9h, ACh-ADh,

B0h-B1h,B4h-B5h, B8h-B9h, BCh-BDh, 4D0h-4D1h

2E8h-2FFh COM2 3F8h-3FFh COM1 B2h-B3h Active Power Management E000 SMBus base address for SB. 500 GPIO Base Address for SB

8259 Master

8259 Slave

400 PM (ACPI) Base Address for SB

cExpress-BT2 Page 37

6.3. Interrupt Request (IRQ) Lines

6.3.1. PIC Mode

IRQ# Typical Intterupt Resource Connected to Pin Available

0 Counter 0 N/A No

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Note (1): These IRQs can be used for PCI devices when onboard device is disabled.

Keyboard controller IRQ1 via SERIRQ / PIRQ No Cascade interrupt from slave PIC N/A No Serial Port 2 (COM2) IRQ3 via SERIRQ / PIRQ Note (1) Serial Port 1 (COM1) IRQ4 via SERIRQ / PIRQ Note (1) Parallel Port (LPT) IRQ5 via SERIRQ / PIRQ Note (1) Generic IRQ6 via SERIRQ / PIRQ Note (1) Generic IRQ7 via SERIRQ / PIRQ Note (1) Real-time clock N/A No Generic IRQ9 via SERIRQ / PIRQ Note (1) Generic IRQ10 via SERIRQ / PIRQ Note (1) Generic IRQ11 via SERIRQ / PIRQ Note (1) PS/2 Mouse IRQ12 via SERIRQ / PIRQ Note (1) Math Processor N/A No Primary IDE controller IRQ14 via SERIRQ / PIRQ Note (1) Secondary IDE controller IRQ15 via SERIRQ / PIRQ Note (1)

Page 38 cExpress-BT2

6.3.2. APIC Mode

IRQ# Typical Intterupt Resource Connected to Pin Available

1 Standard PS/2 Keyboard N/A No 2 N/A N/A 3 Communication Port(COM2) IRQ3 via SERIRQ / PIRQ Note (1) 4 Communication Port(COM1) IRQ4 via SERIRQ / PIRQ Note (1) 6 N/A N/A Note (1) 7 N/A N/A Note (1) 8 High precision event timer N/A No 9 N/A N/A Note (1) 10 N/A N/A Note (1)

System timer N/A No

11 N/A N/A Note (1) 12 PS/2 Mouse IRQ12 via SERIRQ / PIRQ Note (1) 13 N/A N/A Note (1) 14 N/A N/A Note (1) 15 N/A N/A Note (1) 16 N/A PCIE Port 1/2/3/4, eMMC, IGD, PCI Slot 1/2/3/4 Note (1) 17 N/A PCIE Port 1/2/3/4, SDIO Device, PCI Slot 1/2/3/4 Note (1) 18 N/A PCIE Port 1/2/3/4, SD Device, PCI Slot 1/2/3/4 Note (1) 19 N/A PCIE Port 1/2/3/4, AHCI controller, PCI Slot 1/2/3/4 Note (1)

20 N/A Gbe controller, xHCI controller Note (1)

21 22 23

N/A Low Power Audio Engine,TXE Note (1) N/A Intel HDA Note (1) N/A N/A Note (1)

Note (1): These IRQs can be used for PCI devices when onboard device is disabled.

cExpress-BT2 Page 39

6.4. PCI Configuration Space Map

Bus Number Device Number Function Number Routing Description

00h 00h 00h N/A Soc Transaction Router 00h 02h 00h Internal Graphics & Display 00h 10h 00h Internal Storage Control Cluster(MMC Port) 00h 11h 00h Internal Storage Control Cluster(SDIO Port) 00h 12h 00h Internal Storage Control Cluster(SD Port) 00h 13h 00h Internal SATA 00h 14h 00h Internal xHCI USB 00h 18h 00h Internal Serial IO(SIO:DMA) 00h 18h 01h Internal Serial IO(SIO:I2C Port 1) 00h 18h 02h Internal Serial IO(SIO:I2C Port 2) 00h 1Ah 00h Internal Trusted Execution Engine 00h 1Bh 00h Internal HD Audio 00h 1Ch 00h Internal PCI Express Root port 1 00h 1Ch 01h Internal PCI Express Root port 2 00h 1Ch 02h Internal PCI Express Root port 3 00h 1Ch 03h Internal PCI Express Root port 4 00h 1Dh 00h Internal EHCI USB 00h 1Fh 00h N/A Platform Controller Unit(LPC) 00h 1Fh 03h Internal SMBus Controller 03h 00h 00h Internal Texas Instruments PCI-to-PCI Bridge 05h 00h 00h Internal Intel Corporation Ethernet Controller

Page 40 cExpress-BT2

6.5. PCI Interrupt Routing Map

INT Line Intel I.G.D PCIE Root

Port#1

Int0 INTA:16 INTA:16 INTA:16 Int1 INTB:17 INTB:17 Int2 INTC:18 Int3 INTD:19

PCIE Root Port#2

PCIE Root Port#3

PCIE Root Port#4

SD Host # 0 eMMC

SD Host# 1 SDIO

INT Line SD Host#2

SD Card

Int0 Int1 Int2 INTC:18 Int3

SATA Controller

INTE:20 INTF:21 INTF:21 INTG:22

INTC:18 INTD:19

Texas Instruments PCIe to PCI Bridge

xHCI Host Low Power

AUDIO Engine

TXE HDA

INT Line

EHCI Controller

SMBus Controller

GBE Controller

LPSS2 DMA LPSS2 I2C#1 LPSS2 I2C#2

Int0 Int1 Int2 Int3

INTH:23 INTE:20 INTB:17 INTC:18 INTD:19 INTC:18

6.6. PCI Interrupt Routing Map

Device Address

DIMM A A0h DIMM B A4h BMC 50h Extend GPIO 40h

cExpress-BT2 Page 41

7. BIOS Setup

7.1. Menu Structure

This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.

Main Advanced Boot Security Save & Exit

- System Information

- Processor Information

- VGA Firmware Version

- Memory Information

- SOC Information

- System ► Management

- System Date

- System Time

Notes:

► indicates a submenu

Gray text indicates info only

- CPU ►

- Memory ►

- Graphics ►

- SATA ►

- USB ►

- Network ►

- PCI and PCIe ►

- Super IO ►

- ACPI and ► Power Management

- Sound ►

- Serial Port ► Console

- Thermal ►

- Miscellaneous ►

- Boot Configuration ►

CSM Parameters ►

- Password Description

- Secure Boot Menu ►

- Reset Options

- Save Options

Page 42 cExpress-BT2

7.2. Main

The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below for details of the submenus and settings.

7.2.1. System Information

Feature Options Description

BIOS Version Info only ADLINK BIOS version Build Date and Time Info only Date the BIOS was built

7.2.2. Processor Inform atio n

Feature Options Description

CPU Brand String Info only Display CPU brand name Max CPU Speed Info only Display CPU frequency

CPU Signature Info only Display CPU ID Number of Processors Info only Display number of processor

7.2.3. VGA Firmware Version

Feature Options Description

IGFX VBIOS Version IGFX GOP Version

Info only Display legacy VBIOS or GOP driver version

7.2.4. Memory Informa tion

Feature Options Description

Total Memory Info only Display total memory information

7.2.5. SOC Information

Feature Options Description

BayTrail Soc Info only Display SOC stepping TXE FW Version Info only Display version of TXE

cExpress-BT2 Page 43

7.2.6. System Management

7.2.6.1. System Management > Board Information

Board Information Info only

SMC Firmware Read only Display SMC firmware Build Date Read only Display SMC firmware build date SMC Boot loader Read only Display SMC boot loader Build Date Read only Display SMC boot loader build date Hardware Version Read only Display SMC hardware version PCBA Revision Read only Display PCBA revision Serial Number Read only Display SMC serial number Manufacturing Date Read only Display SMC manufacturing date Last Repair Date Read only Display SMC last repair date MAC ID Read only Display SMC MAC ID SEMA Features: Read only Display SEMA features

7.2.6.2. System Management > Temperatures and Fan Speed

Feature Options Description

Temperatures and Fan Info only Board Temperatures Info only Current Read only Display current board temperature Startup Read only Display board startup temperature Min Read only Display board min. temperature Max Read only Display board max. temperature CPU Fan Speed Read only Display CPU fan speed System Fan Speed Read only Display system fan speed

7.2.6.3. System Management > Power Consumption

Feature Options Description

Power Consumption Info only Current Input Current Read only Display input current Current Input Power Read only Display input power GPU-Vcore Read only Display actual GPU-Vcore voltage GFX-Vcore Read only Display actual GFX-Vcore voltage V1.05 Read only Display actual V1.05 voltage

Page 44 cExpress-BT2

Feature Options Description

V1.35 Read only Display actual V1.35 voltage V1.00 Read only Display actual V1.00 voltage V3.30 Read only Display actual V3.30 voltage

VIN Read only Display actual VIN voltage AIN7 Read only Display actual AIN7 voltage

7.2.6.4. System Management > Runtime Statistics

Feature Options Description

Runtime Statistics Info only Total Runtime Read only The returned value specifies the total time in minutes the system

is running in S0 state.

Current Runtime Read only The returned value specifies the time in seconds the system is

running in S0 state. This counter is cleared when the system is removed from the

external power supply.

Power Cycles Read only The returned value specifies the number of times the external

power supply has been shut down

Boot Cycles Read only The Bootcounter is increased after a HW- or SW-Reset or after a

successful power-up.

Boot Reason Read only The boot reason is the event which causes the reboot of the

system.

7.2.6.5. System Management > Flags

Feature Options Description

Flags Info only BMC Flags Read only BIOS Select Read only Display the selection of current BIOS ROM ATX/AT-Mode Read only Display ATX/AT-Mode Exception Code Read only System exception reason

cExpress-BT2 Page 45

7.2.6.6. System Management > Power Up

Feature Options Description

Power Up Info only Power Up watchdog

Attention: F12 disables the Power Up Watchdog.

ECO Mode Disabled

Power-up Mode Attention: The Power-Up Mode only has effect,

if the module is in ATX-Mode.

Enabled Disabled

Enable

Turn on

Remain off Last State

The Power-Up Watchdog resets the system after a certain amount of time after power-up.

Reduces the power consumption of the system

Turn On: The machine starts automatically when the power supply is turned on. Remain Off: To start the machine the power button has to be pressed. Last State: When powered on during a power failure the system will automatically power on when power is restored.

7.2.6.7. System Management > LVDS Backlight

Feature Options Description

LVDS Backlight Info only

LVDS Backlight Bright 255 The value range starts at 0 and ends at 255.

7.2.6.8. System Management > Smart Fan

Feature Options Description

Smart Fan Info only

CPU Smart FanTemperature Source CPU Sensor

System Sensor

CPU Fan Mode AUTO (Smart Fan)

Fan Off Fan On

CPU Trigger Point 1 Read only Trigger Temperature 15 Specifies the temperature threshold at which the BMC turns on

PWM Level 30 Select PWM level CPU Trigger Point 2 Read only Trigger Temperature 60 Specifies the temperature threshold at which the BMC turns on

PWM Level 40 Select PWM level CPU Trigger Point 3 Read only Trigger Temperature 70 Specifies the temperature threshold at which the BMC turns on

PWM Level 63 Select PWM level CPU Trigger Point 4 Read only

Select CPU smart fan source

Select CPU fan mode

the CPU fan with the specified PWM level

CPU fan the specified PWM level

Trigger Temperature 80 Specifies the temperature threshold at which the BMC turns on

CPU fan the specified PWM level

PWM Level 100 Select PWM level

Page 46 cExpress-BT2

7.2.7. System Date and Time

Feature Options Description

System Date Day of Week, MM/DD/YYYY Requires the alpha-numeric entry of the day of the week, day of the

month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)

System Time HH/MM/SS Presented as a 24-hour clock setting in hours, minutes, and seconds

7.3. Advanced

This menu contains the settings for most of the user interfaces in the system.

7.3.1. CPU

Feature Options Description

CPU Infor only CPU Brand Name Info only Display CPU brand name CPU Signature Info only Display CPU signature Processor Family Info only Display processor family Microcode Patch Info only Display microcode patch Max CPU speed Info only Display max. CPU speed Min CPU speed Info only Display min. CPU speed Processor Cores Info only Display number of processor cores Intel HT Technology Info only Display Intel HT Technology support Intel VT-x Technology Info only Display Intel VT-x Technology support 64-bit Info only Display 64-bit support L1 Data Cache Info only Display cache info L1 Code Cache Info only Display cache info L2 Cache Info only Display cache info L3 Cache Inf o only Display cache info Limit CPUID Maximum Disabled

Enabled

Execute Disabled Bit Disabled

Enabled

Intel Virtualization Technology Disabled

Enabled

SB CRID Revision ID

CRID 0 CRID 1 CRID 2

CPU Processor Power Management (PPM) Info only

Disabled for Windows XP

XD can prevent certain classes of malicious buffer overflow attacks when combined with a supporting OS (Windows Server 2003 SP1, Windows XP SP2, SuSE Linux 9.2, Red Hat Enterprise 3 Update 3.)

When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.

Select the Revision ID (Revision ID, CRID 0, CRID 1, CRID 2) reflected in PCI config space

cExpress-BT2 Page 47

Feature Options Description

EIST Disabled

Enabled

CPU C state Report Disabled

Enabled

CPU DTS Disabled

Enabled

Enable/Disable Intel SpeedStep

Enable/Disable CPU C state report to OS

Enabled/Disable digital thermal sensor

7.3.2. Memory

Feature Options Description

Memory Info only Total Memory Info only Display total memory DIMM#0/1 Info only Display DIMM#0/1 SPD Write Protect Enabled

Disabled

Max TOLUD Dynamic Maximum value of TOLUD

Enabled: Writes to SMBus slave addresses A0h – Aeh are disabled

7.3.3. Graphics

Feature Options Description

Graphics Info only

IGFX VBIOS Version Info only

Primary Display Auto

IGD

PCIE

Integrated Graphics Device Enabled

Disabled

Aperture Size 256MB Select the aperture size

DVMT Pre-Allocated 64M Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used

DVMT Total Gfx Mem 256MB Select DVMT5.0 Total Graphic Memory size used by the Internal

LVDS Backlight Mode BMC Mode

GTT Mode

AMI Graphics Output Protocol Policy [UEFI GOP only]

GT – Power Management Control Info only

Submenu User select monitor output by graphics output protocol

Select which graphics device (IGD/PCI) should be primary display

Enabled: Enable Integrated Graphics Device (IGD) when selected as the primary display; Disabled: Always disable IGD

by the Internal Graphics Device.

Graphics Device. Select LVDS backlight control function.

RC6 (Render Standby) Enabled

Disabled

Enable/Disable render standby support

Page 48 cExpress-BT2

7.3.3.1. AMI Graphics Output Protocol Policy

Feature Options Description

Intel(R) Valley View Graphics Controller Info only

Intel(R) GOP Driver Info only

Output Select [List connect device]

Brightness Setting [LFP device connect only]

BIST Enable Enabled

CRT Output Interface.

255 Set GOP Brightness value

Starts or stops the built-in self-test (BIST) on the integrated display

Disabled

panel.

7.3.4. SATA

Feature Options Description

SATA Info only SATA Controller(s) Enabled

Disabled

SATA Mode Selection IDE Mode

AHCI Mode

SATA Test Mode Enabled

Disabled

SATA Controller Speed Gen1

Gen2

SATA Port Configuration Submenu

Enable/Disable Serial ATA.

Select IDE/AHCI

Test Mode enable/disable

SATA speed support Gen1 or Gen2.

7.3.4.1. SATA > SATA Port Configuration

Feature Options Description

SATA Port Configuration Info only Port X Disabled

Enabled

HotPlug Enabled

Disabled

Enable/Disable SATA port X.

Enable/Disable SATA port X hotplug.

7.3.5. USB

Feature Options Description

USB Info only USB Module Version Info only USB Devices Info only Drives, keyboards, mouse, hubs Legacy USB Support Enabled

Disabled Auto

Enables legacy USB support. Auto option disables legacy support if no USB devices are

connected. Disable option will keep USB devices available only for EFI

cExpress-BT2 Page 49

Feature Options Description

applications and setup.

XHCI Hand-off Enabled

Disabled

EHCI Hand-off Enabled

Disabled

USB Mass Storage Driver Support Enabled

Disabled

Chipset USB Configuration Submenu USB hardware delays and time-outs: Info only USB transfer time-out 1 sec

5 sec 10 sec

20 sec

Device reset time-out 10 sec

20 sec

30 sec 40 sec

Device power-up delay Auto

Manual

Mass Storage Devices Info only List current USB mass storage devices.

This is a workaround for OSes without XHCI hand-off support. The XHCI ownership change should be claimed by the XHCI OS driver.

This is a workaround for OSes without EHCI hand-off support. The EHCI ownership change should be claimed by the EHCI OS driver.

Enable/Disable USB mass storage driver support.

The time-out value for control, bulk, and interrupt transfers

USB mass storage device Start Unit command time-out.

Maximum time the device will take before it properly reports itself to the Host Controller. 'Auto' uses default value: for a Root port it is 100 ms, for a Hub port the delay is taken from Hub descriptor.

7.3.5.1. USB > Chipset USB Configuration

Feature Options Description

USB Configuration Info only XHCI Mode Enabled

Disabled Auto

Smart Auto

USB 2.0 (EHCI) Support Enabled

Disabled

USB Per Port Control Enabled

Disabled

USB Port #0~3 Enabled

Disabled

Mode of operation of xHCI controller.

Control the USB EHCI (USB 2.0) functions. One EHCI controller must always be enabled.

Control each of the USB ports (0~3). Enable: Enable USB per port; Disable: Use USB port x settings.

Enable/Disable USB port 0-3.

7.3.6. Network

Feature Options Description

Network Info only Network Stack Enabled

Disabled

Enable/Disable UEFI network stack.

LAN Controller Enabled

Disabled

Wake on LAN Disable

Enabled

Enable/Disable LAN controller.

If Enabled: LAN_PWR is always on; If Disabled: LAN_PWR is off after entering Suspend mode.

Page 50 cExpress-BT2

7.3.7. PCI and PCIe

Feature Options Description

PCI and PCIe Info only PCI Common Settings Info only PCI Latency 32 PCI Bus Clocks

64 PCI Bus Clocks 96 PCI Bus Clocks 128 PCI Bus Clocks 160 PCI Bus Clocks 192 PCI Bus Clocks 224 PCI Bus Clocks 248 PCI Bus Clocks

VGA Palette Snoop Disabled

Enabled

PERR# Generation Enabled

Disabled

SERR# Generation Enabled

Disabled

PCI Express Settings Info only Relaxed Ordering Disabled

Enabled

Extended Tag Disabled

Enabled

No Snoop Disabled

Enabled

Maximum Payload Auto

128 Bytes 256 Bytes 512 Bytes 1024 Bytes 2048 Bytes 4096 Bytes

Value to be programmed into PCI latency timer register.

Enables or Disables VGA palette registers snooping.

Enable or Disable the PCI Express port 1 in the chipset.

Enables or Disables PCI Device to generate SERR#.

Enables or Disables PCI Express device relaxed ordering.

If Enabled, allows device to use 8-bit tag field as a requester.

Enables or Disables PCI Express device No Snoop option.

Set maximum payload of PCI Express device or allow system BIOS to select the value.

Maximum Read Request Auto

128 Bytes 256 Bytes 512 Bytes 1024 Bytes 2048 Bytes 4096 Bytes

PCI Express Link Register Settings Info only ASPM Support

WARNING: Enabling ASPM may cause some

PCI-E devices to fail

Extended Synch Disabled

Link Training Retry Disable

Link Training Timeout (Us) 1000 Defines number of microseconds software will wait before polling

Disabled

Auto Force L0s

Enabled

2 3

Set maximum read request size of PCI Express device or allow system BIOS to select the value.

Set the ASPM Level: Force L0s - Force all links to L0s Auto - BIOS auto configure Disabled - Disables ASPM

If enabled, allows generation of Extended Synchronization patterns.

Defines number of retry attempts software will take to retrain the link if previous training attempt was unsuccessful.

'Link Training' bit in Link Status register. Value range from 10 to

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Feature Options Description

10000 uS.

Unpopulated Links Keep Link ON

Disabled

Restore PCIE Registers Enabled

Disabled

PCIe Configuration Info only PCIe Configuration Submenu

In order to save power, software will disable unpopulated PCI Express links if this option set to Disabled.

On non-PCI Express aware OSes (pre Windows Vista) some devices may not be correctly reinitialized after S3. Enabling this restores PCI Express device configurations on S3 resume. Warning: Enabling this may cause issues with other hardware after S3 resume.

7.3.7.1. PCI and PCIe > PCIe Configuration

Feature Options Description

PCIe Configuration Info only PCI Express Root Port x Submenu

7.3.7.2. PCI and PCIe > PCIe Configuration > PCI Express Port x

Feature Options Description

PCI Express Port x Enabled

Disabled

Enable or disable the PCI Express port x in the chipset.

ASPM Auto PCI Express Active State Power Management settings. URR Disabled

Enabled

FER Disabled

Enabled

NFER Disabled

Enabled

CER Disabled

Enabled

SEFE Disabled

Enabled

SENFE Disabled

Enabled

SECE Disabled

Enabled

PME SCI Disabled

Enabled

Hot Plug Disabled

Enabled

Enable or disable PCI Express Unsupported Request Reporting.

Enable or disable PCI Express Device Fatal Error Reporting.

Enable or disable PCI Express Device Non-Fatal Error Reporting.

Enable or disable PCI Express Device Correctable Error Reporting.

Enable or disable Root PCI Express System Error on Fatal Error.

Enable or disable Root PCI Express System Error on Non-Fatal Error.

Enable or disable Root PCI Express System Error on Correctable Error.

Enable or disable PCI Express PME SCI.

Enable or disable PCI Express hotplug.

Speed Auto

Gen 2

Gen 1

Configure PCIe port speed.

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7.3.8. Super IO

Feature Options Description

Super IO Chip Info only W83627DHG Super IO Configuration Info only Serial Port 1 Configuration

Serial Port

Device Settings

Change Settings

Serial Port 2 Configuration Serial Port

Device Settings

Change Settings

Enabled Disabled

IO=3F8h; IRQ=4

Auto

IO=3F8h; IRQ=4 IO=3F8h; IRQ=3,4,5,6,7,10,11,12 IO=2F8h; IRQ=3,4,5,6,7,10,11,12 IO=3E8h; IRQ=3,4,5,6,7,10,11,12 IO=2E8h; IRQ=3,4,5,6,7,10,11,12

Enabled Disabled

IO=2F8h; IRQ=3

Auto

IO=2F8h; IRQ=3 IO=3F8h; IRQ=3,4,5,6,7,10,11,12 IO=2F8h; IRQ=3,4,5,6,7,10,11,12 IO=3E8h; IRQ=3,4,5,6,7,10,11,12 IO=2E8h; IRQ=3,4,5,6,7,10,11,12

Enable/Disable Serial Port 1 (COM0).

Fixed configuration of serial port.

Select an optimal setting for Super IO device.

Enable/Disable Serial Port 2 (COM1).

Fixed configuration of serial port.

Select an optimal setting for Super IO device.

Parallel Port Configuration Parallel Port

Device Settings

Change Settings

Enabled Disabled

IO=378h; IRQ=5

Auto

IO=378h; IRQ=5 IO=378h; IRQ=5,6,7,9,10,11,12 IO=278h; IRQ=5,6,7,9,10,11,12 IO=3BCh; IRQ=5,6,7,9,10,11,12

Enable/Disable Parallel Port 2 (LPT/LPTE).

Fixed configuration of parallel port.

Select an optimal settings for Super IO Device.

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7.3.9. ACPI and Power Management

Feature Options Description

ACPI and Power Management Info only Enable ACPI Auto Configuration Enabled

Disabled

Enable Hibernation Enabled

Disabled

ACPI Sleep State Suspend Disabled

S3 (Suspend to RAM)

Emulation AT/ATX Emulation AT

ATX

Enables or disables BIOS ACPI Auto Configuration.

Enables or disables system's ability to hibernate (OS/S4 Sleep State). This option may be not effective with some OSes.

Select the highest ACPI sleep state the system will enter when the Suspend button is pressed.

Select Emulation AT or ATX function.If this option set to [Emulation AT]. BIOS will report no suspend functions to ACPI OS.In windows XP, it will make OS show shutdown message during system shutdown.

7.3.10. Sound

Feature Options Description

Sound Info only Azalia Disabled

Enabled

Azalia Docking Support Disabled

Enabled

Control detection of the Azalia device. Disabled = Azalia will be unconditionally disabled. Enabled = Azalia will be unconditionally enabled. Auto = Azalia will be enabled if present, disabled otherwise.

Enable/Disable Azalia docking support of audio controller.

Azalia PME Disabled

Enabled

Enable/Disable power management capability of audio controller.

7.3.11. Serial Port Console

Feature Options Description

Serial Port Console Info only COM0 Info only Console Redirection Disabled

Enabled

Console Redirection Settings Submenu The settings specify how the host computer and the remote

COM1 Info only Console Redirection Disabled

Enabled

Console Redirection Settings Submenu The settings specify how the host computer and the remote

Console Redirection enable or disable.

computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.

Console Redirection enable or disable.

computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.

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7.3.11.1. Serial Port Console > Console Redirection Settings

Feature Options Description

COM0/COM1 Console Redirection Settings

Terminal Type VT100

Bits per second 9600

Data Bits 7

Parity None

Stop Bits 1

Flow Control None

VT-UTF8 Combo Key Support Disabled

Recorder Mode Disabled

Resolution 100x31 Disabled

Legacy OS Redirection 80x24

Putty KeyPad VT100

Redirection After BIOS Post Always Enabled

Info only

VT100+

VT-UTF8 ANSI

19200 38400 57600

115200

Even Odd Mark Space

Hardware RTS/CTS

Enable

80x25

LINUX XTERMR6 SCO ESCN VT400

BootLoader

VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes. ANSI: Extended ASCII char set.

Selects serial port transmission speed. The speed must be matched on the remote computer. Long or noisy lines may require lower speeds.

Select data bits.

Select parity.

Select number of stop bits.

Select flow control.

Enable VT-UTF8 combination key support for ANSI/VT100 terminals.

With this mode enabled only text will be sent. This is to capture terminal data.

Enables or disables extended terminal resolution

On legacy OSes, the number of rows and columns supported by redirection

Select FunctionKey and KeyPad on Putty.

The Settings specify if BootLoader is selected, then legacy console redirection is disabled before booting to legacy OS. Default value is Always Enable which means legacy console redirection is enabled for legacy OS.

7.3.12. Thermal

Feature Options Description

Thermal Info only CPU Temperature Info only Critical Trip Point Disabled

85 C 95 C

Active Cooling Trip Point Disabled

40 C

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This value controls the temperature of the ACPI Critical Trip Point the point at which the OS will shut the system down.

Active Cooling Trip Point.

Feature Options Description

50 C 60 C 70 C

BMC Default

Passive Trip Point Disabled

90 C 80 C

Passive TC1 Value 1 This value sets the TC1 value for the ACPI Passive Cooling

Passive TC2 Value 5 This value value sets the TC2 value for the ACPI Passive Cooling

Passive TSP Value 10 This item sets the TSP value for the ACPI Passive Cooling Formula.

This value controls the temperature of the ACPI Passive Trip Point the point at which the OS will begin throtting the processor.

Formula. Range 1 - 16

It represents in tenths of a second how often the OS will read the temperature when passive cooling is enabled. Range 2 - 32

7.3.13. Miscellaneous

Feature Options Description

Miscellaneous Info only High Precision Timer Enabled

Disabled

SCC Configuration Submenu Security Info only BIOS Security Configuration Submenu

Enable or disable the High Precision Event Timer.

Trusted Computing Submenu

7.3.13.1. Miscellaneous > SCC Configuration

Feature Options Description

OS Selection Windows 8.X

Android Windows 7

SCC Configuration Info only

SCC eMMC Support Enable eMMC 4.5 Support

Enable eMMC 4.41 Support

eMMC AUTO MODE

Disable

SCC eMMC 4.5 DDR50 Support Enabled

Disabled

SCC eMMC 4.5 HS200 Support Enabled

Disabled

eMMC Secure Erase Enabled

Disabled

SCC SD Card Support Enabled

Disabled

OS Selection

SCC eMMC support enable/disable.

SCC eMMC 4.5 DDR50 support enable/disable.

SCC eMMC 4.5 HS200 support enable/disable.

Disable/Enable eMMC secure erase. When enabled, all the data on eMMC will be erased.

SCC SD card support enable/disable.

SDR25 Support for SDCard Enabled

Disabled

Disable/Enable SDR25 capability in SD Card controller.

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Feature Options Description

DDR50 Support for SDCard Enabled

Disabled

MIPI HIS Support Enabled

Disabled

7.3.13.2. Miscellaneous > BIOS Security Configuration

Feature Options Description

BIOS Security Configuration Info only Global SMI Lock Enabled

Disabled

7.3.13.3. Miscellaneous > Trusted Computing

Feature Options Description

Coniguration Info only Security Device Support Enabled

Disabled

Current Status Information Info only

Disable/Enable DDR50 capability in SD Card controller.

MIPI HIS support enable/disable.

Enable or disable SMI lock.

Enables or disables BIOS support for security device. OS will not show security device. TCG EFI protocol and INT1A interface will not be available.

7.4. Boot

7.4.1. Boot Configuration

Feature Options Description

Boot Configuration Info only Setup Prompt Timeout 1 Number of seconds to wait for setup activation key. 65535 (0xFFFF )

means indefinite waiting.

Bootup NumLock State On

Off

Quiet Boot Disabled

Enabled

Fast Boot Disabled

Enabled

WIN8 Support Disabled

Enabled

Boot Option Priorities Info only

Select the keyboard NumLock state.

Enable or disables Quiet Boot option.

Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect on BBS boot options.

If enabled, some of default settings will be configured properly for Windows8.

Affected items: CSM Configuration->Boot option filter CSM Configuration->Video

Hard Drive BBS Priorities Info only CSM Parameters Submenu CSM configuration: Enable/Disable, Option ROM execution settings,

etc.

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7.4.1.1. Boot Configuration > CSM Parameters

Feature Options Description

Compatibility Support Module Configuration

CSM Support Enabled

CSM16 Module Version Info only GataA20 Active Upon Request

Option ROM Messages Force BIOS

INT19 Trap Response Immediate

Boot option filter UEFI and Legacy

Option ROM execution order Info only Network Do not launch

Storage Do not launch

Info

Disable

Always

Keep Current

Postponed

Legacy only UEFI only

UEFI only Legacy only

UEFI only

Legacy only

Enable/Disable CSM Support.

Upon Request – GA20 can be disabled using BIOS services. Always – do not allow disabling of GA20; this option is useful

when any RT code is executed above 1MB. Set display mode for Option ROM.

BIOS reaction on INT19 trapping by Option ROM: Immediate - execute the trap right away; Postponed – execute

the trap during legacy boot. This option controls legacy/UEFI ROM priority.

Controls the execution of UEFI and legacy PXE OpROM.

Controls the execution of UEFI and legacy storage OpROM.

Video Do not launch

Other PCI devices UEFI only

UEFI only

Legacy only

Controls the execution of UEFI and legacy video OpROM.

Determines OpROM execution policy for devices other than network, storage or video.

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7.5. Security

7.5.1. Password Descript io n

Feature Options Description

Administrator Password Enter password User Password Enter password Secure Boot menu Submenu Customizable Secure Boot settings.

7.5.1.1. Security > Secure Boot Menu

Feature Options Description

System Mode Setup Secure Boot Info only Secure Boot Disabled

Enabled

Secure Boot Mode Standard

Custom

Secure Boot can be enabled if:

1. System running in User mode with enrolled Platform Key (PK)

2. CSM function is disabled. Secure Boot mode selector. 'Custom' Mode enables users to change

Image Execution policy and manage Secure Boot keys.

7.6. Save & Exit

Feature Options Description

Save Changes and Exit Yes No Exit system setup after saving the changes. Discard Changes and Exit Yes No Exit system setup without saving any changes. Save Changes and Reset Yes No Reset the system after saving the changes. Discard Changes and Reset Yes No Reset system setup without saving any changes. Save Options Info only Save Changes Yes No Save Changes done so far to any of the setup options. Discard Changes Yes No Discard Changes done so far to any of the setup options. Restore Defaults Yes No Restore/Load Default values for all the setup options. Save as User Defaults Yes No Save the changes done so far as User Defaults. Restore User Defaults Yes No Restore the User Defaults to all the setup options.

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8. BIOS Checkpoints, Beep Codes

This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions.

Checkpoints and Beep Codes Definition

A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process.

Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized, and generated by the system board speaker.

Aptio Boot Flow

While performing the functions of the traditional BIOS, Aptio 5.x core follows the firmware model described by the Intel Platform Innovation Framework for EFI (“the Framework”). The Framework refers the following “boot phases”, which may apply to various status code & checkpoint descriptions:

• Security (SEC) – initial low-level initialization

• Pre-EFI Initialization (PEI) – memory initialization

• Driver Execution Environment (DXE) – main hardware initialization

• Boot Device Selection (BDS) – system setup, pre-OS user interface & selecting a bootable device (CD/DVD, HDD, USB, Network, Shell, …)

Viewing BIOS Checkpoints

Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a OST Card or POST Diagnostic Card. These are PCI add-in cards that show the value of I/O port 80h on a LED display.

Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated.

Keep in mind that not all computers using AMI Aptio BIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMI Aptio BIOS checkpoints.

Analogous to “bootblock” functionality of legacy BIOS

Analogous to “POST” functionality in legacy BIOS

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8.1. Checkpoint Ranges

Status Code Range

0x01 – 0x0B SEC execution 0x0C – 0x0F SEC errors 0x10 – 0x2F PEI execution up to and including memory detection 0x30 – 0x4F PEI execution after memory detection 0x50 – 0x5F PEI errors 0x60 – 0x8F DXE execution up to BDS 0x90 – 0xCF BDS execution 0xD0 – 0xDF DXE errors 0xE0 – 0xE8 S3 Resume (PEI) 0xE9 – 0xEF S3 Resume errors (PEI) 0xF0 – 0xF8 Recovery (PEI) 0xF9 – 0xFF Recovery errors (PEI)

Description

8.2. Standard Checkpoints

8.2.1. SEC Phase

Status Code Description

0x00 Not used Progress Codes 0x01 Power on. Reset type detection (soft/hard). 0x02 AP initialization before microcode loading 0x03 North Bridge initialization before microcode loading 0x04 South Bridge initialization before microcode loading 0x05 OEM initialization before microcode loading 0x06 Microcode loading 0x07 AP initialization after microcode loading 0x08 North Bridge initialization after microcode loading 0x09 South Bridge initialization after microcode loading 0x0A OEM initialization after microcode loading 0x0B Cache initialization

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SEC Error Codes

0x0C – 0x0D Reserved for future AMI SEC error codes 0x0E Microcode not found 0x0F Microcode not loaded

8.2.2. SEC Beep Codes

None

8.2.3. PEI Phase

Status Code Description

Progress Codes

0x10 PEI Core is started 0x11 Pre-memory CPU initialization is started 0x12 Pre-memory CPU initialization (CPU module specific) 0x13 Pre-memory CPU initialization (CPU module specific) 0x14 Pre-memory CPU initialization (CPU module specific) 0x15 Pre-memory North Bridge initialization is started 0x16 Pre-Memory North Bridge initialization (North Bridge module specific) 0x17 Pre-Memory North Bridge initialization (North Bridge module specific) 0x18 Pre-Memory North Bridge initialization (North Bridge module specific) 0x19 Pre-memory South Bridge initialization is started 0x1A Pre-memory South Bridge initialization (South Bridge module specific) 0x1B Pre-memory South Bridge initialization (South Bridge module specific) 0x1C Pre-memory South Bridge initialization (South Bridge module specific) 0x1D – 0x2A OEM pre-memory initialization codes 0x2B Memory initialization. Serial Presence Detect (SPD) data reading 0x2C Memory initialization. Memory presence detection 0x2D Memory initialization. Programming memory timing information 0x2E Memory initialization. Configuring memory 0x2F Memory initialization (other). 0x30 Reserved for ASL (see ASL Status Codes section below) 0x31 Memory Installed 0x32 CPU post-memory initialization is started 0x33 CPU post-memory initialization. Cache initialization 0x34 CPU post-memory initialization. Application Processor(s) (AP) initialization

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Status Code Description

0x35 CPU post-memory initialization. Boot Strap Processor (BSP) selection 0x36 CPU post-memory initialization. System Management Mode (SMM) initialization 0x37 Post-Memory North Bridge initialization is started 0x38 Post-Memory North Bridge initialization (North Bridge module specific) 0x39 Post-Memory North Bridge initialization (North Bridge module specific) 0x3A Post-Memory North Bridge initialization (North Bridge module specific) 0x3B Post-Memory South Bridge initialization is started 0x3C Post-Memory South Bridge initialization (South Bridge module specific) 0x3D Post-Memory South Bridge initialization (South Bridge module specific) 0x3E Post-Memory South Bridge initialization (South Bridge module specific) 0x3F-0x4E OEM post memory initialization codes 0x4F DXE IPL is started PEI Error Codes 0x50 Memory initialization error. Invalid memory type or incompatible memory speed 0x51 Memory initialization error. SPD reading has failed 0x52 Memory initialization error. Invalid memory size or memory modules do not match. 0x53 Memory initialization error. No usable memory detected 0x54 Unspecified memory initialization error. 0x55 Memory not installed 0x56 Invalid CPU type or Speed 0x57 CPU mismatch 0x58 CPU self test failed or possible CPU cache error 0x59 CPU micro-code is not found or micro-code update is failed 0x5A Internal CPU error 0x5B reset PPI is not available 0x5C-0x5F Reserved for future AMI error codes S3 Resume Progress Codes 0xE0 S3 Resume is stared (S3 Resume PPI is called by the DXE IPL) 0xE1 S3 Boot Script execution 0xE2 Video repost 0xE3 OS S3 wake vector call 0xE4-0xE7 Reserved for future AMI progress codes S3 Resume Error Codes 0xE8 S3 Resume Failed 0xE9 S3 Resume PPI not Found

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Status Code Description

0xEA S3 Resume Boot Script Error 0xEB S3 OS Wake Error 0xEC-0xEF Reserved for future AMI error codes Recovery Progress Codes 0xF0 Recovery condition triggered by firmware (Auto recovery) 0xF1 Recovery condition triggered by user (Forced recovery) 0xF2 Recovery process started 0xF3 Recovery firmware image is found 0xF4 Recovery firmware image is loaded 0xF5-0xF7 Reserved for future AMI progress codes Recovery Error Codes 0xF8 Recovery PPI is not available 0xF9 Recovery capsule is not found 0xFA Invalid recovery capsule 0xFB – 0xFF Reserved for future AMI error codes

8.2.4. PEI Beep Codes

# of Beeps Description

1 Memory not Installed 1 Memory was installed twice (InstallPeiMemory routine in PEI Core called twice) 2 Recovery started 3 DXEIPL was not found 3 DXE Core Firmware Volume was not found 4 Recovery failed 4 S3 Resume failed 7 Reset PPI is not available

8.2.5. DXE Phase

Status Code Description

0x60 DXE Core is started 0x61 NVRAM initialization 0x62 Installation of the South Bridge Runtime Services 0x63 CPU DXE initialization is started 0x64 CPU DXE initialization (CPU module specific)

Page 64 cExpress-BT2

Status Code Description

0x65 CPU DXE initialization (CPU module specific) 0x66 CPU DXE initialization (CPU module specific) 0x67 CPU DXE initialization (CPU module specific) 0x68 PCI host bridge initialization 0x69 North Bridge DXE initialization is started 0x6A North Bridge DXE SMM initialization is started 0x6B North Bridge DXE initialization (North Bridge module specific) 0x6C North Bridge DXE initialization (North Bridge module specific) 0x6D North Bridge DXE initialization (North Bridge module specific) 0x6E North Bridge DXE initialization (North Bridge module specific) 0x6F North Bridge DXE initialization (North Bridge module specific) 0x70 South Bridge DXE initialization is started 0x71 South Bridge DXE SMM initialization is started 0x72 South Bridge devices initialization 0x73 South Bridge DXE Initialization (South Bridge module specific) 0x74 South Bridge DXE Initialization (South Bridge module specific) 0x75 South Bridge DXE Initialization (South Bridge module specific) 0x76 South Bridge DXE Initialization (South Bridge module specific) 0x77 South Bridge DXE Initialization (South Bridge module specific) 0x78 ACPI module initialization 0x79 CSM initialization 0x7A – 0x7F Reserved for future AMI DXE codes 0x80 – 0x8F OEM DXE initialization codes 0x90 Boot Device Selection (BDS) phase is started 0x91 Driver connecting is started 0x92 PCI Bus initialization is started 0x93 PCI Bus Hot Plug Controller Initialization 0x94 PCI Bus Enumeration 0x95 PCI Bus Request Resources 0x96 PCI Bus Assign Resources 0x97 Console Output devices connect 0x98 Console input devices connect 0x99 Super IO Initialization 0x9A USB initialization is started 0x9B USB Reset

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Status Code Description

0x9C USB Detect 0x9D USB Enable 0x9E – 0x9F Reserved for future AMI codes 0xA0 IDE initialization is started 0xA1 IDE Reset 0xA2 IDE Detect 0xA3 IDE Enable 0xA4 SCSI initialization is started 0xA5 SCSI Reset 0xA6 SCSI Detect 0xA7 SCSI Enable 0xA8 Setup Verifying Password 0xA9 Start of Setup 0xAA Reserved for ASL (see ASL Status Codes section below) 0xAB Setup Input Wait 0xAC Reserved for ASL (see ASL Status Codes section below) 0xAD Ready To Boot event 0xAE Legacy Boot event 0xAF Exit Boot Services event 0xB0 Runtime Set Virtual Address MAP Begin 0xB1 Runtime Set Virtual Address MAP End 0xB2 Legacy Option ROM Initialization 0xB3 System Reset 0xB4 USB hot plug 0xB5 PCI bus hot plug 0xB6 Clean-up of NVRAM 0xB7 Configuration Reset (reset of NVRAM settings) 0xB8 – 0xBF Reserved for future AMI codes 0xC0 – 0xCF OEM BDS initialization codes DXE Error Codes 0xD0 CPU initialization error 0xD1 North Bridge initialization error 0xD2 South Bridge initialization error 0xD3 Some of the Architectural Protocols are not available 0xD4 PCI resource allocation error. Out of Resources

Page 66 cExpress-BT2

Status Code Description

0xD5 No Space for Legacy Option ROM 0xD6 No Console Output Devices are found 0xD7 No Console Input Devices are found 0xD8 Invalid password 0xD9 Error loading Boot Option (LoadImage returned error) 0xDA Boot Option is failed (StartImage returned error) 0xDB Flash update is failed 0xDC Reset protocol is not available

8.2.6. DXE Beep Codes

# of Beeps Description

1 Invalid password 4 Some of the Architectural Protocols are not available 5 No Console Output Devices are found 5 No Console Input Devices are found 6 Flash update is failed 7 Reset protocol is not available 8 Platform PCI resource requirements cannot be met

8.2.7. ACPI/ASL Checkpoint

Status Code Description

0x01 System is entering S1 sleep state 0x02 System is entering S2 sleep state 0x03 System is entering S3 sleep state 0x04 System is entering S4 sleep state 0x05 System is entering S5 sleep state 0x10 System is waking up from the S1 sleep state 0x20 System is waking up from the S2 sleep state 0x30 System is waking up from the S3 sleep state 0x40 System is waking up from the S4 sleep state 0xAC System has transitioned into ACPI mode. Interrupt controller is in PIC mode. 0xAA System has transitioned into ACPI mode. Interrupt controller is in APIC mode.

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8.3. OEM-Reserved Checkpoint Ranges

Status Code Description

0x05 OEM SEC initialization before microcode loading 0x0A OEM SEC initialization after microcode loading 0x1D – 0x2A OEM pre-memory initialization codes 0x3F – 0x4E OEM PEI post memory initialization codes 0x80 – 0x8F OEM DXE initialization codes 0xC0 – 0xCF OEM BDS initialization codes

Page 68 cExpress-BT2

9. Mechanical Information

9.1. Board-to-Board Connectors

To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When 5 mm receptacles are chosen, the carrier board should be free of components.

Tyco 3-1827253-6 Foxconn QT002206-2131-3H

• 220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm.

• This connector can be used with 5 mm through-hole standoffs (SMT type).

Tyco 3-6318491-6 Foxconn QT002206-4141-3H

• 220-pin board-to-board connector with 0.5mm for a stacking height of 8 mm.

• This connector can be used with 8 mm through-hole standoffs (SMT type).

Common Specifications

• Current capacity: 0.5A per pin

• Rated voltage: 50 VAC

• Insulation resistance: 100M or greater @ 500 VDC

• Temperature rating: -40°C ~ 85°C

• UL certification (ECBT2.E28476)

• Copper alloy (contacts)

• Housing: thermo-plastic molded compound (L.C.P.)

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9.2. Thermal Solution

9.2.1. Heat Spreaders

The function of the heat spreader is to ensure an identical mechanical profile for all COM Express modules. By using a heat spreader, the thermal solution that is built on top of the module is compatible with all COM Express modules.

9.2.2. Heat Sinks

A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless, depending on the thermal requirements.

9.2.3. Installation

Install a heat spreader or heat sink using the following instructions. Step 1: Before mounting the heatsink, install the required memory modules onto the SODIMM socket(s) on the COM Express module.

Step 2: Remove the protective membranes from the thermal pads.

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Step 3: Assemble the heatsink onto the COM Express module. Use the four M2.5, L=6mm screws provided to fasten the heatsink to the module.

Step 4: Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown.

Then press down on the module until it is firmly seated on the carrier board. Step 5: Use the five M2.5, L=16mm screws provided to secure the COM Express module to the carrier board from the solder side.

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Step 6: If you are installing a heatsink with a fan, plug the fan connector into the carrier board as shown.

Page 72 cExpress-BT2

9.3. Mounting Methods

There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the choice of 5 mm or 8mm board-to-board connectors, there is the choice of Top and Bottom mounting. In Top mounting, the threaded standoffs are on the carrier board and the thermal solution is equipped with through-hole standoffs. In Bottom mounting, the threaded standoffs are on the thermal solution and the carrier board has through-hole standoffs.

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9.4. Standoff Types

The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and throughhole standoffs are SMT type. Other types not listed are available upon request.

5mm through-hole standoff (SMT type) P/N: 33-72000-0050

8mm through-hole standoff (SMT type) P/N: 33-72000-0080

5mm threaded standoff (DIP type) P/N: 33-72016-0050

8mm threaded standoff (DIP type) P/N: 33-72015-0050

Page 74 cExpress-BT2

Safety Instructions

Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use.

• Please read these safety instructions carefully.

• Please keep this User‘s Manual for later reference.

• The equipment should be operated only from the type of power source indicated on the rating label. Make sure the voltage of the

power source when connect the equipment to the power outlet.

• If your equipment has a voltage selector switch, make sure that the switch is in the proper position for your area. The voltage

selector switch is set at the factory to the correct voltage.

• For pluggable equipment, that the socket-outlet shall be installed near the equipment and shall be easily accessible.

• Place the power cord such a way that people can not step on it. Do not place anything over the power cord.

• If the equipment is not use for long time, disconnect the equipment from mains to avoid being damaged by transient overvoltage.

• All cautions and warnings on the equipment should be noted.

• Please keep this equipment from humidity.

• Do not use this equipment near water or a heat source.

• Lay this equipment on a reliable surface when install. A drop or fall could cause injury.

• Never pour any liquid into opening; this could cause fire or electrical shock.

• Openings in the case are provided for ventilation. Do not block or cover these openings. Make sure you provide adequate space

around the system for ventilation when you set up your work area. Never insert objects of any kind into the ventilation openings.

• To avoid electrical shock, always unplug all power cables and modem cables from the wall outlets before removing covers.

• Lithium Battery provided (real time clock battery)

“CAUTION – Risk of explosion if battery is replaced with one of an incorrect type. Dispose of used batteries according to the instructions”

• If one of the following situations arises, get the equipment checked by a service personnel:

 The power cord or plug is damaged.  Liquid has penetrated into the equipment.  The equipment has been exposed to moisture.  The equipment has not work well or you can not get it work according to user‘s manual.  The equipment has dropped and damaged.  If the equipment has obvious sign of breakage.

cExpress-BT2 Page 75

Getting Service

ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan Tel: +886-2-8226-5877 Fax: +886-2-8226-5717 Email: service@adlinktech.com

Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com

ADLINK Technology (China) Co., Ltd.

Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com

ADLINK Technology Beijing

Address: Rm. 801, Power Creative E, No. 1, B/D Shang Di East Rd., Beijing, 100085 China Tel: +86-10-5885-8666 Fax: +86-10-5885-8625 Email: market@adlinktech.com

ADLINK Technology Shenzhen

Address: 2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7, High-Tech Industrial Park S., Shenzhen, 518054 China Tel: +86-755-2643-4858 Fax: +86-755-2664-6353 Email: market@adlinktech.com

LiPPERT ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 11, D-68163, Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: emea@adlinktech.com

Page 76 cExpress-BT2

ADLINK Technology, Inc. (French Liaison Office)

Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com

ADLINK Technology Japan Corporation

Address: KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho, Chiyoda-ku, Tokyo 101-0045, Japan Tel: +81-3-4455-3722 Fax: +81-3-5209-6013 Email: japan@adlinktech.com

ADLINK Technology, Inc. (Korean Liaison Office)

Address: 8F Mointer B/D,1675-12, Seocho-Dong, Seocho-Gu, Seoul 137-070, Korea Tel: +82-2-2057-0565 Fax: +82-2-2057-0563 Email: korea@adlinktech.com

ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre, Singapore 349584 Tel: +65-6844-2261 Fax: +65-6844-2263 Email: singapore@adlinktech.com

ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: 1st Floor, #50-56 (Between 16th/17th Cross) Margosa Plaza, Margosa Main Road, Malleswaram, Bangalore-560055, India Tel: +91-80-65605817, +91-80-42246107 Fax: +91-80- 23464606 Email: india@adlinktech.com

cExpress-BT2 Page 77

ADLINK cExpress-BT2 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

cExpress-BT2

Revision History

Preface

Table of Contents

1. Introduction

2. Specifications

2.1. Core System

2.2. Expansion Busses

2.3. SEMA Board Controller

2.4. Debug Headers

2.5. Video

2.6. Audio

2.7. LAN

2.8. Multi I/O and Storage

2.9. TPM (Trusted Platform Module)

2.10. Power Specificatio ns

2.11. Power Consumption

2.12. Operating Temperatures

2.13. Environmental

2.14. Specification Compliance

2.15. Operating Systems

2.16. Functional Diagram

2.17. Mechanical Dimensions

3. Pinouts and Signal Descriptions

3.1. AB / CD Pin Definitions

3.2. Signal Description Terminology

3.3. AB Signal Descriptions

3.3.1. Audio Signals

3.3.2. Analog VGA

3.3.3. LVDS

3.3.4. Gigabit Ethernet

3.3.5. SATA

3.3.6. PCI Express

3.3.7. Express Card

3.3.8. LPC bus

3.3.9. USB

3.3.10. USB Root Segmentation

3.3.11. SPI (BIOS only)

3.3.12. Miscellaneous

3.3.13. SMBus

3.3.14. I2C Bus

3.3.15. General Purpose I/O (GPIO)

3.3.16. Serial Interface Signals

3.3.17. Power And System Management

3.3.18. Power and Ground

3.4. CD Signal Descriptions

3.4.1. PATA IDE

3.4.2. PCI

3.4.3. Module Type Definition

3.4.4. Power and Ground

4. Module interfaces

4.1. Connector, Switch and LED Locations

4.1.1. cExpress-BT2 and the DB40 Module connected

4.2. 40-pin Multipurpose Connector

4.3. Status LEDs

4.4. XDP Debug Header

4.5. Fan Connector

4.6. BIOS Setup Defaults RESET Button

5. Smart Embedded Management Agent (SEMA)

5.1. Board Specific SEMA Functions

5.1.1. Voltages

5.1.2. Main Current

5.1.3. BMC Status

5.1.4. Exception Codes

5.1.5. BMC Flags

6.1. System Memory Map

6.2. I/O Map

6.3. Interrupt Request (IRQ) Lines

6.3.1. PIC Mode

6.3.2. APIC Mode

6.4. PCI Configuration Space Map

6.5. PCI Interrupt Routing Map

6.6. PCI Interrupt Routing Map

7. BIOS Setup

7.1. Menu Structure

7.2. Main