ADLINK cExpress-BT User Manual

cExpress-BT

User’s Manual

Manual Revision: 1.01
Revision Date: September 24, 2014
Part Number: 50-1J051-1010

Revision History

Revision Description Date By

1.00 Initial release 2014-07-23 JC

1.01 Add BIOS Checkpoints, Beep Codes; update eMMC capacity 2014-09-24 JC

Page 2 cExpress-BT

Preface

Copyright 2014 ADLINK Technology, Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by
any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

Disclaimer
The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not

represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or
consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such
damages.

Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's
Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental
protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and
raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to
dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their
respective companies.

cExpress-BT Page 3

Table of Contents

Revision History ............................................................................................................ 2

Preface............................................................................................................................ 3

1. Introduction .......................................................................................................... 8

2. Specifications........................................................................................................ 9

2.1. Core System...........................................................................................................................9

2.2. Expansion Busses...................................................................................................................9

2.3. SEMA Board Controller..........................................................................................................9

2.4. Debug Headers ......................................................................................................................9

2.5. Video................................................................................................................................... 10

2.6. Audio................................................................................................................................... 10

2.7. LAN...................................................................................................................................... 10

2.8. Multi I/O and Storage ......................................................................................................... 10

2.9. TPM (Trusted Platform Module) ........................................................................................ 10

2.10. Power Specifications........................................................................................................... 11

2.11. Power Consumption ........................................................................................................... 11

2.12. Operating Temperatures .................................................................................................... 11

2.13. Environmental .................................................................................................................... 11

2.14. Specification Compliance.................................................................................................... 11

2.15. Operating Systems.............................................................................................................. 11

2.16. Functional Diagram............................................................................................................. 12

2.17. Mechanical Dimensions...................................................................................................... 13

3. Pinouts and Signal Descriptions....................................................................... 14

3.1. AB / CD Pin Definitions ....................................................................................................... 14

3.2. Signal Description Terminology .......................................................................................... 17

3.3. AB Signal Descriptions ........................................................................................................ 18

3.3.1. Audio Signals .....................................................................................................................................18

3.3.2. Analog VGA........................................................................................................................................18

3.3.3. LVDS...................................................................................................................................................18

3.3.4. Gigabit Ethernet ................................................................................................................................19

3.3.5. SATA ..................................................................................................................................................19

3.3.6. PCI Express.........................................................................................................................................20

3.3.7. Express Card ......................................................................................................................................21

Page 4 cExpress-BT

3.3.8. LPC Bus ..............................................................................................................................................21

3.3.9. USB ....................................................................................................................................................21

3.3.10. USB Root Segmentation ..................................................................................................................22

3.3.11. SPI (BIOS only) .................................................................................................................................22

3.3.12. Miscellaneous..................................................................................................................................23

3.3.13. SMBus..............................................................................................................................................23

3.3.14. I2C Bus .............................................................................................................................................23

3.3.15. General Purpose I/O (GPIO) ............................................................................................................23

3.3.16. Serial Interface Signals.....................................................................................................................24

3.3.17. Power And System Management....................................................................................................24

3.3.18. Power and Ground ..........................................................................................................................25

3.4. CD Signal Descriptions ........................................................................................................ 26

3.4.1. USB 3.0 extension..............................................................................................................................26

3.4.2. PCI Express x1....................................................................................................................................26

3.4.3. DDI Channels .....................................................................................................................................27

3.4.4. DDI to DP/HDMI Mapping .................................................................................................................29

3.4.5. PCI Express Graphics x16 (PEG) .........................................................................................................30

3.4.6. Module Type Definition.....................................................................................................................31

3.4.7. Power and Ground ............................................................................................................................31

4. Module Interfaces .............................................................................................. 32

4.1. Connector, Switch and LED Locations ................................................................................ 32

4.1.1. cExpress-BT and the DB40 Module connected..................................................................................32

4.2. 40-pin Multipurpose Connector ......................................................................................... 33

4.3. Status LEDs.......................................................................................................................... 34

4.4. XDP Debug Header ............................................................................................................. 35

4.5. Fan Connector .................................................................................................................... 35

4.6. BIOS Setup Defaults RESET Button ..................................................................................... 36

4.7. Mini SD Slot......................................................................................................................... 37

5. Smart Embedded Management Agent (SEMA) .............................................. 38

5.1. Board Specific SEMA Functions .......................................................................................... 39

5.1.1. Voltages.............................................................................................................................................39

5.1.2. Main Current .....................................................................................................................................39

5.1.3. BMC Status ........................................................................................................................................39

5.1.4. Exception Codes ................................................................................................................................40

5.1.5. BMC Flags ..........................................................................................................................................40

6. System Resources............................................................................................... 41

6.1. System Memory Map ......................................................................................................... 41

cExpress-BT Page 5

6.2. I/O Map............................................................................................................................... 41

6.3. Interrupt Request (IRQ) Lines ............................................................................................. 42

6.3.1. PIC Mode ...........................................................................................................................................42

6.3.2. APIC Mode.........................................................................................................................................43

6.4. PCI Configuration Space Map ............................................................................................. 44

6.5. PCI Interrupt Routing Map.................................................................................................. 45

6.6. SMBus Address Table ......................................................................................................... 45

7. BIOS Setup ..........................................................................................................46

7.1. Menu Structure................................................................................................................... 46

7.2. Main.................................................................................................................................... 47

7.2.1. System Information ...........................................................................................................................47

7.2.2. Processor Information.......................................................................................................................47

7.2.3. VGA Firmware Version ......................................................................................................................47

7.2.4. Memory Information.........................................................................................................................47

7.2.5. SOC Information ................................................................................................................................47

7.2.6. System Management.........................................................................................................................48

7.2.7. System Date and Time.......................................................................................................................51

7.3. Advanced ............................................................................................................................ 51

7.3.1. CPU ....................................................................................................................................................51

7.3.2. Memory .............................................................................................................................................52

7.3.3. Graphics.............................................................................................................................................52

7.3.4. SATA ..................................................................................................................................................53

7.3.5. USB ....................................................................................................................................................53

7.3.6. Network.............................................................................................................................................54

7.3.7. PCI and PCIe.......................................................................................................................................55

7.3.8. Super IO.............................................................................................................................................57

7.3.9. ACPI and Power Management...........................................................................................................57

7.3.10. Sound...............................................................................................................................................58

7.3.11. Serial Port Console ..........................................................................................................................58

7.3.12. Thermal ...........................................................................................................................................59

7.3.13. Miscellaneous..................................................................................................................................60

7.4. Boot .................................................................................................................................... 61

7.4.1. Boot Configuration ............................................................................................................................61

7.5. Security ............................................................................................................................... 62

7.5.1. Password Description ........................................................................................................................62

7.6. Save & Exit .......................................................................................................................... 63

Page 6 cExpress-BT

8. BIOS Checkpoints, Beep Codes......................................................................... 64

8.1. Checkpoint Ranges ............................................................................................................. 65

8.2. Standard Checkpoints......................................................................................................... 65

8.2.1. SEC Phase ..........................................................................................................................................65

8.2.2. SEC Beep Codes .................................................................................................................................66

8.2.3. PEI Phase ...........................................................................................................................................66

8.2.4. PEI Beep Codes ..................................................................................................................................68

8.2.5. DXE Phase..........................................................................................................................................68

8.2.6. DXE Beep Codes.................................................................................................................................71

8.2.7. ACPI/ASL Checkpoint.........................................................................................................................71

8.3. OEM-Reserved Checkpoint Ranges .................................................................................... 72

9. Mechanical Information .................................................................................... 73

9.1. Board-to-Board Connectors................................................................................................ 73

9.2. Thermal Solution ................................................................................................................ 74

9.2.1. Heat Spreaders ..................................................................................................................................74

9.2.2. Heat Sinks ..........................................................................................................................................74

9.2.3. Installation.........................................................................................................................................74

9.3. Mounting Methods............................................................................................................. 77

9.4. Standoff Types .................................................................................................................... 78

Safety Instructions ...................................................................................................... 79

Getting Service ............................................................................................................ 80

cExpress-BT Page 7

1. Introduction

The cExpress-BT is a COM Express® COM.0 R2.1 Type 6 module supporting the Intel® Atom™ processor E3800 Series and Intel®
Celeron® processor system-on-chip (SoC). The cExpress-BT is specifically designed for customers who need high-level processing and
graphics performance with low power consumption in a long product life solution.

The Intel® Atom™ processor E3800 and Intel® Celeron® processor support non-ECC type DDR3L dual-channel memory at 1066/1333 MHz
to provide excellent overall performance. Integrated Intel® Gen7 HD Graphics includes features such as OpenGL 3.1, DirectX 11, OpenCL

1.1 and support for H.264, MPEG2, VC1, VP8 hardware decode. Graphics outputs include VGA, DDI ports supporting HDMI/DVI/DisplayPort
and optional dual-channel 18/24-bit LVDS. The cExpress-BT is specifically designed for customers with high-performance processing
graphics requirements who want to outsource the custom core logic of their systems for reduced development time.

The cExpress-BT has dual stacked SODIMM sockets for up to 8 GB non-ECC type DDR3L memory. In addition, an onboard miniSD card
slot and onboard eMCC memory (optional, 8GB to 64GB) are supported.

The cExpress-BT features a single Gigabit Ethernet port, USB 3.0 ports and USB 2.0 ports, and SATA 3 Gb/s ports. Support is provided for
SMBus and I
hardware monitor, and watchdog timer.

2

C. The module is equipped with SPI AMI EFI BIOS, supporting embedded features such as remote console, CMOS backup,

Page 8 cExpress-BT

2. Specifications

2.1. Core System

¾ CPU: Single, dual or quad-core Intel® Atom™ or Celeron® Processor

• Atom™ E3845 1.91 GHz 542/792 (Turbo) 10W (4C/1333)

• Atom™ E3827 1.75 GHz 542/792 (Turbo) 8W (2C/1333)

• Atom™ E3826 1.46 GHz 533/667 (Turbo) 7W (2C/1066)

• Atom™ E3825 1.33 GHz 533 (No Turbo) 6W (2C/1066)

• Atom™ E3815 1.46 GHz 400 (No Turbo) 5W (1C/1066)

• Celeron® N2930 1.83/2.16 (Burst) GHz, 313/854 (Turbo) 7.5W (4C/1333)

• Celeron® J1900 2.0/2.42 (Burst) GHz, 688/854 (Turbo) 10W (4C/1333)

Supports: Single, dual or quad Out-of-Order Execution (OOE) processor cores, Intel® VT-x, Intel® SSE4.1 and SSE4.2, Intel® 64 architecture,
IA 32-bit, PCLMULQDQ Instruction, DRNG, Intel® Thermal Monitor (TM1 & TM2)

Note: Availability of features may vary between processor SKUs.

¾ Cache: Primary 32 kB, 8-way L1 instruction cache and 24 kB, 6-way L1 write-back data cache
¾ Memory: Dual channel non-ECC 1066/1333 MHz DDR3L memory up to 8GB in dual stacked SODIMM sockets (lower slot must be populated)

¾ Embedded BIOS: AMI EFI with CMOS backup in 8MB SPI BIOS

2.2. Expansion Busses

¾ 3 PCI Express x1 (AB): lanes 0/1/2 (build option: PCIe x4, lose GbE)
¾ LPC bus, SMBus (system), I

2

C (user)

2.3. SEMA Board Controller

¾ Type: ADLINK Smart Embedded Management Agent (SEMA)
¾ Supports:

• Voltage/Current monitoring

• Power sequence debug support

• AT/ATX mode control

• Logistics and Forensic information

• Flat Panel Control

• General Purpose I2C

• Failsafe BIOS (dual BIOS )

• Watchdog Timer and Fan Control

2.4. Debug Headers

¾ 40-pin multipurpose flat cable connector, used in combination with DB-40 debug module providing BIOS POST code LED, BMC

access, SPI BIOS flashing, Power Testpoints, Debug LEDs

¾ 26-pin XDP header for ICE debug of SOC

cExpress-BT Page 9

2.5. Video

¾ GPU Feature Support: 7th generation graphics Intel core architecture with four execution units supporting two independent displays

• 3D graphics hardware acceleration

• Support for DirectX11, OCL 1.1, OGL ES Halt/2.0/1.1, OGL 3.2

• Video decode hardware acceleration including support for H.264, MPEG2, VC-1, WMV and VP8 formats

• Video encode hardware acceleration including support for H.264, MPEG2 and MVC formatsPlayback of Blu-ray disc S3D content using HDMI

(1.4a spec compliant with 3D)

Note: Availability of features may vary between operating systems.

¾ Display Interface support

• DDI1

Supports DisplayPort / HDMI / DVI
Build option upon request supports dual channel 18/24-bit LVDS through eDP to LVDS bridge

• DDI2

Supports DisplayPort / HDMI / DVI

• VGA

Analog VGA supporting resolutions up to 2560x1600x24bpp @60

2.6. Audio

¾ Integrated: Intel® HD Audio integrated in SOC
¾ Audio Codec: located on carrier Express-BASE6 (ALC886 supported)

2.7. LAN

¾ Intel MAC/PHY: Intel® i210 (MAC/PHY) Ethernet controller
¾ Interface: 10/100/1000 GbE connection

2.8. Multi I/O and Storage

¾ Integrated in SOC
¾ USB:

• 1x USB 1.1/2.0/3.0 (USB 0)

• 6x USB 1.1/2.0 (USB 1/2/3/4/5/6, ports 3-6 from USB hub)

¾ SATA: 2x SATA 3Gb/s (SATA0, SATA1)
¾ eMMC: soldered on module bootable eMMC flash storage 8 to 32 GB (optional)
¾ SDIO: onboard miniSD card socket
¾ Serial: 2x UART ports COM 0/1 (COM 1 supports console redirection)
¾ GPIO: 4x GPO and 4x GPI with interrupt

2.9. TPM (Trusted Platform Module)

¾ Chipset: ATMELAT97SC3204 (optional)
¾ Type: TPM 1.2

Page 10 cExpress-BT

2.10. Power Specificatio ns

¾ Power Modes: AT and ATX mode (AT mode start controlled by SEMA)
¾ Standard Voltage Input: ATX = 12V ±5%, 5Vsb ±5% or AT = 12V ±5%
¾ Wide Voltage Input: ATX = 5~20 V, 5Vsb ±5% or AT = 5 ~20V
¾ Power Management: ACPI 4.0 compliant, Smart Battery support
¾ Power States: supports C1-C6, S0, S1, S4, S3, S5, S5 ECO mode (Wake-on-USB S3/S4, WoL S3/S4/S5)
¾ ECO mode: supports deep S5 for 5Vsb power saving

2.11. Power Consumption

TBD

2.12. Operating Temperatures

¾ Standard Operating Temperature: 0°C to 60°C (wide voltage input)
¾ Extreme Rugged Operating Temperature (optional)*: -40°C to 85°C (standard voltage input)

*Intel® Atom™ E3800 Series processors only

2.13. Environmental

¾ Humidity: 5-90% RH operating, non-condensing

5-95% RH storage (and operating with conformal coating).

¾ Shock and Vibration: IEC 60068-2-64 and IEC-60068-2-27

MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D

¾ Halt: Thermal Stress, Vibration Stress, Thermal Shock and Combined Test

2.14. Specification Compliance

¾ PICMG COM.0: Rev 2.1 Type 6, compact size 95 x 95

2.15. Operating Systems

¾ Standard Support: Windows 7/8 32/64-bit, Linux 32/64-bit
¾ Extended Support (BSP): WES7/8, WEC7, Linux, VxWorks

cExpress-BT Page 11

2.16. Functional Diagram

Page 12 cExpress-BT

T

m

2.17. Mechanical Dimensions

connector on bottom side

op View

Side View

All tolerances ± 0.05 mm

Other tolerances ± 0.2 m

cExpress-BT Page 13

3. Pinouts and Signal Descriptions

3.1. AB / CD Pin Definitions

The cExpress-BT is a Type 6 module supporting USB 3.0 and DDI channels on the CD connector. In the table below, all standard pins of the
COM Express specification are described, including those not supported on the cExpress-BT.

Note: Signals not supported on the cExpress-BT module are crossed out

Row A Row B Row C Row D

Pin Name Pin Name Pin Name Pin Name

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35

GND (FIXED)
GBE0_MDI3­GBE0_MDI3+
GBE0_LINK100#
GBE0_LINK1000#
GBE0_MDI2­GBE0_MDI2+
GBE0_LINK#
GBE0_MDI1­GBE0_MDI1+
GND (FIXED)
GBE0_MDI0­GBE0_MDI0+
GBE0_CTREF

SUS_S3#

SATA0_TX+
SATA0_TX-

SUS_S4#

SATA0_RX+
SATA0_RX­GND (FIXED)
SATA2_TX+
SATA2_TX-

SUS_S5#

SATA2_RX+
SATA2_RX-

BATLOW#

(S)ATA_ACT#
AC/HDA_SYNC
AC/HDA_RST#
GND (FIXED)
AC/HDA_BITCLK
AC/HDA_SDOUT

BIOS_DIS0#
THRMTRIP#

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35

GND (FIXED)
GBE0_ACT#
LPC_FRAME#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ0#
LPC_DRQ1#
LPC_CLK
GND (FIXED)

PWRBTN#
SMB_CK
SMB_DAT
SMB_ALERT#

SATA1_TX+
SATA1_TX-

SUS_STAT#

SATA1_RX+
SATA1_RX­GND (FIXED)
SATA3_TX+
SATA3_TX-

PWR_OK

SATA3_RX+
SATA3_RX-

WDT

AC/HDA_SDIN2
AC/HDA_SDIN1
AC/HDA_SDIN0
GND (FIXED)

SPKR
I2C_CK
I2C_DAT
THRM#

C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35

GND FIXED)
GND
USB_SSRX0­USB_SSRX0+
GND
USB_SSRX1­USB_SSRX1+
GND
USB_SSRX2­USB_SSRX2+
GND (FIXED)
USB_SSRX3­USB_SSRX3+
GND

DDI1_PAIR6+
DDI1_PAIR6-

RSVD
RSVD
PCIE_RX6+
PCIE_RX6­GND (FIXED)
PCIE_RX7+
PCIE_RX7­DDI1_HPD
DDI1_PAIR4+
DDI1_PAIR4­RSVD
RSVD
DDI1_PAIR5+
DDI1_PAIR5­GND (FIXED)

DDI2_CTRLCLK_AUX+
DDI2_CTRLDATA_AUX­DDI2_DDC_AUX_SEL

RSVD

D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35

GND FIXED)
GND
USB_SSTX0­USB_SSTX0+
GND
USB_SSTX1­USB_SSTX1+
GND
USB_SSTX2­USB_SSTX2+
GND (FIXED)
USB_SSTX3­USB_SSTX3+
GND

DDI1_CTRLCLK_AUX+
DDI1_CTRLDATA_AUX

RSVD
RSVD
PCIE_TX6+
PCIE_TX6­GND (FIXED)
PCIE_TX7+
PCIE_TX7­RSVD
RSVD
DDI1_PAIR0+
DDI1_PAIR0­RSVD
DDI1_PAIR1+
DDI1_PAIR1­GND (FIXED)
DDI1_PAIR2+
DDI1_PAIR2-

DDI1_DDC_AUX_SEL

RSVD

Page 14 cExpress-BT

Row A Row B Row C Row D

Pin Name Pin Name Pin Name Pin Name

A36 USB6- B36 USB7- C36 DDI3_CTRLCLK_AUX+ D36 DDI1_PAIR3+
A37 USB6+ B37 USB7+ C37 DDI3_CTRLDATA_AUX- D37 DDI1_PAIR3-
A38 USB_6_7_OC# B38 USB_4_5_OC# C38 DDI3_DDC_AUX_SEL D38 RSVD
A39 USB4- B39 USB5- C39 DDI3_PAIR0+ D39 DDI2_PAIR0+
A40 USB4+ B40 USB5+ C40 DDI3_PAIR0- D40 DDI2_PAIR0-
A41 GND (FIXED) B41 GND (FIXED) C41 GND (FIXED) D41 GND (FIXED)
A42 USB2- B42 USB3- C42 DDI3_PAIR1+ D42 DDI2_PAIR1+
A43 USB2+ B43 USB3+ C43 DDI3_PAIR1- D43 DDI2_PAIR1-
A44 USB_2_3_OC# B44 USB_0_1_OC# C44 DDI3_HPD D44 DDI2_HPD
A45 USB0- B45 USB1- C45 RSVD D45 RSVD
A46 USB0+ B46 USB1+ C46 DDI3_PAIR2+ D46 DDI2_PAIR2+
A47 VCC_RTC B47 EXCD1_PERST# C47 DDI3_PAIR2- D47 DDI2_PAIR2-
A48 EXCD0_PERST# B48 EXCD1_CPPE# C48 RSVD D48 RSVD
A49 EXCD0_CPPE# B49 SYS_RESET# C49 DDI3_PAIR3+ D49 DDI2_PAIR3+
A50 LPC_SERIRQ B50 CB_RESET# C50 DDI3_PAIR3- D50 DDI2_PAIR3-
A51 GND (FIXED) B51 GND (FIXED) C51 GND (FIXED) D51 GND (FIXED)
A52 PCIE_TX5+ B52 PCIE_RX5+ C52 PEG_RX0+ D52 PEG_TX0+
A53 PCIE_TX5- B53 PCIE_RX5- C53 PEG_RX0- D53 PEG_TX0-
A54 GPI0 B54 GPO1 C54 TYPE0# D54 PEG_LANE_RV#
A55 PCIE_TX4+ B55 PCIE_RX4+ C55 PEG_RX1+ D55 PEG_TX1+
A56 PCIE_TX4- B56 PCIE_RX4- C56 PEG_RX1- D56 PEG_TX1-
A57 GND B57 GPO2 C57 TYPE1# D57 TYPE2#
A58 PCIE_TX3+ B58 PCIE_RX3+ C58 PEG_RX2+ D58 PEG_TX2+
A59 PCIE_TX3- B59 PCIE_RX3- C59 PEG_RX2- D59 PEG_TX2-
A60 GND (FIXED) B60 GND (FIXED) C60 GND (FIXED) D60 GND (FIXED)
A61 PCIE_TX2+ B61 PCIE_RX2+ C61 PEG_RX3+ D61 PEG_TX3+
A62 PCIE_TX2- B62 PCIE_RX2- C62 PEG_RX3- D62 PEG_TX3-
A63 GPI1 B63 GPO3 C63 RSVD D63 RSVD
A64 PCIE_TX1+ B64 PCIE_RX1+ C64 RSVD D64 RSVD
A65 PCIE_TX1- B65 PCIE_RX1- C65 PEG_RX4+ D65 PEG_TX4+
A66 GND B66 WAKE0# C66 PEG_RX4- D66 PEG_TX4-
A67 GPI2 B67 WAKE1# C67 RSVD D67 GND
A68 PCIE_TX0+ B68 PCIE_RX0+ C68 PEG_RX5+ D68 PEG_TX5+
A69 PCIE_TX0- B69 PCIE_RX0- C69 PEG_RX5- D69 PEG_TX5-
A70 GND (FIXED) B70 GND (FIXED) C70 GND (FIXED) D70 GND (FIXED)
A71 LVDS_A0+ * B71 LVDS_B0+ * C71 PEG_RX6+ D71 PEG_TX6+
A72 LVDS_A0- * B72 LVDS_B0- * C72 PEG_RX6- D72 PEG_TX6-
A73 LVDS_A1+ * B73 LVDS_B1+ * C73 GND D73 GND
A74 LVDS_A1- * B74 LVDS_B1- * C74 PEG_RX7+ D74 PEG_TX7+
A75 LVDS_A2+ * B75 LVDS_B2+ * C75 PEG_RX7- D75 PEG_TX7-
A76 LVDS_A2- * B76 LVDS_B2- * C76 GND D76 GND
A77 LVDS_VDD_EN * B77 LVDS_B3+ * C77 RSVD D77 RSVD
A78 LVDS_A3+ * B78 LVDS_B3- * C78 PEG_RX8+ D78 PEG_TX8+
A79 LVDS_A3- * B79 LVDS_BKLT_EN * C79 PEG_RX8- D79 PEG_TX8-
A80 GND (FIXED) B80 GND (FIXED) C80 GND (FIXED) D80 GND (FIXED)

cExpress-BT Page 15

Row A Row B Row C Row D

Pin Name Pin Name Pin Name Pin Name

A81 LVDS_A_CK+ * B81 LVDS_B_CK+ * C81 PEG_RX9+ D81 PEG_TX9+
A82 LVDS_A_CK- * B82 LVDS_B_CK- * C82 PEG_RX9- D82 PEG_TX9-
A83 LVDS_I2C_CK * B83 LVDS_BKLT_CTRL * C83 TPM_PP D83 RSVD
A84 LVDS_I2C_DAT * B84 VCC_5V_SBY C84 GND D84 GND
A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10+ D85 PEG_TX10+
A86 RSVD B86 VCC_5V_SBY C86 PEG_RX10- D86 PEG_TX10-
A87 RSVD B87 VCC_5V_SBY C87 GND D87 GND
A88 PCIE0_CK_REF+ B88 BIOS_DIS1# C88 PEG_RX11+ D88 PEG_TX11+
A89 PCIE0_CK_REF- B89 VGA_RED C89 PEG_RX11- D89 PEG_TX11-
A90 GND (FIXED) B90 GND (FIXED) C90 GND (FIXED) D90 GND (FIXED)
A91 SPI_POWER B91 VGA_GRN C91 PEG_RX12+ D91 PEG_TX12+
A92 SPI_MISO B92 VGA_BLU C92 PEG_RX12- D92 PEG_TX12-
A93 GPO0 B93 VGA_HSYNC C93 GND D93 GND
A94 SPI_CLK B94 VGA_VSYNC C94 PEG_RX13+ D94 PEG_TX13+
A95 SPI_MOSI B95 VGA_I2C_CK C95 PEG_RX13- D95 PEG_TX13-
A96 TPM_PP B96 VGA_I2C_DAT C96 GND D96 GND
A97 TYPE10# B97 SPI_CS# C97 RSVD D97 RSVD
A98 SER0_TX / CAN_TX B98 RSVD C98 PEG_RX14+ D98 PEG_TX14+
A99 SER0_RX / CAN_RX B99 RSVD C99 PEG_RX14- D99 PEG_TX14-
A100 GND (FIXED) B100 GND (FIXED) C100 GND (FIXED) D100 GND (FIXED)
A101 SER1_TX B101 FAN_PWMOUT C101 PEG_RX15+ D101 PEG_TX15+
A102 SER1_RX B102 FAN_TACHIN C102 PEG_RX15- D102 PEG_TX15-
A103 LID# ** B103 SLEEP# ** C103 GND D103 GND
A104 VCC_12V B104 VCC_12V C104 VCC_12V D104 VCC_12V
A105 VCC_12V B105 VCC_12V C105 VCC_12V D105 VCC_12V
A106 VCC_12V B106 VCC_12V C106 VCC_12V D106 VCC_12V
A107 VCC_12V B107 VCC_12V C107 VCC_12V D107 VCC_12V
A108 VCC_12V B108 VCC_12V C108 VCC_12V D108 VCC_12V
A109 VCC_12V B109 VCC_12V C109 VCC_12V D109 VCC_12V
A110 GND (FIXED) B110 GND (FIXED) C110 GND (FIXED) D110 GND (FIXED)

Notes:

- LID# and SLEEP# signals are not natively supported on the SOC. They instead connect to GPIO pins simulating their behaviour.

- LVDS can be supported by build option that reoutes DDI1 to a eDP to LVDS bridge.

- PCIe (port 3) can be supported by BOM option (lose GbE).

Page 16 cExpress-BT

3.2. Signal Description Terminology

The following terms are used in the COM Express AB/CD Signal Descriptions below.

I Input to the Module
O Output from the Module
I/O Bi-directional input / output signal
OD Open drain output
I 3.3V Input 3.3V tolerant
I 5V Input 5V tolerant
O 3.3V Output 3.3V signal level
O 5V Output 5V signal level
I/O 3.3V Bi-directional signal 3.3V tolerant
I/O 5V Bi-directional signal 5V tolerant
I/O 3.3Vsb Input 3.3V tolerant active in standby state
P Power Input/Output
REF Reference voltage output that may be sourced from a module power plane.
PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected.

The signal is used to indicate the PICMG module type to the Carrier Board.
PU ADLINK implemented pull-up resistor on module
PD ADLINK implemented pull-down resistor on module

cExpress-BT Page 17

3.3. AB Signal Descriptions

3.3.1. Audio Signals

Signal Pin # Description I/O PU/PD Comment

AC_RST# /
HDA_RST#

AC_SYNC /
HDA_SYNC

AC_BITCLK /
HDA_BITCLK

AC _SDOUT /
HDA_SDOUT

AC _SDIN[2:0]
HDA_SDIN[2:0]

A30 Reset output to CODEC, active low. O 3.3VSB

A29 Sample-synchronization signal to the CODEC(s). O 3.3V

A32 Serial data clock generated by the external

CODEC(s).

A33 Serial TDM data output to the CODEC. O 3.3V

B28
B30

Serial TDM data inputs from up to 3 CODECs. I/O 3.3VSB AC_SDIN0: supported

I/O 3.3V

AC_SDIN1: supported
AC_SDIN2: not supported

3.3.2. Analog VGA

Signal Pin # Description I/O PU/PD Comment

VGA_RED B89 Red for monitor.

Analog DAC output, designed to drive a

37.5-Ohm equivalent load.

VGA_GRN B91 Green for monitor

Analog DAC output, designed to drive a

37.5-Ohm equivalent load.

O Analog

O Analog

PD 150R

PD 150R

Shall also be terminated on the
carrier with 150Ω resistor to
ground close to VGA connector

Shall also be terminated on the
carrier with 150Ω resistor to
ground close to VGA connector

VGA_BLU B92 Blue for monitor.

Analog DAC output, designed to drive a

37.5-Ohm equivalent load.
VGA_HSYNC B93 Horizontal sync output to VGA monitor O 3.3V
VGA_VSYNC B94 Vertical sync output to VGA monitor O 3.3V
VGA_I2C_CK B95 DDC clock line (I²C port dedicated to identify

VGA monitor capabilities)

VGA_I2C_DAT B96 DDC data line. I/O OD 3.3V PU 2k2 3.3V

O Analog

I/O OD 3.3V PU 2k2 3.3V

PD 150R

Shall also be terminated on the
carrier with 150Ω resistor to
ground close to VGA connector

3.3.3. LVDS

Signal Pin # Description I/O PU/PD Comment

LVDS_A0+
LVDS_A0-
LVDS_A1+
LVDS_A1-
LVDS_A2+
LVDS_A2-
LVDS_A3+
LVDS_A3-

LVDS_A_CK+
LVDS_A_CK-

A71
A72
A73
A74
A75
A76
A78
A79

A81
A82

LVDS Channel A differential pairs O LVDS

LVDS Channel A differential clock O LVDS

LVDS support is a build
option with eDP to LVDS
bridge on DDI1

Page 18 cExpress-BT

Signal Pin # Description I/O PU/PD Comment

LVDS_B0+
LVDS_B0-
LVDS_B1+
LVDS_B1-
LVDS_B2+
LVDS_B2-
LVDS_B3+
LVDS_B3-

LVDS_B_CK+
LVDS_B_CK-

LVDS_VDD_EN A77 LVDS panel power enable O 3.3V
LVDS_BKLT_EN B79 LVDS panel backlight enable O 3.3V
LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3.3V

LVDS_I2C_CK A83 DDC lines used for flat panel detection and control. O 3.3V PU 2k2 3.3V
LVDS_I2C_DAT A84 DDC lines used for flat panel detection and control. I/O 3.3V PU 2k2 3.3V

B71
B72
B73
B74
B75
B76
B77
B78

B81
B82

LVDS Channel B differential pairs O LVDS

LVDS Channel B differential clock O LVDS

PD 100K

Realtek ePD to LVDS
requirement

3.3.4. Gigabit Ethernet

Gigabit Ethernet Pin # Description I/O PU/PD Comment

GBE0_MDI0+
GBE0_MDI0-
GBE0_MDI1+
GBE0_MDI1-
GBE0_MDI2+
GBE0_MDI2-
GBE0_MDI3+
GBE0_MDI3-

GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. O 3.3VSB PU 10k

GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. O 3.3VSB
GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low. O 3.3VSB
GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low. O 3.3VSB
GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics

A13
A11
A10
A9
A7
A6
A3
A2

Gigabit Ethernet Controller 0: Media Dependent Interface Differential
Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec
modes. Some pairs are unused in some modes according to the
following:

1000 100 10

MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/­MDI[2]+/- B1_DC+/­MDI[3]+/- B1_DD+/-

center tap. The reference voltage is determined by the requirements of
the Module PHY and may be as low as 0V and as high as 3.3V. The
reference voltage output shall be current limited on the Module. In the
case in which the reference is shorted to ground, the current shall be 250
mA or less.

I/O Analog Twisted pair

3.3VSB

GND min

3.3V max

signals for
external
transformer.

3.3.5. SATA

Signal Pin # Description I/O PU/PD Comment

SATA0_TX+
SATA0_TX-

SATA0_RX+
SATA0_RX-

cExpress-BT Page 19

A16

Serial ATA channel 0, Transmit Output differential pair. O SATA AC coupled on Module

A17
A19

Serial ATA channel 0, Receive Input differential pair. I SATA AC coupled on Module

A20

Signal Pin # Description I/O PU/PD Comment

SATA1_TX+
SATA1_TX-

SATA1_RX+
SATA1_RX-

SATA2_TX+
SATA2_TX-

SATA2_RX+
SATA2_RX-

SATA3_TX+
SATA3_TX-

SATA3_RX+
SATA3_RX-

(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity indicator, active low. O 3.3V

B16

Serial ATA channel 1, Transmit Output differential pair. O SATA AC coupled on Module

B17
B19

Serial ATA channel 1, Receive Input differential pair. I SATA AC coupled on Module

B20
A22

Serial ATA channel 2, Transmit Output differential pair. O SATA Not supported

A23
A25

Serial ATA channel 2, Receive Input differential pair. I SATA Not supported

A26
B22

Serial ATA channel 3, Transmit Output differential pair. O SATA Not supported

B23
B25

Serial ATA channel 3, Receive Input differential pair. I SATA Not supported

B26

3.3.6. PCI Express

Signal Pin # Description I/O PU/PD Comment

PCIE_TX0+
PCIE_TX0-

PCIE_RX0+
PCIE_RX0-

A68
A69

B68
B69

PCI Express channel 0, Transmit Output
differential pair.

PCI Express channel 0, Receive Input
differential pair.

O PCIE AC coupled on module

I PCIE AC coupled off module

PCIE_TX1+
PCIE_TX1-

PCIE_RX1+
PCIE_RX1-

PCIE_TX2+
PCIE_TX2-

PCIE_RX2+
PCIE_RX2-

PCIE_TX3+
PCIE_TX3-

PCIE_RX3+
PCIE_RX3-

PCIE_TX4+
PCIE_TX4-

PCIE_RX4+
PCIE_RX4-

PCIE_TX5+
PCIE_TX5-

PCIE_RX5+
PCIE_RX5-

A64
A65

B64
B65

A61
A62

B61
B62

A58
A59

B58
B59

A55
A56

B55
B56

A52
A53

B52
B53

PCI Express channel 1, Transmit Output
differential pair.

PCI Express channel 1, Receive Input
differential pair.

PCI Express channel 2, Transmit Output
differential pair.

PCI Express channel 2, Receive Input
differential pair.

PCI Express channel 3, Transmit Output
differential pair.

PCI Express channel 3, Receive Input
differential pair.

PCI Express channel 4, Transmit Output
differential pair.

PCI Express channel 4, Receive Input
differential pair.

PCI Express channel 5, Transmit Output
differential pair.

PCI Express channel 5, Receive Input
differential pair.

O PCIE AC coupled on module

I PCIE AC coupled off module

O PCIE AC coupled on module

I PCIE AC coupled off module

O PCIE

I PCIE

O PCIE

I PCIE

O PCIE

I PCIE

Standard BOM not supported, used by GbE
alternative route to support x4 without LAN

Standard BOM not supported, used by GbE
alternative route to support x4 without LAN

Not supported

Not supported

Not supported

Not supported

PCIE_CLK_REF+
PCIE_CLK_REF-

A88
A89

PCI Express Reference Clock output for all PCI
Express and PCI Express Graphics Lanes.

O PCIE

Page 20 cExpress-BT

3.3.7. Express Card

Signal Pin # Description I/O PU/PD Comment

EXCD0_CPPE#
EXCD1_CPPE#

EXCD0_PERST#
EXCD1_PERST#

A49
B48

A48
B47

PCI ExpressCard: PCI Express capable card request I 3.3V PU 10k 3.3V

PCI ExpressCard: reset O 3.3V

3.3.8. LPC Bus

Signal Pin # Description I/O PU/PD Comment

LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V
LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V
LPC_DRQ0#

LPC_DRQ1#
LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V PU 8k2 3.3V
LPC_CLK B10 LPC clock output –33MHz nominal O 3.3V Atom clock 33 MHz

B8
B9

LPC serial DMA request I 3.3V

Celeron clock 25 MHz

3.3.9. USB

Signal Pin # Description I/O PU/PD Comment

USB0+
USB0-

USB1+
USB1-

USB2+
USB2-

USB3+
USB3-

USB4+
USB4-

USB5+
USB5-

USB6+
USB6-

USB7+
USB7-

USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up

A46

USB differential data pairs for Port 0 I/O 3.3VSB USB 1.1/ 2.0 compliant

A45
B46

USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant

B45
A43

USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant

A42
B43

USB differential data pairs for Port 2 I/O 3.3VSB USB 1.1/ 2.0 compliant

B42
A40

USB differential data pairs for Port 3 I/O 3.3VSB USB 1.1/ 2.0 compliant

A39
B40

USB differential data pairs for Port 4 I/O 3.3VSB USB 1.1/ 2.0 compliant

B39
A37

USB differential data pairs for Port 5 I/O 3.3VSB USB 1.1/ 2.0 compliant

A36
B37

USB differential data pairs for Port 6 I/O 3.3VSB Not supported

B37

I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.

USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up

for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low. .

I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier

cExpress-BT Page 21

Signal Pin # Description I/O PU/PD Comment

USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up

for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.

USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up

for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.

3.3.10. USB Root Segmentation

P1 P2 P3 P 4

EHCI Controller

Port 0

(1.1/2.0)

Port 1

(1.1/2.0)

Port 2

(1.1/2.0)

USB Hub

Port 3

(1.1/2.0)

P1-P4

Port 4

(1.1/2.0)

HSIC 0

(1.1/2.0)

Port 5

XHCI Controller

Port 6

(1.1/2.0)

I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier

I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier

P6

HSIC 1

SSP1P5

Port 0

(3.0)

USB0+ /A46

USB0-/ A45

USB1+ / B46

USB1- / B4 5

USB2+ / A 43

USB2-/ A42

USB3+ / B43

USB3- / B42

Row A/B

USB4+ / A 40

USB4-/ A39

USB5+ / B40

USB5- / B39

USB6+/ A37

USB6-/ A36

USB7 + / B3 7

USB7-/ B36

USB3_RN0 / C3

USB3_TN0 / D3

USB3_RP0 / C4

USB3_TP0/ D4

USB3_RN1/ C3

USB3_TN1 / D 3

USB3_RP1 / C4

USB3_TP1 /D4

USB3_RN2 / C3

USB3_TN2/ D3

USB3_R P2/ C4

USB3_TP2 / D4

Row C/D

3.3.11. SPI (BIOS only)

Signal Pin # Description I/O PU/PD Comment

SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB Only supports CS0
SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB
SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module

– nominally 3.3V.
The Module shall provide a minimum of 100mA on
SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER.
SPI_POWER shall only be used to power SPI devices on
the Carrier

BIOS_DIS0# A34 Selection strap to determine the BIOS boot device. I PU 10K 3.3V Carrier shall pull to GND

O P 3.3VSB

or leave not- connected.

USB3_RN3/ C3

USB3_TN3 / D 3

USB3_R P3/ C4

USB3_TP3 / D4

BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. I PU 10K 3.3V Carrier shall pull to GND

or leave not- connected

Page 22 cExpress-BT

3.3.12. Miscellaneous

Signal Pin # Description I/O PU/PD Comment

SPKR B32 Output for audio enunciator, the “speaker” in PC-AT

systems

WDT B27 Output indicating that a watchdog time-out event has

occurred.

THRM# B35 Input from off-module temp sensor indicating an over-temp

situation.

THRMTRIP# A35 Active low output indicating that the CPU has entered

thermal shutdown.

FAN_PWMOUT B101 Fan speed control. Uses the Pulse Width Modulation

(PWM) technique to control the fan’s RPM.
FAN_TACHIN B102 Fan tachometer input for a fan with a two pulse output. I OD 3.3V PU 10k 3.3V
TPM_PP C83 Trusted Platform Module (TPM) Physical Presence pin.

Active high. TPM chip has an internal pull down. This

signal is used to indicate Physical Presence to the TPM.

O 3.3V

O 3.3V

I 3.3V

O 3.3V PU 10k 3.3V

O OD 3.3V

I 3.3V

PD 10k 3.3V PD only when TPM on

module

3.3.13. SMBus

Signal Pin # Description I/O PU/PD Comment

SMB_CK B13 System Management Bus bidirectional clock line. Power

sourced through 5V standby rail and main power rails.

SMB_DAT# B14 System Management Bus bidirectional data line. Power

sourced through 5V standby rail and main power rails.

I/O OD 3.3VSB PU 2k2 3.3VSB

I/O OD 3.3VSB PU 2k2 3.3VSB

SMB_ALERT# B15 System Management Bus Alert – active low input can

be used to generate an SMI# (System Management
Interrupt) or to wake the system. Power sourced
through 5V standby rail and main power rails.

I 3.3VSB PU 10k 3.3VSB

3.3.14. I2C Bus

Signal Pin # Description I/O PU/PD Comment

I2C_CK B33 General purpose I²C port clock output/input I/O OD 3.3VSB PU 2k2 3.3VSB Source SEMA BMC or

Baytrail SOC as
alternative.

I2C_DAT B34 General purpose I²C port data I/O line I/O OD 3.3VSB PU 2k2 3.3VSB Source SEMA BMC or

Baytrail SOC as
alternative.

3.3.15. General Purpose I/O (GPIO)

Signal Pin # Description I/O PU/PD Comment

GPO[0] A93 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET

output low

GPO[1] B54 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET

output low

GPO[2] B57 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET

output low

cExpress-BT Page 23

Signal Pin # Description I/O PU/PD Comment

GPO[3] B63 General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET

output low

GPI[0] A54 General purpose input pins.

Pulled high internally on the module.

GPI[1] A63 General purpose input pins.

Pulled high internally on the module.

GPI[2] A67 General purpose input pins.

Pulled high internally on the module.

GPI[3] A85 General purpose input pins.

Pulled high internally on the module.

I 3.3V PU 10K 3.3V

I 3.3V PU 10K 3.3V

I 3.3V PU 10K 3.3V

I 3.3V PU 10K 3.3V

3.3.16. Serial Interface Signals

Signal Pin # Description I/O PU/PD Comment

SER0_TX A98 General purpose serial port transmitter (TTL level output) O CMOS Power rail tolerance 5V / 12V
SER0_RX A99 General purpose serial port receiver (TTL level input) I CMOS Power rail tolerance 5V / 12V
SER1_TX A101 General purpose serial port transmitter (TTL level output) O CMOS Power rail tolerance 5V / 12V
SER1_RX A102 General purpose serial port receiver (TTL level input) I CMOS Power rail tolerance 5V / 12V

3.3.17. Power And System Management

Signal Pin # Description I/O PU/PD Comment

PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge. I 3.3VSB PU 10k

3.3VSB

SYS_RESET# B49 Reset button input. Active low request for module to reset and reboot. May

be falling edge sensitive. For situations when SYS_RESET# is not able to
reestablish control of the system, PWR_OK or a power cycle may be used.

CB_RESET# B50 Reset output from module to Carrier Board. Active low. Issued by module

chipset and may result from a low SYS_RESET# input, a low PWR_OK
input, a VCC_12V power input that falls below the minimum specification, a
watchdog timeout, or may be initiated by the module software.

PWR_OK B24 Power OK from main power supply. A high value indicates that the power is

good. This signal can be used to hold off Module startup to allow carrier

based FPGAs or other configurable devices time to be programmed.
SUS_STAT# B18 Indicates imminent suspend operation; used to notify LPC devices. O 3.3VSB
SUS_S3# A15 Indicates system is in Suspend to RAM state. Active-low output. An inverted

copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be

used to enable the non-standby power on a typical ATX power supply.
SUS_S4# A18 Indicates system is in Suspend to Disk state. Active low output. O 3.3VSB
SUS_S5# A24 Indicates system is in Soft Off state. O 3.3VSB Not supported

WAKE0# B66 PCI Express wake up signal. I 3.3VSB PU 10k

I 3.3VSB PU 10k

3.3VSB

O 3.3VSB

I 3.3V PU 100k

3.3VSB

O 3.3VSB

3.3VSB

connected to
SUS_S4#

Not supported
connected to
WAKE1#

WAKE1# B67 General purpose wake up signal. May be used to implement wake-up on

PS/2 keyboard or mouse activity.

I 3.3VSB PU 10k

3.3VSB

Page 24 cExpress-BT

Signal Pin # Description I/O PU/PD Comment

BATLOW# A27 Battery low input. This signal may be driven low by external circuitry to

signal that the system battery is low, or may be used to signal some other

external power-management event.
LID# LID button. Low active signal used by the ACPI operating system for a LID

switch.
SLEEP# Sleep button. Low active signal used by the ACPI operating system to bring

the system to sleep state or to wake it up again.

I 3.3VSB PU 10k

3.3VSB

I OD

3.3VSB
I OD

3.3VSB

PU 10k

3.3VSB
PU 10K

3.3VSB

Emulated on
GPIO (BIOS)

Emulated on
GPIO (BIOS)

3.3.18. Power and Ground

Signal Pin # Description I/O PU/PD Comment

VCC_12V A104-A109

B104-B109

VCC_5V_SBY B84-B87 Standby power input: +5.0V nominal. See Section 7 “Electrical

VCC_RTC A47 Real-time clock circuit-power input. Nominally +3.0V. P
GND A1, A11, A21, A31, A41, A51,

A57, A66, A80, A90, A96, A100,
A110, B1, B11, B21,B31, B41,
B51, B60, B70, B80, B90, B100,
B110

Primary power input: +12V nominal (wide range 5 ~ 20V).
All available VCC_12V pins on the connector(s) shall be used.

Specifications“ for allowable input range. If VCC5_SBY is used, all
available VCC_5V_SBY pins on the connector(s) shall be used.
Only used for standby and suspend functions. May be left
unconnected if these functions are not used in the system design.

Ground - DC power and signal and AC signal return path. P

P 5~20 V

P 5Vsb ±5%

cExpress-BT Page 25