ADLINK cExpress-BL User Manual
cExpress-BL
User’s Manual
Manual Revision: 1.00
Revision Date: May 7, 2015
Part Number: 50-1J061-1000
Revision History
Revision Description Date By
1.00 Initial release 2015-05-07 JC
Page 2 cExpress-BL
Preface
Copyright 2015 ADLINK Technology, Inc.
This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by
any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not
represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or
consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such
damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's
Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental
protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and
raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to
dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their
respective companies.
cExpress-BL Page 3
Table of Contents
Revision History ............................................................................................................ 2
Preface............................................................................................................................ 3
1 Introduction............................................................................................................ 6
2 Specifications.......................................................................................................... 7
2.1 Core System ..................................................................................................................................7
2.2 Expansion Busses ..........................................................................................................................7
2.3 Video .............................................................................................................................................7
2.4 Audio.............................................................................................................................................8
2.5 LAN................................................................................................................................................8
2.6 Multi I/O and Storage ...................................................................................................................8
2.7 Serial I/O on Module.....................................................................................................................8
2.8 Trusted Platform Module (TPM)...................................................................................................8
2.9 SEMA Board Controller .................................................................................................................8
2.10 Debug ........................................................................................................................................8
2.11 Power Specifications .................................................................................................................9
2.12 Operating Temperatures...........................................................................................................9
2.13 Environmental ...........................................................................................................................9
2.14 Specification Compliance ..........................................................................................................9
2.15 Operating Systems ....................................................................................................................9
2.16 Functional Diagram ................................................................................................................ 10
2.17 Mechanical Drawing............................................................................................................... 11
3 Pinouts and Signal Descriptions......................................................................... 12
3.1 AB/CD Pin Definitions ................................................................................................................ 12
3.2 Signal Description Terminology ................................................................................................. 15
3.3 AB Signal Descriptions ............................................................................................................... 16
3.4 CD Signal Descriptions ............................................................................................................... 25
4 Connector Pinouts on Module............................................................................ 31
4.1 40-pin Debug Connector............................................................................................................ 32
4.2 Status LEDs................................................................................................................................. 34
4.3 XDP Debug header ..................................................................................................................... 35
4.4 Fan Connector............................................................................................................................ 36
4.5 BIOS Setup Defaults Reset Button ............................................................................................. 36
Page 4 cExpress-BL
5 Smart Embedded Management Agent (SEMA) ................................................ 37
5.1 Board Specific SEMA Functions ................................................................................................. 38
6 System Resources................................................................................................. 40
6.1 System Memory Map................................................................................................................. 40
6.2 Direct Memory Access Channels ............................................................................................... 40
6.3 I/O Map...................................................................................................................................... 41
6.4 Interrupt Request (IRQ) Lines .................................................................................................... 43
6.5 PCI Configuration Space Map .................................................................................................... 45
6.6 PCI Interrupt Routing Map......................................................................................................... 46
6.7 SMBus Address Table................................................................................................................. 46
7 BIOS Setup ............................................................................................................ 47
7.1 Menu Structure.......................................................................................................................... 47
7.2 Menu Structure.......................................................................................................................... 48
7.3 Advanced Menu......................................................................................................................... 52
7.4 Boot Menu ................................................................................................................................. 66
7.5 Security Menu............................................................................................................................ 67
7.6 Save & Exit Menu ....................................................................................................................... 67
8 BIOS Checkpoints, Beep Codes........................................................................... 68
8.1 Status Code Ranges.................................................................................................................... 69
8.2 Standard Status Codes ............................................................................................................... 69
8.3 OEM-Reserved Checkpoint Ranges............................................................................................ 76
9 Mechanical Information ...................................................................................... 77
9.1 Board-to-Board Connectors....................................................................................................... 77
9.2 Thermal Solution........................................................................................................................ 78
9.3 Mounting Methods .................................................................................................................... 80
9.4 Standoff Types ........................................................................................................................... 81
Safety Instructions ...................................................................................................... 82
Getting Service ............................................................................................................ 83
cExpress-BL Page 5
1 Introduction
The cExpress-BL is a COM Express® COM.0 R2.1 Type 6 Compact size module featuring the 64-bit 5th Generation Intel® Core™ i7/i5/i3
and Intel® Celeron® Ultra-Low TDP processors (formerly “Broadwell-U”) with CPU, memory controller, graphics processor and I/O hub on a
single chip. Leveraging the benefits provided by the 5
specifically designed for customers who need optimum processing and graphics performance with low power consumption in a long product
life solution. The cExpress-BL’s Intel® processors support Intel® Hyper-Threading Technology (up to 2 cores, 4 threads) and up to 16 GB of
non-ECC DDR3L dual-channel memory at 1333/1600 MHz in dual stacked SODIMM sockets to provide excellent overall performance.
Integrated Intel® Generation 8 Graphics includes features such as OpenGL 4.2, DirectX 11.1, Intel® Clear Video HD Technology, Advanced
Scheduler 2.0, 1.0, XPDM support, and DirectX Video Acceleration (DXVA) support for full AVC/VC1/MPEG2 hardware decode. Graphics
outputs include dual-channel 18/24-bit LVDS (eDP optional) and two DDI ports supporting HDMI/DVI/DisplayPort. The cExpress-BL is
specifically designed for customers with high-performance processing graphics requirements who want to outsource the custom core logic of
their systems for reduced development time.
th
generation Intel® Core™ and Celeron™ System-on-Chip, the cExpress-BL is
The cExpress-BL features a single onboard Gigabit Ethernet port, two USB 3.0 ports, six USB 2.0 ports, and four SATA 6Gb/s ports.
2
Support is provided for SMBus and I
C. The module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded features
such as remote console, CMOS backup, hardware monitor, and watchdog timer.
Page 6 cExpress-BL
2 Specifications
2.1 Core System
¾ CPU: 5th Generation Intel® Core™ processor SoC (formerly “Broadwell-U”)
• Intel® Core™ i7-5650U 2.2 GHz (3.2 GHz Turbo), 15W (2C/GT3)
• Intel® Core™ i5-5350U 1.8 GHz (2.9 GHz Turbo), 15W (2C/GT3)
• Intel® Core™ i3-5010U 2.1 GHz (no Turbo), 15W (2C/GT2)
• Future 5
Supporting: Intel® VT, Intel® TXT, Intel® SSE4.2, Intel® HT Technology, Intel® 64 Architecture, Execute Disable Bit, Intel® Turbo
Boost Technology 2.0, Intel® AVX2, Intel® AES-NI, PCLMULQDQ Instruction, Intel® Device Protection Technology with Intel® Secure
Key, Intel® TSXNI
Note: Availability of features may vary between processor SKUs.
¾ L3 Cache: 4MB for Core™ i7, 3MB for Core™ i5 and Core™ i3, 2MB for Celeron®
th
Generation Intel® Celeron® processor
¾ Memory: Dual channel non-ECC 1600/1333 MHz DDR3L memory up to 16 GB in dual SODIMM socket
¾ BIOS: AMI EFI with CMOS backup in 8MB SPI BIOS with Intel® AMT 10.0 support (AMT supported on i7/i5 SKUs only)
2.2 Expansion Busses
¾ 4x PCI Express x1 (AB): Lanes 0/1/2/3
2
¾ LPC bus, SMBus (system), I
C (user)
2.3 Video
¾ Integrated on Processor: Intel® Generation 8 Graphics core architecture
¾ GPU Feature Support:
• 3 independent and simultaneous display combinations of DisplayPort/HDMI/LVDS monitors (eDP optional in place of LVDS)
• Encode/transcode HD content
• Playback of high definition content including Blu-ray Disc
• Playback of Blu-ray disc S3D content using HDMI (1.4a spec compliant with 3D)
• DirectX Video Acceleration (DXVA) support for accelerated video processing
• Full AVC/VC1/MPEG2 HW decode
• Advanced Scheduler 2.0, 1.0, XPDM support
• DirectX 11.1
• Multi Display Support: 3 independent displays
Note: Availability of features may vary between operating systems.
¾ Display Types
• Single/dual channel 18/24-bit LVDS via eDP-to-LVDS chip
(eDP available
• 2x Digital Display Ports
DDI1 supports DisplayPort/HDMI/DVI
DDI2 supports DisplayPort/HDMI/DVI
cExpress-BL Page 7
as BOM option in place of LVDS)
2.4 Audio
¾ Integrated: Intel® HD Audio integrated on SoC
¾ Codec: Realtek ALC886 on Express-BASE6 Reference Carrier Board
2.5 LAN
¾ Integrated: MAC integrated on SoC
¾ Intel PHY: Intel® Ethernet Controller i218LM
¾ Interface: 10/100/1000 GbE connection
2.6 Multi I/O and Storage
¾ I/O Hub: Integrated on SOC
¾ USB: 2x USB 3.0 ports (USB0,1) and 6x USB 2.0 ports (USB2,3,4,5,6,7)
¾ SATA: 4x SATA 6Gb/s ports
¾ GPIO: 4 GPO and 4 GPI
2.7 Serial I/O on Module
¾ Chipset: Nuvoton NCT5104D
¾ Ports: 2x UARTs Rx/Tx only
¾ Console Redirection: UART0 or UART1 selectable in BIOS
2.8 Trusted Platform Module (TPM)
¾ Chipset: AtmelAT97SC3204
¾ Type: TPM 1.2
2.9 SEMA Board Controller
¾ Type: ADLINK Smart Embedded Management Agent (SEMA)
¾ Functions:
• Voltage/Current monitoring
• Power sequence debug support
• AT/ATX mode control
• Logistics and forensic information
• Flat panel control
• General purpose I2C
• Failsafe BIOS (dual BIOS )
• Watchdog timer and fan control
2.10 Debug
¾ 40-pin flat cable connector to be used with DB-40 debug module
Supports: BIOS POST code LED, BMC access, SPI BIOS flashing, power testpoints, debug LEDs
¾ 60-pin XDP header for ICE debug of CPU/chipset
Page 8 cExpress-BL
2.11 Power Specifications
¾ Power Modes: AT and ATX mode (AT mode startup controlled by SEMA Board Controller)
¾ Standard Voltage Input: ATX = 12V±5% / 5Vsb ±5% or AT = 12V±5%
¾ Wide Voltage Input: ATX = 5~20 V / 5Vsb ±5% or AT = 5 ~20V
¾ Power Management: ACPI 4.0 compliant, Smart Battery support
¾ Power States: supports C1-C6, S0, S3, S4, S5 (Wake-on-USB S3/S4, WoL S3/S4/S5)
¾ ECO mode: supports deep S5 for 5Vsb power saving
2.12 Operating Temperatures
¾ Standard Operating Temperature: 0°C to +60°C (Wide Voltage Input)
¾ Extreme Rugged™ Operating Temperature (optional): -40°C to +85°C (Standard Voltage Input)
2.13 Environmental
¾ Humidity: 5-90% RH operating, non-condensing
5-95% RH storage (and operating with conformal coating).
¾ Shock and Vibration: IEC 60068-2-64 and IEC-60068-2-27
MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D
¾ HALT: Thermal Stress, Vibration Stress, Thermal Shock and Combined Test
2.14 Specification Compliance
¾ PICMG COM.0: Rev 2.1 Type 6, Compact size 95 x 95 mm
2.15 Operating Systems
¾ Standard Support: Windows 7/8.1u 32/64-bit, Linux 32/64-bit
¾ Extended Support (BSP): Windows Embedded Standard 7 (WES7), Windows Embedded 8 Standard (WE8S), Linux, VxWorks
cExpress-BL Page 9
2.16 Functional Diagram
Page 10 cExpress-BL
2.17 Mechanical Drawing
Top View
connectors on bottom side
Side View
All tolerances ± 0.05 mm
Other tolerances ± 0.2 mm
Dimensions: mm
cExpress-BL Page 11
3 Pinouts and Signal Descriptions
3.1 AB/CD Pin Definitions
The cExpress-BL is a Type 6 module supporting USB 3.0 upgrade signals and DDI channels on the CD connector
All pins in the COM Express specification are described, including those not supported on the cExpress-BL. Those not supported on the
cExpress-BL module are crossed out
Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
GND (FIXED)
GBE0_MDI3GBE0_MDI3+
GBE0_LINK100#
GBE0_LINK1000#
GBE0_MDI2GBE0_MDI2+
GBE0_LINK#
GBE0_MDI1GBE0_MDI1+
GND (FIXED)
GBE0_MDI0GBE0_MDI0+
GBE0_CTREF
SUS_S3#
SATA0_TX+
SATA0_TX-
SUS_S4#
SATA0_RX+
SATA0_RXGND (FIXED)
SATA2_TX+
SATA2_TX-
SUS_S5#
SATA2_RX+
SATA2_RX-
BATLOW#
(S)ATA_ACT#
AC/HDA_SYNC
AC/HDA_RST#
GND (FIXED)
AC/HDA_BITCLK
AC/HDA_SDOUT
BIOS_DIS0#
THRMTRIP#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
GND (FIXED)
GBE0_ACT#
LPC_FRAME#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ0#
LPC_DRQ1#
LPC_CLK
GND (FIXED)
PWRBTN#
SMB_CK
SMB_DAT
SMB_ALERT#
SATA1_TX+
SATA1_TX-
SUS_STAT#
SATA1_RX+
SATA1_RXGND (FIXED)
SATA3_TX+
SATA3_TX-
PWR_OK
SATA3_RX+
SATA3_RX-
WDT
AC/HDA_SDIN2
AC/HDA_SDIN1
AC/HDA_SDIN0
GND (FIXED)
SPKR
I2C_CK
I2C_DAT
THRM#
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
GND FIXED)
GND
USB_SSRX0USB_SSRX0+
GND
USB_SSRX1USB_SSRX1+
GND
USB_SSRX2USB_SSRX2+
GND (FIXED)
USB_SSRX3USB_SSRX3+
GND
DDI1_PAIR6+
DDI1_PAIR6RSVD
RSVD
PCIE_RX6+
PCIE_RX6GND (FIXED)
PCIE_RX7+
PCIE_RX7DDI1_HPD
DDI1_PAIR4+
DDI1_PAIR4RSVD
RSVD
DDI1_PAIR5+
DDI1_PAIR5GND (FIXED)
DDI2_CTRLCLK_AUX+
DDI2_CTRLDATA_AUXDDI2_DDC_AUX_SEL
RSVD
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
GND FIXED)
GND
USB_SSTX0USB_SSTX0+
GND
USB_SSTX1USB_SSTX1+
GND
USB_SSTX2USB_SSTX2+
GND (FIXED)
USB_SSTX3USB_SSTX3+
GND
DDI1_CTRLCLK_AUX+
DDI1_CTRLDATA_AUX
RSVD
RSVD
PCIE_TX6+
PCIE_TX6GND (FIXED)
PCIE_TX7+
PCIE_TX7RSVD
RSVD
DDI1_PAIR0+
DDI1_PAIR0RSVD
DDI1_PAIR1+
DDI1_PAIR1GND (FIXED)
DDI1_PAIR2+
DDI1_PAIR2-
DDI1_DDC_AUX_SEL
RSVD
Page 12 cExpress-BL
Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
USB6USB6+
USB_6_7_OC#
USB4USB4+
GND (FIXED)
USB2USB2+
USB_2_3_OC#
USB0USB0+
VCC_RTC
EXCD0_PERST#
EXCD0_CPPE#
LPC_SERIRQ
GND (FIXED)
PCIE_TX5+
PCIE_TX5-
GPI0
PCIE_TX4+
PCIE_TX4GND
PCIE_TX3+
PCIE_TX3GND (FIXED)
PCIE_TX2+
PCIE_TX2GPI1
PCIE_TX1+
PCIE_TX1GND
GPI2
PCIE_TX0+
PCIE_TX0GND (FIXED)
LVDS_A0+
LVDS_A0-
LVDS_A1+
(eDP_TX1+ )*
LVDS_A1-
(eDP_TX1- )*
LVDS_A2+
(eDP_TX0+ )*
LVDS_A2(eDP_TX0- )*
LVDS_VDD_EN
(DP_VDD_EN)*
LVDS_A3+
LVDS_A3-
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
USB7USB7+
USB_4_5_OC#
USB5USB5+
GND (FIXED)
USB3USB3+
USB_0_1_OC#
USB1USB1+
EXCD1_PERST#
EXCD1_CPPE#
SYS_RESET#
CB_RESET#
GND (FIXED)
PCIE_RX5+
PCIE_RX5-
GPO1
PCIE_RX4+
PCIE_RX4GPO2
PCIE_RX3+
PCIE_RX3GND (FIXED)
PCIE_RX2+
PCIE_RX2GPO3
PCIE_RX1+
PCIE_RX1-
WAKE0#
WAKE1#
PCIE_RX0+
PCIE_RX0GND (FIXED)
LVDS_B0+
LVDS_B0-
LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2LVDS_B3+
LVDS_B3LVDS_BKLT_EN
(eDP_BKLT_EN)*
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
C79
DDI3_CTRLCLK_AUX+
DDI3_CTRLDATA_AUXDDI3_DDC_AUX_SEL
DDI3_PAIR0+
DDI3_PAIR0GND (FIXED)
DDI3_PAIR1+
DDI3_PAIR1DDI3_HPD
RSVD
DDI3_PAIR2+
DDI3_PAIR2RSVD
DDI3_PAIR3+
DDI3_PAIR3GND (FIXED)
PEG_RX0+
PEG_RX0-
TYPE0#
PEG_RX1+
PEG_RX1-
TYPE1#
PEG_RX2+
PEG_RX2GND (FIXED)
PEG_RX3+
PEG_RX3RSVD
RSVD
PEG_RX4+
PEG_RX4RSVD
PEG_RX5+
PEG_RX5GND (FIXED)
PEG_RX6+
PEG_RX6-
GND
PEG_RX7+
PEG_RX7GND
RSVD
PEG_RX8+
PEG_RX8-
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
D64
D65
D66
D67
D68
D69
D70
D71
D72
D73
D74
D75
D76
D77
D78
D79
DDI1_PAIR3+
DDI1_PAIR3RSVD
DDI2_PAIR0+
DDI2_PAIR0GND (FIXED)
DDI2_PAIR1+
DDI2_PAIR1DDI2_HPD
RSVD
DDI2_PAIR2+
DDI2_PAIR2RSVD
DDI2_PAIR3+
DDI2_PAIR3GND (FIXED)
PEG_TX0+
PEG_TX0-
PEG_LANE_RV#
PEG_TX1+
PEG_TX1-
TYPE2#
PEG_TX2+
PEG_TX2GND (FIXED)
PEG_TX3+
PEG_TX3RSVD
RSVD
PEG_TX4+
PEG_TX4GND
PEG_TX5+
PEG_TX5GND (FIXED)
PEG_TX6+
PEG_TX6-
GND
PEG_TX7+
PEG_TX7GND
RSVD
PEG_TX8+
PEG_TX8-
cExpress-BL Page 13
Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A95
A96
A97
A98
A99
A100
A101
A102
A103
A104
A105
A106
A107
A108
A109
A110
GND (FIXED)
LVDS_A_CK+
LVDS_A_CK-
LVDS_I2C_CK
/eDP_AUX+ *
LVDS_I2C_DAT
/eDP_AUX- *
GPI3
RSVD
RSVD
/eDP_HPD *
PCIE0_CK_REF+
PCIE0_CK_REF-
GND (FIXED)
SPI_POWER
SPI_MISO
GPO0
SPI_CLK
SPI_MOSI
TPM_PP
TYPE10#
SER0_TX
SER0_RX
GND (FIXED)
SER1_TX
SER1_RX
LID#
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
B95
B96
B97
B98
B99
B100
B101
B102
B103
B104
B105
B106
B107
B108
B109
B110
GND (FIXED)
LVDS_B_CK+
LVDS_B_CKLVDS_BKLT_CTRL
/eDP_BKLT_CTRL *
VCC_5V_SBY
VCC_5V_SBY
VCC_5V_SBY
VCC_5V_SBY
BIOS_DIS1#
VGA_RED
GND (FIXED)
VGA_GRN
VGA_BLU
VGA_HSYNC
VGA_VSYNC
VGA_I2C_CK
VGA_I2C_DAT
SPI_CS#
RSVD
RSVD
GND (FIXED)
FAN_PWMOUT
FAN_TACHIN
SLEEP#
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)
C80
C81
C82
C83
C84
C85
C86
C87
C88
C89
C90
C91
C92
C93
C94
C95
C96
C97
C98
C99
C100
C101
C102
C103
C104
C105
C106
C107
C108
C109
C110
GND (FIXED)
PEG_RX9+
PEG_RX9RSVD
GND
PEG_RX10+
PEG_RX10GND
PEG_RX11+
PEG_RX11GND (FIXED)
PEG_RX12+
PEG_RX12GND
PEG_RX13+
PEG_RX13GND
RSVD
PEG_RX14+
PEG_RX14GND (FIXED)
PEG_RX15+
PEG_RX15GND
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)
D80
D81
D82
D83
D84
D85
D86
D87
D88
D89
D90
D91
D92
D93
D94
D95
D96
D97
D98
D99
D100
D101
D102
D103
D104
D105
D106
D107
D108
D109
D110
GND (FIXED)
PEG_TX9+
PEG_TX9RSVD
GND
PEG_TX10+
PEG_TX10GND
PEG_TX11+
PEG_TX11GND (FIXED)
PEG_TX12+
PEG_TX12GND
PEG_TX13+
PEG_TX13GND
RSVD
PEG_TX14+
PEG_TX14GND (FIXED)
PEG_TX15+
PEG_TX15GND
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)
*Note: eDP is available
as BOM option in place of LVDS.
Page 14 cExpress-BL
3.2 Signal Description Terminology
The following terms are used in the COM Express AB/CD Signal Descriptions below.
I Input to the Module
O Output from the Module
I/O Bi-directional input/output signal
OD Open drain output
I 3.3V Input 3.3V tolerant
I 5V Input 5V tolerant
O 3.3V Output 3.3V signal level
O 5V Output 5V signal level
I/O 3.3V Bi-directional signal 3.3V tolerant
I/O 5V Bi-directional signal 5V tolerant
I/O 3.3Vsb Input 3.3V tolerant active in standby state
P Power Input/Output
REF Reference voltage output that may be sourced from a module power plane.
PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected.
The signal is used to indicate the PICMG module type to the Carrier Board.
PU ADLINK implemented pull-up resistor on module
PD ADLINK implemented pull-down resistor on module
cExpress-BL Page 15
3.3 AB Signal Descriptions
3.3.1 Audio Signals
Signal Pin # Description I/O PU/PD Comment
AC_RST# /
HDA_RST#
AC_SYNC /
HDA_SYNC
AC_BITCLK /
HDA_BITCLK
AC _SDOUT /
HDA_SDOUT
AC _SDIN[2:0]
HDA_SDIN[2:0]
A30 Reset output to codec, active low. O 3.3VSB VSB because PCH uses suspend
power for RESET
A29 Sample-synchronization signal to the codec(s). O 3.3V
A32 Serial data clock generated by the external
codec(s).
A33 Serial TDM data output to the codec. O 3.3V
B28
B30
Serial TDM data inputs from up to 3 codecs. I/O 3.3VSB No AC/HAD_SDIN 2 support on
I/O 3.3V
this platform
3.3.2 Analog VGA
Signal Pin # Description I/O PU/PD Comment
VGA_RED B89 Red for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
VGA_GRN B91 Green for monitor
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
O Analog
O Analog
Not supported
Not supported
VGA_BLU B92 Blue for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
VGA_HSYNC B93 Horizontal sync output to VGA monitor O 3.3V Not supported
VGA_VSYNC B94 Vertical sync output to VGA monitor O 3.3V Not supported
VGA_I2C_CK B95 DDC clock line (I²C port dedicated to identify
VGA monitor capabilities)
VGA_I2C_DAT B96 DDC data line. I/O OD 3.3V Not supported
O Analog
I/O OD 3.3V Not supported
Not supported
Page 16 cExpress-BL
3.3.3 LVDS/eDP
Signal Pin # Description I/O PU/PD Comment
LVDS_A0+
LVDS_A0-
LVDS_A1+
LVDS_A1-
LVDS_A2+
LVDS_A2- -
LVDS_A3+
LVDS_A3-
LVDS_A_CK+
LVDS_A_CK-
A71
A72
A73
A74
A75
A76
A78
A79
A81
A82
LVDS Channel A differential pairs O LVDS
LVDS Channel A differential clock O LVDS
LVDS is default.
(through eDP to LVDS
bridge)
Note: eDP support is a
BOM option
LVDS_B0+
LVDS_B0-
LVDS_B1+
LVDS_B1-
LVDS_B2+
LVDS_B2-
LVDS_B3+
LVDS_B3-
LVDS_B_CK+
LVDS_B_CK-
B71
B72
B73
B74
B75
B76
B77
B78
B81
B82
LVDS Channel B differential pairs O LVDS
LVDS Channel B differential clock O LVDS
LVDS_VDD_EN A77 LVDS panel power enable O 3.3V
LVDS_BKLT_EN B79 LVDS panel backlight enable O 3.3V
LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3.3V PD 100K
Realtek ePD to LVDS
requirement
LVDS_I2C_CK A83 DDC lines used for flat panel detection and control. O 3.3V PU 2k2 3.3V
LVDS_I2C_DAT A84 DDC lines used for flat panel detection and control. I/O 3.3V PU 2k2 3.3V
eDP BOM Option Signal Descriptions
Signal Pin # Description I/O PU/PD Comment
eDP_TX2+
eDP_TX2-
eDP_TX1+
eDP_TX1-
eDP_TX0+
eDP_TX0--
eDP_TX3+
eDP_TX3--
A71
A72
A73
A74
A75
A76
A81
A82
eDP differential pairs O PCIE AC coupled off module
eDP_TX2 pair is not
supported on this
product
eDP differential pairs O PCIE AC coupled off module
eDP_TX3 pair is not
supported on this
product
eDP_VDD_EN A77 eDP power enable O 3.3V
eDP_BKLT_EN B79 eDP backlight enable O 3.3V
eDP_BKLT_CTRL B83 eDP backlight brightness control O 3.3V
eDP_AUX+ A83 eDP AUX+ I/O PCIE AC coupled off module
eDP_AUX- A84 eDP AUX- I/O PCIE AC coupled off module
eDP_HPD A87 Detection of Hot Plug / Unplug and notification of
I 3.3V
the link layer
cExpress-BL Page 17
3.3.4 Gigabit Ethernet
Gigabit Ethernet Pin # Description I/O PU/PD Comment
GBE0_MDI0+
GBE0_MDI0-
GBE0_MDI1+
GBE0_MDI1-
GBE0_MDI2+
GBE0_MDI2-
GBE0_MDI3+
GBE0_MDI3-
GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. O 3.3VSB PU 10k
GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. O 3.3VSB
GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low. O 3.3VSB
GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low. O 3.3VSB
GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics
A13
A12
A10
A9
A7
A6
A3
A2
Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs
0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes.
Some pairs are unused in some modes according to the following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/MDI[3]+/- B1_DD+/-
center tap. The reference voltage is determined by the requirements of the
Module PHY and may be as low as 0V and as high as 3.3V. The reference
voltage output shall be current limited on the Module. In the case in which
the reference is shorted to ground, the current shall be 250 mA or less.
I/O Analog Twisted pair
3.3VSB
GND min
3.3V max
No support on
3.3.5 Serial ATA
signals for
external
transformer.
this product
Signal Pin # Description I/O PU/PD Comment
SATA0_TX+
SATA0_TX-
SATA0_RX+
SATA0_RX-
SATA1_TX+
SATA1_TX-
SATA1_RX+
SATA1_RX-
SATA2_TX+
SATA2_TX-
SATA2_RX+
SATA2_RX-
SATA3_TX+
SATA3_TX-
SATA3_RX+
SATA3_RX-
(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity
A16
Serial ATA channel 0, Transmit Output
A17
differential pair.
A19
Serial ATA channel 0, Receive Input
A20
differential pair.
B16
Serial ATA channel 1, Transmit Output
B17
differential pair.
B19
Serial ATA channel 1, Receive Input
B20
differential pair.
A22
Serial ATA channel 2, Transmit Output
A23
differential pair.
A25
Serial ATA channel 2, Receive Input
A26
differential pair.
B22
Serial ATA channel 3, Transmit Output
B23
differential pair.
B25
Serial ATA channel 3, Receive Input
B26
differential pair.
indicator, active low.
O SATA AC coupled on Module
I SATA AC coupled on Module
O SATA AC coupled on Module
I SATA AC coupled on Module
O SATA AC coupled on Module
I SATA AC coupled on Module
O SATA AC coupled on Module
I SATA AC coupled on Module
O 3.3V
Page 18 cExpress-BL
3.3.6 PCI Express
Signal Pin # Description I/O PU/PD Comment
PCIE_TX0+
PCIE_TX0-
PCIE_RX0+
PCIE_RX0-
PCIE_TX1+
PCIE_TX1-
PCIE_RX1+
PCIE_RX1-
PCIE_TX2+
PCIE_TX2-
PCIE_RX2+
PCIE_RX2-
PCIE_TX3+
PCIE_TX3-
PCIE_RX3+
PCIE_RX3-
PCIE_TX4+
PCIE_TX4-
PCIE_RX4+
PCIE_RX4-
PCIE_TX5+
PCIE_TX5-
A68
A69
B68
B69
A64
A65
B64
B65
A61
A62
B61
B62
A58
A59
B58
B59
A55
A56
B55
B56
A52
A53
PCI Express channel 0, Transmit Output differential
pair.
PCI Express channel 0, Receive Input differential
pair.
PCI Express channel 1, Transmit Output differential
pair.
PCI Express channel 1, Receive Input differential
pair.
PCI Express channel 2, Transmit Output differential
pair.
PCI Express channel 2, Receive Input differential
pair.
PCI Express channel 3, Transmit Output differential
pair.
PCI Express channel 3, Receive Input differential
pair.
PCI Express channel 4, Transmit Output differential
pair.
PCI Express channel 4, Receive Input differential
pair.
PCI Express channel 5, Transmit Output differential
pair.
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE PCIe port 4 is
Connected to LAN
I PCIE PCIe port 4 is
Connected to LAN
O PCIE Not supported
PCIE_RX5+
PCIE_RX5-
PCIE_CLK_REF+
PCIE_CLK_REF-
B52
B53
A88
A89
PCI Express channel 5, Receive Input differential
pair.
PCI Express Reference Clock output for all PCI
Express and PCI Express Graphics Lanes.
I PCIE Not supported
O PCIE
3.3.7 Express Card
Signal Pin # Description I/O PU/PD Comment
EXCD0_CPPE#
EXCD1_CPPE#
EXCD0_PERST#
EXCD1_PERST#
A49
B48
A48
B47
PCI ExpressCard: PCI Express capable card request I 3.3V PU 10k 3.3V
PCI ExpressCard: reset O 3.3V
3.3.8 LPC Bus
Signal Pin # Description I/O PU/PD Comment
LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V
LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V
LPC_DRQ0#
LPC_DRQ1#
B8
B9
LPC serial DMA request I 3.3V
LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V PU 8k2 3.3V
LPC_CLK B10 LPC clock output - 33MHz nominal O 3.3V
cExpress-BL Page 19
3.3.9 USB
Signal Pin # Description I/O PU/PD Comment
USB0+
USB0-
USB1+
USB1-
USB2+
USB2-
USB3+
USB3-
USB4+
USB4-
USB5+
USB5-
USB6+
USB6-
USB7+
USB7-
A46
USB differential data pairs for Port 0 I/O 3.3VSB USB 1.1/ 2.0 compliant
A45
B46
USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant
B45
A43
USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant
A42
B43
USB differential data pairs for Port 2 I/O 3.3VSB USB 1.1/ 2.0 compliant
B42
A40
USB differential data pairs for Port 3 I/O 3.3VSB USB 1.1/ 2.0 compliant
A39
B40
USB differential data pairs for Port 4 I/O 3.3VSB USB 1.1/ 2.0 compliant
B39
A37
USB differential data pairs for Port 5 I/O 3.3VSB USB 1.1/ 2.0 compliant
A36
B37
USB differential data pairs for Port 6 I/O 3.3VSB USB 1.1/ 2.0 compliant
B37
USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
I 3.3VSB PU 10k 3.3VSB Do not pull high on
carrier
USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low. .
USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
I 3.3VSB PU 10k 3.3VSB Do not pull high on
carrier
I 3.3VSB PU 10k 3.3VSB Do not pull high on
carrier
I 3.3VSB PU 10k 3.3VSB Do not pull high on
carrier
Page 20 cExpress-BL
3.3.10 USB Root Segmentation
3.3.11 SPI (BIOS only)
Signal Pin # Description I/O PU/PD Comment
SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB
SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB
SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_POWER A91 Power supply for Carrier Board SPI – sourced from
Module – nominally 3.3V.
The Module shall provide a minimum of 100mA on
SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER.
SPI_POWER shall only be used to power SPI devices
on the Carrier
BIOS_DIS0# A34 Selection strap to determine the BIOS boot device. I PU 10K 3.3V Carrier shall pull to
O P 3.3VSB
GND or leave noconnect.
BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. I PU 10K 3.3V Carrier shall pull to
GND or leave noconnect
cExpress-BL Page 21
3.3.12 Miscellaneous
Signal Pin # Description I/O PU/PD Comment
SPKR B32 Output for audio enunciator, the “speaker” in PC-AT
systems
WDT B27 Output indicating that a watchdog time-out event has
occurred.
THRM# B35 Input from off-module temp sensor indicating an over-
temp situation.
THERMTRIP# A35 Active low output indicating that the CPU has entered
thermal shutdown.
FAN_PWMOUT B101 Fan speed control. Uses the Pulse Width Modulation
(PWM) technique to control the fan’s RPM.
FAN_TACHIN11 B102 Fan tachometer input for a fan with a two pulse output. I OD 3.3V PU 10k 3.3V
TPM_PP11 C83 Trusted Platform Module (TPM) Physical Presence pin.
Active high. TPM chip has an internal pull down. This
signal is used to indicate Physical Presence to the
TPM.
O 3.3V
O 3.3V
I 3.3V
O 3.3V PU 330 ohm 3.3V
O OD 3.3V
I 3.3V
PD 10k 3.3V
PD is only placed
when TPM is
installed on module
3.3.13 SMBus
Signal Pin # Description I/O PU/PD Comment
SMB_CK B13 System Management Bus bidirectional clock line.
Power sourced through 5V standby rail and main power
rails.
I/O OD 3.3VSB PU 2k2 3.3VSB
SMB_DAT# B14 System Management Bus bidirectional data line. Power
sourced through 5V standby rail and main power rails.
SMB_ALERT# B15 System Management Bus Alert – active low input can
be used to generate an SMI# (System Management
Interrupt) or to wake the system. Power sourced
through 5V standby rail and main power rails.
I/O OD 3.3VSB PU 2k2 3.3VSB
I 3.3VSB PU 10k 3.3VSB
3.3.14 I2C Bus
Signal Pin # Description I/O PU/PD Comment
I2C_CK B33 General purpose I²C port clock output/input I/O OD 3.3VSB PU 2k2 3.3VSB
I2C_DAT B34 General purpose I²C port data I/O line I/O OD 3.3VSB PU 2k2 3.3VSB
3.3.15 General Purpose I/O (GPIO)
Signal Pin # Description I/O PU/PD Comment
GPO[0] A93 General purpose output pins. O 3.3V PU 10K 3.3V After hardware
RESET output low
GPO[1] B54 General purpose output pins. O 3.3V PU 10K 3.3V After hardware
RESET output low
GPO[2] B57 General purpose output pins. O 3.3V PU 10K 3.3V After hardware
RESET output low
Page 22 cExpress-BL
Signal Pin # Description I/O PU/PD Comment
GPO[3] B63 General purpose output pins. O 3.3V PU 10K 3.3V After hardware
RESET output low
GPI[0] A54 General purpose input pins.
I 3.3V PU 10K 3.3V
Pulled high internally on the module.
GPI[1] A63 General purpose input pins.
I 3.3V PU 10K 3.3V
Pulled high internally on the module.
GPI[2] A67 General purpose input pins.
I 3.3V PU 10K 3.3V
Pulled high internally on the module.
GPI[3] A85 General purpose input pins.
I 3.3V PU 10K 3.3V
Pulled high internally on the module.
3.3.16 Serial Interface Signals
Signal Pin # Description I/O PU/PD Comment
SER0_TX A98 General purpose serial port transmitter (TTL level output) O CMOS Power rail tolerance 5V/12V
SER0_RX A99 General purpose serial port receiver (TTL level input) I CMOS Power rail tolerance 5V/12V
SER1_TX A101 General purpose serial port transmitter (TTL level output) O CMOS Power rail tolerance 5V/12V
SER1_RX A102 General purpose serial port receiver (TTL level input) I CMOS Power rail tolerance 5V/12V
3.3.17 Power and System Management
Signal Pin # Description I/O PU/PD Comment
PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge. I 3.3VSB PU 10k
3.3VSB
SYS_RESET# B49 Reset button input. Active low request for module to reset and reboot. May
be falling edge sensitive. For situations when SYS_RESET# is not able to
I 3.3VSB PU 10k
3.3VSB
reestablish control of the system, PWR_OK or a power cycle may be used.
CB_RESET# B50 Reset output from module to Carrier Board. Active low. Issued by module
O 3.3VSB
chipset and may result from a low SYS_RESET# input, a low PWR_OK
input, a VCC_12V power input that falls below the minimum specification, a
watchdog timeout, or may be initiated by the module software.
PWR_OK B24 Power OK from main power supply. A high value indicates that the power is
good. This signal can be used to hold off Module startup to allow carrier
I 3.3V PU 100k
3.3VSB
based FPGAs or other configurable devices time to be programmed.
SUS_STAT# B18 Indicates imminent suspend operation; used to notify LPC devices. O 3.3VSB
SUS_S3# A15 Indicates system is in Suspend to RAM state. Active-low output. An inverted
O 3.3VSB
copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be
used to enable the non-standby power on a typical ATX power supply.
SUS_S4# A18 Indicates system is in Suspend to Disk state. Active low output. O 3.3VSB
SUS_S5# A24 Indicates system is in Soft Off state. O 3.3VSB
WAKE0# B66 PCI Express wake up signal. I 3.3VSB PU 10k
3.3VSB
Not
supported
connected
to
WAKE1#
WAKE1# B67 General purpose wake up signal. May be used to implement wake-up on
PS/2 keyboard or mouse activity.
I 3.3VSB PU 10k
3.3VSB
cExpress-BL Page 23
Signal Pin # Description I/O PU/PD Comment
BATLOW# A27 Battery low input. This signal may be driven low by external circuitry to
signal that the system battery is low, or may be used to signal some other
external power-management event.
LID# LID button. Low active signal used by the ACPI operating system for a LID
switch.
SLEEP# Sleep button. Low active signal used by the ACPI operating system to bring
the system to sleep state or to wake it up again.
I 3.3VSB PU 10k
3.3VSB
I OD
3.3VSB
I OD
3.3VSB
PU 10k
3.3VSB
PU 10K
3.3VSB
3.3.18 Power and Ground
Signal Pin # Description I/O PU/PD Comment
VCC_12V A104-A109
B104-B109
VCC_5V_SBY B84-B87 Standby power input: +5.0V nominal. If VCC5_SBY is used, all
VCC_RTC A47 Real-time clock circuit-power input. Nominally +3.0V. P
GND A1, A11, A21, A31,
A41, A51, A57, A66,
A80, A90, A96,
A100, A110, B1,
B11, B21 ,B31, B41,
B51, B60, B70, B80,
B90, B100, B110
Primary power input: +12V nominal (5 ~ 20V wide input).
All available VCC_12V pins on the connector(s) shall be used.
available VCC_5V_SBY pins on the connector(s) shall be used.
Only used for standby and suspend functions. May be left
unconnected if these functions are not used in the system design.
Ground - DC power and signal and AC signal return path. P
P 5~20 V
P 5Vsb ±5%
Emulated
on GPIO
(BIOS)
Emulated
on GPIO
(BIOS)
Page 24 cExpress-BL
3.4 CD Signal Descriptions
3.4.1 USB 3.0 extension
Signal Pin Description I/O PU/PD Comment
USB_SSRX0-
USB_SSRX0+
USB_SSTX0-
USB_SSTX0+
USB_SSRX1-
USB_SSRX1+
USB_SSTX1-
USB_SSTX1+
USB_SSRX2-
USB_SSRX2+
USB_SSTX2-
USB_SSTX2+
USB_SSRX3-
USB_SSRX3+
USB_SSTX3-
USB_SSTX3+
C3
C4
D3
D4
C6
C7
D6
D7
C9
C10
D9
D10
C12
C13
D12
D13
Additional Receive signal differential pairs for the
SuperSpeed USB data path on USB0
Additional Transmit signal differential pairs for the
SuperSpeed USB data path on USB0
Additional Receive signal differential pairs for the
SuperSpeed USB data path on USB1
Additional Transmit signal differential pairs for the
SuperSpeed USB data path on USB1
Additional Receive signal differential pairs for the
SuperSpeed USB data path on USB2
Additional Transmit signal differential pairs for the
SuperSpeed USB data path on USB2
Additional Receive signal differential pairs for the
SuperSpeed USB data path on USB3
Additional Transmit signal differential pairs for the
SuperSpeed USB data path on USB3
I PCIE
O PCIE AC coupled on Module
I PCIE
O PCIE AC coupled on Module
I PCIE Not supported
O PCIE Not supported
I PCIE Not supported
O PCIE Not supported
3.4.2 PCI Express x1
Signal Pin # Description I/O PU/PD Comment
PCIE_TX6+
PCIE_TX6-
PCIE_RX6+
PCIE_RX6-
PCIE_TX7+
PCIE_TX7-
PCIE_RX7+
PCIE_RX7-
D19
D20
C19
C20
D22
D23
C22
C23
PCI Express channel 6, Transmit Output differential pair. O PCIE
PCI Express channel 6, Receive Input differential pair. I PCIE
PCI Express channel 7, Transmit Output differential pair. O PCIE
PCI Express channel 7, Receive Input differential pair. I PCIE
Not supported
Not supported
Not supported
Not supported
cExpress-BL Page 25
3.4.3 DDI Channels
DDI 1
Signal Pin Description I/O PU/PD Comment
DDI1_PAIR0+
DDI1_PAIR0DDI1_PAIR1+
DDI1_PAIR1DDI1_PAIR2+
DDI1_PAIR2DDI1_PAIR3+
DDI1_PAIR3DDI1_PAIR4+
DDI1_PAIR4DDI1_PAIR5+
DDI1_PAIR5DDI1_PAIR6+
DDI1_PAIR6-
DDI1_HPD C24 Digital Display Interface Hot-Plug Detect I PCIE
DDI1_DDC_AUX_SEL D34 Selects the function of DDI1_CTRLCLK_AUX+
D26
D27
D29
D30
D32
D33
D36
D37
C25
C26
C29
C30
C15
C16
Digital Display Interface1 differential pairs O PCIE
IF DDI1_DDC_AUX_SEL is floating I/O PCIe DP1_AUX+ DDI1_CTRLCLK_AUX+ D15
IF DDI1_DDC_AUX_SEL pulled high I/O OD 3.3V HDMI1_CTRLCLK
IF DDI1_DDC_AUX_SEL is floating I/O PCIe DP1_AUX+ DDI1_CTRLCLK_AUX- D16
IF DDI1_DDC_AUX_SEL pulled high I/O OD 3.3V HDMI1_CTRLDATA
I/O OD 3.3V PD 1M
and DDI1_CTRLDATA_AUX-. This pin shall
have a 1M pull-down to logic ground on the
Module. If this input is floating the AUX pair is
used for the DP AUX+/- signals. If pulled-high
the AUX pair contains the CRTLCLK and
CTRLDATA signals.
Pair 4 to Pair 6
Not supported
Page 26 cExpress-BL
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