Manual Rev.: 2.00
Revision Date: November 22, 2012
Part No: 50-1G019-1000
Advance Technologies; Automate the World.
Revision History
RevisionRelease DateDescription of Change(s)
2.002012/11/22Initial Release
aTCA-6155
Preface
Copyright 2012 ADLINK Technology Inc.
This document contains proprietary infor mation protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufa cturer.
In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global
environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE)
directive. Environmental protection is a top priority for ADLINK.
We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little
impact on the environment as possible. When products are at their
end of life, our customers are encouraged to dispose of them in
accordance with the product disposal and/or recovery programs
prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks
of their respective companies.
Preface iii
Using this Manual
Audience and Scope
The aTCA-6155 User’s Manual is intended for hardware
technicians and systems operators with knowledge of installing,
configuring and operating ATCA systems.
Manual Organization
This manual is organized as follows:
Chapter 1, Introduction: Introduces the aTCA-6155, its features,
mation, power consumption, and board layout drawings.
Chapter 3, Functional Description: Describes the aTCA-6155’s
functional components and board interfaces.
Chapter 4, Hardware Platform Management: Describes the
hardware platform management system, including IPMI sensors,
commands, and firmware upgrade procedure.
Chapter 5, Getting Started: Describes the installation of components to the aTCA-6155.
Chapter 6, Driver Installation: Provides information on how to
install the aTCA-6155 device drivers.
Chapter 7, Watchdog Timer: Describes the watchdog functionality of the aTCA-6155.
Chapter 8, BIOS Setup: Describes basic navigation for the
AMIBIOS®8 BIOS setup utility.
Important Safety Instructions: Presents safety instructions all
users must follow for the proper setup, installation and usage of
equipment and/or software.
Getting Service: Contact information for ADLINK’s worldwide
offices.
ivPreface
aTCA-6155
Conventions
Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.
Additional information, aids, and tips that help users perform
tasks.
NOTE:
NOTE:
Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to com-
CAUTION:
WARNING:
plete a task.
Information to prevent serious physical injury, component
damage, data loss, and/or program corruption when trying to
complete a specific task.
The aTCA-6155 is a highly integrated multi-core dual-processor
AdvancedTCA processor blade supporting six sockets for
DDR3-1066 VLP RDIMM up to 48GB maximum system mem ory
capacity. IO features include two 10Gigabit Ethernet ports (XAUI,
1000BASE-KX4) compliant with PICMG 3.1 option 1/9, four Gigabit Ethernet 10/100/1000BASE-T ports to the face plate and
AdvancedTCA Base Interface channels. More detailed features
are outlined below and a functional block diagram is shown in the
next section.
X Two Six-Cor e Intel® Xeon® Processor L5638 or Quad -Core
Intel® Xeon® Processor L5618
X Server-class Intel® 5520/ICH10R chipset
X DDR3-1066 JEDEC standard VLP RDIMM (REG/ECC),
up to 48GB
X Onboard 4GB bootable USB interface NAND flash
X Three Intel® 82576EB PCI-Express Gigabit Ethernet con-
trollers
X Intel® 82599EB PCI-Express 10Gigabit Ethernet (XAUI)
controller
X Dual PICMG 3.1 option 1/9 Fabric Interface channels
X Modular Fabric riser card for other PICMG Fabric Interface
protocols
X Failover system BIOS
X Analog UXGA high color graphics
aTCA-6155
Introduction 1
1.2Block Diagram
DDR3Ͳ1066 RDIMM
DDR3Ͳ1066 RDIMM
DDR3Ͳ1066 RDIMM
MidͲSize
AMC
SAS 1/2/3 to RTM
F
R
O
N
T
P
A
N
E
L
RGB
USB1/2/3
COM1
SAS 0
To RTM
RTM
AMC.2 E2
AMC.2 T4
SAS1064E
PCI 32bit/33Mhz
ATI
ES1000
2.5" HDD
4GB NAND Flash
SATA x4,
USB5/6/7/8
NehalemͲEP
(5638/5618)
PCIͲE x4
PCIͲE x4
PCIͲE x4
Intel
CPU
QPIQPI
SATA
USB4
USB Header
USB Header
Intel
TylersburgͲ36D
(5520)
IOH
Intel
ICH10R
USB9
USB10
Intel
NehalemͲEP
(5638/5618)
CPU
PCIͲE x4
PCIͲE x8
PCIͲE x4
LPC
To RTM
Static
Switch
AMC.2 E2
AMC.2 T4
AMC.2 T4
Copper SerDes
Intel
82576EB
Copper SerDes
GbE 1/2 to Front Panel
BIOS BIOS
TPM
LPC
Super
I/O
COM2
COM3
COM4
DDR3Ͳ1066 RDIMM
DDR3Ͳ1066 RDIMM
DDR3Ͳ1066 RDIMM
SAS x3, SATA x4, USB5/6/7/8,
COM3, PCIͲE x4, SerDes x2
Intel
82576EB
Copper
SerDes
C
Port0
H
1
Port1
/
FRC
C
Port2
H
Port3
2
Intel
82576EB
UCH 1/2 SerDes
BCH 1/2
IPMC
BMRͲH8S
IPMB 0/1
RTM
Telecom Clock
FCH1/2
Z
O
N
E
3
Z
O
N
E
2
Z
O
N
E
1
Figure 1-1: aTCA-6155 Functional Block Diagram
2Introduction
aTCA-6155
1.3Package Contents
Before opening the product box, please check the shipping carton
for any damage. If the shipping carton and contents are damaged,
notify the dealer for a replacement. Retain the shipping carton and
packing material for inspection by the dealer. Obtain authorization
before returning any product to ADLINK.
Check that the following items are included in the package. If there
are any missing items, contact your dealer:
X aTCA-6155 AdvancedTCA processor blade (CPU, RAM
specifications will differ depending on options selected)
X RJ-45 to DB9 cable
This product must be protected from static discharge and physical shock. Never remove any of the components except at a
CAUTION:
static-free workstation. Use the anti-static bag shipped with the
product when putting the board on a surface. Wear an anti-static
wrist strap properly grounded on one of the system's ESD ground
jacks when installing or servicing system components.
The following shows the LED in the front panel which included the
Hot-swap LED, User LED, Media LED, and OOS LED.
Hot-swap LED
Hot-swap LED
(Blue)
OffM0FRU not installed
OnM1FRU inactive
Long blinkM2FRU activation request
OffM3FRU activation in process
OffM4FRU active
Short blinkM5FRU deactivation reque st
Short blinkM6FRU deactivation in process
FRU State numberFRU State Name
10Specifications
Out of Service LED
OOS LED (Red)StateRemark
BlinkDuring BIOS POSTFRU State M4
OffBIOS POST OKFRU State M4
OnAfter OS shutdownFRU State M1
Media LED
Media LED (Green)StateRemark
BlinkAccessing Disk I/O
OffDisk I/O idle
User LED
User LED (Amber)StateRemark
This LED is reserved for
OnDefault On
Base Fabric Channel LED
BASE Channel and Fabric Channel LED
Fabric 2 Speed/Link
1Gbps – OFF
10Gbps – ON (Amber)
Fabric 2 ACT (Amber)
Blink when accessing
Ethernet I/O
Fabric 1 Speed/Link
1Gbps - OFF
10Gbps – ON (Amber)
Fabric 1 ACT (Amber)
Blink when accessing
Ethernet I/O
customer applications and
can be controlled via GPIO.
BCH2 Speed/Link
100 Mbps: Green
1Gbps: Amber
BCH2 ACT(Amber)
Blink when accessing
Ethernet I/O
BCH1 Speed/Link
100 Mbps: Green
1Gbps: Amber
BCH1 ACT (Amber)
Blink when accessing
Ethernet I/O
aTCA-6155
Specifications 11
GbE LED
LED2: Speed and Link
RJ-45
1Gbps: Amber,
100Mbps: Green
LED1: ACT
Blinking when accessing I/O
Color: Amber
2.8Compliance
The aTCA-6155 conforms to the following specifications:
X PICMG 3.0 R2.0 ECN0002 AdvancedTCA
X PICMG 3.1 Ethernet over AdvancedTCA option 1 and 9
X AMC.0 Advanced Mezzanine Card R2.0 Midsize
X AMC.1 PCI Express R1.0
X AMC.2 E2 / Type 4
X AMC.3 Storage R1.0
The Intel Xeon® processor 5600 series is the first generation
dual-processor server/workstation solution to implement key new
technologies:
X Integrated Memory controller
X Point-to-point link interface based on Int el® QuickPath
Interconnect (Intel® QPI)
The processor is optimized for performance with the power efficiencies of a low-power micro-architecture to enable smaller, quieter systems.
The Intel® Xeon processors L5638 and L5618 are multi-core processors based on 32 nm process technology. Processor features
include two Intel® QPI point-to-point links with 5.86GT/s, 12MB of
shared cache, and an integrated memory controller. The processors support all the existing Streaming SIMD Extensions 2 (SSE2),
Streaming SIMD Extensions 3 (SSE3) and Streaming SIMD
Extensions 4 (SEE4). Also supported are: Execute Disable Bit,
Intel® 64 Technology, Enhanced Intel® SpeedStep Technology,
Intel® Virtualization Technology (Intel® VT), and Intel®
Hyper-Threading Technology.
aTCA-6155
The Intel® Xeon® Processor L5638 has a max. TDP of 60 W and
the Intel® Xeon® Processor L5618 has a max. TDP of 40 W. Both
processors have an elevated case temperature specification. The
elevated case temperatures are intended to meet the short-term
thermal profile requirements of NEBS Level 3. These 2-socket
processors are ideal for thermally constrained form factors in
embedded servers, communications and storage markets.
Functional Description 13
Supported Processors, Maximum Power Dissip ation
The following tables describe the processors supported on the
aTCA-6155 and their maximum power dissipation.
Intel® L5638Intel® L5618
L2 cache12 MB12 MB
Clock2.00 GHz1.87 GHz
QPI5.86 GT/s5.86 GT/s
Max. Power60 W40 W
Memory
The aTCA-6155 supports DDR3-1066 RDIMM in six sockets
(3 per processor) up to 48GBytes. The available COTS
DDR3-1066 RDIMM densities are 1 GB, 2GB, 4GB and 8GB.
Memory configuration changes can only be performed at the
factory. Failure to comply with the above may result in damage
NOTE:
NOTE:
to your board or improper operation.
14Functional Description
aTCA-6155
Chipset
Intel® 5520/ICH10R Chipset Overview
The Intel® 5520 Chipset I/O Hub (IOH) provides a connection
point between various I/O components and Intel® QuickPath In terconnect (Intel® QPI) based processors. The Intel® 5520 Chipset
is combined with Intel® Xeon® Processor 5500 in their respectiv e
two socket platforms. The Intel® Xeon® 5500 Platform consists of
the Intel Xeon Processor 5500 Series, the Intel 5520 Chipset I/O
Hub (IOH), the I/O Controller Hub (Intel® ICH10), and the I/O subsystem. The processor includes an integrated Memory Controller
(IMC) that resides within the proc essor package. This platform is
the first single processing platform that introduces the Intel QuickPath Interconnect. Intel QuickPath Interconnect is Intel’s next generation point-to-point system interconnect interface and replaces
the Front Side Bus.
The term IOH refers to the Intel 5520 Chipset I/O Hub (IOH)
and ICH10R refers to the Intel® 82801JIR ICH10R I/O
NOTE:
NOTE:
The IOH provides the interface between the processor Intel QuickPath Interconnect and industry-standard PCI Express components. The two Intel QuickPath Interconnect interfaces are
full-width links (20 lanes in each direction). The two x16 PCI
Express Gen2 ports are also configurable as x8 and x 4 links com pliant to the PCI Express Base Specification, Revision 2.0. The
single x4 PCI Express Gen2 port can bifurcate into two independent x2 interfaces.In addition, the legacy IOH supports a x4 ESI
link interface for the legacy bridge. The IOH supports the following
features and technologies:
Controller Hub 10 components.
X Intel® QuickPath Interconnect profile
X Interface to CPU or other IOH (limited configurations) PCI
Express Gen2
X Intel® I/O Accelerated Technology (In tel® I/OAT) and Intel®
Quick Data Technology (updated DMA engine with virtualization enhancements)
X Integrated Intel® Management Engine (Intel® ME)
Functional Description 15
ATI ES1000 Graphics Controller
The aTCA-6155 provides an analog VGA port on the front panel
powered by an AMD ES1000 2D graphics controller with the following features:
X 32-bit PCI bus (Rev 2.2), 3.3 V with bus mastering support
X Support for SPI Serial and Flash Memory video BIOS
X One CRT controller capable of supporting two identical
simultaneous display paths
X Dual integrated DACs for CRT display support
X Support for external TMDS transmitter via 24-bit digital out-
put to drive most popular TMDS transmitters up to 165MHz
frequency
X Independent DDC lines for both DACs and TMDS connec-
tions; also full AppleSense support on DAC connection
X Static and dynamic Power Management support (APM as
well as ACPI) with full VESA DPMS and Energy Star com-
pliance
X Comprehensive testability including full internal scan, mem-
ory BIST, I/O xor tree and Iddq
X Full ACPI 1.0b, OnNow, and IAPC (Instantly Available PC)
power management, including PCI power management reg-
isters
X Bi-endian support for compliance on a variety of processor
platforms
X Bus mastering of 2D display lists
X Triple 10-bit palette DAC supports pixel rates to 350MHz
X DDC1 and DDC2 for plug and play monitors
X Flexible memory support:
Z DDR1 and DDR2 SDRAM and SGRAM
Z 16-bit interface
Z 8MB to 256MB
X Up to 1GB/s bandwidth.
X Single chip solution in 0.13 micron process, 1.2V CMOS
technology in a BGA package
16Functional Description
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