ADLINK ACL-8112 User Manual

Enhanced Multi-Function

Data Acquisition Card

NuDAQ®

ACL-8112 Series

User’s Manual

Recycled Paper

©Copyright 2004 ADLINK TECHNOLOGY INC.

All Rights Reserved.

Manual Rev. 3.70: August 02, 2004

Part No.: 50-11012-202

The information in this document is subject to change without prior notice in
order to improve reliability, design, and function and does not represent a
commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special,
incidental, or consequential damages arising out of the use or inability to use
the product or documentation, even if advised of the possibility of such
damages.

This document contains proprietary information protected by copyright. All
rights are reserved. No part of this manual may be reproduced by any
mechanical, electronic, or other means in any form without prior written
permission of the manufacturer.

Trademarks

NuDAQ and ACL-8112 are registered trademarks of ADLINK TECHNOLOGY
INC.. Other product names mentioned herein are used for identification
purposes only and may be trademarks and/or registered trademarks of their
respective companies.

Getting Service from ADLINK

Customer Satisfaction is top priority for ADLINK TECHNOLOGY INC. If you
need any help or service, please contact us.

ADLINK TECHNOLOGY INC.

Web Site http://www.adlinktech.com

Sales & Service [e-mail]

TEL [phone] FAX [phone]

Address 9F, No. 166, Jian Yi Road, Chungho City, Taipei, 235 Taiwan

Please email or FAX your detailed information for prompt, satisfactory, and
consistent service.

Detailed Company Information

Company/Organization

Contact Person

E-mail Address

Address

Country

TEL FAX

Web Site

Questions

Product Model

OS:
Computer Brand:
M/B: CPU:

Environment

Detail Description

Chipset: BIOS:
Video Card:
NIC:
Other:

Suggestions for ADLINK

Table of Contents

Chapter 1 Introduction...................................................................... 1

1.1 Features...............................................................................................3

1.2 Applications..........................................................................................4

1.3 Specifications .......................................................................................4

1.4 Software Support .................................................................................8

Chapter 2 Installation........................................................................ 9

2.1 What You Have ....................................................................................9

2.2 Unpacking ..........................................................................................10

2.3 ACL-8112's Layout.............................................................................11

2.4 Jumper and DIP Switch Description...................................................13

2.5 Base Address Setting.........................................................................13

2.6 Analog Input Channel Configuration ..................................................15

2.7 DMA Channel Setting.........................................................................16

2.8 Internal/External Trigger Setting.........................................................17

2.9 Clock Source Setting..........................................................................18

2.10 IRQ Level Setting ...............................................................................18

2.11 D/A Reference Voltage Setting ..........................................................19

2.12 A/D Input Range Setting ....................................................................20

Chapter 3 Signal Connections ....................................................... 21

3.1 Connectors Pin Assignment ...............................................................21

3.2 Analog Input Signal Connection .........................................................24

3.3 Analog Output Signal Connection ......................................................26

3.4 Digital I/O Connection ........................................................................26

3.5 Timer / Counter Connection ...............................................................27

3.6 Daughter Board Connection...............................................................28

Chapter 4 Registers.........................................................................29

4.1 I/O Port Address.................................................................................30

4.2 A/D Data Registers ............................................................................31

4.3 A/D Channel Multiplexer Register ......................................................31

4.4 A/D Range Control Register...............................................................33

4.5 A/D Operation Mode Control Register................................................35

4.6 Interrupt Status Register ....................................................................36

4.7 Software Trigger Register ..................................................................36

4.8 Digital I/O register ..............................................................................37

4.9 D/A Output Register ...........................................................................38

4.10 Internal Timer/Counter Register .........................................................39

Table of Contents • i

Chapter 5 Operation Theory...........................................................41

5.1 A/D Conversion ..................................................................................41

5.2 D/A Conversion ..................................................................................44

5.3 Digital Input and Output .....................................................................44

5.4 Timer/Counter Operation ...................................................................45

Chapter 6 Calibration & Utilities ....................................................49

6.1 What you need...................................................................................49

6.2 VR Assignment ..................................................................................50

6.3 D/A Adjustment ..................................................................................50

6.4 A/D Programmable Gain Amplifier adjustments.................................51

6.5 A/D Adjustment ..................................................................................51

Chapter 7 C Language Library ....................................................... 53

7.1 _8112_Initial.......................................................................................54

7.2 _8112_Switch_Card_No ....................................................................56

7.3 _8112_DI ...........................................................................................57

7.4 _8112_DI _Channel ...........................................................................58

7.5 _8112_DO..........................................................................................59

7.6 _8112_DA ..........................................................................................60

7.7 _8112_AD_Input_Mode .....................................................................61

7.8 _8112_AD_Set_Channel ...................................................................63

7.9 _8112_AD_Set_Range ......................................................................64

7.10 _8112_AD_Set_Mode........................................................................67

7.11 _8112_AD_Soft_Trig..........................................................................69

7.12 _8112_AD_Aquire..............................................................................70

7.13 _8112_CLR_IRQ................................................................................71

7.14 _8112_AD_DMA_Start.......................................................................72

7.15 _8112_AD_DMA_Status ....................................................................74

7.16 _8112_AD_DMA_Stop.......................................................................75

7.17 _8112_AD_INT_Start.........................................................................76

7.18 _8112_AD_INT_Status ......................................................................77

7.19 _8112_AD_INT_Stop .........................................................................78

7.20 _8112_AD_Timer ...............................................................................79

7.21 _8112_TIMER_Start ..........................................................................80

7.22 _8112_TIMER_Read .........................................................................81

7.23 _8112_TIMER_Stop...........................................................................81

Appendix A Demo Programs..........................................................83

Warranty Policy .....................................Error! Bookmark not defined.

ii • Table of Contents

How to Use This Guide

This manual is designed to help you use the ACL-8112. The manual
describes how to modify various settings on the ACL-8112 card to meet your
requirements. It is divided into seven chapters:

Chapter 1

Gives an overview of the product features, applications, and

Chapter 2

Describes how to install the ACL-8112. The layout of the ACL-

Chapter 3

Describes the connectors' pin assignment and how to connect

Chapter 4

Describes the details of register format and structure of the

Chapter 5

Describes how to operate the ACL-8112. The A/D, D/A, DIO

Chapter 6

Describes how to calibrate the ACL-8112 for accurate

Chapter 7

Describes how to program the ACL-8112 by using the C

Appendix A

Introduction

specifications.

Installation

8112 is shown, the switch setting for base address, and jumper
setting for analog input channel configuration, reference
voltage setting, trigger source, interrupt level and DMA channel
are specified.

Signal Connection

the outside signal and devices with the ACL-8112.

Registers

ACL-8112, this information is very important for programmers
who want to control the hardware by low-level programming.

Operation Theory

and timer/counter functions are introduced. Also, some
programming concepts are specified.

Calibration & Utility

measurement.

C Language Library

language library in DOS environment.

Demo Program

Describes some demonstration programs.

How to Use This Guide ● iii

1

Introduction

The ACL-8112 is a high performance, high speed multi-function data
acquisition card for IBM PC or compatible computers.

The ACL-8112 series is designed to combine all data acquisition functions,
such as A/D, D/A, DIO and timer/counter into a single board. The high-end
specifications of the card makes it ideal for a wide range of applications
requiring high speed. Figure 1.1 shows the block diagram of ACL-8112.

The ACL-8112 Series consists of three models, the ACL-8112HG, ACL­8112DG and ACL-8112PG. The ACL-8112HG provides special high-gain
programmable instrument amplifier for low level input applications, such as
measurement of thermo-coupling signals. The ACL-8112DG provides high
speed sampling rates ( up to 100 KHz) at all gains ( x1, x2, x4, and x8) and
the ACL-8112PG provides 16 single-ended inputs with sampling up to 100
KHz with 5 levels of gain (x1, x2, x4, x8, x16)

All ACL-8112 Series feature 16 single-ended inputs or 8 differential inputs,
two12-bit double-buffered analog outputs, 16 digital inputs and 16 digital
outputs, and one timer/counter channel.

Introduction • 1

...

DI 1

D/I 0

16 BIT

EXT.CLK

TO PACER TRIG

OUT 0

<

16 BIT

16 BIT

16 BIT

COUNTER #0

COUNTER #2

COUNTER #1

FR/2

2MHz

OSC.

4 MHz

REGISTER

DIGITAL INPUT

12 Bit

A/D Converter

...

DI 15

16 BIT

DIGITAL INPUT

PACER

REGISTER

DO 15

D/O 0

DO 1

EOC

INPUT

BUFFER

(B.B 774)

INTERNAL BUS

TRIG

TRIG

SOFTWARE

TRIG

LOGIC

CONTROL

DACK

DRQ

TRIG

EXTERNAL

LOGIC

INTERRUPT

IRQ SELECT

#1 OR #3

DMA SELECT

DATA

BUFFER

PC/AT BUS

+5V

GAIN

12-Bit

Code Latch

+15

12-Bit

Code Latch

AMP

SELECT

-15

DC/DC

CONVERTER

I/O PORT DECODER

Figure 1.1 ACL - 8112 BLOCK DIAGRAM

D/A #0 12 BIT

MULITIPLYING D/A

<

GND

REF 0 IN

D/A 0 OUT

2 • Introduction

D/A #1 12 BIT

MULITIPLYING D/A

or

Analog

8 Differential

...

Multiplexer

>

16 channel

Single-ended

>

>

MUX SCAN

CONTROL

<

GND

CH 0

CH 1

REF 1 IN

D/A 1 OUT

CH 2

ANALOG

INPUT

CH 15

1.1 Features

The ACL-8112 series Enhanced Multi-function Data Acquisition Card
provides the following advanced features:

• AT-Bus

• 16 single-ended or eight differential analog input channels for ACL-

8112DG/HG, 16 single-ended for ACL-8112PG

• Bipolar or unipolar input signals for ACL-8112DG/HG, bipolar for ACL­8112PG

• Programmable gain

• High gain for ACL-8112HG:( x0.5, x1, x5, x10, x50, x100, x500,

x1,000)

• Normal gain for ACL-8112DG (x0.5, x1, x2, x4, x8)

• Five Levels programmable gain for ACL-8112PG (x1, x2, x4, x8, x16),

x0.5 gain can be set by jumper

• On-chip sample & hold

• Two 12-bit monolithic multiplying analog output channels

• 16 digital output channels

• 16 digital input channels

• Three programmable 16-bit down counters

• Programmable sampling rate of up to 100KHz

• Three A/D trigger modes: software trigger, programmable pacer

trigger, and external pulse trigger

• AT interrupt IRQ capability: nine IRQ levels (IRQ3~IRQ15) are jumper
selectable

• Integral DC-to-DC converter for stable analog power source

• 37-pin D-type connector

• Compact size: half-size PCB

Introduction • 3

1.2 Applications

• Industrial and laboratory ON/OFF control

• Energy management

• Annunciation

• 16 TTL/DTL compatible digital input channels

• Security controller

• Product test

• Period and pulse width measurement

• Event and frequency counting

• Waveform and pulse generation

• BCD interface driver

1.3 Specifications

Analog Input (A/D)

♦

Converter:

•

Resolution:

•

Number of channels:

•

ACL-8112DG/HG: 16 single-ended or eight differential

ACL-8112PG: 16 single-ended

Input Range:

•

ACL-8112HG

•

Bipolar : ±10V, ± 5V, ±1V, ±500 mV, ±100mV, ±50mV, ±10mV, ±5mV

Unipolar: 0 to 10V, 0 to 1V, 0 to 0.1V, 0 to 0.01V

ACL-8112DG:

•

Bipolar : ±10V, ± 5V, ±2.5V, ±1.25V, ±0.625

ADS774 or equivalent, successive approximation type

12-bit

(Programmable)

:

Unipolar: 0 to 10V, 0 to 5V, 0 to 2.5V, 0 to 1.25V

4 • Introduction

ACL-8112PG:

•

Bipolar : ± 10V, ± 5V, ±2.5V, ±1.25V, ±0.625V

Or

Bipolar : ± 5V, ±2.5V, ±1.25V, ±0.625V, ±0.3125V

Conversion Time:

•

Overvoltage protection:

•

Accuracy:

•

(ACL-8112HG)

GAIN = 0.5, 1
GAIN = 5, 10
GAIN = 50, 100
GAIN = 500, 1000

(ACL-8112DG)

GAIN = 0.5, 1
GAIN = 2, 4
GAIN = 8

(ACL-8112PG)

GAIN = 0.5, 1, 2, 4
GAIN = 8, 16

Input Impedance:

•

8µs

Continuous ± 35V maximum

0.01% of FSR ±1 LSB

0.02% of FSR ±1 LSB

0.04% of FSR ±1 LSB

0.04% of FSR ±1 LSB

0.01% of FSR ±1 LSB

0.02% of FSR ±1 LSB

0.04% of FSR ±1 LSB

0.015% of FSR ±1 LSB

0.02% of FSR ±1 LSB

10MΩ

AD conversion trigger modes:

•

Data Transfer:

•

Sampling Rate:

•

• 100 KHz maximum for single channel

• 100 KHz maximum for multiplexing on ACL-8112PG

• 20 KHz maximum for multiplexing on ACL-8112DG/HG

Analog Output (D/A)

Converter:

•

Number of channels:

•

Resolution:

•

Pooling, DMA, Interrupt

DAC7541 or equivalent, monolithic multiplying

Two double-buffered analog outputs

12-bit

Software, Pacer, and External trigger

Introduction • 5

Output Range:

•

Internal reference: (unipolar) 0 to 5V or 0 to 10V

External reference: (unipolar) max. +10V or -10V

Settling Time:

•

Linearity:

•

Output driving capability:

•

Digital I/O (DIO)

♦

Number of channels:

•

Input Voltage:

•

Low: Min. 0V; Max. 0.8V

High: Min. +2.0V

Input Load:

•

Low: +0.5V @ -0.2mA max.

High: +2.7V @+20mA max.

Output Voltage:

•

Low: Min. 0V; Max. 0.4V

High: Min. +2.4V

Driving Capacity:

•

Low: Max. +0.5V at 8.0mA (Sink)

High: Min. 2.7V at 0.4mA (Source)

30µs

±1/2 bit LSB

±5mA max.

16 TTL compatible inputs and outputs

Programmable Counter

♦

Device:

•

A/D pacer:

•
2MHz time base

Pacer Output:

•

Counter:

•
clock source

6 • Introduction

8254

32-bit timer (two 16-bit counter cascaded together) with a

0.00046 Hz to 100 KHz

One 16-bit counter with internal 2MHz time base or external

General Specifications

♦

I/O Base Address:

•

Interrupt IRQ:

•

DMA Channel

•

Connector:

•

Operating Temperature:

•

Storage Temperature:

•

Humidity:

•

Power Consumption:

•

ACL-8112DG/HG: +5 V @ 430 mA typical

+12V @ 150 mA typical

ACL-8112PG: +5 V @ 450 mA typical

12 V @ 150 mA typical

Dimension:

•

ACL-8112DG/HG: 162mm(L) x 115mm(W)

ACL-8112PG: 163 mm(L) x 123 mm(W)

5 to 95%, non-condensing

16 consecutive address location

IRQ3, 5, 6, 7, 9, 10, 11, 12, 15 (nine levels)

: CH1 and CH3 (Jumper selectable)

37-pin D-type connector

0°C to 55°C

-20°C to 80°C

Introduction • 7

1.4 Software Support

Programming Library

For users who are writing their own programs, we provide MS-DOS Borland
C/C++ programming library.

ACLS-DLL2 is the Development Kit for NuDAQ ISA-Bus Cards with Analog
I/O for windows 3.1/95(98)/NT. ACLS-DLL2 can be used in many
programming environments, such as VC++, VB, and Delphi. ACLS-DLL2 is
included in the ADLINK CD. To use this package a license is required.

LabView Driver

The ACLS-LVIEW includes the ACL-8112’s Vis, which is used to interface
with NI’s LabView software package. The ACLS-LVIEW supports Windows­95(98)/NT. ACLS-LVIEW is included in the ADLINK CD. To use this package
a license is required.

8 • Introduction

2

Installation

This chapter describes how to install the ACL-8112 series products. Please
use the following steps to install the product.

• Check what you have (section 2.1)

• Unpacking (section 2.2)

• Check the PCB and jumper location(section 2.3)

• Install the hardware and setup the jumpers and switches (sections 2.4

to 2.12)

• Cabling with external devices (section 2.13)

2.1 What You Have

In addition to this User's Manual, the package includes the following items:

• ACL-8112 Enhanced Multi-function Data Acquisition Card

• ADLINK CD

If any of these items are missing or damaged, contact ADLINK or the dealer
from whom the product was purchased. Save the shipping materials and
carton for future shipping or storage.

Note:

The utilities and libraries in the CD-ROM only support the ACL-8112
series under DOS environment. If you need to develop applications
under Windows 3.1, Windows 95 or Windows NT, please contact our
dealer for purchasing software development kit ACLS-DLL2.

Installation • 9

2.2 Unpacking

The card contains electro-static sensitive components that can be easily be
damaged by static electricity.

Therefore, the card should be handled on a grounded anti-static mat. The
operator should be wearing an anti-static wristband, grounded at the same
point as the anti-static mat.

Inspect the card module carton for obvious damage. Shipping and handling
may cause damage to the module. Ensure there is no shipping and handling
damage on the modules carton before continuing.

After opening the card module carton, extract the system module and place it
only on a grounded anti-static surface with component side up.

Again, inspect the module for damages. Press down on all the socketed IC's
to make sure that they are properly seated. Do this only with the module
place on a firm flat surface.

Note:

You are now ready to install your card.

DO NOT ATTEMPT TO INSTALL A DAMAGED BOARD IN THE
COMPUTER

.

10 • Installation

2.3 ACL-8112's Layout

INT

EXT1 EXT2

-5V

-10V

JP2

JP1

DIFF

SING

JP3

CN3

VR6

VR5

VR3 VR4

VR1 VR2

ADS774

INTTRG

JP4

CN1

. . . . . . . .

JP6

EXTCLK

INTCLK

SW1

EXTTRG

CN2

. . . . . . . .

8254

DACK

DRQ

JP5

JP7

1 3 X

1 3 X

JP8

3 5 6 7910111215NC

8112 Ver C.

Figure 2.1-1 PCB Layout of the ACL-8112DG/HG Ver C.

Installation • 11

12 • Installation

Figure 2.1-2 PCB Layout of the ACL-8112PG

2.4 Jumper and DIP Switch Description

ACL8112's channels and base address can be changed by setting jumpers
and DIP switches on the card. The card's jumpers and switches are preset at
the factory. The jumper settings can be changed for the user’s applications.

A jumper switch is closed (sometimes referred to as "shorted") with the
plastic cap inserted over two pins of the jumper. A jumper is open when the
plastic cap is inserted over one or no pin(s) of the jumper.

2.5 Base Address Setting

The ACL-8112 requires 16 consecutive address locations in the I/O address
space. The base address of the ACL-8112 is restricted by the following
conditions.

1. The base address must be within the range Hex 200 to Hex 3FF.

2. The base address should not conflict with any PC reserved I/O
address. See Appendix A.

3. The base address must not conflict with any add-on card on the
user’s PC. Please check your PC before installing the ACL-8112.

The ACL-8112's base address of registers is selected by a 6-positions DIP

SW1

switch
possible base address combinations are listed as Table 2.2. The base
address may be modified if the address HEX 220 has been occupied by
another add-on card.

. The default setting of base address is set to be HEX 220. All

SW1 : Base Address = Hex 220

ON

2 3 4 5

1

DIP

A ( 8 7 6 5

Figure 2.2 Default Base Address Setting

Installation • 13

I/O port

Address(Hex) A9

200-20F

--

(1)

210-21F

--

(1)

220-22F

(default)

230-23F

--

(1)

--

(1)

:

300-30F

--

(1)

:

3F0-3FF

--

(1)

1

A8

ON

(0)

ON

(0)

ON

(0)

ON

(0)

OFF

(1)

OFF

(1)

2

A7

ON

(0)

ON

(0)

ON

(0)

ON

(0)

ON

(0)

OFF

(1)

3

A6

ON

(0)

ON

(0)

ON

(0)

ON

(0)

ON

(0)

OFF

(1)

4

A5

ON

(0)

ON

(0)

OFF

(1)

OFF

(1)

ON

(0)

OFF

(1)

5

A4

ON

(0)

OFF

(1)

ON

(0)

OFF

(1)

ON

(0)

OFF

(1)

Table 2.2 Possible Base Address Combinations

A0, ..., A9 corresponds to the PC Bus address lines
A9 is fixed at “1”.

How to define/determine the base address of the ACL-8112?
DIP1 to DIP5 of SW1 corresponds to the PC bus address line A8 to
A4 respectively. A9 is always 1 and A0 to A3 are always 0. If you want
to change the base address, you can only change the values of A8 to
A4 (the shadow area of the table below). The following table is an
example, of how to set a base address of Hex 220

Base Address: Hex 220

2 2 0

1 0 0 0 1 0 0 0 0 0

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

14 • Installation

2.6 Analog Input Channel Configuration

(This section applies to ACL-8112DG and ACL-8112HG only.)

The ACL-8112 offers 16 single-ended or eight differential analog input
channels. JP3 controls the analog input channel configuration. The setting of
JP3 is illustrated below:

SING

Single-ended
(default setting)

Differential Input

Figure 2.3 Analog Input Channels Configuration

JP3

DIFF

SING

JP3

DIFF

Installation • 15

2.7 DMA Channel Setting

The A/D data transfer of the ACL-8112 is designed with DMA transfer
capabilities. The setting of the DMA for channel 1 or channel 3 is controlled
by JP7 and JP8 on the ACL-8112DG/HG, and JP1 and JP2 on the ACL­8112PG. Possible settings are shown below:

Note:

On floppy disk only machine, we suggest you set the DMA to level 3.
If you have a hard disk installed on the computer, level 1 is
preferable.

NO

DMA

DRQ
JP8/JP2

3

1

X

DACK
JP7/JP1

1 3 X

DMA 1

(Default)

DMA 3

Figure 2.4 DMA Channel Setting

16 • Installation

2.8 Internal/External Trigger Setting

The A/D conversion trigger source of the ACL-8112 can come from an
internal or external source. The internal or external trigger source is set by
JP4 on the ACL-8112DG/HG and by JP5 on the ACL-8112PG, as shown
on Figure 2.5. Note that there are two internal trigger sources, one is by
software trigger and the other is by the programmable pacer trigger, which
is controlled by the mode control register (see section 4.5).

Internal Trigger
(default setting)

INTTRG

EXTTRG

JP4 / JP5

JP4 / JP5

External Trigger

INTTRG

EXTTRG

Figure 2.5 Trigger Source Setting

Internal Clock
Source : 2MHz

(default setting)

External Clock
Source

INTCLK

EXTCLK

INTCLK

EXTCLK

JP6 / JP4

JP6 / JP4

Figure 2.6 Timer's Clock Source Setting

Installation • 17

2.9 Clock Source Setting

Q

The 8254 programmable interval timer is used in the ACL-8112. It provides
three independent 16-bit programmable down counters. The input of
counter 2 is connected to a precision 2MHz oscillator which is the internal
pacer. The input of counter 1 is cascaded from the output of counter 2.
Channel 0 is free for user's applications. There are two selections for the
clock source of channel 0: the internal 2MHz clock or an external clock
signal from connector CN3 pin 37. The setting for the clock is shown in
Figure 2.6.

2.10 IRQ Level Setting

The ACL-8112 can connect to any one of the interrupt lines of the PC I/O
channel. The interrupt line is selected by JP5 of ACL-8112DG/HG or JP3 of
ACL-8112PG. If the user wishes to use the interrupt capability of ACL-8112,
select an interrupt level and place the jumper in the appropriate position to
enable the particular interrupt line.

The default interrupt level is IRQ15, which is selected by placing the jumper
on the pins in row number 15. Figure 2.7 shows the default interrupt jumper
setting IRQ15. The jumper can be removed from IRQ15 to other new pins to
change to another IRQ level.

Note:

Please note that no other add-on cards can share the same interrupt
level simultaneously.

JP5 / JP3

No Interrupt :

56 791011 1215 X

3

IRQ

JP5 / JP3

Interrupt level :

15

IR

(default setting)

IRQ

Figure 2.7 IRQ Level Setting

18 • Installation

5 6 7 9 10 11 12 15 X

3

2.11 D/A Reference Voltage Setting

The D/A converter's reference voltage source can be internally or externally
generated. The external reference voltage is connected via CN3 pin 31
(ExtRef1) and pin 12 (ExtRef2), see section 3.1. The D/A reference source of
channel 1 and channel 2 are selected using JP2 for the ACL-8112DG/HG
and JP6 and JP7 for the ACL-8112PG respectively. Possible settings are
shown below:

D/A CH1 is External

D/A CH2 is External

D/A CH1 is External

D/A CH2 is Internal

D/A CH1 is Internal

D/A CH2 is External

D/A CH1 is Internal

D/A CH2 is Internal

JP2 or JP7 JP6

INTREF

JP2 or JP7 JP6

INTREF

JP2 or JP7 JP6

INTREF

JP2 or JP7 JP6

INTREF

INTREF

ExtRef2 ExtRef1

INTREF

ExtRef2 ExtRef1

INTREF

ExtRef2 ExtRef1

INTREF

ExtRef2 ExtRef1

Figure 2.8 D/A Voltage Setting

Installation • 19

The internal voltage can be set to -5V or -10V which is selected by JP1 for

A

A

the ACL-8112DG/HG and JP8 for the ACL-8112PG. Possible configurations
are specified in Figure 2.9. Note that the internal reference voltage is used
only when JP2 of the ACL-8112DG/HG or JP6 and JP7 of the ACL-8112PG
is set to internal reference.

Reference Voltage is

-10V

-5V (default setting)

-5V

-10V

Reference Voltage is

-10V

Figure 2.9 Internal Reference Voltage Setting

-5V

JP1 /
JP8

JP1 /
JP8

2.12 A/D Input Range Setting

(This section is for the ACL-8112PG only)

The A/D input range of the ACL-8112PG can be set to ±5V or ±10V using
JP9.

10

/D Input Range is +/-

5V (default setting)

/D Input Range is +/-

10V

JP9

5

10

JP9

5

20 • Installation