A-Data ADS7616A4A
A
Synchronous DRAM 2M x 16 Bit x 4 Banks
General Description
The ADS7616A4A are four-bank Synchronous
DRAMs organized as 2,097152 words x 16 bits x 4
banks.
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
Ordering Information.
Part No. Frequency Interface Package
ADS7616A4A-55 183Mhz LVTTL 400mil 54pin TSOPII
Features
•JEDEC standard LVTTL 3.3V power supply
•MRS Cycle with address key programs
-CAS Latency (2 & 3)
-Burst Length (1,2,4,8,& full page)
-Burst Type (sequential & Interleave)
•4 banks operation
ll inputs are sampled at the positive edge of
•
the system clock
•Burst Read single write operation
•Auto & Self refresh
•4096 refresh cycle
•DQM for masking
•Package:54-pins 400 mil TSOP-Type II
ADS7616A4A-6 166Mhz LVTTL 400mil 54pin TSOPII
ADS7616A4A-7 143Mhz LVTTL 400mil 54pin TSOPII
Pin Assignment
54
V
DD
DQ0
V
DDQ
DQ1
DQ2
SSQ
V
DQ3
DQ4
DDQ
V
DQ5
DQ6
SSQ
V
DQ7
DD
V
LDQM
/WE
/CAS
/RAS
/CS
BS0
BS1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28
Vss
DQ15
53
Vss
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Q
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
54-pin plastic TSOP II 400 mil
Rev 1.0 April, 2001
1
A-Data ADS7616A4A
Pin Description
PIN NAME FUNCTION
CLK System Clock Active on the positive edge to sample all inputs.
CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS Chip Select Disables or Enables device operation by masking or enabling all input
except CLK, CKE and L(U)DQM
A0~A11 Address Row / Column address are multiplexed on the same pins.
Row address : RA0~RA11
Column address : CA0~CA8
BA0~BA1 Banks Select Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ15 Data Data inputs / outputs are multiplexed on the same pins.
L(U)DQM Data Mask Makes data output Hi-Z,
/RAS Row Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low
/CAS Column Address Strobe Latches Column addresses on the positive edge of the CLK with /CAS low
/WE Write Enable Enables write operation and row recharge.
VDD/VSS Power Supply/Ground Power and Ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers.
NC No Connection This pin is recommended to be left No Connection on the device.
Block Diagram
CLK
CKE
Address
Clock
Generator
Mode
Register
Address
Buffer
&
Refresh
Counter
Row Decoder
Bank3
Bank2
Bank1
Bank0
/CS
/RAS
/CAS
/WE
Rev 1.0 April, 2001
Command Decoder
Control Logic
Column
Address
Buffer
&
Refresh
Counter
Amplifier
Column Decoder
Data Control Circuit
Data Latch
L(U)DQM
DQ
2
A-Data ADS7616A4A
Absolute Maximum Ratings
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, Vout -3.0 ~ VCC+0.3 V
Voltage on VDD supply relative to Vss VDD, VDDQ -0.3 ~ 4.6 V
Storage temperature TSTG -55 ~ +150
Power dissipation PD 1 W
Short circuit current IOS 50 mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
℃
DC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1
Input logic low voltage VIL -0.3 0 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH=-2mA
Output logic low voltage VOL - - 0.4 V IOL=2mA
Input leakage current IIL -5 - 5 uA 3
Output leakage current IOL -5 - 5 uA 4
Note : 1. VIH (max)=4.6V AC for pulse width ≦ 10ns acceptable.
2.V
3.Any input 0V ≦ V
4.Dout is disabled, 0V ≦ V
IL(min)=-1.5V AC for pulse width ≦ 10ns acceptable.
IN ≦ VDD + 0.3V, all other pins are not under test = 0V.
OUT ≦ VDD.
AC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter Symbol Value Unit Note
AC input high / low level voltage VIH / VIL 2.4 / 0.4 V
Input timing measurement reference level voltage Vtrip 1.4 V
Input rise / fall time TR / tF 2 ns
Output timing measurement reference level Voutfef 1.4 V
Output load capacitance for access time measurement CL 50 pF 2
Note: 1. 3.15V ≦ VDD ≦ 3.6V is applied for ADS7616A4A55.
2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details,
refer to AC/DC output load circuit.
Rev 1.0 April, 2001
3
A-Data ADS7616A4A
A
Capacitance
TA= 25℃, f-=1Mhz, VDD=3.3V
Parameter Pin Symbol Min Max Unit
CLK Cl1 - 3.5 pF Input capacitance
A0~A11,BA0,BA1,CKE,/CS,/RAS,
/CAS,/WE,DQM
Data input / output capacitance DQM CI/O - 6.5 pF
Cl2 - 3.8 pF
Output load circuit
3.3 V
1200 ohms
Output
870 ohms50 pF
VOH(DC) = 2.4V,IOH= -2m
VOL(DC) = 0.4V,IOL= 2mA
DC Characteristics I
Parameter Symbol Min Max Unit Note
Input leakage current ILI -5 5 uA 1
Output leakage current ILO -5 5 uA 2
Output high voltage VOH 2.4 - V IOH = -4mA
Output low voltage VOL - 0.4 V IOL = 4mA
Note : 1.VIN = 0 TO 3.6V, All other pins are not tested under VIN = 0V.
2.D
OUT is disabled, VOUT = 0 to 3.6.
Rev 1.0 April, 2001
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A-Data ADS7616A4A
DC Characteristics II
Parameter Symbol Test condition
Speed
Unit Note
-5.5 -6 -7
Operating Current IDD1
Precharge standby
current in power down
mode
Precharge standby
current in Non power
down mode
Active standby current
in Non power down
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3
Burst length=1, One bank active
tRC≧tRC(min),I
CKE≦V
CKE≦V
CKE≧V
tCK=min input signals are
changed one time during 2clks. All
other pins ≧VDD-0.2V or ≦
0.2V
CKE≧V
Input signals are stable.
CKE≧V
tCK=min input signals are
changed one time during 2clks. All
other pins ≧VDD-0.2V or ≦
OL=0mA
IL(max), tCK=min
IL(max), tCK=∞
IH(min), /CS≧VIH(min),
IH(min), tCK=∞
IH(min), /CS≧VIH(min),
90 85 70 mA 1
1
mA
1
40
mA
10
60
mA
mode
IDD3P
Burst mode operating
IDD4
current
Auto refresh current IDD5
Self refresh current IDD6
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output
open.
2. Min. of tRRC is shown at AC characteristics.
0.2V
CKE≧V
Input signals are stable.
t
All banks active
tRRC≧tRRC(min), All banks
active
CKE≦0.2V
IL(min), tCK=min
CK≧tCK(min),IOL=0 mA
10
110 105 100 mA 1
190 180 170 mA 2
2 mA
Rev 1.0 April, 2001
5
A-Data ADS7616A4A
AC Characteristics
Speed
Parameter Symbol
System clock
Cycle time
Clock high pulse width tCHW
Clock low pulse width tCLW
Access time form
clock
/RAS cycle time Operation tRC
/RAS to /CAS delay tRCD
/RAS active time tRAS
/RAS precharge time tRP
/CAS to /CAS delay tCCD
DQM to data – in mask tDQM
Data – out hold time tOH
Data – input setup time tDS
Data – input hold time tDH
Address setup time tAS
Address hold time tAH
CKE setup time tCKS
CKE hold time tCKH
Command setup time tCMS
Command hold time tCMH
CLK to data output in low Z-time tOLZ
MRS to new command tMRD
Power down exit time tPDE
Self refresh exit time tSRE
Refresh time tREF
Note : 1. Assume tR / tF (input rise and fall time) is 1 ns.
2. Access times to be measured with input signals of 1v / ns edge rate.
3.A new command can be given tRRC after self refresh exit.
/CAS Latency = 3 tCK3
/CAS Latency = 2 tCK2
/CAS Latency = 3 tAC3
/CAS Latency = 2 tAC2
-5.5 -6 -7
Min Max Min Max Min Max
5.5
1000
7.5
2 - 2 -
2 - 2 -
- 5 - 5
- 5.4 - 5.4
57 - 57 -
15 - 15 -
42 100K 42 100K
15 - 15 -
1 - 1 -
0 - 0 -
2.75 - 2.75 -
1.5 - 1.5 -
0.8 - 0.8 -
1.5 - 1.5 -
0.8 - 0.8 -
1.5 - 1.5 -
0.8 - 0.8 -
1.5 - 1.5 -
0.8 - 0.8 -
1 - 1 -
1 - 1 -
1 - 1 -
1 - 1 -
- 64 64
6 7
7.5
1000
1000 ns
7.5
2.5 - ns 1
2.5 - ns 1
- 5.4
- 5.4
57 -- ns
15 - ns
42 100K ns
15 - ns
1 - CLK
0 - CLK
3 - ns
1.5 - ns 1
0.8 - ns 1
1.5 - ns 1
0.8 - ns 1
1.5 - ns 1
0.8 - ns 1
1.5 - ns 1
0.8 - ns 1
1 - ns
2 - CLK
1 - CLK
1 - CLK 3
64 ms
Unit Note
ns 2
Rev 1.0 April, 2001
6
A-Data ADS7616A4A
Command Truth-Table
Command CKEn-1 CKEn /CS /RAS /CAS /WE DQM ADDR A10/AP BA
Mode Register Set H X L L L L X OP code
No Operation H X
Bank Active H X L L H H X RA V
Read L
H X L H L H X CA
Read with Auto Precharge
Write L
H X L H L L X CA
Write with Auto Precharge
Precharge All Bank H X
H X L L H L X X
Precharge select Bank
Burst Stop H X L H H L X X
DQM H X V X
Auto Refresh H H L L L H X X
Entry H L L L L H X
Self Refresh
Exit L H
Entry H L
Precharge
Power down
Exit L H
H X X X
L H H H
H X X X
L H H H
H X X X
L H H H
H X X X
L H H H
X X
V
H
V
H
L V
X
X
X
X
X
Clock Suspend
Entry H L
Exit L H X X
Rev 1.0 April, 2001
H X X X
L V V V
7
X
X
A-Data ADS7616A4A
Package Information
SYMBOL
A 1.20 0.047
A1 0.05 0.10 0.15 0.002 0.004 0.006
A2 0.95 1.00 1.05 0.037 0.039 0.041
B 0.30 0.35 0.45 0.012 0.014 0.018
c 0.12 0.21 0.005 0.008
D 22.22 BSC 0.875 BSC
HE 11.56 11.76 11.96 0.460 0.463 0.470
E 10.03 10.16 10.29 0.390 0.400 0.410
e 0.80 BSC 0.031
L 0.40 0.50 0.60 0.016 0.020 0.024
L1 0.80 REF 0.031 REF
MIN. NOM. MAX. MIN. NOM. MAX.
S
θ
0 ° - 8 ° 0 ° - 8 °
MILLIMETER INCH
0.71 REF 0.028 REF
400mil 54pin TSOP II Package
Rev 1.0 April, 2001
8
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