A-Data ADS4616A4A
A
Synchronous DRAM 512K x 16 Bit x 2 Banks
General Description
The ADS4616A4A are two-bank Synchronous
DRAMs organized as 524,288 words x 16 bits x 2
banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
Ordering Information.
Part No. Frequency Interface Package
ADS4616A4A-5 200Mhz LVTTL 400mil 50pin TSOPII
ADS4616A4A -6 166Mhz LVTTL 400mil 50pin TSOPII
ADS4616A4A -7 143Mhz LVTTL 400mil 50pin TSOPII
Pin Assignment
Features
•Single 3.3V +/- 0.3V power supply
•MRS Cycle with address key programs
-CAS Latency (2 & 3)
-Burst Length (1,2,4,8, & full page)
-Burst Type (sequential & Interleave)
•2 banks operation
ll inputs are sampled at the positive edge of
•
the system clock
•Burst Read single write operation
•Auto & Self refresh
•4096 refresh cycle
•DQM for masking
•Package:50-pins 400 mil TSOP-Type II
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
SSQ
V
DQ6
DQ7
V
DDQ
LDQM
/WE
/CAS
/RAS
/CS
(BS)A11
A10
A0
A1
A2
A3
V
DD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
26
27
Vss
DQ15
DQ14
Q
Vss
DQ13
DQ12
V
DD
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
Q
50-pin plastic TSOP II 400 mil
Rev 1 December, 2001
1
A-Data ADS4616A4A
Pin Description
PIN NAME FUNCTION
CLK System Clock Active on the positive edge to sample all inputs.
CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS Chip Select Disables or Enables device operation by masking or enabling all input
except CLK, CKE and L(U)DQM
A0~A10 Address Row / Column address are multiplexed on the same pins.
Row address : A0~A10
Column address : A0~A7
DQ0~DQ15 Data Data inputs / outputs are multiplexed on the same pins.
L(U)DQM Data Mask Makes data output Hi-Z,
/RAS Row Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low
/CAS Column Address Strobe Latches Column addresses on the positive edge of the CLK with /CAS low
/WE Write Enable Enables write operation and row recharge.
VDD/VSS Power Supply/Ground Power and Ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers.
NC No Connection This pin is recommended to be left No Connection on the device.
Block Diagram
CLK
CKE
Address
/CS
/RAS
/CAS
/WE
Clock
Generator
Mode
Register
Command Decoder
Control Logic
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
Row Decoder
Amplifier
Column Decoder
Data Control Circuit
Bank B
Bank A
Data Latch
DQM
Input & Output
Buffer
DQ
Rev 1 December, 2001
2
A-Data ADS4616A4A
Absolute Maximum Ratings
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, Vout -0.3~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -0.3~ 4.6 V
Storage temperature TSTG -55 ~ +150
Power dissipation PD 1 W
Short circuit current IOS 50 mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
℃
DC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high voltage VIH 2.0 VDD+0.3 V 1
Input logic low voltage VIL -0.3 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH=-2mA
Output logic low voltage VOL - - 0.4 V IOL=2mA
Input leakage current IIL -5 - 5 uA 3
Output leakage current IOL -5 - 5 uA 4
Note : 1. VIH (max)=V
2.V
3.Any input 0V ≦ V
4.Dout is disabled, 0V ≦ V
IL(min)=V
+2.0V with a pulse width < 3ns
DDH
-2.0V with a pulse < 3ns and – 1.5V with a pulse < 5ns
SSQ
IN ≦ VDD + 0.3V, all other pins are not under test = 0V.
OUT ≦ VDD.
AC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter Symbol Value Unit Note
AC input high / low level voltage VIH / VIL 1.4 / 1.4 V
Input timing measurement reference level voltage Vtrip 1.4 V
Input rise / fall time TR / tF 1 ns
Output timing measurement reference level Voutfef 1.4 V
Output load capacitance for access time measurement CL 50 pF
Rev 1 December, 2001
3
A-Data ADS4616A4A
Capacitance
TA= 25℃, f-=1Mhz, VDD=3.3V
Parameter Pin Symbol Min Max Unit
CLK C11 2.5 4 pF Input capacitance
A0~A11,BA0,BA1,CKE,/CS,/RAS,
/CAS,/WE,DQM
Data input / output capacitance DQM CI/O 4 6.5 pF
C12 2.5 5 pF
Output load circuit
1.4 V
50 ohms
Output
Z= 50 ohms
30 pF
DC Characteristics I
Parameter Symbol Min Max Unit Note
Input leakage current ILI -5 5 uA 1
Output leakage current ILO -5 5 uA 2
Output high voltage VOH 2.4 - V IOH = -2mA
Output low voltage VOL - 0.4 V IOL = 2mA
Note : 1.VIN = 0 TO 3.6V, All other pins are not tested under VIN = 0V.
2.D
OUT is disabled, VOUT = 0 to 3.6.
Rev 1 December, 2001
4
A-Data ADS4616A4A
DC Characteristics II
Parameter Symbol Test condition
-5 -6 -7
Speed
Unit Note
Operating Current IDD1
Precharge standby
current in power
down mode
Precharge standby
current in Non power
down mode
Active standby
current in power
down mode
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
Burst length=1, One bank active
tRC≧tRC(min),I
CKE≦V
CKE≦V
CKE≧V
tCK=min input signals are
changed one time during 2clks.
All other pins ≧VDD-0.2V or ≦
0.2V
CKE≧V
Input signals are stable.
CKE≦V
CKE≧V
OL=0mA
IL(max), tCK=min
IL(max), tCK=∞
IH(min), /CS≧VIH(min),
IH(min), tCK=∞
IL(max), tCK=min
IH(min), /CS≧VIH(min),
70 60 50 mA 1
1
mA
1
35 30 25
mA
8
45 40 35 mA
Active standby
current in Non power
down mode
Burst mode operating
current
Auto refresh current IDD5
Self refresh current IDD6
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output
open.
2. Min. of tRRC is shown at AC characteristics.
IDD3N
IDD4
tCK=min input signals are
changed one time during 2clks.
All other pins ≧VDD-0.2V or ≦
0.2V
t
CK≧tCK(min),IOL=0 mA
All banks active
tRRC≧tRRC(min), All banks
active
CKE≦0.2V
3 mA
120 110 100 mA 1
60 55 50 mA 2
200 uA
Rev 1 December, 2001
5
A-Data ADS4616A4A
AC Characteristics
Parameter Symbol
/CAS Latency = 3 tCK3 5 6 7System clock
Cycle time
Clock high pulse width tCHW 2 - 2 - 2 - ns 1
Clock low pulse width tCLW 2 - 2 - 2 - ns 1
form clock
Row cycle time tRC
/RAS to /CAS delay tRCD 14 - 18 - 20 - ns
/RAS active time tRAS 40 100K 42 100K 45 100K ns
/RAS precharge time tRP 14 - 18 - 20 - ns
/RAS to /RAS bank active delay tRRD 10 - 12 - 14 - ns
/CAS to /CAS delay tCCD 1 - 1 - 1 - CLK
Data – out hold time tOH 1.5 - 2 - 2.5 - ns
Data – input setup time tDS 1.5 - 1.5 - 1.5 - ns 1
/CAS Latency = 2 tCK2 7
/CAS Latency = 3 tAC3 - 4.5 - 5 - 5Access time
/CAS Latency = 2 tAC2 - 4.5 - 5.5 - 5.5
-5 -6 -7
Min Max Min Max Min Max
54
1000
-
1000
8
60 - 65 -
1000 ns
10
Unit Note
ns 2
ns
Data – input hold time tDH 1 - 1 - 1 - ns 1
Address setup time tAS 1.5 - 1.5 - 1.5 - ns 1
Address hold time tAH 1 - 1 - 1 - ns 1
Power down exit time tPDE 5 - 5 - 5 - CLK
Refresh time tREF 64 64 64 ms
Note : 1. Assume tR / tF (input rise and fall time) is 1 ns.
2. Access times to be measured with input signals of 1v / ns edge rate.
3.A new command can be given tRRC after self refresh exit.
Rev 1 December, 2001
6
A-Data ADS4616A4A
Command Truth-Table
Command CKEn-1 CKEn /CS /RAS /CAS /WE A10 A9-A0
Mode Register Set H X L L L L X V
No Operation H X L H H H X X
Bank Active H X L L H H V
Read
Read with Auto Precharge
Write
Write with Auto Precharge
Precharge All Bank H X
Precharge select Bank
Burst Stop H X L H H L X
DQM H X X
Entry H L L L L H
Self Refresh
Exit L H
Entry H L X
Precharge
Power down
Exit L H X
Entry H L X
Clock Suspend
Exit L L X
H X L H L H
H X L H L L
H X L L H L
H X X X
L H H H
L
H
L
H
L X
V
V
X
X
X
Rev 1 December, 2001
7
A-Data ADS4616A4A
Package Information
5050
SYMBOL
A 1.20 0.047
A1 0.05 0.10 0.15 0.002 0.006
A2 0.95 1.00 1.05 0.037 0.039 0.041
B 0.30 0.45 0.012 0.018
c 0.12 0.21 0.005 0.008
D 21.08 BSC 0.830 BSC
HE 11.56 11.76 11.96 0.460 0.463 0.471
E 10.03 10.16 10.29 0.395 0.400 0.405
e 0.80 BSC 0.0315
L 0.40 0.50 0.60 0.016 0.020 0.024
L1 0.80 REF 0.031 REF
MIN. NOM. MAX. MIN. NOM. MAX.
S
θ
0 ° - 5 ° 0 ° - 5 °
MILLIMETER INCH
0.71 REF 0.028 REF
400mil 50pin TSOP II Package
2626
2525
Rev 1 December, 2001
8
Loading...