ACT ACT-5260PC-150F17T, ACT-5260PC-150F17M, ACT-5260PC-150F17I, ACT-5260PC-150F17C, ACT-5260PC-133F17T Datasheet

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– RISC TurboEngines For The Future © SCD5260 REV A 3/29/99

Integer Control

Floating point Control

ACT5260

64-Bit Superscaler Microprocessor

Features

■ Full militarized QED RM5260 microprocessor

■ Dual Issue superscalar QED RISCMark - can issue one

integer and one floating-point instruction per cycle
microprocessor - can issue one integer and one
floating-point instruction per cycle

● 100, 133 and 150MHz frequency (200MHz future option)

Consult Factory for latest speeds

● 260 Dhrystone2.1 MIPS

● SPECInt95 4.8. SPECfp95 5.1

■ High performance system interface compatible with R4600,

R4700 and R5000

● 64-bit multiplexed system address/data bus for optimum

price/performance up to 100 MHz operating frequency

● High performance write protocols maximize uncached

write bandwidth

● Operates at input system clock multipliers of 2 through 8

● 5V tolerant I/O's

● IEEE 1149.1 JTAG boundary scan

■ Integrated on-chip caches - up to 3.2GBps internal data rate

● 16KB instruction - 2 way set associative

● 16KB data - 2 way set associative

● Virtually indexed, physically tagged

● Write-back and write-through on per page basis

● Pipeline restart on first double for data cache misses

■ Integrated memory management unit

● Fully associative joint TLB (shared by I and D translations)

● 48 dual entries map 96 pages

● Variable page size (4KB to 16MB in 4x increments)

■ Embedded supply de-coupling capacitors and Pll filter

components

■ High-performance floating point unit - up to 400 MFLOPS

● Single cycle repeat rate for common single precision

operations and some double precision operations

● Two cycle repeat rate for double precision multiply and

double precision combined multiply-add operations

● Single cycle repeat rate for single precision combined

multiply-add operation

■ MIPS IV instruction set

● Floating point multiply-add instruction increases

performance in signal processing and graphics
applications

● Conditional moves to reduce branch frequency

● Index address modes (register + register)

■ Embedded application enhancements

● Specialized DSP integer Multiply-Accumulate instruction

and 3 operand multiply instruction

● I and D cache locking by set

● Optional dedicated exception vector for interrupts

■ Fully static CMOS design with power down logic

● Standby reduced power mode with WAIT instruction

● 5 Watts typical at 3.3V, less than 175 mwatts in Standby

■ 208-lead CQFP, cavity-up package (F17)

■ 208-lead CQFP, inverted footprint (F24), Intended to duplicate

the commercial QED footprint (Consult Factory)

■ 179-pin PGA package (Future Product) (P10)

BLOCK DIAGRAM

Data Set A

Store Buffer

Write Buffer
Read Buffer

Data Set B

Control

Floating-point

Register File

Unpacker/Packer

Floating-point

MAdd, Add, Sub,Cvt

Div, SqRt

DBus

Sys AD

FPIBus

Phase Lock Loop

Data Tag A

DTLB Physical

Data Tag B

Address Buffer

Instruction Tag A

ITLB Physical

Instruction Tag B

Tag Aux Tag

Joint TLB

Coprocessor 0

System/Memory

Control

PC Incrementer

Branch Adder

Instruction TLB Virtual

Program Counter

Instruction Set A

Instruction Select

Integer Instruction Register

FP Instruction Register

Instruction Set B

Integer/Address Adder

DVA

IVA

Integer Multiply, Divide

IntIBus

Load Aligner

Integer Register File

Data TLB Virtual

Shifter/Store Aligner

Logic Unit

ABus

Technology

DESCRIPTION:

The ACT5260 is a highly integrated superscalar
microprocessor that implements a superset of the
MIPS IV Instruction Set Architecture(ISA). It has a
high performance 64-bit integer unit, a high
throughput, fully pipelined 64-bit floating point unit,
an operating system friendly memory management
unit with a 48-entry fully associative TLB, a 16 KByte
2-way set associative instruction cache, a 16 KByte
2-way set associative data cache, and a
high-performance 64-bit system interface. The
ACT5260 can issue both an integer and a floating
point instruction in the same cycle.

The ACT5260 is ideally suited for high-end
embedded control applications such as
internetworking, high performance image
manipulation, high speed printing, and 3-D
visualization.

Integer Unit

Like the R5000, the ACT5260 implements the
MIPS IV Instruction Set Architecture, and is therefore
fully upward compatible with applications that run on
processors implementing the earlier generation
MIPS I-III instruction sets. Additionally, the ACT5260
includes two implementation specific instructions not
found in the baseline MIPS IV ISA but that are useful
in the embedded market place. Described in detail in
the QED RM5260 datasheet, these instructions are
integer multiply-accumulate and 3-operand integer
multiply.

The ACT5260 integer unit includes thirty-two
general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add,
sub, logical, shift) and an autonomous multiply/divide
unit. Additional register resources include: the HI/LO
result registers for the two-operand integer multiply/
divide operations, and the program counter(PC).

HARDWARE OVERVIEW

The ACT5260 offers a high-level of integration
targeted at high-performance embedded
applications. Some of the key elements of the
ACT5260 are briefly described below.

Superscalar Dispatch

The ACT5260 has an efficient asymmetric
superscalar dispatch unit which allows it to issue an
integer instruction and a floating-point computation
instruction simultaneously. With respect to
superscalar issue, integer instructions include alu,
branch, load/store, and floating-point load/store,
while floating-point computation instructions include
floating-point add, subtract, combined multiply-add,
converts, etc. In combination with its high throughput
fully pipelined floating-point execution unit, the
superscalar capability of the ACT5260 provides
unparalleled price/performance in computationally
intensive embedded applications.

CPU Registers

Like all MIPS ISA processors, the ACT5260 CPU
has a simple, clean user visible state consisting of 32
general purpose registers, two special purpose
registers for integer multiplication and division, a
program counter, and no condition code bits.

Register File

The ACT5260 has thirty-two general purpose
registers with register location 0 hard wired to zero.
These registers are used for scalar integer
operations and address calculation. The register file
has two read ports and one write port and is fully
bypassed to minimize operation latency in the
pipeline.

ALU

The ACT5260 ALU consists of the integer adder/
subtractor, the logic unit, and the shifter. The adder
performs address calculations in addition to
arithmetic operations, the logic unit performs all
logical and zero shift data moves, and the shifter
performs shifts and store alignment operations. Each
of these units is optimized to perform all operations in
a single processor cycle

For additional Detail Information regarding the
operation of the Quantum Effect Design (QED)
RISCMark
Microprocessor see the latest QED datasheet
(Revision 1.1 July 1998).

 RM5260, 64-Bit Superscalar

Pipeline

For integer operations, loads, stores, and other
non-floating-point operations, the ACT5260 uses the
simple 5-stage pipeline also found in the circuits
R4600, R4700, and R5000. In addition to this
standard pipeline, the ACT5260 uses an extended
seven stage pipeline for floating-point operations.
Like the R5000, the ACT5260 does virtual to physical
translation in parallel with cache access.

Aeroflex Circuit Technology SCD5260 REV A 3/29/99 Plainview NY [phone]

2

Absolute Maximum Ratings

1

Symbol Rating Range Units

2

to 4.6 V

V

TERM

Tc

T

BIAS

T

STG

I

IN

I

OUT

Notes:

1. Stresses above those listed under "AbsoluteMaximums Rating" may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

2. V

IN minimum = -2.0V for pulse width less than 15nS. VIN maximum should not exceed +5.5 Volts.

3. When V

4. No more than one output should be shorted at one time. Duration of the short should not exceed more than 30 second.

IN < 0V or VIN > Vcc.

Terminal Voltage with respect to GND
Operating Temperature
Case Temperature under Bias
Storage Temperature
DC Input Current
DC Output Current

-0.5

-55 to +125 °C

-55 to +125 °C

-55 to +125 °C
20

3

mA

50 mA

Recommended Operating Conditions

Symbol Parameter Minimum Maximum Units

V

CC

V

IH

V

IL

T

C

Power Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature Case
For 133MHz Parts only

+3.135 +3.465 V

0.7V

CC

-0.5 0.2V

V

+ 0.5 V

CC

CC

-55 +125 °C

-40 +125 °C

V

(VCC = 3.3V ±5%; 133MHz parts: Tc =-40°C to +125°C, All other parts Tc =-55°C to +125°C)

DC Characteristics

Parameter Sym Conditions

Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Input High Voltage
Input Low Voltage
Input Current
Input Current
Input Current
Input Capacitance
Output Capacitance

Aeroflex Circuit Technology SCD5260 REV A 3/29/99 Plainview NY [phone]

V
V
V
V

C

OL1

OH1

OL2

OH2

V
V

I

IN1

I

IN2

I

IN3

C

OUT

IH

IL

IN

IOL = 20 µA
IOL = 20 µA
IOL = 4 mA
IOL = 4 mA

V

= 0V

IN

V

= V

IN

V

IN

CC

= 5.5V

3

100 / 133 / 150MHz

Min Max

- 0.1 V

Vcc - 0.1 - V

- 0.4 V

2.4 - V

0.7V

-0.5 0.2V

CC

V

+ 0.5 V

CC

CC

-20 +20 µA

-20 +20 µA

-250 +250 µA

- 10 pF

- 10 pF

Units

V