Acrosser AR-B9612 User Manual

AR-B9612

User’s Guide

Version : 2.1

1. OVERVIEW

This chapter provides an overview of your system features and
capabilities. The following topics are covered:

l Introduction
l Packing List
l Features

1.1 INTRODUCTION

The AR-B9612 PC/104, CPU module is a lower power
consuming, high performance 386 based computer. By
using the space saving features of the ALI M6117 CPU, this
module is able to support up to 4MB’s of DRAM and 1.5 MB’s
of Flash memory on board. The unit also comes with two
RS-232C/RS-485 ports adding a high degree of versatility to
any project. The AR-B9612 is an excellent choice for mobile
systems, or as a controller for machines that are too small to
accommodate traditional industrial PC’s.

The AR-B9612 offers embedded applications the speed and
stability of a 386SX with the size of a true PC/104 module.

AR-B9612 User’s Guide

1-1

din PS/2 to IBM

1.2 PACKING LIST

The accessories are included with the system. Before you begin
installing your AR-B9612 board, take a moment to make sure
that the following items have been included inside the
AR-B9612 package.

l This user’s guide
l 1 AR-B9612 PC/104 386SX Single CPU board
l 1 Keyboard adapter cable
l 2 RS-232C interface cable
l 1 Power adapter cable

Accessory Description

Keyboard adapter cable 1 4-pin to 6-pin mini-

standard type adapt cable
Power adapter cable 4-pin power adapter cable
RS-232C interface cable 2 10-pin RS-232C interface cable

Table 1-1 Accessories

AR-B9612 User’s Guide

1-2

1.3 FEATURES

The system provides a number of special features that enhance
its reliability, ensure its availability, and improve its expansion
capabilities, as well as its hardware structure.

l 80386SX-33/40 MHz CPU
l PC/104 extension bus
l Up to 4MB DRAM system
l Supports 2 RS-232C/RS-485 serial port
l PC/AT compatible keyboard interface
l Supports up to 1.5MB flash disk
l Programmable watchdog timer
l Flash BIOS
l Powered-on LED indicator
l Signal 5V power requirement
l Multi-layer PCB for noise reduction
l Dimensions : 90.2mmX95.9mm

AR-B9612 User’s Guide

1-3

AR-B9612 User’s Guide

1-4

2. SYSTEM CONTROLLER

This chapter describes the major structure. The following
topics are covered:

l Microprocessor
l DMA Controller
l I/O Port Address Map
l Interrupt Controller
l Serial Port
l Real-Time Clock and Non-Volatile RAM
l Timer
l Watch-Dog Timer
l FLASH Disk

2.1 MICROPROCESSOR

The AR-B9612 use the ALI M6117 CPU, it is designed to
perform like Intel’s 386SX system with deep green features.

The 386SX core is the same as M1386SX of Acer Labs. Inc. and
100% object code compatible with the Intel 386SX
microprocessor. System manufacturers can provide 386
CPU based systems optimized for both cost and size.
Instruction pipelining and high bus bandwidth ensure short
average instruction execution times and high system throughput.
Furthermore, it can keep the state internally from charge leakage
while external clock to the core is stopped without storing the
data in registers. The power consumption here is almost zero
when clock stops. The internal structure of this core is 32-bit
data and address bus with very low supply current. Real
mode as well as protected mode are available and can run
MS-DOS, MS-Windows, OS/2 and UNIX.

AR-B9612 User’s Guide
2-1

2.2 DMA CONTROLLER

The equivalent of two 8237A DMA controllers are implemented
in the AR-B9612 card. Each controller is a four channel DMA
device which will generate the memory addresses and control
signals necessary to transfer information directly between a
peripheral device and memory. This allows high speed
information transfer with less CPU intervention. The two
DMA controllers are internally cascaded to provide four DMA
channels for transfers to 8-bit peripherals (DMA1) and three
channels for transfers to 16-bit peripherals (DMA2). DMA2
channel 0 provides the cascade interconnection between the two
DMA devices, thereby maintaining IBM PC/AT compatibility.

Following is the system information of DMA channels:

DMA Controller 1 DMA Controller 2

Channel 0: Spare Channel 4: Cascade for controller 1
Channel 1: IBM SDLC Channel 5: Spare
Channel 2: Diskette adapter Channel 6: Spare
Channel 3: Spare Channel 7: Spare

Table 2-1 DMA Channel Controller

2-2 AR-B9612 User’s Guide

2.3 I/O PORT ADDRESS MAP

Hex Range

000-01F DMA controller 1
020-021 Interrupt controller 1
022-023 ALI M6117 chipset address
040-04F Timer 1
050-05F Timer 2
060-06F 8042 keyboard/controller
070-071 Real-time clock (RTC), non-maskable interrupt (NMI)
080-09F DMA page registers

0A0-0A1 Interrupt controller 2

0C0-0DF DMA controller 2

0F0 Clear Math Co-processor
0F1 Reset Math Co-processor

0F8-0FF Math Co-processor

170-178 Fixed disk 1

1F0-1F8 Fixed disk 0

201 Game port
208-20A EMS register 0
218-21A EMS register 1

278-27F Parallel printer port 3 (LPT 3)

2E8-2EF Serial port 4 (COM 4)

2F8-2FF Serial port 2 (COM 2)

300-31F Prototype card/Streaming Type Adapter
378-37F Parallel printer port 2 (LPT 2)

380-38F SDLC, bisynchronous
3A0-3AF Bisynchronous
3B0-3BF Monochrome display and printer port 1 (LPT 1)
3C0-3CF EGA/VGA adapter
3D0-3DF Color/Graphics monitor adapter
3E8-3EF Serial port 3 (COM 3)

3F0-3F7 Diskette controller
3F8-3FF Serial port 1 (COM 1)

Table 2-2 I/O Port Address Map

Device

AR-B9612 User’s Guide
2-3

2.4 INTERRUPT CONTROLLER

IRQ9 : Rerouting to INT 0Ah from hardware IRQ2

The ALI’s M6 117 also provides two cascaded 8259 Programmable
Interrupt Controllers (PIC). They accept requests from peripherals,
resolve priorities on pending interrupts in service, issue interrupt
requests to the CPU, and provide vectors which are used as
acceptance indices by the CPU to determine which interrupt
service routine to execute.

Following is the system information of interrupt levels:

InInterrupt Level

Description

NMI
CTRL1

IRQ 0
IRQ 1
IRQ 2

IRQ 3
IRQ 4
IRQ 5
IRQ 6
IRQ 7

Parity check
CTRL2

System timer interrupt from timer 8254
Keyboard output buffer full

IRQ8 : Real time clock
IRQ10 : Spare

IRQ11 : Spare
IRQ12 : Spare
IRQ13 : Reserved for math. coprocessor

IRQ14 : Spare
IRQ15 : Reserved for watchdog

Serial port 2
Serial port 1
Spare
Spare
Spare

Figure 2-1 Interrupt Controller

2-4 AR-B9612 User’s Guide

2.5 SERIAL PORT

The ACEs (Asynchronous Communication Elements ACE1 to
ACE4) are used to convert parallel data to a serial format on the
transmit side and convert serial data to parallel on the receiver
side. The serial format, in order of transmission and reception, is
a start bit, followed by five to eight data bits, a parity bit (if
programmed) and one, one and half (five-bit format only) or two
stop bits. The ACEs are capable of handling divisors of 1 to
65535, and produce a 16x clock for driving the internal
transmitter logic.

Provisions are also included to use this 16x clock to drive the
receiver logic. Also included in the ACE is a complete MODEM
control capability, and a processor interrupt system that may be
software tailored to the computing time required to handle the
communications link.

The follows is summary of each ACE accessible registers

DLAB Port Address Register

Receiver buffer (read) 0 base + 0

Transmitter holding register (write)
0 base + 1 Interrupt enable
X base + 2 Interrupt identification (read only)
X base + 3 Line control
X base + 4 MODEM control
X base + 5 Line status
X base + 6 MODEM status
X base + 7 Scratched register
1 base + 0 Divisor latch (least significant byte)
1 base + 1 Divisor latch (most significant byte)

Table 2-3 ACE Accessible Register

AR-B9612 User’s Guide
2-5

(1) Receiver Buffer Register (RBR)

Bit 0-7: Received data byte (Read Only)

(2) Transmitter Holding Register (THR)

Bit 0-7: Transmitter holding data byte (Write Only)

(3) Interrupt Enable Register (IER)

Bit 0: Enable Received Data Available Interrupt (ERBFI)
Bit 1: Enable Transmitter Holding Empty Interrupt (ETBEI)
Bit 2: Enable Receiver Line Status Interrupt (ELSI)
Bit 3: Enable MODEM Status Interrupt (EDSSI)
Bit 4: Must be 0
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0

(4) Interrupt Identification Register (IIR)

Bit 0: “0” if Interrupt Pending
Bit 1: Interrupt ID Bit 0
Bit 2: Interrupt ID Bit 1
Bit 3: Must be 0
Bit 4: Must be 0
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0

(5) Line Control Register (LCR)

Bit 0: Word Length Select Bit 0 (WLS0)
Bit 1: Word Length Select Bit 1 (WLS1)

WLS1 WLS0 Word Length

0 0 5 Bits
0 1 6 Bits
1 0 7 Bits

1 1 8 Bits
Bit 2: Number of Stop Bit (STB)
Bit 3: Parity Enable (PEN)
Bit 4: Even Parity Select (EPS)
Bit 5: Stick Parity
Bit 6: Set Break
Bit 7: Divisor Latch Access Bit (DLAB)

2-6 AR-B9612 User’s Guide

(6) MODEM Control Register (MCR)

Bit 0: Data Terminal Ready (DTR)
Bit 1: Request to Send (RTS)
Bit 2: Out 1 (OUT 1)
Bit 3: Out 2 (OUT 2)
Bit 4: Loop
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0

(7) Line Status Register (LSR)

Bit 0: Data Ready (DR)
Bit 1: Overrun Error (OR)
Bit 2: Parity Error (PE)
Bit 3: Framing Error (FE)
Bit 4: Break Interrupt (BI)
Bit 5: Transmitter Holding Register Empty (THRE)
Bit 6: Transmitter Shift Register Empty (TSRE)
Bit 7: Must be 0

(8) MODEM Status Register (MSR)

Bit 0: Delta Clear to Send (DCTS)
Bit 1: Delta Data Set Ready (DDSR)
Bit 2: Training Edge Ring Indicator (TERI)
Bit 3: Delta Receive Line Signal Detect (DSLSD)
Bit 4: Clear to Send (CTS)
Bit 5: Data Set Ready (DSR)
Bit 6: Ring Indicator (RI)
Bit 7: Received Line Signal Detect (RSLD)

AR-B9612 User’s Guide
2-7

Generate 16x Clock

(9) Divisor Latch (LS, MS)

LS MS

Bit 0: Bit 0 Bit 8
Bit 1: Bit 1 Bit 9
Bit 2: Bit 2 Bit 10
Bit 3: Bit 3 Bit 11
Bit 4: Bit 4 Bit 12
Bit 5: Bit 5 Bit 13
Bit 6: Bit 6 Bit 14
Bit 7: Bit 7 Bit 15

Desired

Baud Rate

50 2304 --­75 1536 ---

110 1047 0.026

134.5 857 0.058
150 768 --­300 384 --­600 192 ---

1200 96 --­1800 64 --­2000 58 0.69
2400 48 --­3600 32 --­4800 24 --­7200 16 ---

9600 12 --­14400 8 --­19200 6 --­28800 4 --­38400 3 --­57600 2 ---

Table 2-4 Serial Port Divisor Latch

Divisor Used to

Present Error Difference

Between Desired and Actual

2-8 AR-B9612 User’s Guide

2.6 REAL-TIME CLOCK AND NON-VOLATILE
RAM

The AR-B9612 contains a real-time clock compartment that
maintains the date and time in addition to storing configuration
information about the computer system. It contains 14 bytes
of clock and registers and 50 bytes of general purpose RAM.
Because of the use of CMOS technology, it consumes very little
power and can be maintained for long period of time using an
internal lithium battery.

Address Description

00 Seconds
01 Second alarm
02 Minutes
03 Minute alarm
04 Hours
05 Hour alarm
06 Day of week
07 Date of month
08 Month

09 Year
0A Status register A
0B Status register B
0C Status register C
0D Status register D
0E Diagnostic status byte

0F Shutdown status byte

10 Diskette drive type byte, drive A and B

11 Fixed disk type byte, drive C

12 Fixed disk type byte, drive D

13 Reserved

14 Equipment byte

15 Low base memory byte

16 High base memory byte

AR-B9612 User’s Guide
2-9

Address Description

The output of this timer is tied to interrupt request 0.

plication programs can load different counts into

17 Low expansion memory byte

18 High expansion memory byte

19-2D Reserved
2E-2F 2-byte CMOS checksum

30 Low actual expansion memory byte

31 High actual expansion memory byte

32 Date century byte

33 Information flags (set during power on)

34-7F Reserved for system BIOS

Table 2-5 Real-Time Clock & Non-Volatile RAM

2.7 TIMER

The AR-B9612 provides three programmable timers, each with a
timing frequency of 1.19 MHz.

Timer 0

Timer 1 This timer is used to trigger memory refresh cycles.

Timer 2 This timer provides the speaker tone.

(IRQ 0)

Ap
this timer to generate various sound frequencies.

2-10 AR-B9612 User’s Guide