0.1 COPYRIGHT NOTICE AND DISCLAIMER............................................................................................................................ 3
0.2 WELCOME TO THE AR-B1550 CPU BOARD............................................................................................................................. 3
0.3 BEFORE YOU USE THIS GUIDE ............................................................................................................................................... 3
0.4 RETURNING YOUR BOARD FOR SERVICE ............................................................................................................................. 3
0.5 TECHNICAL SUPPORT AND USER COMMENTS..................................................................................................................... 3
1.2 PACKING LIST ........................................................................................................................................................................... 5
2. SYSTEM CONTROLLER..............................................................................................................................................6
2.5 SERIAL PORT............................................................................................................................................................................ 9
3. SETTING UP THE SYSTEM.......................................................................................................................................14
3.2 SYSTEM SETTING....................................................................................................................................................................14
3.2.1 Hard Disk (IDE) Connector (CN4)........................................................................................................................................15
3.2.4 Power Connector (J3)..........................................................................................................................................................16
3.2.5 CPU Select..........................................................................................................................................................................16
3.2.7 LED Header (J4) .................................................................................................................................................................17
3.2.8 USB Connector(CN6)-Reserved..........................................................................................................................................17
3.2.9 Ethernet LAN Jumper (JP3).................................................................................................................................................17
3.2.11 Test Jumper (JP4).............................................................................................................................................................18
3.2.13 Parallel Port Connector (CN2)...........................................................................................................................................19
5.2 STANDARD CMOS SETUP.......................................................................................................................................................24
5.3 BIOS FEATURES SETUP..........................................................................................................................................................26
5.4 CHIPSET FEATURES SETUP...................................................................................................................................................28
5.5 POWER MANAGEMENT...........................................................................................................................................................29
Multiple Monitor Support ..................................................................................................................................................................32
Video Memory Size..........................................................................................................................................................................32
5.9 IDE HDD AUTO DETECTION....................................................................................................................................................32
5.10.1 Save & Exit Setup .............................................................................................................................................................32
5.10.2 Exit Without Saving...........................................................................................................................................................32
APPENDIX A. ADDRESS MAPPING..........................................................................................................................33
Appendix b. INTERRUPT REQUEST (IRQ)……………………..……………………………………………………………..35
2
AR-B1550 User’s Guide
0.PREFACE
0.1 COPYRIGHT NOTICE AND DISCLAIMER
September 2000
Acrosser Technology makes no representations or warranties with respect to the contents hereof and specifically
disclaims any implied warranties of merchantability or fitness for any particular purpose. Furthermore, Acrosser
Technology reserves the right to revise this publication and to make changes from time to time in the contents
hereof without obligation of Acrosser Technology to notify any person of such revisions or changes. Changes will
be posted on the Internet (WWW.ACROSSER.COM) as soon as possible, but there is obligation on the part of
Acrosser to this fact.
Possession, use, or copying of the software described in this publication is authorized only pursuant to a valid
written license from Acrosser or an authorized sublicensor.
(C) Copyright Acrosser Technology Co., Ltd., 2000. All rights Reserved.
No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated
into any language or computer language, in any form or any means, electronic, mechanical, magnetic, optical,
chemical, manual or otherwise, without the prior written consent of Acrosser Technology.
Acrosser, AMI, IBM PC/AT, ALI, Windows 3.1, MS-DOS, …are registered trademarks.
All other trademarks and registered trademarks are the property of their respective holders.
0.2 WELCOME TO THE AR-B1550 CPU BOARD
This guide introduces the Acrosser AR-B1550 CPU board.
The following information describes this card’s functions, features, and how to start, set up and operate your ARB1550. General system information can also be found here.
0.3 BEFORE YOU USE THIS GUIDE
If you have not already installed this AR-B1550, refer to the Chapter 3, “Setting Up The System” in this guide.
Check the packing list, make sure the accessories are complete.
The AR-B1550 diskette provides the newest information about the card. Please refer to the files of the enclosed utility diskette. It contains the modification, hardware & software information, and it has updates to
product functions that may not be mentioned here.
0.4 RETURNING YOUR BOARD FOR SERVICE
If your board requires servicing, contact the dealer from whom you purchased the product for service information.
If you need to ship your board to us for service, be sure it is packed in a protective carton. We recommend that
you keep the original packaging for this purpose.
You can assure efficient servicing of your product by following these guidelines:
1. Include your name, address, daytime telephone and facsimile numbers and E-mail.
2. A description of the system configuration and/or software at the time is malfunction,
3. And a brief description of the symptoms.
0.5 TECHNICAL SUPPORT AND USER COMMENTS
User’s comments are always welcome as they assist us in improving the usefulness of our products and the
understanding of our publications. They form a very important part of the input used for product enhancement
and revision.
We may use and distribute any of the information you supply in any way we believe appropriate without incurring
any obligation. You may, of course, continue to use the information you supply.
If you have suggestions for improving particular sections or if you find any errors, please indicate the manual title
and book number.
Please send your comments to Acrosser Technology Co., Ltd. or your local sales representative.
Internet electronic mail to: webmaster@acrosser.com
Check our FAQ sheet for quick fixes to known technical problems.
3
AR-B1550 User’s Guide
0.6 ORGANIZATION
This manual covers the following topics (see the Table of Contents for a detailed listing):
l Chapter 1, “Overview”, provides an overview of the system features and packing list.
l Chapter 2, “System Controller” describes the major structure.
l Chapter 3, “Setting Up the System”, describes how to adjust the jumper, and the connector’s settings.
l Chapter 4, “Installation”, describes setup procedures including information on the utility diskette.
l Chapter 5, “BIOS Console”, provides the BIOS options settings.
0.7 STATIC ELECTRICITY PRECAUTIONS
Before removing the board from its anti-static bag, read this section about static electricity precautions.
Static electricity is a constant danger to computer systems. The charge that can build up in your body may be
more than sufficient to damage integrated circuits on any PC board. It is, therefore, important to observe basic
precautions whenever you use or handle computer components. Although areas with humid climates are much
less prone to static build-up, it is always best to safeguard against accidents that may result in expensive repairs.
The following measures should be sufficient to protect your equipment from static discharge:
• Touch a grounded metal object to discharge the static electricity in your body (or ideally, wear a grounded
wrist strap).
• When unpacking and handling the board or other system components, place all materials on an anti-static
surface.
• Be careful not to touch the components on the board, especially the “golden finger” connectors on the bottom
of the board.
4
AR-B1550 User’s Guide
1. OVERVIEW
This is a AR-B1550 Pentium Grade Firewall CPU Board with Ethernet, DOM.
This chapter provides an overview of your system features and capabilities. The following topics are covered:
l Specification
l Packing List
l Features
1.1 SPECIFICATION
l CPU : NS GEODE GX1/GXLV
l Chipset:Cyrix CS5530
l RAM Memory:Onboard 32MB/64MB/128MB SDRAM
l Flash Disk:Supports one socket for DiskOnModule
l Ethernet:3 x 10M/100M-Base2 with RJ-45 connector (PCI BUS)
l BIOS:AMI or AWARD flash BIOS
l RTC:BQ3287MT Chips (RESERVED)
l Speaker:Supports external speaker
l LED Indicator:Power, HD and LAN LEDs
l Jumper:3 x 2 Jumper select base clock and CPU clock multiplier
l Power Connector:One 8-pin 2.5mm JST
l Power Req.:5V, 2.5A
l PC Board:6 layers,EMI considered
l Dimensions:145 mm x 102 mm
1.2 PACKING LIST
Some accessories are included with the system. Before you begin installing your AR-B1550 board, take a moment
to make sure that the following items have been included inside the AR-B1550 package.
l The quick setup manual
l 1 AR-B1550 all-in-one single CPU board
l AR-B9459 I/O Board (extension card)
l Software utility diskettes.
1.3 FEATURES
The system provides a number of special features that enhance its reliability, ensure its long-term availability, and
improve its expansion capabilities, as well as its hardware structure.
l CPU NS GEODE GX1/GXLV
l Cyrix CS5530 Chipset
l Onboard 32MB/64MB SDRAM
l Supports DOM Flash Disk
l 3 x 10/100M-Base2 Ethernet
l AMI or AWARD flash BIOS
l Power Req.: 5V, 2.5A
l Dimensions: 145 mm x 102 mm
5
AR-B1550 User’s Guide
2. SYSTEM CONTROLLER
This chapter describes the main structure of the AR-B1550 CPU board. The following topics are covered:
l Microprocessors
l DMA Controller
l Keyboard Controller
l Interrupt Controller
l Serial Port
l Parallel Port
2.1 MICROPROCESSOR
The AR-B1550 uses the NS GEODE GX1/GXLV CPU (or other GXM CPUs), it is an advanced 32-bit x86
compatible processor offering high performance, fully accelerated 2D graphics, a 64-synchronous DRAM controller
and a PCI bus controller, all on a single chip. This latest generation of the MediaGX processor enables a new
class of premium performance notebook/desktop, and IPC computer designs.
The MediaGX MMX enhanced processor companion chips provide advanced video and audio functions and permit
direct interface to memory. This high-performance 64-bit processor is x86 instruction set compatible and supports
MMX technology.
This processor is the latest member of the NS MediaGX family, offering high performance, fully accelerated 2D
graphics, synchronous memory interface and a PCI bus controller, all on a single chip. As described in separate
manuals, the CS5520 and the CS5530 I/O Companion chips fully enable the features of the MediaGX processor
with MMX support. These features include full VGA and VESA video, 16-bit stereo sound, IDE interface, ISA
interface, SMM power management, and AT compatibility logic. In addition, the newer CS5530 provides an Ultra
DMA/33 interface, MPEG2 assist, and is AC97 Version 2.0 audio compliant.
In addition to the advanced CPU features, the MediaGX processor integrates a host of functions which are typically
implemented with external components. A full-function graphics accelerator provides pixel processing and
rendering functions.
The NS MediaGX MMX-Enhanced Processor represents a new generation of x86-compatible 64-bit
microprocessors with sixth-generation features. The decoupled load/store unit (within the memory management
unit) allows multiple instructions in a single clock cycle. Other features include single-cycle execution, single-cycle
instruction decode, 16KB write-back cache, and clock rates up to 266MHz. These features are possible by the use
of advanced-process technologies and superpipelining.
2.2 DMA CONTROLLER
The equivalent of two 8237A DMA controllers are implemented on the AR-B1550 board. Each controller is a fourchannel DMA device that will generate the memory addresses and control signals necessary to transfer
information directly between a peripheral device and memory. This allows high-speed information transfer with less
CPU intervention. The two DMA controllers are internally cascaded to provide four DMA channels for transfers to
8-bit peripherals (DMA1) and three channels for transfers to 16-bit peripherals (DMA2). DMA2 channel 0 provides
the cascade interconnection between the two DMA devices, thereby maintaining IBM PC/AT compatibility.
The Following is the system information for the DMA channels:
Slave with four 8-bit chnls Master with three 16-bit chnls
The 8042 processor is programmed to support the keyboard serial interface. The keyboard controller receives
serial data from the keyboard, checks its parity, translates scan codes, and presents it to the system as a byte data
in its output buffer. The controller can interrupt the system when data is placed in its output buffer, or wait for the
system to poll its status register to determine when data is available.
Data can be written to the keyboard by writing data to the output buffer of the keyboard controller.
Each byte of data is sent to the keyboard controller in a series with an odd parity bit automatically inserted. The
keyboard controller is required to acknowledge all data transmissions. Therefore, another byte of data will not be
sent to keyboard controller until acknowledgment is received for the previous byte sent. The “output buffer full”
interruption may be used for both send and receive routines.
2.4 INTERRUPT CONTROLLER
The equivalent of two 8259 Programmable Interrupt Controllers (PIC) are included on the AR-B1550 board. They
accept requests from peripherals, resolve priorities on pending interrupts in service, issue interrupt requests to the
CPU, and provide vectors which are used as acceptance indices by the CPU to determine which interrupt service
routine to execute. These two controllers are cascaded with the second controller representing IRQ8 to IRQ15,
which is rerouted through IRQ2 on the first controller.
The following is the system information of interrupt levels:
Interrupt LevelDescription
NMIParity check
CTRL1
CTRL2
IRQ0
IRQ1
IRQ2
IRQ3Serial port(depends on setup assignment)
IRQ4Serial port(depends on setup assignment)
IRQ5Reserved
IRQ6Reserved for floppy disk adapter
IRQ7Parallel port 1
keyboard output buffer full
Rerouting to IRQ8 to IRQ15
IRQ8:Real time clock
IRQ9:Reserved
IRQ10:LAN adapters(based on PCI INT routing)
IRQ11:LAN adapters(based on PCI INT routing)
IRQ12:Reserved for PS/2 mouse
IRQ13:Math.Co-processor
IRQ14:Hard disk adapter
IRQ15:LAN adapters(based on PCI INT routing
0F0 Clear Math Co-processor
0F1 Reset Math Co-processor
0F8-0FF Math Co-processor
170-178 Reserved for Fixed disk 1
1F0-1F8 Fixed disk 0
201 Reserved for Game port
208-20A EMS register 0
218-21A EMS register 1
278-27F Parallel printer port (depends on setup assignment)
2E8-2EF Serial port (depends on setup assignment)
2F8-2FF Serial port (depends on setup assignment)
300-31F Prototype card/streaming type adapter
320-33F Reserved
378-37F Parallel printer port (depends on setup assignment)
380-38F SDLC, bisynchronous
3A0-3AF Bisynchronous
3B0-3BF Monochrome display and printer port 3 (LPT 3)
3C0-3CF EGA/VGA adapter
3D0-3DF Color/graphics monitor adapter
3E8-3EF Serial port 3 (depends on setup assignment)
3F0-3F7 Reserved for diskette controller
3F8-3FF Serial port (depends on setup assignment)
I/O Port Address Map
Device
2.4.2 Real-Time Clock and Non-Volatile RAM
The AR-B1550 contains a real-time clock compartment that maintains the date and time in addition to storing
configuration information about the computer system. It contains 14 bytes of clock and control registers and
114 bytes of general purpose RAM. Because of the use of CMOS technology, it consumes very little power
and can be maintained for long periods of time using an internal Lithium battery. The contents of each byte in
the CMOS RAM are listed as follows:
8
Address Description
00 Seconds
01 Second alarm
02 Minutes
03 Minute alarm
04 Hours
05 Hour alarm
06 Day of week
07 Date of month
08 Month
09 Year
0A Status register A
0B Status register B
0C Status register C
0D Status register D
0E Diagnostic status byte
0F Shutdown status byte
10 Diskette drive type byte, drive A and B
11 Fixed disk type byte, drive C
12 Fixed disk type byte, drive D
13 Reserved
14 Equipment byte
15 Low base memory byte
16 High base memory byte
17 Low expansion memory byte
18 High expansion memory byte
19-2D Reserved
2E-2F 2-byte CMOS checksum
30 Low actual expansion memory byte
31 High actual expansion memory byte
32 Date century byte
33 Information flags (set during power on)
34-7F Reserved for system BIOS
Real-Time Clock & Non-Volatile RAM
AR-B1550 User’s Guide
2.4.3 Timer
The AR-B1550 provides three programmable timers, each with a timing frequency of 1.19 MHz.
Timer 0 The output of this timer is tied to interrupt request 0. (IRQ 0)
Timer 1 This timer is used to trigger memory refresh cycles.
Timer 2 This timer provides the speaker tone.
Application programs can load different counts into this timer to generate various sound frequencies.
2.5 SERIAL PORT
The ACEs (Asynchronous Communication Elements ACE1 to ACE4) are used to convert parallel data to a serial
format on the transmit side and convert serial data to parallel on the receiver side. The serial format, in order of
transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one,
1.5 (in a five-bit format only) or two stop bits(in a 6,7, or 8-bit format). The ACEs are capable of handling divisors of
1 to 65535, and produce a 16x clock for driving the internal transmitter logic.
Provisions are also included to use this 16x clock to drive the receiver logic. Also included in the ACE a completed
MODEM control capability, and a processor interrupt system that may be software tailored to the computing time
9
AR-B1550 User’s Guide
WLS1
WLS0
Word Length
required to handle the communications link.
The following table is a summary of each ACE accessible register
0 base + 1 Interrupt enable
X base + 2 Interrupt identification (read only)
X base + 3 Line control
X base + 4 MODEM control
X base + 5 Line status
X base + 6 MODEM status
X base + 7 Scratched register
1 base + 0 Divisor latch (least significant byte)
1 base + 1 Divisor latch (most significant byte)
ACE Accessible Registers
(1) Receiver Buffer Register (RBR)
Bit 0-7: Received data byte (Read Only)
(2) Transmitter Holding Register (THR)
Bit 0-7: Transmitter holding data byte (Write Only)
(3) Interrupt Enable Register (IER)
Bit 0: Enable Received Data Available Interrupt (ERBFI)
Bit 1: Enable Transmitter Holding Empty Interrupt (ETBEI)
Bit 2: Enable Receiver Line Status Interrupt (ELSI)
Bit 3: Enable MODEM Status Interrupt (EDSSI)
Bit 4: Must be 0
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0
(4) Interrupt Identification Register (IIR)
Bit 0: “0” if Interrupt Pending
Bit 1: Interrupt ID Bit 0
Bit 2: Interrupt ID Bit 1
Bit 3: Must be 0
Bit 4: Must be 0
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0
(5) Line Control Register (LCR)
Bit 0: Word Length Select Bit 0 (WLS0)
Bit 1: Word Length Select Bit 1 (WLS1)
0 0 5 Bits
0 1 6 Bits
1 0 7 Bits
1 1 8 Bits
Bit 2: Number of Stop Bit (STB)
Bit 3: Parity Enable (PEN)
Bit 4: Even Parity Select (EPS)
Bit 5: Stick Parity
Bit 6: Set Break
Bit 7: Divisor Latch Access Bit (DLAB)
Register
10
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