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AR-B1380/AR-B1380A
Half Size All-In-One
386SX CPU CARD
User’s Guide
Edition: 1.2
Book Number: AR-B1380-02.0801
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AR-B1380/AR-B1380A User’s Guide
Table of Contents
0.
1.
2.
3.
4.
5.
PREFACE...........................................................................................................................................................3
0.1 COPYRIGHT NOTICE AND DISCLAIMER............................................................................................................................ 3
0.2 WELCOME TO THE AR-B1380/1380A CPU BOARD............................................................................................................ 3
0.3 BEFORE YOU USE THIS GUIDE..........................................................................................................................................3
0.4 RETURNING YOUR BOARD FOR SERVICE........................................................................................................................ 3
0.5 TECHNICAL SUPPORT AND USER COMMENTS................................................................................................................ 3
0.6 ORGANIZATION................................................................................................................................................................... 4
0.7 STATIC ELECTRIC ITY PRECAUTIONS...............................................................................................................................4
OVERVIEW.........................................................................................................................................................5
1.1 INTRODUCTION................................................................................................................................................................... 5
1.2 PACKING LIST...................................................................................................................................................................... 5
1.3 FEATURES........................................................................................................................................................................... 6
SYSTEM CONTROLLER ...................................................................................................................................7
2.1 MICROPROCESSOR............................................................................................................................................................ 7
2.2 DMA CONTROLLER............................................................................................................................................................. 7
2.3 KEYBOARD CONTROLLER................................................................................................................................................. 8
2.4 INTERRUPT CONTROLLER................................................................................................................................................. 8
2.4.1 I/O Port Address Map ................................................................................................................................................... 9
2.4.2 I/O Channel Pin Assignment (Bus1)............................................................................................................................ 10
2.5 REAL-TIME CLOCK AND NON-VOLATILE RAM................................................................................................................ 11
2.6 TIMER................................................................................................................................................................................. 12
2.7 SERIAL PORTS.................................................................................................................................................................. 12
2.8 PARALLEL PORT............................................................................................................................................................... 15
2.9 SOLID STATE DISKS.......................................................................................................................................................... 16
2.10 ETHERNET CONTROLLER ................................................................................................................................................ 16
2.11 VGA CONTROLLER............................................................................................................................................................ 16
SETTING UP THE SYSTEM.............................................................................................................................17
3.1 OVERVIEW......................................................................................................................................................................... 17
3.2 INDEX OF THE CONNECTORS AND JUMPERS ............................................................................................................... 17
3.2 INDEX OF THE CONNECTORS AND JUMPERS ............................................................................................................... 18
3.3 SYSTEM SETTING ................................................................................................................................................................... 18
3.3.1 CN1: Hard Disk Drive Connector................................................................................................................................ 20
3.3.2 CN2: Floppy Disk Drive Connector............................................................................................................................. 21
3.3.3 CN3: Parallel Port Connector ..................................................................................................................................... 21
3.3.4 CN6: Ethernet RJ-45 Header...................................................................................................................................... 22
3.3.5 CN7 & CN8: PC/104 Connector ................................................................................................................................. 22
3.3.6 PS/2 Keyboard and Mouse......................................................................................................................................... 25
3.3.7 Power Connector....................................................................................................................................................... 26
3.3.8 J5: External Speaker Header...................................................................................................................................... 26
3.3.9 J7: Reset Header....................................................................................................................................................... 26
3.3.10 Board Battery Configuration................................................................................................................................. 27
3.3.11 JP3: CPU Base Clock Selector............................................................................................................................ 27
3.3.12 Serial Port........................................................................................................................................................... 29
3.3.13 LED Headers and Indicator.................................................................................................................................. 30
3.3.14 DRAM Configuration............................................................................................................................................ 31
CRT/LCD FLAT PANEL DISPLAYS................................................................................................................32
4.1 DB1: CRT CONNECTOR.................................................................................................................................................... 32
4.2 LCD FLAT PANEL DISPLAY..................................................................................................................................................... 32
4.2.1 Inverter Board Description.......................................................................................................................................... 33
4.2.2 LCD Settings and Connectors..................................................................................................................................... 33
4.3 SUPPORTED LCD PANELS..................................................................................................................................................... 36
SOFTWARE INSTALLATION..........................................................................................................................37
5.1 OVERVIEW......................................................................................................................................................................... 37
5.2 UTILITY DISKETTE............................................................................................................................................................. 38
5.2.1 VGA Driver................................................................................................................................................................. 38
5.2.2 SSD Utility.................................................................................................................................................................. 38
5.3 WRITE PROTECT FUNCTION............................................................................................................................................ 41
5.3.1 Hardware Write Pr otect.............................................................................................................................................. 41
5.3.2 Software Write Pr o tect ............................................................................................................................................... 41
5.3.3 Enable the Software Write Protect.............................................................................................................................. 41
5.3.4 Disable the Software Write Protect............................................................................................................................. 41
5.4 WATCHDOG TIMER........................................................................................................................................................... 42
5.4.1 Acrosser’s Watchdog Timer Program.............................................................................................. ........................... 42
5.4.2 Built-in Watchdog Timer............................................................................................................................................. 44
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AR-B1380/AR-1380A User’s Guide
5.4.3 INDEX 38H: WD Report register -.............................................................................................................................. 45
6. SOLID STATE DISK...................................................................................................................................................48
6.1 OVERVIEW............................................................................................................................................................................... 48
6.2 SWITCH SETTING .............................................................................................................................................................. 48
6.2.1 Overview.................................................................................................................................................................... 49
6.2.2 SW2-1 & SW2-2: I/O Port Address Setup................................................................................................................... 49
6.2.3 SSD & D.O.C. Setup.................................................................................................................................................. 49
6.2.4 SW2-5 & SW2-6: SSD Drive Number Selector ........................................................................................................... 50
6.2.5 SW2-7 & SW2-8: ROM Type Select........................................................................................................................... 52
6.3 M1-M3: MEMORY TYPE SETTINGS................................................................................................................................... 52
6.4 ROM DISK INSTALLATION.................................................................................................................................................54
6.4.1 UV EPROM (27Cxxx)......... ........................................................................................................................................ 54
6.4.2 Large Page 5V FLASH Disk....................................................................................................................................... 55
6.4.3 Small Page 5V FLASH ROM Disk.............................................................................................................................. 57
6.4.4 RAM Disk................................................................................................................................................................... 59
6.4.5 Combination of ROM and RAM Disk.......................................................................................................................... 60
7. BIOS CONSOLE........................................................................................................................................................61
7.1 BIOS SETUP OVERVIEW......................................................................................................................................................... 61
7.2 STANDARD CMOS SETUP ...................................................................................................................................................... 62
7.3 ADVANCED CMOS SETUP...................................................................................................................................................... 63
7.4 ADVANCED CHIPSET SETUP............................................................................................................................................ 66
7.5 PERIPHERAL SETUP............................................................................................................................................................... 68
7.6 PASSWORD SETTING............................................................................................................................................................. 70
7.6.1 Setting Password........................................................................................................................................................ 70
7.6.2 Passwo r d Ch e ckin g.................................................................................................................................................... 70
7.7 LOAD DEFAULT SETTING....................................................................................................................................................... 70
7.7.1 Auto Config u r a tio n w ith O p timal Setting...................................................................................................................... 70
7.7.2 Auto Config u r a tio n w ith Fa il Sa fe Se tting.................................................................................................................... 70
7.8 BIOS EXIT ................................................................................................................................................................................ 70
7.8.1 Save Settings and Exit................................................................................................................................................ 71
7.8.2 Exit Without Saving..................................................................................................................................................... 71
7.9 BIOS UPDATE.......................................................................................................................................................................... 71
8. SPECIFICATIONS & SSD TYPES SUPPORTED......................................................................................................73
8.1 SPECIFICATIONS.................................................................................................................................................................... 73
8.2 SSD TYPES SUPPOR TED................................................................................................................................................. 74
9. USING MEMORY BANKS..........................................................................................................................................76
10. PLACEMENT & DIMENSIONS.................................................................................................................................78
10.1 PLACEMENT.......................................................................................................................................................................... 78
10.2 DIMENSIONS.....................................................................................................................................................................78
11. PROGRAMMING THE RS-485.................................................................................................................................79
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AR-B1380/AR-B1380A User’s Guide
0. PREFACE
0.1 COPYRIGHT NOTICE AND DISCLAIMER
November 1999
This document is copyrighted, 1999, by Acros ser Technology Co., Ltd. All rights are reserved. No part of
this manual ma y be reproduced, copied, transcribed, stored in a retrieval system , or translated into any
language or computer language in any form or by any means, s uch as electronic, mechanical, m agnetic,
optical, chemical, manual or other means without the prior written permission of original manufacturer.
Acrosser technolog y assum es no responsibilit y or warr anty with respec t to the conte nts in this m anual and
specifically disclaims any implied warranty of merchantability or fitness for any particular purpose.
Furthermore, Acr osser Technology reserves the ri ght to make improvements to the products described in
this manual at any times without notice. Such revision will be posted on the Internet
(WWW.ACROSSER.COM
Possession, use, or copying of the soft ware described in th is publication is a uthorized only pursuant to a
valid written license from Acrosser or an authorized sub licensor.
ACKNOWLEDGEMENTS
Acrosser, ALI, AMI, PC/AT, WIN31, WIN 95, Windows NT, NEC, HITACHI, ORION, SHARP, FUJITSU, SONY,
AKM , I N TE L , M I TS U B I S H I , N S , S GS - TH O M S O N , TI , TO S H I B A , A M D… a r e registered trademarks.
All other trademarks and registered trademarks are the property of their respective holders.
This document is produced with Adobe Acrobat 3.01.
) as soon as possible.
0.2 WELCOME TO THE AR-B1380/1380A CPU BOARD
This guide introduces the Acrosser AR-B1380/1380A CPU BOARD. The information provided in this manual
describes in this card’s functions, features. It also helps you s tar t, s et up a nd op erate your AR-B1380/ 138 0A.
General system information can also be found in this publication.
0.3 BEFORE YOU USE THIS GUIDE
Please refer to C hapter 3, “Sett ing up the Syst em” in this gui de, if you have not already i nstalled this ARB1380/1380A. Check the packing list before you ins tall and make sure all the ac cessories are included in
the package.
The AR-B1380/1380A CD provides the newest information regardin g the CPU card. Please refer to the
README.DOC file of the en closed utilit y diskette. It conta ins th e modification and har d ware & s of t war e
information, and it has updates to product functions that may not be mentioned here.
0.4 RETURNING YOUR BOARD FOR SERVICE
If your board requires any services, contact the distributor or sales representative from whom you
purchased the produc t for service inform ation. If you need to ship your board to us f or service, be sur e it is
packed in a protec tive c ar t on. We recommend that you keep the orig in al s hip pi ng c onta iner f or th is p urpos e.
You can help assure efficient servicing for your product by following these guidelines:
1. Include your name, address, telephone, facsimile number and e-mail.
2. A description of the system configuration and/or software at the time of malfunction.
3. A brief description of problem occurred.
0.5 TECHNICAL SUPPORT AND USER COMMENTS
User’s comm ents are always welcome as the y assist us in improving th e quality of our products a nd the
readability of our publications. They create a very important part of the input used for product enhancement
and revision.
We may use and distribute an y of the information you provide in any way approp riate without incurr ing any
obligation. You may, of course, continue to use the information you provide.
If you have any suggestio ns for improving particular sections or if you find any errors, please send your
comments to Acros ser Techno logy Co., Ltd . or your lo cal sales r epresentat ive and ind icate the m anual tit le
and book number.
Internet electronic mail to: webmaster@acrosser.com
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AR-B1380/AR-1380A User’s Guide
0.6 ORGANIZATION
This manual covers the following topics (see the Table of Contents for a detailed listing):
Chapter 1, “Overview,” provides an overview of the system features and packing list.
!
Chapter 2, “System Controllers,” describes the major structure.
!
Chapter 3, “Setting Up the System,” describes how to adjust the jumpers, and the connector
!
settings.
Chapter 4, “CRT/LCD Flat Panel Displays”, describes the configuration and installation
!
procedure by using LCD and CRT displays.
Chapter 5, “Software Installation,” describes the utility diskette, solid-state disk’s write protect
!
function, and the watchdog timer.
Chapter 6, “Solid State Disk,” describes the various types of SSD’s installation methods.
!
Chapter 7, “BIOS Console,” providing the BIOS settings.
!
Chapter 8, Specifications & SSD Types Supported
!
Chapter 9, Using the Memory Banks
!
Chapter 10, Placement & Dimensions
!
Chapter 11, Programming the RS-485
!
0.7 STATIC ELECTRICITY PRECAUTIONS
Before removing the board from its anti-static bag, read this section about static electricity precautions.
Static electricit y is a constant dan ger to computer systems. The c harge that can build up in your body m ay
be more than suff ic ient to d amage integrated c irc uits on any PC board. It is, therefore, important to observe
basic precautions wh enever you use or han dle computer components. Alth ough areas with hum id clim ates
are much less prone to static build-up, it is always best to safeguard aga inst accidents that ma y result in
expensive repairs. T he following measures shou ld generally be sufficient to protect your equipment from
static discharge:
(1) Touch a grounded metal object to discharge the static electricity in your body (or ideally, wear a
grounded wrist strap).
(2) When unpacking a nd handling the board or other system com ponents, place all materials o n an antic
static surface.
(3) Be careful not t o touch the com ponents on the bo ard, especially the “ golden finger” conn ectors on the
bottom of every board.
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AR-B1380/AR-B1380A User’s Guide
1. OVERVIEW
This chapter provides an overview of your system features and capabilities. The following topics are
covered:
! Introduction
! Packing List
! Features
1.1 INTRODUCTION
The AR-B1380/AR-B1380A is a new generation half size, 386 ISA interface card. This card offers much greater
performance than the older cards such as support for 20MB DRAM using one 72-pin SIMM bank, 42 pin two SOJ
one RS-232C/485 connector and one RS-232C port and 3MB/1.5MB/1.5MB solid state disk capacity for EPROM,
FLASH and SRAM.
The 6 layer PCB CPU board is equipped with an IDE HDD interface, a floppy disk interface, 1 parallel port, and 2
serial ports and a watchdog timer. It provides 2 bus interfaces, ISA bus and a PC/104 compatible expansion bus.
Based on the PC/104 expansion bus, you could easily install numerous PC/104 modules. This 386 CPU card is
excellent for embedded systems, MMI’s, workstations, medical applications or POS/POI systems. As well, an RS232C/485 port is provided for remote control capabilities. RS-485 has not been offered until recently on 386 cards.
A watchdog timer, which has a software programmable time-out interval, is also provided on this CPU card. It
ensures that the system does not hang up if a program cannot execute normally.
For diskless application, the AR-B1380/AR-B1380A provides up to 3 MB of bootable EPROM, FLASH, or SRAM
disk by using 64Kx8 to 1Mx8 memory chips.
The AR-B1380A has VGA and LAN onboard, and offers the most exciting possibilities yet to the industry. The
onboard VGA/LCD controller brings about a whole new dimension of industrial computing. No longer do you have
to worry about adding an extra card to your system. Eliminating the need for a separate VGA card saves space.
The VGA/LCD unit comes with 1MB of V-RAM on board and uses the C&T 65545 Chipset , to suppo rt a wi de range
of LCD Panels.
1.2 PACKING LIST
These accessories are included with the system. Before you begin installing your AR-B1380/A R-B1380A
CPU board, take a moment to make sure that the following items have been included inside the ARB1380/AR-B1380A package.
For the AR-B1380 package, it includes
AR-B1380 Accessories Description
1 Quick setup guide Introduction of the hardware features of AR-B1380
1 AR-B1380 ISA interface CPU board Well protected in the anti-static bag.
1 Hard diskette drive cable 2.54 mm 40 pin IDC type cable
1 Floppy disk drive interface cable 34 pin IDC type cable
1 Parallel port interface cable 26 pin Mini-IDC to DB-25 female
1 RS-232C interface cable + PS/2 Mouse 10 pin IDC to DB-9 male + PS2 Mouse
1 Software Utility CD Manual file in PDF format & S.S.D. utility
Table 1-1 AR-B1380 Packing List
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AR-B1380/AR-1380A User’s Guide
AR-B1380A Accessories Description
1 Quick setup guide Introduction of the hardware features of AR-B1380A
1 AR-B1380A ISA interface CPU
Well protected in the anti-static bag.
board
1 Hard diskette drive cable 2.54 mm 40 pin IDC type cable
1 Floppy disk drive interface cable 34 pin IDC type cable
1 Parallel port interface cable 26 pin Mini-IDC to DB-25 female cable
1 RS-232C interface cable+ PS2
10 pin IDC to DB-9 male + PS2 Mouse
Mouse
2 Software Utility CD Manual file in PDF format, S.S.D. utility and VGA and
Ethernet drivers
Table 1-2 AR-B1380A Packing List
1.3 FEATURES
This system prov ides a number of special f eatures that enhance its reliab ility, ensure its availabilit y, and
improve its expansion capabilities, as well as its hardware structure.
ALI M6117C, 80386SX-25/33/40 MHz CPU (33 MHz CPU is standard)
!
ISA and non-stack through PC/104 extension bus
!
2 MB DRAM onboard system with a DRAM socket and SIMM bank for expansion
!
On-board CRT and LCD panel displays (available for AR-B1380A only)
!
Supports 2 IDE hard disk drive
!
Supports 8-pin/4pin 2.5mm connector
!
Supports 2 floppy disk drives with 34-pin 2.54mm connector (for 1380 only)
!
Supports 1 SPP/EPP/ECP mode parallel port
!
Supports 1 RS-232C and 1 RS-232C/RS-485 serial ports
!
On-board Ethernet compatible 10 Base-T NE2000; shielded RJ-45 edge connector (for 1380A )
!
PS/2 keyboard and mouse
!
3 sockets for up to 3MB/1.5MB / 1.5MB EPROM/FLASH/SRAM
!
Supports 1 DiskOnChip
!
Onboard buzzer or an external speaker with a 4-pin header
!
Programmable watchdog timer
!
8 TTL level loads maximum (8 mil trace minimum)
!
AMI Flash BIOS
!
Built-in watchdog and power LEDs and 2 headers for external PW/WD and HDD LEDs
!
Signal 5V power requirement
!
Multi-layer PCB for noise reduction
!
Dimensions: 185mmX122mm (7.28” x 4.80”)
!
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AR-B1380/AR-B1380A User’s Guide
2. SYSTEM CONTROLLER
This chapter desc ribes the m ajor structure of the AR-B1380/ AR-B1380A CPU b oard. The foll owing topics
are covered:
Microprocessor
!
DMA Controller
!
Keyboard Controller
!
Interrupt Controller
!
Real-Time Clock and Non-Volatile RAM
!
Timer
!
Serial Port
!
Parallel Port
!
Solid State Disks
!
Ethernet Controller
!
VGA Controller
!
2.1 MICROPROCESSOR
The AR-B1380/AR-B138 0A uses the ALI M61 17 CPU. It is des igned to perform like Intel’s 386SX s ystem
with deep green features.
The 386SX core is th e sam e as th e M138 6SX of Acer Labs. I nc. an d 10 0% obje ct cod e comp at ible wit h
th e I n t e l 3 8 6 S X m icroprocess or. System m anufacturers can pro vide 386 CPU based system s optimized
for both cost and size. Instruction pipelining and high bus bandwidth ensure short average instruction
execution times and high system throughput. Furthermore, it can minimize charge leakage while the
external clock is stopped, without stor ing t he data in r egisters . The po wer c onsu m ption here is alm ost zer o
when the clock stops. The internal structure of this core is 32-bit and it’s address bus with a very low
supply current. Real m ode as well as protected mode are av ailable and can run MS-DO S, MS-Windows,
OS/2 and UNIX.
2.2 DMA CONTROLLER
The equivalent of two 8237A DMA co ntrollers are implem ented in the AR-B13 80/AR-B1380A CPU board.
Each controller is a four-channe l DMA de vice that will generate t he mem ory addresses and control si gnals
necessary to transfer information directl y between a peripheral device and memory. This allows high-speed
information transfer with less CPU intervention. The two DMA c ontr ollers ar e internal ly cascade d to pro vide
four DMA channels for transfers to 8-bit peripherals (DMA1) and three channels for transfers to 16-bit
peripherals (DMA2) . DM A 2 chan nel 0 provides t he c asc ade inter c o nnect ion be tween the two D MA de vic es ,
thereby maintaining IBM PC/AT compatibility.
The following is the system DMA channel.
DMA Controller 1 DMA Controller 2
Channel 0: Spare Channel 4: Cascade for controller 1
Channel 1: IBM SDLC Channel 5: Spare
Channel 2: Diskette adapter Channel 6: Spare
Channel 3: Spare Channel 7: Spare
Table 2-1 DMA Channel Controller
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2.3 KEYBOARD CONTROLLER
The 8042 processor is programmed to support a keyboard serial interface. The keyboard controller
receives serial data from the keyboard, checks its parity, translates scan codes, and presents it to the
system as a b yte dat a in its output buff er. The controller can interrupt the s ystem when data is placed i n its
output buffer, or wait for the system to poll its status register to determine when data is available.
Data can be written to the keyboard by writing data to the output buffer of the keyboard controller.
Each byte of data is sent t o the keyboard controller in series with an odd parit y bit automatically inser ted.
The keyboard contro ller is requir ed to ack nowledge all data transm is sions. Ther efore, anot her byte of dat a
will not be sent to the ke yboard controller until an ac knowledgment is r eceived for the previous b yte. The
“output buffer full” interruption may be used for both send and receive routines.
2.4 INTERRUPT CONTROLLER
The equivalent of two 82 59 Programmable Interrupt Controllers (PIC) are included on th e AR-B1380/ARB1380A board. They accept requests from the peripherals, resolve priorities on pending interrupts in
service, issue int er rupt r e q ues ts to the CPU, and prov ide vec t or s which are used as acc eptanc e i ndexe d by
the CPU to determine which interrupt service routine should be executed.
The following is the system interrupts levels:
InInterrupt Level
Description
NMI
CTRL1
IRQ 0
IRQ 1
IRQ 2
IRQ 3
IRQ 4
IRQ 5
IRQ 6
IRQ 7
Parity check
CTRL2
System timer interrupt from timer 8254
Keyboard output buffer full
IRQ8 : Real time clock
IRQ9 : Rerouting to INT 0Ah from hardware IRQ2
IRQ10 : LAN
IRQ11 : Reserved for watchdog
IRQ12 : Spare
IRQ13 : Math. coprocessor
IRQ14 : Hard disk adapter
IRQ15 : Reserved for watchdog
Serial port 2
Serial port 1
Parallel port 2
Floppy disk adapter
Parallel port 1
Figure 2-1 Interrupt Controller
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2.4.1 I/O Port Address Map
Hex Range Device Factory Preset
000-01F DMA controller 1
020-021 Interrupt controller 1
022-023 ALI M6117 chipset address
040-04F Timer 1
050-05F Timer 2
060-06F 8042 keyboard/controller
070-071 Real-time clock (RTC), non-maskable interrupt
(NMI)
080-09F DMA page registers
0A0-0A1 Interrupt controller 2
0C0-0DF DMA controller 2
0F0 Clear Math Co-processor
0F1 Reset Math Co-processor
0F8-0FF Math Co-processor
170-178 Fixed disk 1
1F0-1F8 Fixed disk 0
201 Game port
208-20A EMS register 0
218-21A EMS register 1
278-27F Parallel printer port 2 (LPT 2)
2E8-2EF Serial port 4 (COM 4)
2F8-2FF Serial port 2 (COM 2)
300-31F Prototype card/streaming type adapter
320-33F LAN adapter
378-37F Parallel printer port 1 (LPT 1)
380-38F SDLC, bisynchronous
3A0-3AF Bisynchronous
3B0-3BF Monochrome display and printer port 3 (LPT 3)
3C0-3CF EGA/VGA adapter
3D0-3DF Color/graphics monitor adapter
3E8-3EF Serial port 3 (COM 3)
3F0-3F7 Floppy controller
3F8-3FF Serial port 1 (COM 1)
Table 2-2 I/O Port Address Map
NOTE: The I/O address marked “✓” or “▲” is the BIOS default settings. “✓” means the I/O address is not adjustable;
“▲” means it is adjustable in the BIOS setup.
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
▲
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2.4.2 I/O Channel Pin Assignment (Bus1)
I/O Pin Signal Name Input/Output I/O Pin Signal Name Input/Output
A1 -IOCHCK Input B1 GND Ground
A2 SD7 Input/Output B2 RSTDRV Output
A3 SD6 Input/Output B3 +5V Power
A4 SD5 Input/Output B4 IRQ9 Input
A5 SD4 Input/Output B5 -5V Power
A6 SD3 Input/Output B6 PDRQ2 Input
A7 SD2 Input/Output B7 -12V Power
A8 SD1 Input/Output B8 PZWS Input
A9 SD0 Input/Output B9 +12V Power
A10 /IORDY Input B10 GND Ground
A11 AEN Output B11 -MEMW Output
A12 SA19 Input/Output B12 -MEMR Output
A13 SA18 Input/Output B13 -IOW Input/Output
A14 SA17 Input/Output B14 -IOR Input/Output
A15 SA16 Input/Output B15 -DACK3 Output
A16 SA15 Input/Output B16 DRQ3 Input
A17 SA14 Input/Output B17 -DACK1 Output
A18 SA13 Input/Output B18 DRQ1 Input
A19 SA12 Input/Output B19 -REFRESH Input/Output
A20 SA11 Input/Output B20 BUSCLK Output
A21 SA10 Input/Output B21 IRQ7 Input
A22 SA9 Input/Output B22 IRQ6 Input
A23 SA8 Input/Output B23 IRQ5 Input
A24 SA7 Input/Output B24 IRQ4 Input
A25 SA6 Input/Output B25 IRQ3 Input
A26 SA5 Input/Output B26 -DACK2 Output
A27 SA4 Input/Output B27 TC Output
A28 SA3 Input/Output B28 BALE Output
A29 SA2 Input/Output B29 +5V Power
A30 SA1 Input/Output B30 OSC Output
A31 SA0 Input/Output B31 GND Ground
Table 2-3 I/O Channel Pin Assignments
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AR-B1380/AR-B1380A User’s Guide
I/O Pin Signal Name Input/Output I/O Pin Signal Name Input/Output
C1 -SBHE Input/Output D1 -MEM16 Input
C2 LA23 Input/Output D2 -IO16 Input
C3 LA22 Input/Output D3 IRQ10 Input
C4 LA21 Input/Output D4 IRQ11 Input
C5 LA20 Input/Output D5 IRQ12 Input
C6 LA19 Input/Output D6 IRQ15 Input
C7 LA18 Input/Output D7 IRQ14 Input
C8 LA17 Input/Output D8 -DACK0 Output
C9 -MRD16 Input/Output D9 DRQ0 Input
C10 -MWR16 Input/Output D10 -DACK5 Output
C11 SD8 Input/Output D11 DRQ5 Input
C12 SD9 Input/Output D12 -DACK6 Output
C13 SD10 Input/Output D13 DRQ6 Input
C14 SD11 Input/Output D14 -DACK7 Output
C15 SD12 Input/Output D15 DRQ7 Input
C16 SD13 Input/Output D16 +5V Power
C17 SD14 Input/Output D17 -MASTER Input
C18 SD15 Input/Output D18 GND Ground
Table 2-4 I/O Channel Pin Assignments
2.5 REAL-TIME CLOCK AND NON-VOLATILE RAM
The AR-B1380/AR-B1380A contains a real-time clock compartment that maintains the date and time in
addition to storing co nfiguration inform ation about the com puter system. It contains 14 bytes of clock and
control registers and 114 bytes of general purpose RAM. Because of the use of CMOS technology, it
consumes ver y little power and can be maintained f or long peri od of time us ing an internal Li thium batter y.
The contents of each byte in the CMOS RAM are listed as follows:
Address Description
00 Seconds
01 Second alarm
02 Minutes
03 Minute alarm
04 Hours
05 Hour alarm
06 Day of week
07 Date of month
08 Month
09 Year
0A Status register A
0B Status register B
0C Status register C
0D Status register D
0E Diagnostic status byte
0F Shutdown status byte
10 Diskette drive type byte, drive A and B
11 Fixed disk type byte, drive C
12 Fixed disk type byte, drive D
13 Reserved
14 Equipment byte
15 Low base memory byte
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AR-B1380/AR-1380A User’s Guide
Address Description
16 High base memory byte
17 Low expansion memory byte
18 High expansion memory byte
19-2D Reserved
2E-2F 2-byte CMOS checksum
30 Low actual expansion memory byte
31 High actual expansion memory byte
32 Date century byte
33 Information flags (set during power on)
34-7F Reserved for system BIOS
Table 2-5 Real-Time Clock & Non-Volatile RAM
2.6 TIMER
The AR-B1380/AR-B1380A provides three programmable timers, each with a timing frequency of 1.19 MHz.
Timer 0 The output of this timer is tied to interrupt request 0. (IRQ 0)
Timer 1 This timer is used to trigger memory refresh cycles.
Timer 2 This timer provides the speaker tone.
Application pro grams can load different counts int o this timer to generate vario us sound
frequencies.
2.7 SERIAL PORTS
The ACEs (Asynchron ous Comm unication Elem ents ACE1 to ACE4) ar e used to con vert parallel da ta to a
serial format on the tr ansm it side an d con vert s erial d ata to parall el on the rec eiver s ide. T he seria l form at,
in order of transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if
programmed) and one, 1.5 (five-bit format only) or two stop bits. The ACEs are capable of handling
divisors of 1 to 65535, and produce a 16x clock for driving the internal transmitter logic.
Provisions are no t only included the use of 1 6x clock to dri ve the recei ver logic but a lso included t he ACE
as a complete MODE M control capability, a nd a pr oc es s or interr u pt system that may be s of t ware ta ilor e d t o
the computing time required to handle the communications link.
The following table is a summary of each ACE accessible register
DLAB Port Address Register
Receiver buffer (read) 0 base + 0
Transmitter holding register (write)
0 base + 1 Interrupt enable
X base + 2 Interrupt identification (read only)
X base + 3 Line control
X base + 4 MODEM control
X base + 5 Line status
X base + 6 MODEM status
X base + 7 Scratched register
1 base + 0 Divisor latch (least significant byte)
1 base + 1 Divisor latch (most significant byte)
Table 2-6 ACE Accessible Registers
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(1) Receiver Buffer Register (RBR)
Bit 0-7: Received data byte (Read Only)
(2) Transmitter Holding Register (THR)
Bit 0-7: Transmitter holding data byte (Write Only)
(3) Interrupt Enable Register (IER)
Bit 0: Enable Received Data Available Interrupt (ERBFI)
Bit 1: Enable Transmitter Holding Empty Interrupt (ETBEI)
Bit 2: Enable Receiver Line Status Interrupt (ELSI)
Bit 3: Enable MODEM Status Interrupt (EDSSI)
Bit 4: Must be 0
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0
(4) Interrupt Identification Register (IIR)
Bit 0: “0” if Interrupt Pending
Bit 1: Interrupt ID Bit 0
Bit 2: Interrupt ID Bit 1
Bit 3: Must be 0
Bit 4: Must be 0
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0
AR-B1380/AR-B1380A User’s Guide
(5) Line Control Register (LCR)
Bit 0: Word Length Select Bit 0 (WLS0)
Bit 1: Word Length Select Bit 1 (WLS1)
WLS1 WLS0 Word
0 0 5 Bits
0 1 6 Bits
1 0 7 Bits
1 1 8 Bits
Bit 2: Number of Stop Bit (STB)
Bit 3: Parity Enable (PEN)
Bit 4: Even Parity Select (EPS)
Bit 5: Stick Parity
Bit 6: Set Break
Bit 7: Div isor Latch Access Bit (DLAB)
(6) MODEM Control Register (MCR)
Bit 0: Data Terminal Ready (DTR)
Bit 1: Request to Send (RTS)
Bit 2: Out 1 (OUT 1)
Bit 3: Out 2 (OUT 2)
Bit 4: Loop
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0
Length
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AR-B1380/AR-1380A User’s Guide
(7) Line Status Register (LSR)
Bit 0: Data Ready (DR)
Bit 1: Overrun Error (OR)
Bit 2: Parity Error (PE)
Bit 3: Framing Error (FE)
Bit 4: Break Interrupt (BI)
Bit 5: Transmitter Holding Register Empty (THRE)
Bit 6: Transmitter Shift Register Empty (TSRE)
Bit 7: Must be 0
(8) MODEM Status Register (MSR)
Bit 0: Delta Clear to Send (DCTS)
Bit 1: Delta Data Set Ready (DDSR)
Bit 2: Training Edge Ring Indicator (TERI)
Bit 3: Delta Receive Line Signal Detect (DSLSD)
Bit 4: Clear to Send (CTS)
Bit 5: Data Set Ready (DSR)
Bit 6: Ring Indicator (RI)
Bit 7: Received Line Signal Detect (RSLD)
(9) Divisor Latch (LS, MS)
LS MS
Bit 0: Bit 0 Bit 8
Bit 1: Bit 1 Bit 9
Bit 2: Bit 2 Bit 10
Bit 3: Bit 3 Bit 11
Bit 4: Bit 4 Bit 12
Bit 5: Bit 5 Bit 13
Bit 6: Bit 6 Bit 14
Bit 7: Bit 7 Bit 15
Desired
Baud Rate
Divisor Used to
Generate 16x Clock
50 2304 --75 1536 ---
110 1047 0.026
134.5 857 0.058
150 768 --300 384 --600 192 ---
1200 96 --1800 64 --2000 58 0.69
2400 48 --3600 32 --4800 24 --7200 16 ---
9600 12 --14400 8 --19200 6 --28800 4 --38400 3 --57600 2 ---
Table 2-7 Serial Port Divisor Latch
Present Error Difference
Between Desired and
Actual
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AR-B1380/AR-B1380A User’s Guide
2.8 PARALLEL PORT
(1) Register Address
Port Address Read/Write Register
base + 0 Write Output data
base + 0 Read Input data
base + 1 Read Printer status buffer
base + 2 Write Printer control latch
Table 2-8 Registers’ Address
(2) Printer Interface Logic
The parallel portion of the SMC37C669 mak es the attachment of various d evices that accept eight bits of
parallel data at standard TTL level.
(3) Data Swapper
The system mic roproces sor can rea d the c onte nts of the pr inter ’s Data Latch through the Dat a Swapper b y
reading the Data Swapper address.
(4) Printer Status Buffer
The system m icroproces sor can re ad the pr inter statu s by rea ding the address of the Printer Status Buffer .
The bit definitions are described as follows:
12345670
XXX
-ERROR
SLCT
PE
-ACK
-BUSY
Figure 2-2 Printer Status Buffer
NOTE: X represents not used.
Bit 7: T his signal m ay becom e active dur ing data entr y, whe n the print er is off -line during pr inting, or
when the print head is changing position or in an error state. When Bit 7 is active, the printer is
busy and cannot accept data.
Bit 6: This bit represents the current state of the printer’s ACK signal. A0 means the printer has
received the character and is ready to accept another . Normally, this signal will be active for
approximately 5 microseconds before receiving a BUSY message stops.
Bit 5: A1 means the printer has detected the end of the paper.
Bit 4: A1 means the printer is selected.
Bit 3: A0 means the printer has encountered an error condition.
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(5) Printer Control Latch & Printer Control Swapper
The system microprocessor can read the contents of the printer control latch by reading t he address of
printer control swapper. Bit definitions are as follows:
12345670
XX
STROBE
AUTO FD XT
INIT
SLDC IN
IRQ ENABLE
DIR(write only)
Figure 2-3 Bit Definitions
NOTE: X represents not used.
Bit 5: Dir ection co ntrol bit. W hen logic 1, th e output buff ers in th e parall el port ar e disa bled a llowing
data driven from exter nal s ourc es to be read; when l o gic 0, they work as a printer port. T his bit
is writing only.
Bit 4: A1 in this position allows an interrupt to occur when ACK changes from low state to high state.
Bit 3: A1 in this bit position selects the printer.
Bit 2: A0 starts the printer (50 microseconds pulse, minimum).
Bit 1: A1 causes the printer to line-feed after a line is printed.
Bit 0: A0.5 microsecond m inimum highl y active pulse clocks data into the printer. Valid data must be
present for a minimum of 0.5 microseconds before and after the strobe pulse.
2.9 SOLID STATE DISKS
The AR-B1380/1380A provides three JEDEC DIP sockets and supports three kinds of solid-state disks,
EPROM, FLASH, and SR A M. With EPROM, the tota l memory is up to 3M B, and FLAS H or ` SRA M is up to
1.5MB. The three sockets can be configured as three sockets for SSD or two sockets for SSD plus 1
socket for DiskOnChip. The DiskOnChip socket supports memory from 2MB to 144MB. The
DiskOnModule is connected to the onboard IDE connector. All the flash disks are ideal for diskless
systems, and are also h ighl y reliab le for high-s peed ac c ess applic atio ns, as contr ollers for industria l use, or
line test instruments, etc.
2.10 ETHERNET CONTROLLER
The Ethernet controller of the AR-B1380A is a highly integrated design that provides all Media Access
Control (MAC) and Enc ode-Decode (ENDEC) f unctions in acc ordance with the I EEE 802.3 stan dard. The
Ethernet controller ca n i nte r f ac e direc tl y with t he PC- A T ISA bus without an y exte r nal de vice. The interface
to PC-AT ISA bus is fully compatible with NE2000 Ethernet adapter cards, so all software programs
designed for the NE2000 standard can run on the Ethernet controller card without any modification.
Microsoft’s Plug and Play and the jumper less software configuration function are both supported. The
capability of t he PnP and Non-Pn P m ode auto s witch f unction allows the user s to configure network cards .
No jumpers or switches are needed to set additionally when using either the PC or PnP function. The
integrated 8Kx16 SRAM and 10BASE-T transceiver make the Ethernet controller more cost-effective.
2.11 VGA CONTROLLER
AR-B1380A provides a super VGA controll er for CRT and LCD displays. It supports CRT color m onitors,
STN, Dual-Scan, TFT (see note below), monochrome and color panels. It can be connected to create a
compact video solut ion for the industr ial environm ent. 1MB of VRAM o n-boarded allo ws a maximum CRT
resolution of 1280X 1024 and a LCD res olution of 640 X480 with 64K col ors. TFT res olution can be set at
640X480 or at 800X600. It fulfills the needs for higher graphics performance.
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AR-B1380/AR-B1380A User’s Guide
3. SETTING UP THE SYSTEM
This section describes pin assignments for the system’s external connectors and the jumper settings.
! Overview
System Settings
!
3.1 OVERVIEW
The AR-B1380/AR-B138 0A is an al l-in-one half size, P entium single CPU boar d. This section prov ides the
hardware jumper settings, the connectors’ locations, and the pin assignments.
CAUTION: This CPU board doesn’t support double-sided SIMM-type DRAM. It only supports single-s ided
SIMMs.
LED1
1
H1
JP3
SIMM1
1
J5
CN1
1
2
U4
U9
JP12
U5
U8
11
JP7
U17
JP8
1
H2
J8
ALi M6117C
104
105
BUS1 BUS2
1
1
CN4
JP5
J7
1
2
SW2
2
1
P1P2
P7
P3
P5P6
104
105
U15
CN2 CN3
J4
U7
VGA
JP2
1
JP10
M2
M3
1
2
3
1
1
2
3
2
1
1
2
3
1
J6
JP6
ABC
M1
ABC
CN5
1
1
U10
U14
CBA
U20
CN8
1
2
CN7
1
JP1
JP4
[MEM1]
[MEM2]
[MEM3]
P4
1
123
JP11
1
JP9
J9
J1
H3
J2
A
B
C
J3
DB1
CN6
DB2
CN9
Figure 3-1 Jumper & Connector Placement
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3.2 INDEX OF THE CONNECTORS AND JUMPERS
Name Function Page
CN1 Hard disk (IDE) connector 20
CN2 Floppy disk drive connector 21
CN3 Printer connector 21
CN4 2.00mm LCD panel display connector 33
CN5 RS-232C /RS-485 connector 29
CN6 RJ-45 header 22
CN7 PC/104 40-pin bus C&D 22
CN8 PC/104 64-pin bus A&B 22
CN9 PS/2 Mini-Din keyboard connector 25
DB1 Analog monitor (CRT) connector 32
DB2 Serial port A RS-232 connector 29
J1 3-pin JST touch screen connector 35
J2 8-pin JST power connector 26
J3 4-pin JST power connector 26
J4 HDD LED header 30
J5 External speaker header 26
J6 Power LED Header 30
J7 Reset header 30
J8 External battery header 30
J9 PS2/mouse connector 25
JP1/JP4 3 Pin RS-485 adapter selectors 29
JP2 3 Pin DE/E signal from M or LP 33
JP3 6 Pin CPU base clock selector 27
JP5 6 Pin LCD voltage selector 33
JP6 3 Pin 1MX8 EPROM selector 52
JP7 3 Pin PS/2 mouse selector 25
JP8 3 Pin battery charger selector 29
JP9 3 Pin RS-485 terminator selector 29
JP10 6 Pin S.S.D. &D.O.C. Selector 49
JP11 9 Pin RS-232/RS-485 selector for CN5 29
LED1 Power/Watchdog LED 30
M1~M3 Memory type setting 52
SIMM1 DRAM socket for SIMM memory socket 31
SW2
SW2-1 & SW2-2 Set the base I/O port address 49
SW2-3 & SW2-4 Set the memory address 49
SW2-5 & SW2-6 Set the drive number of solid state disk 50
SW2-7 & SW2-8 Set the used ROM memory chips 52
Table 3-1 Index of the Connectors and Jumpers
3.3 SYSTEM SETTING
Jumper pins allow you to set s pecific s ystem par ameter s. Set th em b y changing the pin loc ation of jum per
blocks. (A jumper block is a s mall plast ic-encased co nductor that sl ips over the pins.) To change a jumper
setting, remove the jum per from its current location with your fingers or small needle-nos ed pliers. Place
the jumper over the two pin s designat ed f or the desire d settin g. Press the jum per even ly onto the p ins. Be
careful not to bend the pins.
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AR-B1380/AR-B1380A User’s Guide
Jumper use:
Jumper caps are usually small plastic caps used to short two pins on a jumper block.
Most jumper caps look like this:
A Jumper
Cap
Most jumper blocks look like this:
A 3 Pin
Jumper Block
If the jumper is placed over pins one and two then 1-2 are ON.
Jumper On
Pins 1 + 2.
If the jumper is placed over pins two and three then 2-3 are ON.
Jumper On
Pins 2 + 3.
Otherwise, the jumper can be left to the side or completely off the block to keep both 1-2 and 2-3 open/off.
We will show the locations of the AR-B1380/AR-B1380A jumper pins, and the factory-default settings.
CAUTION: Do not touch any electronic component unless you are safely grounded. Wear a grounded wrist
strap or touch an exposed metal part of the system unit chas sis. The static dis charges from your finger s
can permanently damage electronic components.
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3.3.1 CN1: Hard Disk Drive Connector
A 40-pin header type connector (CN1) is provided to interfac e with up to two e mbedded hard disk driv es
(IDE AT bus). T his interf ac e, thr o ugh a 40- pin c ab le, a llo ws the us er to c onn ect u p to two drives in a “ daisy
chain” fashion. To enable or disable the hard disk controller, please use BIOS Setup program. The
following table illustrates the hard disk drive’s 40-pin connector pin assignments.
Figure 3-2 CN1: Hard Disk (IDE) Connector
Pin Signal Pin Signal
1 -RESET 2 GROUND
3 DATA 7 4 DATA 8
5 DATA 6 6 DATA 9
7 DATA 5 8 DATA 10
9 DATA 4 10 DATA 11
11 DATA 3 12 DATA 12
13 DATA 2 14 DATA 13
15 DATA 1 16 DATA 14
17 DATA 0 18 DATA 15
19 GROUND 20 VDOM
21 NOT USED 22 GROUND
23 -IOW 24 GROUND
25 -IOR 26 GROUND
27 -IORDY 28 HDALE
29 NOT USED 30 GROUND
31 IRQ 14 32 -IOCS16
33 HDA 1 34 NOT USED
35 HDA 0 36 HDA 2
37 / HDCS0 38 / HDCS1
39 / HD LED 40 GROUND
Table 3-2 HDD Pin Assignment
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3.3.2 CN2: Floppy Disk Drive Connector
The AR-B1380/AR-B1380A provides a 34-pin header type connector for supporting up to two floppy disk
drives.
Figure 3-3 CN2: FDD Port Connector
Pin Signal Pin Signal
1-33(odd) GROUND 18 DIR
2 DRVEN 0 20 -STEP OUTPUT PULSE
4 NOT USED 22 /-WRITE DATA
6 DRVEN 1 24 / WGATE
8 / INDEX 26 /-TRK 0
10 / MTR0 28 /-WRITE PROTECT
12 /DRV1 30 -READ DATA
14 / DRV0 32 /HDSEL
16 /MTR1 34 DISKCHG
Table 3-3 FDD Pin Assignment
3.3.3 CN3: Parallel Port Connector
To use the parallel p ort, an ada pter cable has c onnected to the CN3 (26-p in header t ype) connector. T his
adapter cable is mounted on a bracket and is included in your AR-B1380/AR-B1380A package. The
connector for the parallel port is a 25 pin D-type female connector.
13
25
DB-25
D-Type Connector
Figure 3-4 CN3: Parallel Port Connector
1
14
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AR-B1380/AR-1380A User’s Guide
CN3 DB-25 Signal CN3 DB-25 Signal
1 1 -Strobe 2 14 -Au t o F o r m F eed
3 2 PD10 4 15 -Error
5 3 PD11 6 16 -Initialize
7 4 PD12 8 17 -Printer Select In
9 5 PD13 10 18 Ground
11 6 PD14 12 19 Ground
13 7 PD15 14 20 Ground
15 8 PD16 16 21 Ground
17 9 PD17 18 22 Ground
19 10 -Acknowledge 20 23 Ground
21 11 Busy 22 24 Ground
23 12 PS1 24 25 Ground
25 13 Printer Select 26 -- PRCG
Table 3-4 Parallel Port Pin Assignment
3.3.4 CN6: Ethernet RJ-45 Header
The system supports onboard network connectivity. To utili ze this function, ins tall the network driver from
the utility diskette, and connect the cable to the following RJ-45 header.
Figure 3-5 CN6: RJ-45 Header
J9 : R J 4 5 HEADER Signal J 9 : RJ45 HEADER Signal
1 TPTX+ 8 No connection
2 TPTX- 9 No connection
3 TPRX+ 10 No connection
4 No connection 11 LED 5 No connection 12 LED +
6 TPRX- 13 LAN CG
7 No connection 14 LAN CG
Table 3-5 RJ-45 Pin Assignments
3.3.5 CN7 & CN8: PC/104 Connector
Page 22
Figure 3-6 CN7&CN8: PC/104 Connector
Page 24
(1) CN7: 40-Pin PC/104 Connector Bus C & D
AR-B1380/AR-B1380A User’s Guide
Figure 3-7 CN7: 40-Pin PC/104 Connector Bus C & D
(2) CN8: 64-Pin PC/104 Connector Bus A & B
Figure 3-8 CN8: 64 Pin PC/104 Connector Bus A & B
(3) PC/104 Channel Signal Description
Name Description
BUSCLK [Output]
RSTDRV [Output]
SA0 - SA19
[Input / Output]
LA17 - LA23
[Input/Output]
SD0 - SD15
[Input/Output]
BALE [Output]
-IOCHCK [Input]
IOCHRDY
[Input, Open collector]
IRQ 3-7, 9-12, 14, 15
-IOR
[Input/Output]
-IOW [Input/Out put]
-SMEMR [Output]
-MEMR
[Input/Output]
The BUSCLK signal of the I/O channel is asynchronous to
the CPU clock.
This signal goes high during power-up, low line-voltage or
hardware reset
The System Address lines run from bit 0 to 19. They are
latched onto the falling edge of "BALE"
The Unlatched Address line run from bit 17 to 23
System Data bit 0 to 15
The Buffered Address Latch Enable is used to latch SA0 SA19 onto the falling edge. This signal is forced high
during DMA cycles
The I/O Channel Check is an active low signal which
indicates that a parity error exist on the I/O board
This signal lengthens the I/O, or memory read/write cycle,
and should be held low with a valid address
The Interrupt Request signal indicates I/O service request
[Input]
attention. They are prioritized in the following sequence :
(Highest) IRQ 9, 10, 11, 12, 13, 15, 3, 4, 5, 6, 7 (Lowest)
The I/O Read signal is an active low signal which instructs
the I/O device to drive its data onto the data bus
The I/O write signal is an active low signal which instructs
the I/O device to read data from the data bus
The System Memory Read is low while any of the low 1
mega bytes of memory are being used
The Memory Read signal is low while any memory location
is being read
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AR-B1380/AR-1380A User’s Guide
Name Description
-SMEMW [Output]
-MEMW
[Input/Output]
DRQ 0-3, 5-7 [Input]
-DACK 0-3, 5-7
[Output]
AEN [output]
-REFRESH
[Input/Output]
TC [Output]
SBHE [Input/Output]
-MASTER [Input]
-MEMCS16
[Input, Open collector]
-IOCS16
[Input, Open collector]
OSC [Output]
-ZWS
[Input, Open collector]
The System Memory Write is low while any of the low 1
mega bytes of memory is being written
The Memory Write signal is low while any memory location
is being written
DMA Request channels 0 to 3 are for 8-bit data transfers.
DMA Request channels 5 to 7 are for 16-bit data transfers.
DMA request should be held high until the corresponding
DMA has been completed. DMA request priority is in the
following sequence:(Highest) DRQ 0, 1, 2, 3, 5, 6, 7
(Lowest)
The DMA Acknowledges 0 to 3, 5 to 7 are the
corresponding acknowledge signals for DRQ 0 to 3 and 5
to 7
The DMA Address Enable is high when the DMA controller
is driving the address bus. It is low when the CPU is driving
the address bus
This signal is used to indicate a memory refresh cycl e and
can be driven by the microproces sor on the I/O channel
Terminal Count provides a pulse when the terminal count
for any DMA channel is reached
The System Bus High Enable indicates the high byte
SD8 – SD15 on the data bus
The MASTER is the signal from the I/O processor which
gains control as the master and should be held low for a
maximum of 15 micros econds or system memory m ay be
lost due to the lack of refresh
The Memory Chip Select 16 indicates that the present data
transfer is a 1-wait state, 16-bit data memory operat i on
The I/O Chip Select 16 indicates that the present data
transfer is a 1-wait state, 16-bi t data I/O operation
The Oscillator is a 14.31818 MHz signal used for the color
graphic card
The Zero Wait State indicates to the microprocessor that
the present bus cycle can be completed without inserting
additional wait cycle
Table 3-6 I/O Channel Signal’s Description
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3.3.6 PS/2 Keyboard and Mouse
JP7: PS/2 Mouse Selector
JP7 PS/2 Mouse Selector Setting
1-2
2-3
(Factory Preset)
Table 3-1 JP7: PS/2 Mouse Setting
Note: If you want to use PS/2 m ouse, please select “2-3” for JP7, with which the PS/2 m ouse device will
occupy IRQ12. If “1-2” of JP7 is selected, IRQ12 can be configured for other devices.
CN9: 6-pin MiNi-Din PS/2 Keyboard Connector
CN9 is a Mini-DIN 6-pin connector with support for a PS/2 keyboard. This connector is also IBMcompatible with the keyboard adapter cable. When you use the PS/2 mouse, adjust JP7 to “2-3” and
connect the adapter cable to CN9.
Figure 3-9 CN9: 6-Pin Mini Din Keyboard Connector
J9 PS/2 /Mouse Selector
A PC/AT compatible m ouse can be used by connecting the provided ad apter cable between J9 and the
/mouse. The pin assignments of the J9 connector are as follows:
Figure 3-10 J9: AUX. Keyboard Connector
IRQ12
PS/2 mouse
1. Data
2. N.C.
3. GND
4. VCC
5. Clock
6. N.C.
1 MSData
2 KBData
3. GND
4. VCC
5. MSClock
6. KBClock
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AR-B1380/AR-1380A User’s Guide
3.3.7 Power Connector
(1) J2: 8-Pin Power Connector
The J2 is an 8-pin power connector, you can directly connect the power supply to the on board power
connector for stand alone applications.
Figure 3-2 J2: 8-Pin Power Connector
(2) J3: 4-Pin Power Connector
Figure 3-3 J3: 4-pin Power Connector
1. GND
2. +5 VDC
3. +5 VDC
4. GND
5. GND
6. +12 VDC
7. –12 VDC
8. –5 VDC
1. +5 VDC
2. GND
3. GND
4. +12 VDC
3.3.8 J5: External Speaker Header
Besides the on board buzzer, you can use an external speaker by connecting J5 header directly.
1. Speaker+
2. Speaker-
3. Speaker-
4. Speaker-
Figure 3-4 J5: External Speaker Header
3.3.9 J7: Reset Header
J7 is used to connect to an external reset switch. Shorting these two pins will reset the system.
1. Reset+
2. Reset-
Figure 3-5 J7: Reset Header
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3.3.10 Board Battery Configuration
You may use either the onboard battery or connect an external battery to this board.
(1) JP8: External/Onboard Battery Selector
JP8 Battery Charger Setting
1-2
(Factory Preset)
Non-rechargeable
(Use of the external Battery)
2-3 Rechargeable
(Use of the onboard Battery)
Table 3-8 JP8: Battery Charger Selector
(2) J8: External Battery Connector
The J8 allows the users to connec tor an exter nal 4 .5 to 6 VDC bat ter y to the AR- B13 80/AR-B 1380A. If the
on-board battery is f ully discharged, the SRAM disk will draw the battery current. T he battery charger on
AR-B1380/AR-B1380A doesn’t source charge current to the external battery, which connects to J8.
1 Battery+
2 Battery-
Figure 3-15 J8: External Battery Connector
3.3.11 JP3: CPU Base Clock Selector
The CPU base clock (Input clock) is twice as fast as the operating clock.
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JP3 CPU Base Clock Setting
1-2, 4-6 16.7 MHz
1-2, 3-5 25 MHz
1-2, 5-6 30 MHz
1-3, 5-6
33.3 MHz
(Factory Preset)
2-4, 5-6 37.5 MHz
1-3, 2-4 40 MHz
Table 3-9 JP1: CPU Base Clock Select
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3.3.12 Serial Port
(1) JP11: RS-232/RS-485 Selector for CN5
The JP11 selects the on-board RS-232/RS-485 for COM B, if choose RS-232 connecting with CN7; if
choose RS-485 connecting with J9.
CN5: RS-232 or
RS-485 Selector
Setting
CN5 is RS-485
1-2,4-5,7-8
compatible
CN5 is RS-485
2-3,5-6,8-9
compatible
(Factory Preset)
Table 3-10 JP11: RS-232/RS-485 Select for CN5
(2) JP9: RS-485 Terminator Selector
RS-485 may need to be terminated when there are multiple blocks on one line.
JP9 RS-485 Terminator Setting
1-2 Enable
2-3
Disable
(Factory Preset)
Table 3-11 JP9: RS-485 Terminator
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(3) JP1 & JP4: External RS-485 Adapter Selector
JP1 and JP4 can be set i ndepende ntly. J P1 selects COMB por t and J P4 selec ts COM A port. JP4 sel ects
the external RS-485 for COMB port connecting with CN7. JP4 selects the external RS-485 for COMA
connecting with DB2.
JP1/JP4 RS-485 Adapter Selector JP1: CN5 JP4: DB2
1-2 Reserved for Acrosser’s RS-
485 Adapter
2-3
RS-232C
(Factory Preset)
Table 3-12 JP1 & JP4: External RS-485 Adapter Selectors
(4) CN5 & DB2: RS-232C Connector
There are two serial ports with an EIA RS-232C interface on the AR-B13 80/AR-B1380 A. COM A uses one
on-board D-type 9-p in male con nector (DB2) which is located at the top of the card, a nd COM B uses one
10-pin header (CN5). Use the BIOS Setup program to configure these two serial ports, and adjust the
jumpers on JP1 and JP4.
CN5 DB2 Signal CN7 DB2 Signal
1 1 -DCD 2 6 -DSR
3 2 RXD 4 7 -RTS
5 3 TXD 6 8 -CTS
7 4 -DTR 8 9 -RI
9 5 GND 10 -- Not Used
Table 3-13 Serial Port Pin Assignments
Note: CN5 can be configured f or RS-232 or RS-485. When it is RS-485 compatible, you mu st set
JP11 to “1-2, 4-5, 7-8” and JP1 to “1-2.”
3.3.13 LED Headers and Indicator
This system provides LED headers and a LED indicator for the users to easily monitor the system’s
operation.
(1) J6: External Power LED Header
J6 is used to connect to the external power LED.
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1 Power LED+
2 Power LED3 Power LED-
Figure 3-17 J6: External Power LED Header
Note: J6 & JP6 are aligned with each other. Please be careful with their orientation and pin locations during installation.
(2) J4: HDD LED Header
J4 is used to connect to the external Hard Disk LED.
1 LED+
2 LED-
Figure 3-18 J4: HDD LED Header
(3) LED1: Power/Watchdog LED
The AR-B1380/AR-B1380A provides a rectangular LED indicator to indicate the status of the Power/
Watchdog timer. LED1 is located at the upper-left corner of the board above the SIMM socket.
3.3.14 DRAM Configuration
There is 2MB DRAM onboard. For memory expansion, a SOJ socket and 72-pin SIMM socket are provided.
The SIMM socket suppor ts single-sided SI MM modules (Single-L ine Memory Modules ), which is designed
to accommodate 256Kx 36 bit to 4Mx36- SIMMs. This prov ides the user with up to 32MB of m ain memory.
The 32-bit SIMM ( without parity bit) als o can be used on the AR- B1380/AR-B1380A bo ard. There are six
on-board memory configurations available. Please refer to the following table for details:
SIMM Total Memory
1Mx32 (x36) 4MB
4Mx32 (x36) 16MB
Table 3-14 DRAM Configuration
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4. CRT/LCD FLAT PANEL DISPLAYS
This section describes the configuration and installation procedure when using the LCD and CRT displays.
Connecting the CRT Monitor
!
LCD Flat Panel Displays
!
Supported LCD Panels
!
4.1 DB1: CRT CONNECTOR
The DB1 is used to connect with a VGA monitor when you are using the on-board VGA controller as a display
adapter. Pin assignments for the DB1 connector are as follows:
Figure 4-1 DB1: CRT Connector
DB1 Signal DB1 Signal
1 Red 9 Not Used
2 Green 10 Ground
3 Blue 11 Not Used
4 Not Used 12 Not Used
5 Ground 13 Horizontal Sync
6 AGND 14 Vertical Sync
7 AGND 15 Not Used
8 AGND --
Table 4-1 CRT Connector Pin Assignments
4.2 LCD FLAT PANEL DISPLAY
This section des cribes the configuration and installation proce dure for a LCD displa y. Skip this section if
you are using a CRT monitor only. (AR-B1380 doesn’t provide the LCD function).
Use the Flash Mem ory Writer utility to downl oad the ne w BIOS file into the RO M chip to c o nf igur e the B IO S
default setting for dif ferent types of LCD pa nel. And then set your s ystem properly and conf igure the ARB1380A VGA module for the right type of LCD panel you are using.
If you are using a differ ent LCD panel oth er than thos e listed, c hoose the t ype of LCD panel you are usi ng.
From the panel description column
The following shows the block diagram when using TK AR-B1380A for an LCD display.
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AR-B1380A
CPU Boad
VBL Control
+12V, +5V
Figure 4-2 LCD Panel Block Diagram
VEE
Inverter
Board
LCD
Panel
FL HIGH
Voltage
This block diagram shows that the AR-B1380A still needs other components to be used for LCD panel.
The inverter board provides the control for the brightness and the contrast of the LCD panel while the
transfer is the one that supplies the high voltage to drive the LCD panel. Each item will be explained further
in this section.
Pin 1
CN4
Inverter & Contrast
AR-B1380A
CPU Board
Pin 1
LCD
Panel
Figure 4-3 LCD Panel Cable Installation Diagram
NOTE: Be careful wi th the pin or ientatio n when inst alling the co nnectors and the cabl es. A w ron g c on ne ct io n
can easily destroy your LCD panel. Pin 1 of the cable connector is indicate d with a stick er and pin1 of the
ribbon cable usually has a different color.
4.2.1 Inverter Board Description
The inverter bo ard su pplies the hig h vo ltage s ignals to drive the LCD pan el b y co nverting the 12- volt s ignal
from the AR-B1380A i nto high voltage AC signal for LCD pane l. It can be installed freely on the spac e
provided over the VR board. If the VR bo ard is installed on the bracket, you have to pro vide a place to
install the inverter board into your system.
4.2.2 LCD Settings and Connectors
The AR-B1380A supports CRT color monitors, STN, Dual-Scan, TFT, monoc hrome and color panels. It
can be connected to create a compact video solution for the industrial environment. 1MB of RAM onboarded allows a m ax im um CRT resolution of 1024X7 68 an d a L CD r esol uti on of 640X 48 0 with 64 K c o lor s.
For different VGA disp lay modes, your monitor must poss ess certain characteristics drives to display the
mode you want.
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(1) JP2: DE/E Signal from M or LP
JP2 DE/M Signal Setting
(Factory Preset)
(2) JP5: LCD Voltage Selector
(Factory Preset)
1-2
DE/M
2-3 E/LP
Table 4-2 JP2: DE/E Signal from M or LP Select
JP5 LCD Voltage Selector Setting
3-5, 4-6
3.3 VDC
1-3, 2-4 5 VDC
Table 4-3 LCD Voltage Selector
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(3) CN4: LCD Panel Display Connector
Attach a display panel connector to this 44-pin connector with pin assignments shown as below:
NOTE: AR-B1380 doesn’t provide this function.
Figure 4-4 CN4: LCD Display Connector
Pin Signal Pin Signal
1 GND 2 SHFCLK
3 GND 4 LP
5 FLM 6 GND
7 P0 8 P1
9 P2 10 P3
11 P4 12 P5
13 GND 14 P6
15 P7 16 P8
17 P9 18 P10
19 P11 20 GND
21 P12 22 P13
23 P14 24 P15
25 P16 26 P17
27 GND 28 P18
29 P19 30 P20
31 P21 32 P22
33 P23 34 GND
35 VLCD 36 VLCD
37 +12V 38 +12V
39 GND 40 GND
41 DE 42 ENABLK
43 GND 44 ENAVEE
Table 4-4 LCD Display Assignments
(4) J1: Touch Screen Connector
The J1 is a 3-pin JST connector connecting to the touch screen module to provide touch screen
functionality.
1. RXD2F+
2. TXD2F
3. GND
Figure 4-5 J1: Touch Screen Connector
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4.3 SUPPORTED LCD PANELS
At present, this VGA card can provide a solution with an inverter transfer board for the following list of
standard LCD panels. Consult your Acrosser representative for new developments. When using other
models of standard LCD panels in the market.
NO. Manufacture Model No. Description
1 NEC NL-6448AC30-10 TFT 9.4”
2 NEC NL-6448AC32-10 TFT 10.2”
3 NEC NL-6448AC33-10 TFT 10.4”
4 HITACHI LMG5371 MONO 9.4” Dual
Scan
5 HITACHI LMG9200 DSTN 9.4”
6 HITACHI LMG9400 DSTN 10.4”
7 ORION OGM-640CN03C-S DSTN 10.4”
8 SHARP LQ10D321 TFT 10.4”
Table 4-5 LCD Panel Type List
CAUTION:
1) If you want to use LCD pa nel, you must update the AR-B1 380A’s BIOS. Please contact Ac rosser for
the latest BIOS update.
2) If you need details to update th e BIOS version or use other LCDs, pleas e contact the sales de partment.
The details about s upporte d LCDs are l isted at the Ac rosser W ebsite. You c an then d ownload the suitable
BIOS. The address is as follows:
http:\\www.acrosser.com
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5. SOFTWARE INSTALLATION
This chapter describes the of the utility diskette installation procedure. The following topics are covered:
!
Overview
!
Utility Diskette
!
Write Protect Function
!
Watchdog Timer
5.1 OVERVIEW
This chapter provid es inform ation for you to set up a working system based on the AR-B1 380/AR-B1380A
CPU card. Please carefull y read the details of the CPU card’s hardware des criptions before installation,
especially jumper settings, switch settings and cable connections.
The following lists the proper installation steps:
Step 1 :
Step 2 :
Step 3 :
Step 4 :
Step 5 :
Step 6 :
Step 7 :
Step 8 :
Step 9 :
Step 10:
Step 11:
Step 12:
Read the CPU card’s hardware description in this manual.
Install the SIMM module onto the CPU card.
Set the jumpers.
Make sure that the power supply connected to your passive CPU board backplane is
turned off.
Plug the CPU card into a fr ee AT- bus slot or PIC MG s lot on the back plane a nd se cure it in
place with a screw to the system chassis.
Connect all necessary cables . Make sure that the FDC, HDC, serial and parallel cables
are connected to pin 1 of the related connector.
Connect the hard dis k/floppy disk flat cables fr om the CPU card to the drives. Connect a
power source to each drive.
Plug the keyboard into the keyboard connector.
Turn on the power.
Configure your system with the BIOS Setup program then re-boot your system.
If the CPU card does not work, turn off the power and read the hardware description
carefully again.
If the CPU card still does n ot per f orm properly, return the car d to your de al er f or immediate
service.
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5.2 UTILITY DISKETTE
AR-B1380 provides one diskette with the SSD utility and manual file
AR-B1380A provides two utility diskettes: DISK1 for the WIN31 and MS-DOS VGA drives; Disk2 for the
LAN drover, SSD utiliti es and the manual file. If your oper at ion system is neither WIN31 nor WIN95, please
contact Acrosser f or the pr oper VGA drivers . Als o you m a y refer to th e Readm e.tx t for any trou blesh ootin g
before installing the driver.
5.2.1 VGA Driver
(1) WIN 3.1 Driver
For the WIN31 operati ng system, you must decompress the c ompress file in the DOS mode. A nd then
follow these steps:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:
Step 7:
Step 8:
Execute the SETUP.EXE file in the DOS mode.
A:\>SETUP
The screen shows the chip type. Press any key to enter the main menu.
There are nine item s in the main m enu. Select the <W indows Version 3.1> item. Notice
the function ke y defined. Pr ess [ENTER] to select the <All Res olutions>. When this line
appears with the [*] symbol, it means this item is selected. Press [End] to start the
installation.
The screen will show the dialog box to ask you to type the WIN31’s path. The default is
C:\WINDOWS.
Follow the on screen m essages. When the setup is com pleted, the system will generate
the message as follows.
Installation is done!
Change to your Windows directory and type SETUP to run the W indows Setup program.
Choose one of the new drivers marked with an *. Please refer to the User’s Guide to
complete the installation.
Press [Esc] ke y to return to the m ain m enu, and re- press [Es c] again to ret urn to the DO S
mode.
Enter WIN31. You can find the <Chips CPL> icon located in the {CONTROL PANEL}
group.
Adjust the <Refresh Rate>, <Cursor Animation>, <Font size>, <Resolution>, and <Big
Cursor> functions.
5.2.2 SSD Utility
To support the AR- B1380/AR-B1380A solid state dis k’s operations, the following files have been pro vided
on the enclosed diskette’s directory <SSD>.
(A) WD1380.EXE/WD6117C.EXE
WD1380.EXE : These two programs demonstrate how to enable and trigger the watchdog timer.
WD6117C.EXE: It allows you to test the <TIME-OUT & RESET> function when the watchdog timer is
enabled.
Note: Please refer to Section 5.4 for details when using the watchdog timer.
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(B) WD6117C.CPP
WD1380.EXE : This is the source file of the “WD6117C.”
(C) WP1380.EXE
WP1380.EXE : This program demonstrates how to e nable and disab le the software wr ite protected
function. It also shows the current protect mode of write or read only memory.
(D) RFG.EXE
RFG.EXE : This program is used to gener ate the ROM pattern files in a binar y format. Each
ROM pattern file has the same size as the FLASH or EPROM and can be easily
programmed on to the FLA SH with an on-board program mer or on to EPROM with
any EPROM progr amm er. If you have spec ified a DOS dr ive in the *. PGF fil e, RF G
will generate bootable ROM pattern files for the EPROM or FLASH disk . The RFG
supports the following commands DOS:MS-DOS, PC-DOS, DR-DOS, and X-DOS.
NOTE: If you want to use AR-B380/AR-B1380A with any DOS, which is not supported by RFG, please
send your requirement to Acrosser Technology Co., Ltd. or contract your local sales representative.
The RFG.EXE pro vided in the utilit y diskette is a program that converts the files you list in the PGF and
convert them into a ROM pattern file. The RFG will determine how many EPROMs are needed and
generate the same number of ROM pattern files. These ROM pattern files are named with the name
assigned by the ROM_NAME i n the PGF and the extension names are *.R01, *.R02….etc. To generate
ROM pattern files.
The ROM File Generator main menu will be displayed on the s creen. There are 7 options on the m ain
menu. They serve the following functions:
Quit to DOS
Quits and exits to the DOS
OS Shell
Exits from the RFG tem porarily to the DOS prompt. Type <EXIT > to return to the RFG main
menu.
Load PFG File
If this option is used, the R FG will pr ompt you for the PGF file nam e. This option is usef ul if you
have not previousl y entered a PGF nam e or you wish to us e a different PGF file. The RFG will
check and displa y the PGF filenam e, ROM pattern file name, EPROM capacity, DOS versio n
and the number of ROM pattern files that will be generated.
Type Current PGF File
This option instructs the RFG to use the DOS type command to display the contents of the
current PGF file.
Generate ROM File(s)
If there is no m istake in your *.PG F file, then this m enu option will g enerate ROM pattern f iles.
The number of ROM pattern f iles gener a ted by the RFG will depend on the tot al c apac ity needed
by your files. For instance, if 3 files are generated, then you will need to use 3 EPROMs (The
size depends upon the num ber stated in your PGF). T he ROM pattern f iles will ha ve the sam e
file names, but will have different extension names. For example:
TEST.R01, TEST.R02, TEST.R03…etc.
Display Error in PGF File
This option displays errors that were detected in your PGF.
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Help to PGF File
This option gives info rmation on how to write a PGF file and ho w to generate RO M pattern files.
An example PGF is also included.
Move the reverse video b ar to <Gener ate ROM File(s )> then press [ENT ER]. The ROM pattern
file is a binar y file. The file size will be the same size as the EPROM that you as signed in the
PGF. For example, if you are using 128KX8 EPROM memory chips, then the size of ROM
patterns file will be 131072 bytes. For other chips the file size will be:
64KX8 EPROM----65536 bytes
256KX8 EPROM—262144 bytes
512KX8 EPROM---524288 bytes
1MX8 EPROM -----1048576 bytes
(E) RFGDEMO.PGF
RFGDEMO.PGF This file provides a sample PROGRAM GROUP FILE, which illustrates how to
create ROM pattern files correctly.
The PGF is an ASCI I text fi le that can b e creat ed by us ing any tex t editor, word proc essor or DO S <COP Y
CON> command. The PG F lists what files will be co pied and if DOS is going t o be copied. This file can
have any DOS filenam e, but the extension name must be *.PGF . For example: the followings are va lid
filenames.
RFGDEMO.PGF
MYRFG.PGF
MSDOS.PGF
….
An examples of the *.PGF file is as follows.
ROM_NAME=TEST1 ; ROM pattern file name is TEST1
;The output file names will be TEST1.R01, TEST1.R02..etc.
DOS_DRIVE=C: ; DOS system drive unit is drive C:
;If user does not want to copy DOS
;system files onto the ROM disk
;write as DOS_DRIVE=NONE
ROM_SIZE=128 ;128 means 128KX8 (27C/29F010) EPROM size used
;256 means 512KX8 (27C/29F020) EPROM size used
;512 means 512KX8 (27C/29F040) EPROM size used
;1024 means 1MX8 (27C080) EPROM size used
The following two files are options which dep ending on whether you want the ROM disk to be boota ble or
not.
CONFIG.SYS
AUTOEXEC.BAT
;Below are user’s files
A:\USER1.COM ; File USER1.COM on root of drive A:
USER2.EXE ; File USER2.EXE on current directory & drive
C:\TTT\U SE R3 .TXT ; Fi le US ER 3. TXT on su b-d ir ect or y TTT of d ri ve C:
Note: Anything appearing after a “ ;” semicolon is considered a text note that does not affect the PGF file, but it is a
good organizational idea to keep these notes for future use.0
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5.3 WRITE PROTECT FUNCTION
The AR-B1380/AR-B1380A provides hardware and software write protect functions for small page 5V
FLASH disks and o nly software write protected functions f or SRAM disk s. This is to prevent your data on
5V FLASH or SRAM disks from accidental ok deletion or overwrite. If your FLASH/SRAM disk is write
protected, any write operation to the protected FLASH/SRAM disk will get a write protect error:
Write protect error writing drive A
About, Retry, Fail?
5.3.1 Hardware Write Protect
To enable the hardware protect function for small page 5V FLASH disk, please refer to the “Switch Setting”.
5.3.2 Software Write Protect
If you need the write protect function and sometimes you have to write or update data on your
FLASH/SRAM disk , you can us e the s oft ware write protec t instea d of har dwar e write pr otect. T he sof t ware
writes protect function is enabled or disabled by writing a data to an I/O port.
5.3.3 Enable the Software Write Protect
Writes data 80h to the base port+0 address
Example 1: (in assembly language)
MOV DX, 210H ; If the base I/O address is 210H
MOV AL, 80H ; Enable byte = 80h
OUT DX, AL
Example 2: (in BASICA language)
OUT &H210, &H80; REM If the base I/O address is 210h
Example 3: (in Turbo C language)
Outportb (0x210,0x80);/*If the base I/O address is 210h*/
5.3.4 Disable the Software Write Protect
Writes data 0 to the base port+0 address
Example 1: (in assembly language)
MOV DX, 210H ; If the base I/O address is 210h
MOV AL, 00H ; Disable byte=00h
OUT DX, AL
Example 2: (in BASICA language)
OUT &H210, &H00; REM If the base I/O address is 210h
Example 3: (in Turbo C language)
Outportb (0x210,0x00);/*If the base I/O address is 210h*/
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5.4 WATCHDOG TIMER
This section describes how to use, disable, enable, and trigger the Watchdog Timer.
AR-B1380/AR-B1380 A provides two methods for the users to utilize the watch dog timer function. One is
the watchdog timer built in the chipset, which m akes use of the C PU’s regist ers to us e the watchd og tim er.
The other is the watchdog tim er program programmed by Across er, which helps you to use the watch dog
timer through the use of the IRQ11 and IRQ15.
The SSD directory in t he di sk ette includes the watchd og tim er util it y files, “W D1380.EX E,” W D 6117C.EX E,”
and WD6117C.CPP.” ”WD6117C.EXE” and WD6117C.CPP” are ALI M6117C’s built-in watchdog timer
program. “WD6117C.EXE” demonstrates how to set/enable/disable/trigger the watchdog timer.
“WD6117C” is the so urce file of the “W D6117C.” The other is “WD1380.EXE” program med by Acrosser.
You may choose either the Diskonchip watchdog timer or Acrosser’s program to utilize the watchdog timer.
5.4.1 Acrosser’s Watchdog Timer Program
The AR-B1380/AR-B1380A is equipped with a programmable time-out period watchdog timer. You can use
this program to enable the watchdog timer. Once you have enabled the watchdog timer, the program
should trigger it ever y time before it tim es out. If your program fails to trigger or d isable this tim er befor e it
times out because of a system hang-up, it will ge nerate a reset signal to res et the system. The time- out
period can be programmed to be from 3 to 42 seconds.
Enable (D7)
Time Factor (D0-D2)
Watchdog
Register
Write and Trigger
Time Base
Counter
and
Compartor
Watchdog
LED
Figure 5-1 Watchdog Block Diagram
(1) Set up the Watchdog Timer by IRQ15/IRQ11
RESET
The watchdog timer is a circuit that may be used from your program software to detect crashes or hang-ups.
Whenever the watchdog timer is enabled, the LED will blink to indicate that the timer is counting. The
watchdog timer is automatically disabled after reset.
Once you have enabled the watchdog timer, your program must trigger the watchdog timer every time
before it times-out. Af ter you trigger the watchdog t imer, it will be set to zero a nd start to count again. If
your program fails to tr igger the watchdog timer before time-out, it will gen erate a reset pulse to reset th e
system or trigger the IRQ15 signal to tell your program that the watchdog has timed out.
The factor of the watchdog timer time-out constant is approximately 6 seconds. The period for the
watchdog timer time-out pe riod is between 1 to 7 timer factors. If you want to reset your s ystem when the
watchdog times out, the following table lists the relation of timer factors between time-out period.
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Time Factor Time-Out Period (Seconds)
80H 3
81H 6
82H 12
83H 18
84H 24
85H 30
86H 36
87H 42
Table 5-1 Time-Out Setting
If you want to generate an IRQ15 signal to warn your program when the watchdog times out, the following
table lists the r elation of the tim er factors between tim e-out periods. And if you use the IRQ15 signal to
warn your program when the watchd og timer times out, please enter the BIOS Setup, in the <Peripheral
Setup> menu, set the two items <OnBoard PCI IDE> and <IDE Prefetch> to Primary.
Time Factor Time-Out Period (Seconds)
0C0H 3
0C1H 6
0C2H 12
0C3H 18
0C4H 24
0C5H 30
0C6H 36
0C7H 42
Table 5-2 Time-Out Setting
If you want to generate an IRQ11 signal to warn your program when the watchdog times out, the following
table lists the relation of timer factor s between time-out periods . And if you use the IRQ11 signal to warn
your program when the watchdog times out, p leas e en ter the BIOS Setup, in the <P er ip her al S etup > menu,
set the two items <OnBoard PCI IDE> and <IDE Prefetch> to Primary.
Time Factor Time-Out Period (Seconds)
0E0H 3
0E1H 6
0E2H 12
0E3H 18
0E4H 24
0E5H 30
0E6H 36
0E7H 42
Table 5-3 Time-Out Setting
NOTE
1. If you program the watchdog to generate an IRQ15 or IRQ11 sig nal when it times out, you should initial
an IRQ15 interrupt vector and enable the s econd interrupt c ontroller (8259 PIC) in order to enable C PU to
process this interrupt. An interrupt service routine is required too.
2. Before you initiali ze the interrupt vector of IRQ15/I RQ11 as well as enable the PIC, please ena ble the
watchdog timer in advanc e. Ot herwise, t he watch dog tim er will generat e an in terrupt at the tim e watch dog
timer is enabled.
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(2) Enable the Watchdog Timer
To enable the watchdog timer, you have to output a byte of timer factor to the watchdog register whose
address is 214H or Base Por t. The followin g is a BASICA program , which dem onstrates ho w to enable the
watchdog timer and set the time-out period at 24 seconds.
1000 REM Points to command register
1010 WD_REG% = 214H
1020 REM Timer factor = 84H (or 0C4H)
1030 TIMER_FACTOR% = %H84
1040 REM Output factor to watchdog register
1050 OUT WD_REG%, TIMER_FACTOR%
.,etc.
(3) Trigger the Watchdog Timer
After you enable the watchdog t im er, your program must write t he sam e f actor as enab ling to t he watchd og
register at least once ever y time-out period to its previous settin g. You can change the t ime-out period b y
writing another tim er f actor to the watchdog re gister at any tim e, and you mus t trigger th e watchdo g before
the new time-out period in the next trigger. Below is a BASICA program, which demonstrates how to trigger
the watchdog timer:
2000 REM Points to command register
2010 WD_REG% = 214H
2020 REM Timer factor = 84H (or 0C4H)
2030 TIMER_FACTOR% = &H84
2040 REM Output factor to watchdog register
2050 OUT WD_REG%, TIMER_FACTOR%
.,etc.
(4) Disable Watchdog Timer
To disable the watchdog timer, simply write a 00H to the watchdog register.
3000 REM Points to command register
3010 WD_REG% = BASE_PORT%
3020 REM Timer factor = 0
3030 TIMER_FACTOR% = 0
3040 REM Output factor to watchdog register
3050 OUT WD_REG%, TIMER_FACTOR%
., etc.
5.4.2 Built-in Watchdog Timer
Once you have enabled the watchdog timer, your program must trigger the watchdog timer every time
before it times-out. Af ter you trigger the watchdog t imer, it will be set to zero a nd start to count again. If
your program fails to tr igger the watchdog timer before time-out, it will gen erate a reset pulse to reset th e
system or trigger an IRQ or NMI signal to tell your pro gram that the watchdo g has timed out. The t ime-out
period can be programmed to be 30.5μseconds to 512 seconds with 30.5μseconds per step.
The following are the watchdog timer registers:
• Index 37H : WD Enable Register
• Index 38H : WD Report Register
• Index 39H, 3AH, 3BH : WD 24-bit Timer Counter
• Index 3CH : WD Status Register
(1) INDEX 37H: WD Enable Register
This register is used to enable or disable the watchdog timer.
Bit 7 Reserved. Please do not set this bit. In the old version M6117C
data sheet, this bit is counter read mode.
Bit 6=0 Disable the watchdog timer
Bit 6=1 Enable the watchdog timer
Bit 5-0 Other function. Please do not modify these bits.
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5.4.3 INDEX 38H: WD Report register -
This register is used to select the watchdog report when the watchdog times out.
Bit 7-4 Watchdog Timer Time-out Report Signal Select
0000 No output signal
0001 IRQ3 selected
0010 IRQ4 selected
0011 IRQ5 selected
0100 IRQ6 selected
0101 IRQ7 selected
0110 IRQ9 selected
0111 IRQ10 selected
1000 IRQ11 selected
1001 IRQ12 selected
1010 IRQ14 selected
1011 IRQ15 selected
1100 NMI selected
1101 System reset selected
1110 No output signal
1111 No output signal
Bit 3-0 Other function. Please do not modify these bits.
Note
1) If you program the watchdog to generate an IRQ signal when it times out, you shou ld initialize the IR Q
interrupt vector and enabl e the s econd i nter rup t c ontr oller (8259 PIC) in ord er to e nab le the C PU to pr oces s
this interrupt. An interrupt service routine is required too.
2) Before you init iate the i nterrupt vector of the IRQ a nd enable t he PIC, please enab le the watc hdog tim er
previously. Otherwise the watchdog timer will generate an interrupt at the time the watchdog timer is
enabled.
(3) INDEX 39H, 3Ah, and 3Bh:WD TIMER COUNTER (24 bits) -
These registers are used to set the desired counter for the watchdog to count down. The time base of each
count is 30.5μsec.
INDEX 3Bh 3Ah 39h
Data Bit D7…D0 D7…D0 D7…D0
24-bit Counter D23…D16 D15…D8 D7…D0
For example:
INDEX
3Bh 3Ah 39h
00h 00h 01h
00h 00h 02h
00h 01h 00h 7.8 m sec
00h 02h 00h 15.6 m sec
01h 00h 00h 2 sec
02h 00h 00h 4 sec
0FFh 0FFh 0FFh 512 sec
Watchdog Timer
30.5 μsec
61.0 μsec
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(4) INDEX 3Ch: Timeout Status & Reset Watchdog
Bit 7(read only)
0: Timer timeout not happened
1: Timer timeout happened
Bit 5 Write this bit “1” to reset timer
The value on this bit has no meaning.
Bit 6, Bit 4-0 Other function. Please do not modify these
bits.
(5) Basic Operation: Programming Watchdog
If you would like to acc ess the M6117C conf iguration register, you need to unlock the register at
first and lock it again after finishing the operation.
a) Unlock Configuration Register
Mov al, 13h
Out 22h, al
Nop
Nop
Mov al, 0c5h
Out 23h, al
Nop
Nop
b) Lock Configuration Register
Mov al, 13h
Out 22h, al
Nop
Nop
Mov al, 00h
Out 23h, al
Nop
Nop
c) Read the Value in the Configuration Register
Example 1: Read data from INDEX 3Ch
Unlock_Cfg_Reg ;Unlock configuration register
Mov al, 3ch ;Points to index 3ch
Out 22h, al
Nop
Nop
In al, 23h ;Read out
Nop
Nop
Push ax ;Save to stack
Lock_Cfg_Reg ;Lock configuration register
Pop ax ;Restore ax and result in al register
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d) Write Data to Configuration Register
Example 1: Write data 68h to INDEX 3Bh
Unlock_Cfg_Reg ;Unlock configuration register
Mov al, 3bh ;Points to index 3bh
Out 22h, al
Nop
Nop
Mov al, 68h
Out 23h, al ;Write data
Nop
Nop
Lock_Cfg_Reg ;Lock configuration register
AR-B1380/AR-B1380A User’s Guide
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6. SOLID STATE DISK
The section describes the various type SSD installation steps as follows. This chapter describes the
procedure of the installation. The following topics are covered:
!
Overview
!
Switch Setting
!
Jumper Setting
!
ROM Disk Installation
6.1 OVERVIEW
The AR-B1380A pro vides three 32-pin JEDEC DIP s ockets, which may be populated with up to 3MB of
EPROM or 1.5MB of FLA SH or 1.5M B of SRAM dis k. It is ide al for dis kles s systems, high reliabi lity and/or
high speed access applications, as a controller for industrial or line test instruments, etc.
If small page (less or equal to 512 bytes per page) 5V FLASHs were used, you could format FLASH disk
and copy files onto FLASH disk just like using a normal floppy disk. You can use all of the related DOS
command (such as COPY, DEL…etc.) to update files on the 5V FLASH disk.
The write protect functi on allows you to prevent your data on sm all page 5V FLASH or SRAM disk from
accidental deletion or overwrite.
An on-board Lithium battery or an external b attery pack that c ould be connected ensures data retenti on of
SRAM to the AR-B1380/AR-B1380A.
Caution:
(1) DRAM U9 (on board) is a standard memory, if you want to expand memory capacity, you should
follow the default order, the priority is U4, and then SIMM1.
(2) When SIMM1 apply in Win31 VGA driver, because of the restriction of design, the maximum
capacity is 16MB.
6.2 SWITCH SETTING
We will show the locations of the AR-B1380/AR-B1380A switch, and the factory-default settings.
CAUTION: Make sure the jumper settings and the switch setting are correct before starting up the system.
LED1
1
H1
JP3
SIMM1
1
2
1
H2
J5
CN1
CN4
JP5
JP12
1
U4
U9
JP8
J8
1
104
105
BUS1 BUS2
U5
U8
11
JP7
U17
ALi M6117C
J7
1
1
2
2
1
Figure 6-1 Switch & SSD Type Jumper Location
CN2 CN3
JP2
P1P2
U15
SW2
P7
P3
P5P6
104
105
U7
VGA
1
1
2
CN8
CN7
J4
1
M2
JP10
M3
1
J6
JP6
ABC
1
2
3
M1
ABC
1
2
3
2
1
1
2
3
J1
H3
J2
123
1
CN5
P4
JP1
1
JP11
JP4
1
1
[MEM1]
U10
[MEM2]
U14
CBA
U20
[MEM3]
1
JP9
J9
J3
A
B
C
DB1
CN6
DB2
CN9
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6.2.1 Overview
There is one DIP Switch (SW2) located on the AR-B1380/AR-B1380A. It performs the following functions:
Figure 6-2 SW2: Switch Select
SW2-1& SW2-2 Set the base I/O port address
SW2-3 & SW2-4 Set the memory address
SW2-5 & SW2-6 Set the drive number for the solid state
disks
SW2-7 & SW2-8 Set the ROM memory chips
6.2.2 SW2-1 & SW2-2: I/O Port Address Setup
SW2-1 & SW2-2 are provi ded to selec t one of the four base port ad dresses for the watchd og timer and the
solid state disk . The AR-B1380/AR-B13 80A occupies 6 I/O port address es. Followings state selectio ns of
base port address. T he following table lists the base port a ddress selections for the solid-state disk s and
watchdog timer.
SW2-1 SW2-2 Solid State Disk Watchdog
OFF OFF 210–213H 214-215H
ON OFF 290-293H 294-295H
OFF ON 310-313H 314-315H
ON ON 390-393H 394-395H
X X 76H-77H
Table 6-1 I/O Port Address Select
6.2.3 SSD & D.O.C. Setup
Before you are going to set up S. S.D. or D.O.C, you m ust adjus t the settings of JP10 a nd SW 2-3 & SW 2- 4.
JP10 is a 6-pin jum per located between M3. It is use d to select th e SSD or DOC m emory that the s ystem
is being installed. SW2-3 & SW2-4 are used to select the memory base address. The AR-B1380/ARB1380A‘s SSD firmware occupies 8KB of memory. You must select an appropriate address so that the ARB1380/AR-B1380A will not conflict with the m emory installed on other add-on memory cards. Addit ionally,
be sure not to use shadow RAM area or EMM driver’s page frame in this area.
JP10 &SW2-3/SW2-4: SSD & DOC Setup
JP10
SW2-3 SW2-4
1-2, 3-4 OFF OFF C800H --1-2, 3-4 ON OFF CC00H --1-2, 3-4 OFF ON D800H --1-2, 3-4 ON ON DC00H --3-4, 5-6 OFF OFF C800H CA00H
3-4, 5-6 ON OFF CC00H CE00H
3-4, 5-6 OFF ON D800H DA00H
3-4, 5-6 ON ON DC00H DE00H
Table 6-2 S.S.D./D.O.C. Firmware Address Selectors
S.S.D D.O.C
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If you are not going to use the solid-state dis k (S.S.D.), you can use BIO S setup program to disable the
S.S.D. under a BIOS. The AR-B1380A will not occupy any memory address if the SSD BIOS is disabled.
If you are going to install the EMM386.EX E driver, pleas e use the [X] option to prevent EMM38 6.EXE from
using the particular range of segment address as an EMS page, which is used by AR-B1380A. For
example, write a statement in the CONFIG.SYS file as follow: (If the memory configuration of ARB1380/AR-B1380A is C800:0)
DEVICE=C:\DOS\EMM386.EXE X=C800-C9FF
6.2.4 SW2-5 & SW2-6: SSD Drive Number Selector
The AR-B1380/AR-B1380 A’s SSD can sim ulate one or two disk drives . You can assign the drive l etter of
the AR-B1380/AR-B1380A by configuring SW2-5 & SW2-6.
You can make the c omputer to boot from SSD b y copying DOS boot files into the SSD. If your SSD does
not have abootable os., t he c om puter wil l bo ot f r om your hard disk or floppy disk. In this cond ition, the SSD
BIOS of AR-B1380/AR-B1380A will set the drive letter of the SSD to the desired drive letter automatically.
The SSD BIOS will sim ulate one disk drive when only (FLASH) EPROM or SRAM (starting from MEM1
socket) is installed. T he drive number s with respect to the switch s etting when the AR- B1380/AR-B1380 A
simulates single disk drives.
SW2-5 SW2-6 Occupies floppy disk number (SSD)
OFF OFF 0 or 1 (Note 1)
ON OFF 0 or 2 (Note 2)
OFF ON 0
ON ON 0
Table 6-3 SSD Drive Number
NOTE
1. If there is no Dos on this SSD, th e disk number wil l be 1 (B:). If an y DOS is fou nd by the AR- B1380/ARB1380A SSD BIOS, the dis k number will b e 0 under a dvanced cm os setup m enu, you can change t he disk
number from 0(A:) to 1( B) of networ k at the f irst boot devic e by press ing the <ES C> during s ystem bootup.
(A:) But, you can change the disk number from 0 to 1 by pressing the <ESC> key during system bootup.
2. If there is no Dos on this SSD, t he disk num ber will be 2 (C: or D: or…). If an y Dos is found b y the ARB1380/AR-B1380A SSD BIOS, the disk number will be 0 under advanced cmos setup menu, you can
change the disk num ber from 0(A:) to 1( B) of network at the first boot d evic e b y pressing the <ESC > dur ing
system bootup.
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(1) Simulate 2 Disk Drive
When (FLASH) EPROM and SRAM are both used on the AR-B1380/AR-B1380A, or you only have installed
SRAM that does not start from the MEM1 socket, the AR-B13 80/AR-B1380A will simulate two disk drives .
The drive numbers respect to those switch settings when AR-B1380/AR-B1380A simulates two disk drives.
SW2-5 SW2-6
OFF OFF 0 or 1 (Note 1) 2
ON OFF 0 or 2 (Note 2) 3
OFF ON 0 1
ON ON 0 2
Table 6-4 SSD Drive Number when Simulating 2 Disk Drives
Occupies floppy disk number
FLASH (EPROM) SRAM
NOTE
1) If there is no DOS on this SSD, the disk number will be 1 (B:). If any DOS is found by the AR-B1380/ARB1380A SSD BIO S, the disk letter will be 0 (A:). under advanced cm os setup menu, you c an change the
disk number fr om 0(A:) to 1(B) of network at the firs t boot device by pressing the <E SC> during system
bootup.
2) If there is no DOS on this SSD, the disk number will be 2 (C: or D: or….). If any DOS is found by the ARB1380/AR-B1380A SS D BIOS, the d isk number will be 0 (A:). un der advanced c mos setup m enu, you can
change the disk num ber from 0(A:) to 1( B) of network at the first boot d evic e b y pressing the <ESC > dur ing
system bootup.
(2) Disk Drive Name Arrangement
If any logical hard disk drives exist in your system , there will als o be a diff erent disk number depend ing on
which version DOS you are using.
The solid-state disk drive number with the respec tive DOS drive designati on are listed in table as f ollows.
The solid-state disk drive number is changeable as the DOS version. The following table expresses the
variety.
Condition
No Logical hard disk A: B: C: D: -- -- -- --
1 Logical hard disk A: B: C: D: E: -- -- -2 Logical hard disk A: B: C: D: E: F: -- -3 Logical hard disk A: B: C: D: E: F: G: -4 Logical hard disk A: B: C: D: E: F: G: H:
Table 6-5 SSD Drive Number for DOS Version before 5.0
Floppy disk No. Logical hard disk
0 1 2 3 1 2 3 4
Condition
No Logical hard disk A: B: C: D: -- -- -- --
1 Logical hard disk A: B: D: E: C: -- -- -2 Logical hard disk A: B: E: F: C: D: -- -3 Logical hard disk A: B: F: G: C: D: E: -4 Logical hard disk A: B: G: H: C: D: E: F:
Table 6-6 SSD Drive Number for DOS Version 5.0 and Newer
Floppy disk No. Logical hard disk
0 1 2 3 1 2 3 4
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6.2.5 SW2-7 & SW2-8: ROM Type Select
SW2-7 & SW2-8 are used to select the of ROM disk section memory type
SW2-7 SW2-8 EPROM Type
OFF OF F UV EP ROM (2 7Cxxx)
ON O FF 5V FLASH 29Fxxx (*Note)
OFF ON 5V FLASH (29Cxxx & 28 Eexxx)
ON ON 12V FLASH (28Fxxx)
Table 6-7 ROM Type Select
NOTE: It is also used to perform the hardware write protection of the small page 5V FLASH (29Cxxx or
28EExxx) disk.
6.3 M1-M3: MEMORY TYPE SETTI NGS
Before installing the m emory into m emor y sockets MEM1 thr ough MEM 3 (U31, U32 and U 33 respect ively),
you have to configure the memory type, which will be used (ROM/RAM) on the AR-B1380/AR-B1380A.
Each socket is equipped with jumper to select the memory type.
You can configure the AR-B1380/AR-B1380A as a (FLASH) EPROM disk (ROM only), a SRAM disk
(SRAM only) or a combination of (FLASH) EPROM and SRAM disk.
It is not necessary to insert memory chips into all of the sockets. The number of SRAM chips required
depends on your RAM d isk capacity. The number of EPROM chips required de pends on the total size of
files that you plan to copy onto the ROM disk and whether or not it will be bootable.
Insert the first mem or y chip into ME M1 if you ar e goi ng to conf igur e it as a ROM or SRAM disk . If you use a
combination of ROM a nd RAM, then insert the ( FLASH) EPROM chip star ting with the MEM1, and ins ert
the SRAM chips starting from the first socket, which is configured as SRAM.
!
M1: is used to configure the memory type of MEM1
!
M2: is used to configure the memory type of MEM2
!
M3: is used to configure the memory type of MEM3
CAUTION: When the power is turned off, please note the following precautions.
1) If your data has been stored in the SRAM disk, do not change the jumper position or data will be lost.
(3) Mak e sure jum pers are set proper l y. If you m istak enly set the j um pers f or SRAM and you have EPROM
or FLASH installed, the EPROM or FLASH will drain the battery’s power.
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Function M1-M3 Setting JP6 Setting
1MX8 EPROM
2-3
(ONLY)
EPROM:
128Kx8, 256Kx8,
512Kx8
5V/12V FLASH
(64Kx8M, 128Kx8,
256Kx8)
(Factory Preset)
5V FLASH
(512K*8 only)
SRAM only
Table 6-8 M1~M3 & JP6: Memory Type Setting
Note: J6 and JP6 are aligned with each other. Please be careful with these two jumpers during installation.
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6.4 ROM DISK INSTALLATION
This section describes the various types of SSDs’ installation steps as follows.
6.4.1 UV EPROM (27Cxxx)
(1) Switch and Jumper Setting
Step 1:
Step 2:
Step 3:
Use jumper block to set the memory type as ROM (FLASH).
Select the proper I/O bas e port, firmware address, di sk drive number and EPR OM type on
SW2.
Insert programmed EPROM(s) or FLASH(s) chips into sockets starting at MEM1.
Figure 6-4 UV EPROM (27CXXX) Switch Setting
Function M1-M3 Setting JP6 Setting
1MX8 EPROM (ONLY)
EPROM:
128Kx8, 256Kx8,
512Kx8
Table 6-9 UV EPROM Jumper Setting
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(2) Software Programming
Using the UV EPROM, please refer to the follow steps:
Step 1:
Turn on the power and boot DOS from the hard disk drive or floppy disk drive.
Step 2:
Make a Program Group File (*.PGF file)
Step 3:
Use the RFG.EXE to generate RO M pa ttern f iles , a nd c ount the RO M numbers as the
pattern files edited by the user.
Step 4:
Under DOS prompt type the command as follows.
C:\>RFG [file name of PGF]
Step 5:
In the RFG.EXE main menu, choose the <Load PGF File> item, that is *.PGF file.
Step 6:
Choose the <Gener ate ROM File(s)>, the tools progr am will genera te the ROM f iles,
for programming the EPROMs.
Step 7:
Program the EPROMs
Using the instruments of the EPROM wri ter to load and write the ROM pattern files
into the EPROM chips. Make sure that the program without any error verifies the
EPROMs.
Step 8:
Install EPROM chips
Be sure to place the progr ammed EPROMs (R01, R02….) into socket s tarting from
MEM1 and ensure that the chips are installed in the sockets in the proper orientation.
AR-B1380/AR-B1380A User’s Guide
6.4.2 Large Page 5V FLASH Disk
If you are using large page 5V FLASH as ROM disk, it has the same installation procedure as step 1 to step
4 when using the UV EPROM.
(1) Switch and Jumper Settings
Step 1:
Step 2:
Step 3:
SW2-8Off
Use jumper block to set the memory type as ROM (FLASH).
Select the proper I/O bas e por t, f irmware address, dis k drive number and l arge p age 5V
FLASH type on SW2.
Insert programmed EPROM(s) or FLASH(s) chips into sockets starting at MEM1.
SW2-1~SW2-6 Off
SW2-7 On
Figure 6-6 5V Large FLASH (29FXXX) Switch Setting
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Function M1-M3 Setting JP6 Setting
5V/12V FLASH
(64Kx8M, 128Kx8,
256Kx8)
5V FLASH
(512K*8 only)
Figure 6-7 Large Page 5V FLASH Jumper Setting
(2) Software Programming
Then, you should create a PGF and generate the ROM pattern files by using the RFG.EXE.
Step 1:
Make a Program Group File (*.PGF file)
Step 2:
Generate ROM pattern files
Step 3:
Turn off your system, and then install the FLASH EPROMs into the sockets.
NOTE: Place the appropri ate number of FLASH EPR OM chips (the num bers depends
on the ROM pattern files generat ed by RFG.EXE) into the soc ket starting from MEM1
and ensure that the chi ps ar e inst alled i n the soc kets in the proper ori entatio n. L ine up
and insert the AR-B1380/AR-B1380A board into any free slot of your computer.
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6.4.3 Small Page 5V FLASH ROM Disk
(1) Switch and Jumper Settings
Step 1:
Step 2:
Step 3:
SW2-1~SW2-7 Off
SW2-8 On
Use jumper block to set the memory type as ROM (FLASH).
Select the proper I/O base port, firmware addres s, disk drive number and EPR OM type
on SW2.
Insert programmed EPROM(s) or FLASH(s) chips into sockets starting at MEM1.
Figure 6-8 5V FLASH (29CXXX & 28EEXXX) Switch Setting
Function M1-M3 Setting JP6 Setting
5V/12V FLASH
(64Kx8M, 128Kx8,
256Kx8)
5V FLASH
512K*8 only
Figure 6-9 5V FLASH (29CXXX & 28EEXXX) Jumper Setting
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(2) Using Tool Program
If small page 5V FL ASH EPROMs are used, it is the same procedur e as step 1 to step 4 of using the UV
EPROM:
Step 1:
Making a Program Group File (*.PGF file)
Step 2:
Generating ROM pattern files
Step 3:
Installing FLASH EPROMs
Step 4:
Programming FLASH EPROMs
Step 5:
Reboot system
(3) Typing DOS Command
You can use another way to f ormat and copy files to the 5V FLASH EPROM. T his method provides the
convenience of using a R AM disk. You can use the DOS <FOR MAT> and <COPY> comm and to format
and copy files. Follow the following steps to format and copy files to the FLASH disk. It is the same
procedure as step 1 to step 4 of using the UV EPROM.
Step 1:
Turn on your computer, when th e screen shows the SSD BIOS menu, please hit the
<Ctrl+ ->key during the system boot-up, this enables you to enter the FLASH setup
program. If the program does not show up, check the switch setting of SW2.
Step 2:
Use <Page-Up>, <Page- Down>, <Right>, and < Left> arrow keys to select the correct
FLASH memory type and how many memory chips are going to be used.
Step 3:
Press the [F4] key to save the current settings.
Step 4:
After the DOS is loaded, use the DOS [FORMAT] command to format the FLASH disk.
To format the disk and copy DOS system files to the disk.
C:\>FORMAT [ROM disk letter] /S /U
To format the disk without copying DOS system files.
C:\>FORMAT [ROM disk letter] /U
Step 5:
Copy your program or files to the FLASH disk by using DOS [COPY] command.
CAUTION: It is not recommended that the user f ormat the disk and cop y files to the FL A SH d isk very often.
Since the FLASH EPROM ’s write c ycle lif e tim e is f rom 10,000 t o 10 0,000 tim es, writing da ta to t he FLAS H
too often will reduc e the life tim e of the FLASH EPR OM chips, especiall y the FLASH EPROM chip in the
MEM1 socket.
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6.4.4 RAM Disk
(1) Switch and Jumper Setting
AR-B1380/AR-B1380A User’s Guide
Step1:
Use jumper block to set the memory type as ROM (FLASH).
Step2:
Select the proper I/O base port, firmware address, and disk drive number on SW2.
Step3:
Insert programmed SRAM chips into sockets starting at MEM1.
NOTE: If you use the SRAM, please skip the SW2-7 & SW2-8 setting.
Function M1-M3 Setting JP6 Setting
SRAM
Figure 6-10 SRAM Jumper Setting
(2) Software Programming
It is very easy to use the RAM disk. The RAM disk operates just like a normal floppy disk. A newly installed RAM disk
needs to be formatted before files can be copied to it. Use the DOS command [FORMAT] to format the RAM disk.
Step 1:
Use jumper block to select the memory type as SRAM refer.
Step 2:
Select the proper I/O base port, firmware address and disk drive number on SW2.
Step 3:
Insert SRAM chips into sockets starting from MEM1
Step 4:
Turn on power and boot DOS from hard disk drive or floppy disk drive.
Step 5:
Use the DOS command [FO RMAT ] to form at the RAM dis k. If you are instal ling SRA M
for the first time.
To format the RAM disk and copy DOS system files onto the RAM disk.
C:\>FORMAT [RAM disk letter] /S /U
To format the RAM disk without copying DOS system files into the RAM disk.
C:\>FORMAT [RAM disk letter] /U
Step 6:
Use the DOS comm and [COPY] to copy files o nto the RAM disk. F or example, if you
want to copy file <EDIT.EXE> to the RAM disk from drive C: and the RAM disk is
assigned as drive A:.
COPY C:EDIT.EXE A:
NOTE: In addition, you can use any other DOS command to operate the RAM disk.
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6.4.5 Combination of ROM and RAM Disk
The AR-B1380/AR-B1380 A c an be conf igur ed as a co mbination of one ROM disk and one R AM d isk. Each
disk occupies a drive unit.
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:
Step 7:
Step 8:
NOTE: Users can onl y boot DOS fr om the ROM dis k drive if the AR- B1380/AR-B13 80A is c onfigured as a
ROM and a RAM disk. You don’t need to copy DOS onto the RAM disk.
Use jumper block to select the proper ROM/RAM configuration you are going to use.
Insert the first programm ed EPROM into the socket mem1, the sec ond into the socket
MEM2, etc.
Insert the SRAM chips starting from the first socket assigned as SRAM.
Select the proper I/O base port, firmware address and disk drive number on SW2.
Turn on power and boot DOS from hard disk drive or floppy disk drive.
Use the DOS command [FORMAT] to format the RAM disk.
C:\>FORMAT [RAM disk letter] /U
If 5V FLASH (small page) is being used for the first time.
And then use the DOS command [FORMAT] to format the FLASH disk.
If large page 5V FLASH is being installed for the first time, please use the FLASH
programming utility RFG.EXE to program ROM pattern files.
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7. BIOS CONSOLE
This chapter describes the AR-B1380/AR-B1380A BIOS menu displays and explains how to perform
common tasks needed to g et up and running, and pre sents detailed expl anations of the elem ents found in
each of the BIOS menus. The following topics are covered:
! BIOS Setup Overview
! Standard CMOS Setup
! Advanced CMOS Setup
! Advanced Chipset Setup
!
Password Setting
! Load Default Setting
!
BIOS Exit
! BIOS Update
7.1 BIOS SETUP OVERVIEW
BIOS is a program us ed to initialize a nd set up the I/O s ystem of the c omputer, which inc ludes the ISA bus
and connected devices such as the video display, diskette drive, and the keyboard.
The BIOS provides a m enu-based interface to the console s ubsystem. The console subs ystem contains
special software, called firmware that interacts directly with the hardware components and facilitates
interaction between the system hardware and the operating system.
The BIOS Default Values e nsure that the s ystem will function at its normal capab ility. In the worst s ituation
the user may have corrupted the original settings set by the manufacturer.
After the computer t urned on, the BIO S will per form a diagnost ics of the s ystem and wil l displa y the si ze of
the memory that is being t ested. Press the [Del] k ey to enter the BIOS Setup pr ogram, and then the ma in
menu will show on the screen.
The BIOS Setup main m enu includes some options. Use the [Up/D own] arrow key to highlight the opt ion
that you wish to modify, and then press the [Enter] key to assure the option and configure the functions.
CAUTION
1) AR-B1380/AR-B13 80A BIOS t he f actor y-default sett ing is use d to t he <Auto C onf igurati on with Op tim al
Settings> Acros ser recommends using t he BIOS default sett ing, unless you ar e very familiar with t he
setting function, or you can contact the technical support engineer.
2) If the BIOS loss s etting, th e CMOS wil l detect the < Auto Configur ation with Fail Saf e Settings > to boot
the operation system , this option will reduce the perform ance of the system. Acrosser recommends
choosing the <Auto Configuration with Optimal Setting> in the main menu. The option is best-case
values that should optimize system performance.
3) The BIOS settings are described in detail in this section.
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7.2 STANDARD CMOS SETUP
The <Standard CM OS Setup> op tion allows you to recor d some basic s ystem hardware c onfiguratio n and
set the system c lock and err or han dling. If the CPU boar d is a lread y inst alled in a work ing s ystem , you will
not need to select this option anymore.
Figure 7-2 BIOS: Standard CMOS Setup
Date & Time Setup
Highlight the <Date > field a nd then press the [Pa ge Up] /[ Page Do wn] or [+]/[-] k e ys to set th e curr ent dat e.
Follow the month, day and year format.
Highlight the <Tim e> field a nd then pres s the [Pa ge Up] /[Pag e Down] or [+]/ [-] k e ys to set the current date.
Follow the hour, minute and second format.
The user can bypass the d ate and time prompts by creating an AUTOEXEC.BAT file. For information o n
how to create this file, please refer to the MS-DOS manual.
Floppy Setup
The <Standard CMOS Setup> option records the types of floppy disk drives installed in the system.
To enter the conf iguration value for a particular dr ive, highlight its corresponding field and then s elect the
drive type using the left-or right-arrow key.
Hard Disk Setup
The BIOS supports various types for user settings , The BIOS supports <Pr i Mas t er> and <Pri Slave> so the
user can install up to t wo hard disks. For the mas ter and slave jumpers, please refer to the hard disk’s
installation descriptions and the hard disk jumper settings.
You can select <AUTO > under the <TYPE> and <MODE> fields. This will enable auto detec tion of your
IDE drives during bo ot up. This will allow you t o change your hard drives ( with the power off) and then
power on without having to r econfigure your hard drive t ype. If you us e o ld er har d disk drives, which do not
support this feature, then you must configure the hard disk drive in the standard method as described
above by the <USER> option.
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Boot Sector Virus Protection
This option protec ts the boot sector and partit ion table of your hard dis k against accidental m odifications.
Any attempt to write to them will caus e the system to hal t and display a warnin g message. If this occurs,
you can either allow the operation to continue or use a bootable virus-free floppy disk to reboot and
investigate your system. The default setting is <Disabled>. This setting is recommended because it
conflicts with ne w operat ing system s. Inst allation of ne w operating system requires that you disable this to
prevent write errors.
7.3 ADVANCED CMOS SETUP
The <Advanced CMOS SETUP> option consists of configuration entries that allow you to improve your
system performanc e, or let you set up some s ystem features according t o your preference. Som e entries
here are required by the CPU board’s design to remain in their default settings.
Figure 7-3 BIOS: Advanced CMOS Setup
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1 st Boot Device
2 nd Boot Device
3 rd Boot Device
4 th Boot Device
These options determine the priority of the boot up device, which the system looks for first to boot the
system. According to th e default sett ing, the s ystem searches the h ard disk first, then the flopp y drive, and
last the CDROM.
Available options: Disabled, IDE-0, IDE-1, IDE-2, IDE-3, Floppy, ARMD-FDD, ARMD-HDD, CDROM, SCSI, and
NETWORK
Boot From Card BIOS
Select Yes to boot up the system from the SSD BIOS, and No to boot the system from the system’s
onboard BIOS.
Available options: No, Yes
Note: It is recommended to configure this function at its default setting, Yes.
Try Other Boot Devices
If you have other boot up device other than have been mentioned above, such as
Floppy, ARMD-FDD, CDROM, SCSI, and network,
choose yes. This device is prior to the devices that have
IDE-0, IDE-1, IDE-3, IDE-4,
been mentioned above.
Available options: No, Yes
Quick Boot
This category speeds up P ower On Self Test (POST) after you power on the c omputer. If it is set enabled,
BIOS will shorten or skip some check items during POST.
Available options: Disabled, enabled
Floppy Drive Swap
The option reverses the drive letter assignments of your floppy disk drives in the Swap A, B setting,
otherwise leave on the default setting of Disabled (No Swap). This works separately from the BIOS
Features flopp y disk s wap f eature. I t is func tional l y the sam e as ph ysicall y interc hang ing th e co nnectors of
the floppy disk drives. W hen th e setting is < Enabled>, the BIOS will be swapped floppy drive assi gnments
so that Drive A becomes Drive B, and Drive B becomes Drive A under DOS.
Available options: Disabled, Enabled
Floppy Drive Seek
If the <Flopp y Drive Se ek> it em is s etting Enabled, the BIOS will seek the flopp y <A> drive one tim e upon
bootup.
Available options: Disabled, Enabled
Floppy
Access Control
This option determines the floppy access method, which can be either read only or normal (read/write).
When set to read onl y, the data in the h ard disk is being read inst ead of bein g written.” Nor mal” allows t he
floppy to be read or written.
Available options: Normal, Read only
HDD Access Control
This option determines the floppy access method, which can be either read only or normal (read/write).
When set to read onl y, the data in the h ard disk is being read inst ead of bein g written.” Nor mal” allows t he
floppy to be read or written.
Available options: Disabled, Enabled
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PS/2 Mouse Support
The setting of Enable d allows the system to detect a PS/2 mouse on boot up. If detec ted, IRQ12 will be
used for the PS/2 mouse. IRQ 12 will be reserved for expansion car ds and theref ore the PS/2 m ouse will
not function.
Available options: Disabled, Enabled
Typematic Rate
This item specifies the speed at which a keyboard keystroke is repeated.
Available options: Fast, Slow
System Keyboard
This function specifies that a keyboard would be attached to the computer.
Available options: Absent, Present
Primary Display
The option is used to set the type of video display card installed in the system.
Available options: Absent, VGA/EGA, CGA40x25, and CGA80x25
Password Check
This option enables password checking every time the com puter is powered on or every time the BIOS
Setup is executed. If Always is chosen, a user password prompt appears every time the computer is
turned on. If Setup is chosen, the password prompt appears if the BIOS executed.
Available options: Setup, Always
Wait for ‘F1’ If Error
AMIBIOS POST error messages are followed by:
Press <F1> to continue
If this option is set to Disabled, the AMIBIOS does n ot wait for you to press the <F1> key after an error
message.
Available options: Disabled, Enabled
Hit ‘DEL’ Message Display
Set this option to Disabled to prevent the message as follows:
Hit ‘DEL’ if you want to run setup
It will prevent the message from appearing on the first BIOS screen when the computer boots.
Available options: Disabled, Enabled
C000, 32K Shadow
C800, 32K Shadow
D000, 32K Shadow
D800, 32K Shadow
E000, 32K Shadow
E800, 32K Shadow
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These options co ntrol the loc ation of the c ontents of t he 32KB of RO M beginning at the specif ied memor y
location. If no adapter RO M is using the named ROM area, this area is made availab le to the local bus.
The settings are:
SETTING DESCRIPTION
Disabled
The video ROM is not copied to RAM. The
contents of the video RO M cannot be read fr om or
written to cache memory.
Enabled
The contents of C000h - C7FFFh are written to t he
same address in system memory (RAM) for faster
execution.
Table 7-1 Shadow Setting
INTERNAL –FLASH-DISK
This option selects the SSD BIOS memory address.
Available options: Disabled, C8000H, D0000H, D8000H, E0000H, and E8000H
7.4 ADVANCED CHIPSET SETUP
This option contr ols the conf iguration of the boar d’s chipset . Control k eys for this sc reen are the sam e as
for the previous screen.
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Figure 7-4BIOS: Advanced Chipset Setup
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AT Bus Clock
This option sets the polling clock speed of ISA Bus (PC/104).
Available options: 14.318/2, PLCK2/3, PLCK2/4, PLCK2/5, PLCK2/6, PLCK2/8, PLCK2/10, PLCK2/12
NOTE:
1. PCLK means the CPU inputs clock.
2. Acrosser recommends user setting at the range of 8MHz to 10MHz.
Slow Refresh
This option sets the DRAM refresh cycle time.
Available options: 15us, 60us, 120us
RAS Precharge time
The DRAM RAS precharge time.
Available options: 1.5T,2.5T, 3.5T
RAS Active Time Insert Wait
The options set the DRAM time insert wait: RAS Active and CAS Precharge function setting.
Available options: Enabled, Disabled
CAS Precharge Time insert Wait
Whenever mem ory reads or writes, it will ins ert 1T between the f alling edges for both RASJ and CASJ, if
D(4) of index 11h is set to high.
Available options: Enabled, Disabled
Memory Write Insert Wait
This option sets the Memory Write Insert Wait
Available options: Enabled, Disabled
ISA I/O High Speed
This option allo ws the ISA car d to operate at a higher ATCLK during s pecific I/O accessing cycles . The
below table describes the frequency that it can improve.
High Frequency Normal Frequency (AT Bus Clock)
7.159 MHz 7.159MHz
PCLK2/2 PCLK2/3
PCLK2/3 PCLK2/4
PCLK2/4 PCLK2/5
PCLK2/5 PCLK2/6
PCLK2/6 PCLK2/8
PCLK2/8 PCLK2/10
PCLK2/10 PCLK2/12
Available options: Enabled, Disabled
ISA Memory High Speed
This option allows the ISA card to operate at higher ATCLK during specific memory accessing cycles.
Same as ISA I/O High Speed, the above table describes the frequency that it can improve.
Available options: Enabled, Disabled
ISA Write cycle end insert wait
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I/O Recovery / Recovery Period
If an I/O Recovery Feature option is enabled, t he BIOS ins ert a de lay tim e between two I /O comm ands.
The delay time is defined in I/O Recovery Period option.
Available options for I/O Recovery: Enabled, Disabled
Available options for I/O Recover y: 0 us, 0.25 us, 0. 50 us, 0.7 5 us, 1.00 us, 1 .25 us, 1.50 us, 1.75 us, 2. 00
us, 2.25 us, 2.75 us, 3.00us, 3.25us, 3.50 us
16Bit ISA Insert Wait
This option enables the 16Bit ISA Insert Wait Function. When the s ystem is at read/write status, it will
insert the wait time to extend the read/write time.
Available options: Enabled, Disable
Watch Dog Timer Output Control
This option selec ts the Watch Dog T imer period, whic h is from 30 Seconds to 120 Seconds. The default
value is Disabled which the watch dog Timer function disables.
Available options: 30SEC, 60SEC, 75SEC, 90SEC, 105SEC, 120SEC,
Watch Dog Timeout Period Trigger Signal
To configure this functio n, the user mus t select a period of time in the abo ve item to enable the watc hdog
Timer. The value, Reset, means to reset the system every certain period of time. When another value,
(either IRQ3, IRQ4, IRQ 9, IRQ 10, IRQ11, IRQ12, or I RQ15) is s elected, t he wat ch dog T imer will gener ate
a pulse to trigger the device set to that IRQ every certain period of time.
Available options: IRQ3, IRQ4, IRQ10, IRQ10, IRQ11, IRQ12, IRQ12, IRQ12, IRQ15, RESET
7.5 PERIPHERAL SETUP
This section is used to configure the peripheral features.
Hard Disk Delay
If this option is set to Disabled and the system BIOS executes too fast, the result is that the BIOS can’t find
the hard disk drive. Therefore, it is recommended to select a hard disk delay period to prevent the BIOS
from executing too fast.
Availabie options: 3sec, 5sec, 10sec, 15sec.
OnBoard Primary IDE
This options specifies the onboard IDE controller channels that will be used.
Availabie options: Enabled, Disabled.
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OnBoard FDC
This option enables the floppy drive controller on the AR-B1380/1380A.
Availabie options: Auto, Enabled, Disabled.
OnBoard Serial Port 1
This option enables the serial port on the AR-B1380/1380A.
Available options: Disabled, 3F8h, 2F8h, 3E8h, 2E8h
OnBoard Serial Port 1 IRQ
This option selects the IRQ for the onboard serial port.
Available options: 3,4,5,9
OnBoard Serial Port 2
This option enables the serial port on the AR-B1380/1380A.
Available options: Disabled, 3F8h, 2F8h, 3E8h, 2E8h
OnBoard Serial Port2 IRQ
This option selects the IRQ for the onboard serial port2.
Available options: 3,4,5,9
AR-B1380/AR-B1380A User’s Guide
Onboard Parallel Port
This option configures the onboard the parallel port.
Available options: Auto, disabled, 378, 278, 3BC
Parallel Port Mode
This option specifies the parallel port mode. ECP and EPP are both bi-directional data transfer schemes
that adhere to the IEEE P1284 specifications.
Available options: Normal, ECP, EPP
EPP version
This option specifies the EPP version.
Available options: Normal, 1.9, 1.7
Parallel Port IRQ
This option selects the IRQ for the parallel port IRQ.
Available options: 5, 7
Parallel Port DMA Channel
This option is only available if the setting for the parallel Port Mode option is ECP.
Available options: 0. 1, 3
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7.6 PASSWORD SETTING
This BIOS Setup has an optional password f eature. The system c an be configured so that all users must
enter a password ever y time the s yst em boots or when BIOS Setup is executed. User c an set either a
Supervisor password or a User password.
7.6.1 Setting Password
Select the appropriate password icon (Supervisor or User) from the Security section of the BIOS Setup
main menu. Enter the password and press [E nter]. The screen does not display the character s entered.
After the new password is entered, retype the new password as prompted and press [Enter].
If the password confirmation is incorrect, an error message appears. If the new password is entered
without error, press [Es c] to return to the BIO S Main Menu. The pas sword is stored in CMO S RAM after
BIOS completes. T he next time the s ystem boots, you are prom pted for the pass word function is presen t
and is enabled.
Enter new supervisor password:
7.6.2 Password Checking
The password check option is enabled in Advanced Setup by choosing either Always (the password
prompt appears ever y time the system is powered on) or Setup (the pass word prompt appears only when
BIOS is run). The password is stored in CMOS RAM. User can enter a password by typing on the
keyboard. As user select Supervisor or User. The BIOS prompts for a password, user must set the
Supervisor password before user can set the User password. Enter 1-6 character as password. The
password does not appear on the screen when typed. Make sure you write it down.
7.7 LOAD DEFAULT SETTING
In this section perm it user to select a group of setting for all BIOS Setup options. Not only can you use
these items to quick ly set system configuration par am eters, you can ch oose a group of s ettings th at hav e a
better chance of working when the system is having configuration related problems.
7.7.1 Auto Configuration with Optimal Setting
User can load the optim al default settings for the BIOS. T he Optimal def ault settings are best-c ase values
that should optimize system performance. If CMOS RAM is corrupted, the optimal settings are loaded
automatically.
Load high performance settings (Y/N) ?
7.7.2 Auto Configuration with Fail Safe Setting
User can load the F ail-Safe BIOS Setup option sett ings by selecting the Fail-Saf e item from the Default
section of the BIOS Setup main menu.
The Fail-Safe settings provide f ar from optim al system perf ormance, but are th e most st able settings. Use
this option as a diagnostic aid if the system is behaving erratically.
Load failsafe settings (Y/N) ?
7.8 BIOS EXIT
This section is used to exit the BIOS main menu in t wo types situation. After making your ch ang es , you can
either save them or exit the BIOS menu and without saving the new values.
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7.8.1 Save Settings and Exit
This item set in the <St andard CMO S Setup >, <Adva nced CMOS Setup>, <Advanc ed Chips et Setup > and
the new password ( if it has been cha nge d) wil l be stored in the C MOS. The CMOS check sum is c alc u late d
and written into the CMOS.
As you select this functio n, the following message will appear at the center of the screen to as sist you to
save data to CMOS and Exit the Setup.
Save current settings and exit (Y/N) ?
7.8.2 Exit Without Saving
When you select this option, the following message will appear at the center of the screen to help to
Abandon all Data and Exit Setup.
Quit without saving (Y/N) ?
7.9 BIOS UPDATE
The BIOS program instructions are conta ined within com puter chips called FLA SH ROMs that are loc ated
on your system board. T he chips can be electronic ally re programm ed, allo wing you to upgra de your BIOS
firmware without removing and installing chips.
The AR-B1380/AR-B138 0A provides FLASH BIOS up date function for you to easil y upgrade newer BIOS
version. Please follow the operating steps for updating new BIOS:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:
Step 7:
Turn on your system and pres s <F5> to s k ip the CON FIG.S YS and AUT OEX EC.BAT f iles.
Keep your system in the real mode.
Insert the FLASH BIOS diskette into the floppy disk drive.
In the MS-DOS mode, you can type the AMIFLASH program.
A:\>AMIFLASH
The screen will show the message as follows:
Enter the BIOS File name from which Flash EPROM will be programmed.
Press <ENTER> after inserting the file name or press <ESC> to exit.
And then please enter the file name to the box of <Enter File Name>. And the box of
<Message> will sho w the notice as follow. In t he bottom of this windo w always show the
gray statement.
Flash EPROM Programming is going to start. System will not be usable until
Programming of Flash EPROM is successfully complete. In case of any error, existing
Flash EPROM must be replaced by new program Flash EPROM.
When the above statement disappears, press the <Y> key to updating the new BIOS.
And then the <Mess age> box will s how the <Progra mming Flash EPROM >, and the gray
statement shows <Please Wait>.
The BIOS update is successful, the message will show <Flash Update Completed - Pass>.
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NOTE
1) If the system didn’t detec t the boot proced ure, during po wer on, please press the [F5 ] key imm ediately.
The system will pass the CONFIG.SYS and AUTOEXEC.BAT files.
. 2) Now the onboard BIOS is the newest BIOS, if user needs to add som e functions in the future, pleas e
contact technical supporting engineers, they will provide the newest BIOS for updating.
3) The included file of AMIFLASH.EXE is Version 6.31.
http:\\www.acrosser.com
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8. SPECIFICATIONS & SSD TYPES SUPPORTED
8.1 SPECIFICATIONS
AR-B1380-All-In-One 386SX CPU Card with SSD,DOC
AR-B1380-All-In-One 386SX CPU Card with SSD,DOC, VGA, AND LAN
CPU & Chipset:
Bus Interface:
DRAM:
IDE Interface:
Floppy interface:
VGA/LCD Display:
(AR-B1380A only)
Ethernet:
(AR-B1380A only)
Serial Port:
Parallel Port:
Keyboard and Mouse:
Real Time Clock:
System BIOS:
Watchdog:
Solid State Disks:
Speaker
LED Indicator:
Power Connector:
Power Req.:
Operating Temp.:
Storage Temp.:
Reset Header:
Humidity:
CE Design-in:
PC Board:
Dimensions:
Weight:
ALI M6117C, 25/33/40 MHz (onboard 33 MHz for standard)
ISA(PC/AT) and non-stack through PC/104 bus.
2 MB EDO RAM onboard with one SOJ socket (2MB) and one 72-p in SIMM
socket for (16MB/4MB)
One IDE with 40-pin 2.54mm connector supports up to 2 IDE drives and IDE
flash modules.(DOM, DiskOnModule)
Supports 2 floppy drive with 34-pin 2.54mm connector.
C&T F65545 VGA chipset with 1 MB VRAM (1024X768/256 colors)
CRT with 15-pin HDB connector
LCD with 44-pin 2.0mm connector
10Base-T NE2000 Compatible with shielded RJ-45 edge connector.
Supports1 RS-232C and 1RS-232C/RS-485 serial ports.
1 SPP/EPP/ECP mode printer port with 26-pin 2.54mm connector
PS/2 compatible with 6-pin mini-DIN and 6-pin 2.0 mm JST connector
BQ3287MT or compatible chips
AMI flash BIOS (Including SSD BIOS),( VGA BIOS AR-B1380A only).
Programmable watchdog timer.(Acrosser’s standard and M6117C build-in)
Supports 3 sockets for up to 3MB/ 1.5MB/1.5MB EPROM /Flash/SRAM
Can be configured as three socket SSD sockets o r two SSD sockets and one D .O.C.
socket
Onboard buzzer and 1 connector header for external speaker
On-board PW/WD LED and 2 headers for external PW/WD and HDD LEDs
One 8-pin (2.5mm) JST connector
+5V only, 1.0A maximum (based on 33 MHz CPU)
0 to 60 degree C. (140 degree F.)
-10 to 75 degree C.
2-pin reset.
0 to 85% (non-condensing)
Add EMI components to COM ports, Parallel port, CRT port, Keyboard port,
and PS/2 mouse port.
6 layers
185 mmX122mm (7.28”X4.80”)
285g w/o memory chips & DRAM SIMMs
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8.2 SSD TYPES SUPPORTED
The following list contains SRAMs supported by the AR-B1380/AR-B1380A:
AKM AKM628128 (128Kx8, 1M bits)
HITACHI HM628128 (128Kx8, 1M bits)
NEC UPD431000A (128Kx8, 1M bits)
SONY CXK581000P/M (128Kx8, 1M bits)
HITACHI HM628512 (512Kx8, 4M bits)
NEC UPD434000 (512Kx8, 4M bits)
SONY CXK584000P/M (512Kx8, 4M bits)
The following list contains large page 5V FLASHs supported by the AR-B1380/AR-B1380A:
AMD Am29F512 (64Kx8, 512K bits)
AMD Am29F010 (128Kx8, 1M bits)
AMD Am29F020 (256Kx8, 2M bits)
AMD Am29F040 (512Kx8, 4M bits)
The following list contains small page 5V FLASHs supported by the AR-B1380/AR-B1380A:
ATMEL AT29C512 (64Kx8, 512K bits)
SST PH29EE512 (64Kx8, 512K bits)
ATMEL AT29C010 (128Kx8, 1M bits)
SST 28EE010 (128Kx8, 1M bits)
SST 28EE011 (128Kx8, 1M bits)
SST PH29EE010 (128Kx8, 1M bits)
WINBOND W29EE011 (128Kx8, 1M bits)
ATMEL AT29C020 (256Kx8, 2M bits)
ATMEL AT29C040 (512Kx8, 4M bits)
ATMEL AT29C040A (512Kx8, 4M bits)
SST PH28SF040 (512Kx8, 4M bits)
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The following list contains EPROMs supported by the AR-B1380/AR-B1380A:
AMD Am27C010 (128Kx8, 1M bits)
ATMEL AT27C010 (128Kx8, 1M bits)
FUJITSHU MBM27C1001 (128Kx8, 1M bits)
HITACHI HN27C101 (128Kx8, 1M bits)
INTEL D27C010 (128Kx8, 1M bits)
MITSHUBISHI M5M27C101 (128Kx8, 1M bits)
NEC D27C1001 (128Kx8, 1M bits)
NS NM27C010 (128Kx8, 1M bits)
SGS-THOMSON M27C1001 (128Kx8, 1M bits)
TI TMS27C010 (128Kx8, 1M bits)
TOSHIBA TCS711000 (128Kx8, 1M bits)
AMD Am27C020 (256Kx8, 2M bits)
ATMEL AT27C020 (256Kx8, 2M bits)
FUJITSU MBM27C2001 (256Kx8, 2M bits)
HITACHI HN27C201 (256Kx8, 2M bits)
INTEL D27C020 (256Kx8, 2M bits)
MITSHUBISHI M5M27C201 (256Kx8, 2M bits)
NEC D27C2001 (256Kx8, 2M bits)
NS NM27C020 (256Kx8, 2M bits)
SGS-THOMSON M27C2001 (256Kx8, 2M bits)
TI TMS27C020 (256Kx8, 2M bits)
TOSHIBA TCS712000 (256Kx8, 2M bits)
AMD Am27C040 (512Kx8, 4M bits)
ATMEL AT27C040 (512Kx8, 4M bits)
FUJITSU MBM27C4001 (512Kx8, 4M bits)
HITACHI HN27C401 (512Kx8, 4M bits)
INTEL D27C040 (512Kx8, 4M bits)
MITSUBISHI M5M27C401 (512Kx8, 4M bits)
NEC D27C4001 (512Kx8, 4M bits)
NS NM27C040 (512Kx8, 4M bits)
SGS-THOMSON M27C4001 (512Kx8, 4M bits)
TI TMS27C040 (512Kx8, 4M bits)
TOSHIBA TCS714000 (512Kx8, 4M bits)
ATMEL AT27C080 (1Mx8, 8M bits)
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9. USING MEMORY BANKS
This appendix provides the information about how to access the memory on the AR-B1380/AR-B1380A
without using the AR-B1380/AR-B1380A SSD BIOS. The AR-B1380/AR-B1380 A hardware divides every
8K bytes of memor y into a memory bank. To ac cess the data in the mem ory, you have to assign the chi p
number and the bank number. On e very chip, t he mem ory bank num ber st arts from zero. The las t mem ory
bank number depends on t he size of the mem ory chip used o n the AR- B1380/ AR-B1380A. For exam ple, if
you use the 256K bytes memory chip , th e bank number on ever y chip would be i n the range of 0 to 31. T he
chip numbers and the bank numbers are determined by the bank select register on the AR-B1380/ARB1380A.
The I/O address of these registers are determined by SW2-1/SW2-2
. The memory address of the memory bank is located on the range selected by SW2-3/SW2-4.
The I/O port addres s of the bank select reg ister is bas e port+0, a nd the I/O port address of the chip s elect
register is base port +2. The following is the format of the bank selects register and bank enables register.
Register I/O Port D7 D6 D5 D4 D3 D2 D1 D0
Bank Select Register Base +0 WPE A6 A5 A4 A3 A2 A1 A0
Chip Select Register Base +2 0 0 0 1 CS1 CS0 X X
Where:
WPE Write protect enable bit
A6~A0 Bank select bits, A0 is the LSB
CS1~CS0 Chip select bits of MEM1 to MEM3
Where:
CS1-CS0: Chip select
CS1 CS0 Socket
0 0 Disable
0 1 MEM1
1 0 MEM2
1 1 MEM3
For different t ypes of m emor y, A0 to A6 h ave d iff erent expl anatio ns. T hese b its ar e used to selec t th e bank
number of specific memory located in CS0 and CS1.
Memory
64KB EPROM (FLASH)
128KB EPROM (FLASH)
256KB EPROM (FLASH)
512KB EPROM (FLASH)
1MB EPROM (FLASH)
128KB SRAM
512KB SRAM
NOTE: BS0 to BS5 are the memory bank select bits. For example, 128KB memory has sixteen 8K-b yte
banks; so 4 bits (BS0 to BS3) are required.
A5 A4 A3 A2 A1 A0
A6
0 1 0 BS2 BS1 BS0
0
0 0 BS3 BS2 BS1 BS0
0
BS4 1 BS3 BS2 BS1 BS0
0
BS4 BS5 BS3 BS2 BS1 BS0
0
BS4 BS5 BS3 BS2 BS1 BS0
BS6
1 0 BS3 BS2 BS1 BS0
0
BS5 BS4 BS3 BS2 BS1 BS0
0
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AR-B1380/AR-B1380A User’s Guide
Example 1:
Example 2:
th
Select the 10
bank of the MEM1 on the AR-B1380/AR-B1380A. The AR-B1380/AR-
B1380A is using 27C020 (256K*8), and the base port is &H210.
100 base_port=&H210
110 OUT base_port+0, & H59
Select the 40
th
bank of MEM3 on t he AR- B13 80/AR-B1380A. T he AR- B13 80/AR-B1380A
is using 27C040 (512K*8), and the base port is &H390.
200 base_port=&H290
210 OUT base_port+0,&HD7
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10. PLACEMENT & DIMENSIONS
10.1 PLACEMENT
LED1
H1
JP3
SIMM1
1
1
J5
10.2 DIMENSIONS
CN1
1
2
U4
U9
JP12
U5
U8
11
JP7
U17
ALi M6117C
J8
104
105
BUS1 BUS2
H2
JP8
1
CN2 CN3
CN4
P1P2
P7
P3
P5P6
JP5
104
105
1
2
1
J7
1
U15
SW2
2
1
U7
VGA
1
2
JP2
1
JP10
CN8
CN7
J4
1
2
3
1
M2
1
2
3
2
1
M3
1
2
3
1
J6
JP6
1
1
ABC
M1
ABC
CBA
CN5
U20
U10
U14
JP1
JP4
[MEM1]
[MEM2]
[MEM3]
J1
H3
J2
123
1
P4
1
JP11
J3
A
B
C
DB1
CN6
1
JP9
DB2
J9
CN9
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Unit: mil (1 inch = 25.4 mm = 1000 mil)
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AR-B1380/AR-B1380A User’s Guide
11. PROGRAMMING THE RS-485
The majority of the c ommunicativ e operations of the RS-485 are the same as the RS-2 32. When the R S485 proceeds with the transmission, which needs control the TXC signal, the installation steps are as
follows:
Step 1:
Step 2:
Step 3:
Step 4:
NOTE: Please refer t o Section 3.3.12 space of the “ Serial Port” for the detaile d description of the COM
port’s register.
(1) Initialize COM port
Step 1:
Step 2:
NOTE:
Enable TXC (Data Terminal Relay)
Send out data
Waiting for data empty
Disable TXC
Initialize COM port i n the receiver interrupt mode, an d /or transmitter interrupt mode. (All of
the communication protocol buses of the RS-485 are in the same.)
Disable TXC (transmitter control), the bit 0 of the address of offset+4 just sets to “0”.
Set the AR-B1380/AR-B1380A CPU card’s DTR signal to the control RS-485’s TXC
communication.
(2) Send out one character (Transmit)
Step 1:
Step 2:
Step 3:
Step 4:
(3) Send out one block data (Transmit – the data more than two characters)
Step 1:
Step 2:
Step 3:
Step 4:
Enable the TXC signal, and the bit 0 of the address of offset+4 sets to “1”.
Send out the data. (Write this character to the offset+0 of the current COM port address)
Wait for the buffer’s data e m pty. Check the tr ansm itter hold ing regist er (T HRE, bit 5 of the
address of offset+5), and tr ansmitter shift r egister (TSRE, bit 6 of the addr ess of offset+5)
are set to “0”.
Disabled the TXC signal, and the bit 0 of the address of offset+4 sets to “0”
Enable the TXC signal, and the bit 0 of the address of offset+4 sets to“1”.
Send out the data. (Write all data to the offset+0 of the current COM port address)
Wait for the buffer ’s data empty. Check transmitter holding r egister (THRE, bit 5 of the
address of offset+5), and tr ansmitter shift r egister (TSRE, bit 6 of the addr ess of offset+5)
are set to “0”.
Disabled the TXC signal, and the bit 0 of the address of offset+4 sets to “0”
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(4) Receive data
The RS-485’s operation of receiving data is the same as RS-232’s.
(5) Basic Language Example
a.) Initialize 86C450 UART
10 OPEN “COM1:9600,m,8,1”AS #1 LEN=1
20 REM Reset DTR
30 OUT &H3FC, (INP(%H3FC) AND &HFA)
40 RETURN
b.) Send out one character to COM1
10 REM Enable transmitter by setting DTR ON
20 OUT &H3FC, (INP(&H3FC) OR &H01)
30 REM Send out one character
40 PRINT #1, OUTCHR$
50 REM Check transmitter holding register and shift register
60 IF ((INP(&H3FD) AND &H60) >0) THEN 60
70 REM Disable transmitter by resetting DTR
80 OUT &H3FC, (INP(&H3FC) AND &HEF)
90 RETURN
c.) Receive one character from COM1
10 REM Check COM1: receiver buffer
20 IF LOF(1)<256 THEN 70
30 REM Receiver buffer is empty
40 INPSTR$”
50 RETURN
60 REM Read one character from COM1: buffer
70 INPSTR$=INPUT$(1,#1)
80 RETURN
Note:
If the content in Setting is inconsistent with the CD-ROM. Please refer to the Setting as priority.
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