Achronix Synthesis User Manual

1

Synthesis User Guide

Using Synplify-Pro to target

Speedster22i HD devices

UG018 – April 15, 2013

UG018, April 15, 2013

Table of Contents

Introduction ................................ ................................................................ ....... 3

Synplify Pro Introduction .................................................................................. 4

Resource Sharing .......................................................................................................................... 6

Verilog ............................................................................................................................................ 6

Place and Route ............................................................................................................................ 7

Timing Report ................................................................................................................................ 7

Implementation Result ................................................................................................................... 7

Constraints ..................................................................................................................................... 7

Options .......................................................................................................................................... 7

Synthesis Optimization Recommendations .................................................... 8

Hanging Nets ......................................................................................................................... 8

Clock Constraints ................................................................................................................... 9

Pipelining ............................................................................................................................... 9

Retiming ................................................................................................................................. 9

Memories ............................................................................................................................. 10

Block RAM (BRAM) ...................................................................................................................... 10

Local Ram (LRAM) ....................................................................................................................... 12

Finite State Machines .......................................................................................................... 12

Finite State Machine (FSM) Compiler........................................................................................... 12

Replication of States that have high fan-ins ................................................................................. 13

Example Synplify-Pro Project File ................................................................. 15

Revision History .............................................................................................. 17

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Synthesis User Guide

RTL Design

Mapped Netlist

Synthesis using

Synplify Pro

Place and Route

ACE

Bitstream Generation

If Timing

Not Met

Introduction

This User Guide describes how to use Synplify Pro from Synopsys to synthesize a design and
generate a netlist for implementation on an Achronix Speedster22i HD device. Suggested
Optimization Techniques are also included.

Synplify-Pro reads in standard RTL and outputs a Mapped netlist which is used by the
Achronix CAD Environment (ACE) tool. The netlist file uses a .vma extension.

A high level overview of the Achronix design flow is shown in Figure 1 below.

Figure 1 – Synthesis Flow

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Synplify Pro Introduction

We assume you have Synplify-Pro installed and the ‘synplify_pro’ command added to your
$PATH. This guide uses Unix for examples, the Windows version of Synplify Pro has the
same options.

In the Linux command shell type “synplify_pro” to invoke the Synplify-Pro Synthesis tool.
When invoked, the following window will be displayed:

Figure 2 – Synplify Pro invoked from the command shell

Click on the “Open Project” button from the left-side and the following dialog-box will
appear (shown in Figure 3).

Figure 3 – Dialog Box to select the “New Project”

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Select or click on the “New Project” button, then the following window will appear

(shown in Figure 4):

Figure 4 – Properly select the Project database for the synthesis.

After selecting and saving the project file inside the desired directory path, you will have to
add the source RTL files. There are two ways to add the source RTL files. One is using the

“Add File” option from the Left menu bar and the other one is to ‘right click’ on the project
file and select “Add Source File”. Selecting the source will direct the user to a dialog box of

RTL files. Below is an example of the dialog box:

Figure 5 – Add the source file under the user’s project directory

From this dialog box “Select Files to Add to Project” choose your RTL files and then click
“Add” followed by “OK”. The Verilog/VHDL file(s) will now be added to the project for

synthesis.

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After adding the RTL files, the next step is to set the Implementation Options. By selecting
this option the following window will appear (Shown in Figure 6):

Figure 6 – Implementation Options

This dialog box shows the default options. For example the “Fanout Guide” defaults to
10,000, but you can modify this to any value. You can also check or uncheck the “Hard limit
to Fanout” option as well as the “Disable I/O Insertion” option.

If you do not want to infer IO buffers during synthesis, you will need to check the box under
the “Value” column. In the “Implementation Options” dialog box, “Device” is selected by
default. You can go through each tab and select the proper option according to your needs.
Here are some Achronix guidelines for these options.

Resource Sharing

Resource sharing can have a significant performance impact on loops and other critical
structures. Reviewing the synthesis results can identify resource sharing, for example
multiplexers in front of multipliers. Turning resource sharing off during synthesis can
improve performance.

Note: In some cases having resource sharing can actually improve performance. It is worth
experimenting as results are very design dependant

Verilog

Under this TAB section the user may define the Top-Level design module name. Achronix
also recommends selecting the Verilog 2001 from the Verilog Language box. The User can
also provide the parameter name of any parameter existing in the design along with a value
for the parameter. If you define the parameters in this manner, Synplify Pro will propagate

this value through the design. In this section the user can also add “Include Path Order” and

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