Achronix Speedster22i User Manual sBus
1
Speedster22i sBus Interface
User Guide
UG047, October 24, 2013
UG047, October 24, 2013
Copyright Info
Copyright © 2013 Achronix Semiconductor Corporation. All rights reserved. Achronix is a
trademark and Speedster is a registered trademark of Achronix Semiconductor Corporation.
All other trademarks are the property of their prospective owners. All specifications subject
to change without notice.
NOTICE of DISCLAIMER: The information given in this document is believed to be accurate
and reliable. However, Achronix Semiconductor Corporation does not give any
representations or warranties as to the completeness or accuracy of such information and
shall have no liability for the use of the information contained herein. Achronix
Semiconductor Corporation reserves the right to make changes to this document and the
information contained herein at any time and without notice. All Achronix trademarks,
registered trademarks, and disclaimers are listed at http://www.achronix.com and use of this
document and the Information contained therein is subject to such terms.
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Table of Contents
Copyright Info ......................................................................................................................... 2
List of Figures ........................................................................................................................ 5
List of Tables .......................................................................................................................... 6
Preface ............................................................................................................... 7
About this Guide .................................................................................................................... 7
Target Readership (or Audience) ........................................................................................... 7
Reference Documents ........................................................................................................... 7
Conventions used in this Guide ............................................................................................. 8
Terminologies used in this Guide ........................................................................................... 8
Chapter 1 – sBus Overview .............................................................................. 9
Introduction ............................................................................................................................ 9
Operation ............................................................................................................................. 10
Features ............................................................................................................................... 10
Bus .............................................................................................................................................. 10
Accessible IPs .............................................................................................................................. 10
Chapter 2 – sBus Functional Description ...................................................... 11
Port List ................................................................................................................................ 11
Read Operation .................................................................................................................... 11
32-bit Data-width Mode ................................................................................................................ 11
8-bit Data-width Mode .................................................................................................................. 12
Write Operation .................................................................................................................... 13
32-bit Data-width Mode ................................................................................................................ 13
8-bit Data-width Mode .................................................................................................................. 13
Chapter 3 – sBus Interfaces ........................................................................... 15
Master Interface ................................................................................................................... 15
Slave Interface ..................................................................................................................... 16
Chapter 4 – sBus Master Implementation ..................................................... 17
Single Master for Single Slave Implementation .................................................................... 17
Master Specifications for PLL sBus Controller .............................................................................. 17
Master Actions for PLL sBus Controller ........................................................................................ 17
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Read Operation ............................................................................................................................ 17
Write Operation ............................................................................................................................ 17
Single Master for Multiple Slaves Implementation ............................................................... 18
Master Specifications for Ethernet MAC and SerDes sBus Controller .......................................... 18
Master Actions for Ethernet MAC and SerDes sBus Controller .................................................... 18
Read Operation ............................................................................................................................ 18
Write Operation ............................................................................................................................ 18
Design Considerations ................................................................................................................. 18
Multiple Masters for a Single/Multiple Slave(s) Implementation ........................................... 19
Design Considerations ................................................................................................................. 19
Chapter 5 – sBus Design Examples ............................................................... 20
sBus Master Design ............................................................................................................. 20
Design Example ........................................................................................................................... 20
Master State Machine ................................................................................................ .................. 21
sBus Master Operation ........................................................................................................ 22
Clocking Considerations ...................................................................................................... 22
Appendix A – sBus Master Verilog Code....................................................... 23
Appendix B – Revision History ...................................................................... 27
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List of Figures
Figure 1: The HD1000 FPGA with sBus interfaces ................................................................................... 9
Figure 2: The sBus interface signals ......................................................................................................... 10
Figure 3: 32-bit Data Width sBus Read Operation ................................................................................... 12
Figure 4: 8-bit Data Width sBus Read Operation ..................................................................................... 12
Figure 5: 32-bit Data Width sBus Write Operation .................................................................................. 13
Figure 6: 8-bit Data Width sBus Write Operation .................................................................................... 14
Figure 7: Single Master for a single sBus Slave ....................................................................................... 15
Figure 8: Single Master for two sBus Slaves ............................................................................................ 16
Figure 9: sBus Slave Interface .................................................................................................................. 16
Figure 10: sBus Master Block Diagram.................................................................................................... 20
Figure 11: sBus Master State Machine ..................................................................................................... 21
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List of Tables
Table 1: HD1000 sBus Port Definition ..................................................................................................... 11
Table 2: HD1000 sBus Master Signal Definitions ................................................................................... 20
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Preface
About this Guide
The Achronix sBus is a serial bus implemented on the AC22IHD1000-F53C3 FPGA device to
allow users to access configuration registers for several of the Hard IPs available on the
device, through the FPGA fabric. This guide provides details on the implementation and uses
of the sBus. You will learn about the IP control registers that can be configured, status
registers, and how to access them for reads and writes, using the sBus, as appropriate.
Examples are provided to help you with the implementation of your own system designs.
This guide consists of the following chapters:
Chapter 1 – sBus Overview provides an overview of the sBus implemented on the
AC22IHD1000-F53C3 FPGA device.
Chapter 2 – sBus Functional Description covers more details of the sBus functionality.
Chapter 3 – sBus Interfaces describes the master and slave interfaces for the sBus.
Chapter 4 – sBus Master Implementation provides information about designing with the
sBus functional block.
Chapter 5 – sBus Design Examples provides detailed design examples for a single and
multiple IP access.
Appendix A – sBus Master Verilog Code provides a code example for a sample sBus
master design.
Appendix B – Revision History highlights the revisions to this document.
Target Readership (or Audience)
This guide is intended for embedded systems and sub-systems designers working with the
Achronix HD1000, 22-nm FPGA. You should have knowledge of FPGAs, Controllers,
Development environments and other relevant technologies.
This guide does not include board design and layout information. If you want assistance with
board design and layout, please contact Achronix.
Reference Documents
Speedster22i FPGA Family Datasheet (DS004)
Speedster22i Development Kit User Guide (UG034)
ACE User Guide (UG001)
Achronix Software & License User Guide (UG002)
Bitporter User Guide (UG004)
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Conventions used in this Guide
Item
Format
Examples
Command-line entries
Courier bold font face
$ Open top_level_name.log
File Names
Courier font face
filename.ext
GUI buttons, menus and
radio buttons
Helvetica bold font face
Click OK to continue.
File → Open
Variables
Italic emphasis
design_dir/output.log
Window and dialog box
headings and sub-headings
Heading in quotation
marks
Under “Output Files,” select ...
Window and dialog box
names
Initial caps
From the Add Files dialog box, ...
Terminology
Synonyms
Examples
Speedster22i
HD1000
Refers to the Achronix FPGA
family
sBus
Serial bus, SBUS
Refers to the serial bus on the
HD1000
This document uses the conventions shown in the following table.
Terminologies used in this Guide
This document uses the terminologies and synonyms shown in the following table.
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Chapter 1 – sBus Overview
Fabric
DDR
Interlaken
16-bit
Ethernet
MAC
32-bit
SerDes
PCIe
sBus
Port
Control
Logic
HD1000
Hard IP
Area
PLL
In this chapter, you will learn the following about the sBus serial bus:
Introduction
Operation
Features
Introduction
The sBus is a serial bus on the Achronix AC22IHD1000-F53C3 (“HD1000”) FPGA to enable
designers to communicate with registers on the Ethernet, SerDes, PCIe, Interlaken, and DDR
hard IPs. You can write to the IP registers to configure properties and read from the registers
to verify current configuration. The sBus provides communications between the FPGA fabric
and the interfaces of the hard IPs to the FPGA fabric. The control logic for the sBus is
implemented in the FPGA fabric.
Figure 1 shows the HD1000 FPGA with the sBus highlighted.
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Note: PLL registers are 8-bit but the interface is 32-bit. Upper 24-bits are ignored.
Figure 1: The HD1000 FPGA with sBus interfaces
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